coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11986 -gerrit commit 053def9a0e66e82ed828bf9b25259791edf2519c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 10 10:46:17 2015 -0500 northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training Change-Id: If26e5d148a906d63bd1407b8ffa58f08ae6b4275 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 9 ++++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 ++ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 36 ++++++++++++++++++++++++++- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 3 ++- 4 files changed, 47 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2d8ab34..2841b18 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -4134,7 +4134,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) calculate_and_store_spd_hashes(pMCTstat, pDCTstat); - if (load_spd_hashes_from_nvram(pDCTstat) < 0) { + if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { pDCTstat->spd_data.nvram_spd_match = 0; } else { @@ -4149,6 +4149,13 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) allow_config_restore = !!nvram; +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash()) + allow_config_restore = 0; +#else + allow_config_restore = 0; +#endif + if (!allow_config_restore) pDCTstat->spd_data.nvram_spd_match = 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 196d96d..425f1ef 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -297,6 +297,7 @@ struct MCTStatStruc { u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ uint32_t TSCFreq; + uint16_t nvram_checksum; } __attribute__((packed)); /*============================================================================= @@ -792,6 +793,7 @@ struct amd_s3_persistent_node_data { struct amd_s3_persistent_data { struct amd_s3_persistent_node_data node[MAX_NODES_SUPPORTED]; + uint16_t nvram_checksum; } __attribute__((packed)); /*=============================================================================== diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 0a508cb..6e92f3a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -139,6 +139,36 @@ void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash) *spd_hash = *spd_hash ^ (*spd_hash << 37); } +uint16_t calculate_nvram_mct_hash(void) +{ + uint32_t nvram; + uint16_t ret; + + ret = 0; + if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) + ret |= nvram & 0xf; + if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) + ret |= (nvram & 0x3) << 4; + if (get_option(&nvram, "ECC_memory") == CB_SUCCESS) + ret |= (nvram & 0x1) << 6; + if (get_option(&nvram, "ECC_redirection") == CB_SUCCESS) + ret |= (nvram & 0x1) << 7; + if (get_option(&nvram, "ecc_scrub_rate") == CB_SUCCESS) + ret |= (nvram & 0x1) << 8; + if (get_option(&nvram, "interleave_chip_selects") == CB_SUCCESS) + ret |= (nvram & 0x1) << 9; + if (get_option(&nvram, "interleave_nodes") == CB_SUCCESS) + ret |= (nvram & 0x1) << 10; + if (get_option(&nvram, "interleave_memory_channels") == CB_SUCCESS) + ret |= (nvram & 0x1) << 11; + if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) + ret |= (nvram & 0x1) << 12; + if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) + ret |= (nvram & 0x1) << 13; + + return ret; +} + static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) { ssize_t s3nv_offset; @@ -169,7 +199,7 @@ static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) } #ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { struct amd_s3_persistent_data *persistent_data; @@ -180,6 +210,8 @@ int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) memcpy(pDCTstat->spd_data.nvram_spd_hash, persistent_data->node[pDCTstat->Node_ID].spd_hash, sizeof(pDCTstat->spd_data.nvram_spd_hash)); memcpy(pDCTstat->spd_data.nvram_memclk, persistent_data->node[pDCTstat->Node_ID].memclk, sizeof(pDCTstat->spd_data.nvram_memclk)); + pMCTstat->nvram_checksum = persistent_data->nvram_checksum; + return 0; } #endif @@ -233,6 +265,8 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* for (channel = 0; channel < 2; channel++) persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed; + persistent_data->nvram_checksum = calculate_nvram_mct_hash(); + if (restored) { if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored)) *restored = 1; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h index 56e627e..8a72695 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h @@ -17,9 +17,10 @@ #include "mct_d.h" void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash); +uint16_t calculate_nvram_mct_hash(void); #ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat); +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); #endif #ifdef __RAMSTAGE__

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Patch merged into coreboot/master: southbridge/amd/sb700: Indicate iSATA/eSATA port type
by gerrit＠coreboot.org 10 Nov '15

10 Nov '15

the following patch was just integrated into master: commit f89a05ed9f7307df32ef5fa1fd558db7f594c269 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 9 19:34:16 2015 -0500 southbridge/amd/sb700: Indicate iSATA/eSATA port type Change-Id: I8ee757d07c82c151b36def6b709163ff144d244f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11984 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11984 for details. -gerrit

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Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Properly initialize SB700 SATA PHYs
by gerrit＠coreboot.org 10 Nov '15

10 Nov '15

the following patch was just integrated into master: commit 2b206775fa5e956772b54295a563c5a69e2117b6 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 9 18:57:23 2015 -0500 mainboard/asus/kgpe-d16: Properly initialize SB700 SATA PHYs Change-Id: I5323462dcb8a4e84786be38cc85070eb48d4a31d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11982 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11982 for details. -gerrit

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option
by Stefan Reinauer 10 Nov '15

10 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12400 -gerrit commit d480c009f2f272d97857d2ba1866e122e284e5b2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 10 18:26:52 2015 -0600 mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option ... and set the mask describing the number of ports in Kconfig Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/Kconfig | 4 ++++ src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 29061ca..c4528e5 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -80,6 +80,10 @@ config IRQ_SLOT_COUNT int default 13 +config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD + hex + default 0x3f + config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index c841aa9..dc698d0 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -16,6 +16,7 @@ interleave_nodes = Disable interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable +sata_ahci_mode = Enable ieee1394_controller = Enable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 40799d5..dfd5159 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -40,7 +40,8 @@ entries 464 1 e 2 compute_unit_siblings 465 1 e 1 cpu_c_states 466 1 e 1 cpu_cc6_state -467 1 r 0 allow_spd_nvram_cache_restore +467 1 e 1 sata_ahci_mode +468 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum

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Patch merged into coreboot/master: southbridge/amd/sb700: Add AHCI support
by gerrit＠coreboot.org 10 Nov '15

10 Nov '15

the following patch was just integrated into master: commit 5d7dc5545dc51152abada7677073ab1e8ee97960 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 9 18:09:50 2015 -0500 southbridge/amd/sb700: Add AHCI support Change-Id: I147284e6a435f4b96d6821a122c1f4f9ddc2ea33 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11981 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11981 for details. -gerrit

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New patch to review for coreboot: mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12400 -gerrit commit d3deaab71228aa7957695a2e58fdee7a2da730b7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 10 18:26:52 2015 -0600 mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/Kconfig | 4 ++++ src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 29061ca..c4528e5 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -80,6 +80,10 @@ config IRQ_SLOT_COUNT int default 13 +config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD + hex + default 0x3f + config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index c841aa9..dc698d0 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -16,6 +16,7 @@ interleave_nodes = Disable interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable +sata_ahci_mode = Enable ieee1394_controller = Enable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 40799d5..dfd5159 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -40,7 +40,8 @@ entries 464 1 e 2 compute_unit_siblings 465 1 e 1 cpu_c_states 466 1 e 1 cpu_cc6_state -467 1 r 0 allow_spd_nvram_cache_restore +467 1 e 1 sata_ahci_mode +468 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum

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Patch set updated for coreboot: northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11980 -gerrit commit 1a519cb8bf07e8c868b853396a2e30c4ae004a9b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 8 19:54:56 2015 -0500 northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged Change-Id: I5fee5f5fdf30ab6e3c4f94ed3e54ea66c1204352 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 3 +++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 21 +++++++++++++++++++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1d48070..2d8ab34 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1368,6 +1368,7 @@ restartinit: printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n"); if (restore_mct_information_from_nvram(0) != 0) printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); + pMCTstat->GStatus |= 1 << GSB_ConfigRestored; #endif printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); @@ -2095,6 +2096,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, if (is_fam15h()) exit_training_mode_fam15(pMCTstat, pDCTstatA); + + pMCTstat->GStatus |= 1 << GSB_ConfigRestored; } /* FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 1ac7bbf..196d96d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -312,6 +312,7 @@ struct MCTStatStruc { #define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/ #define GSB_EnDIMMSpareNW 17 /* Indicates that DIMM Spare can be used without a warm reset */ /* NOTE: This is a local bit used by memory code */ +#define GSB_ConfigRestored 18 /* Training configuration was restored from NVRAM */ /*=============================================================================== Local DCT Status structure (a structure for each DCT) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 8ed7e3c..0a508cb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -209,7 +209,7 @@ static uint32_t read_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t d return pci_read_config32(dev, reg); } -static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data) +static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t * restored) { uint8_t node; uint8_t dimm; @@ -232,6 +232,13 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* for (node = 0; node < MAX_NODES_SUPPORTED; node++) for (channel = 0; channel < 2; channel++) persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed; + + if (restored) { + if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored)) + *restored = 1; + else + *restored = 0; + } } void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data) @@ -1030,6 +1037,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste int8_t save_mct_information_to_nvram(void) { uint8_t nvram; + uint8_t restored = 0; if (acpi_is_wakeup_s3()) return 0; @@ -1051,7 +1059,16 @@ int8_t save_mct_information_to_nvram(void) copy_mct_data_to_save_variable(persistent_data); /* Save RAM SPD data at the same time */ - copy_cbmem_spd_data_to_save_variable(persistent_data); + copy_cbmem_spd_data_to_save_variable(persistent_data, &restored); + + if (restored) { + /* Allow training bypass if DIMM configuration is unchanged on next boot */ + nvram = 1; + set_option("allow_spd_nvram_cache_restore", &nvram); + + printk(BIOS_DEBUG, "Hardware configuration unchanged since last boot; skipping write\n"); + return 0; + } /* Obtain CBFS file offset */ s3nv_offset = get_s3nv_file_offset();

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Patch set updated for coreboot: southbridge/amd/sb700: Add AHCI support
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11981 -gerrit commit 3be5590b0360e09ae193b61629f20d3434bc826f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 9 18:09:50 2015 -0500 southbridge/amd/sb700: Add AHCI support Change-Id: I147284e6a435f4b96d6821a122c1f4f9ddc2ea33 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/include/device/pci_ids.h | 2 + src/southbridge/amd/sb700/Kconfig | 4 + src/southbridge/amd/sb700/early_setup.c | 73 ++++++--- src/southbridge/amd/sb700/ide.c | 42 +++--- src/southbridge/amd/sb700/sata.c | 256 ++++++++++++++++++++++---------- 5 files changed, 259 insertions(+), 118 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index fcaf4aa..664ac49 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -311,6 +311,8 @@ #define PCI_DEVICE_ID_ATI_SB700_LPC 0x439D #define PCI_DEVICE_ID_ATI_SB700_SATA 0x4390 +#define PCI_DEVICE_ID_ATI_SB700_SATA_AHCI 0x4391 +#define PCI_DEVICE_ID_ATI_SB700_SATA_AHCI_AMD 0x4394 #define PCI_DEVICE_ID_ATI_SB700_IDE 0x439C #define PCI_DEVICE_ID_ATI_SB700_HDA 0x4383 #define PCI_DEVICE_ID_ATI_SB700_PCI 0x4384 diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 0a0b7f1..9a0ddb2 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -42,6 +42,10 @@ config SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA bool default n +config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD + hex + default 0xf + config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 394e058..26fcebd 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -350,9 +350,13 @@ static void sb700_devices_por_init(void) { device_t dev; u8 byte; -#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 - u32 dword; -#endif + uint32_t dword; + uint8_t nvram; + uint8_t sata_ahci_mode; + + sata_ahci_mode = 0; + if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) + sata_ahci_mode = !!nvram; printk(BIOS_INFO, "sb700_devices_por_init()\n"); /* SMBus Device, BDF:0-20-0 */ @@ -513,34 +517,56 @@ static void sb700_devices_por_init(void) /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ pci_write_config8(dev, 0x50, 0x01); + if (!sata_ahci_mode){ #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 - /* SP5100 default SATA mode is RAID5 MODE */ - dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0); - /* Set SATA Operation Mode, Set to IDE mode */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 0); - pci_write_config8(dev, 0x40, byte); + /* SP5100 default SATA mode is RAID5 MODE */ + dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0); + + /* Set SATA Operation Mode, Set to IDE mode */ + byte = pci_read_config8(dev, 0x40); + byte |= (1 << 0); + pci_write_config8(dev, 0x40, byte); - dword = 0x01018f00; - pci_write_config32(dev, 0x8, dword); + dword = 0x01018f00; + pci_write_config32(dev, 0x8, dword); - /* set SATA Device ID writable */ - dword = pci_read_config32(dev, 0x40); - dword &= ~(1 << 24); - pci_write_config32(dev, 0x40, dword); + /* set SATA Device ID writable */ + dword = pci_read_config32(dev, 0x40); + dword &= ~(1 << 24); + pci_write_config32(dev, 0x40, dword); - /* set Device ID accommodate with IDE emulation mode configuration*/ - pci_write_config32(dev, 0x0, 0x43901002); + /* set Device ID consistent with IDE emulation mode configuration */ + pci_write_config32(dev, 0x0, 0x43901002); - /* rpr v2.13 4.17 Reset CPU on Sync Flood */ - abcfg_reg(0x10050, 1 << 2, 1 << 2); + /* rpr v2.13 4.17 Reset CPU on Sync Flood */ + abcfg_reg(0x10050, 1 << 2, 1 << 2); #endif + } /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ - printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-18-0\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-17-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0); - /*PHY Global Control*/ + if (sata_ahci_mode) { + /* Switch to AHCI mode (AMD inbox) */ + dword = pci_read_config32(dev, 0x40); + dword |= (0x1 << 24); /* Lock Flash Device ID = 1 */ + pci_write_config32(dev, 0x40, dword); + + /* Deactivate Sub-Class Code write protection */ + byte = pci_read_config8(dev, 0x40); + byte |= (1 << 0); + pci_write_config8(dev, 0x40, byte); + + dword = pci_read_config32(dev, 0x08); + dword &= ~(0xff << 16); /* Sub-Class Code = 0x6 */ + dword |= (0x6 << 16); + dword &= ~(0xff << 8); /* Operating Mode Selection = 0x1 */ + dword |= (0x1 << 8); + pci_write_config32(dev, 0x08, dword); + } + + /* PHY Global Control */ pci_write_config16(dev, 0x86, 0x2C00); } @@ -687,6 +713,11 @@ static void sb700_pci_cfg(void) /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0); + if (dev == PCI_DEV_INVALID) + dev = pci_locate_device(PCI_ID(0x1002, 0x4391), 0); + if (dev == PCI_DEV_INVALID) + dev = pci_locate_device(PCI_ID(0x1002, 0x4394), 0); + /* rpr7.12 SATA MSI and D3 Power State Capability. */ byte = pci_read_config8(dev, 0x40); byte |= 1 << 0; diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c index 89d7cdf..5a5532d 100644 --- a/src/southbridge/amd/sb700/ide.c +++ b/src/southbridge/amd/sb700/ide.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -18,6 +19,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <option.h> #include "sb700.h" static void ide_init(struct device *dev) @@ -26,6 +28,12 @@ static void ide_init(struct device *dev) /* Enable ide devices so the linux ide driver will work */ u32 dword; u8 byte; + uint8_t nvram; + uint8_t sata_ahci_mode; + + sata_ahci_mode = 0; + if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) + sata_ahci_mode = !!nvram; conf = dev->chip_info; @@ -35,25 +43,25 @@ static void ide_init(struct device *dev) dword &= ~(1 << 16); pci_write_config32(dev, 0x70, dword); - /* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */ - byte = pci_read_config8(dev, 0x54); - byte |= 0xf; - pci_write_config8(dev, 0x54, byte); - - /* Enable I/O Access&& Bus Master */ - dword = pci_read_config16(dev, 0x4); - dword |= 1 << 2; - pci_write_config16(dev, 0x4, dword); - - /* set ide as primary, if you want to boot from IDE, you'd better set it - * in $vendor/$mainboard/devicetree.cb */ + if (!sata_ahci_mode) { + /* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */ + byte = pci_read_config8(dev, 0x54); + byte |= 0xf; + pci_write_config8(dev, 0x54, byte); + /* Enable I/O Access&& Bus Master */ + dword = pci_read_config16(dev, 0x4); + dword |= 1 << 2; + pci_write_config16(dev, 0x4, dword); - if (conf->boot_switch_sata_ide == 1) { - struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - byte = pci_read_config8(sm_dev, 0xAD); - byte |= 1 << 4; - pci_write_config8(sm_dev, 0xAD, byte); + /* set ide as primary, if you want to boot from IDE, you'd better set it + * in $vendor/$mainboard/devicetree.cb */ + if (conf->boot_switch_sata_ide == 1) { + struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + byte = pci_read_config8(sm_dev, 0xad); + byte |= 1 << 4; + pci_write_config8(sm_dev, 0xad, byte); + } } } diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 9fc2647..72c1de8 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,18 +21,19 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/io.h> +#include <option.h> #include "sb700.h" -static int sata_drive_detect(int portnum, u16 iobar) +static int sata_drive_detect(int portnum, uint16_t iobar) { u8 byte, byte2; int i = 0; - outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6); + outb(0xa0 + 0x10 * (portnum % 2), iobar + 0x6); while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7), - (byte != (0xA0 + 0x10 * (portnum % 2))) || + (byte != (0xa0 + 0x10 * (portnum % 2))) || ((byte2 & 0x88) != 0)) { printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); - if (byte != (0xA0 + 0x10 * (portnum % 2))) { + if (byte != (0xa0 + 0x10 * (portnum % 2))) { /* This will happen at the first iteration of this loop * if the first SATA port is unpopulated and the * second SATA port is populated. @@ -61,15 +63,15 @@ void __attribute__((weak)) sb7xx_51xx_setup_sata_phys(struct device *dev) pci_write_config32(dev, 0x90, 0x01B48016); pci_write_config32(dev, 0x94, 0x01B48016); pci_write_config32(dev, 0x98, 0x01B48016); - pci_write_config32(dev, 0x9C, 0x01B48016); + pci_write_config32(dev, 0x9c, 0x01B48016); /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ - pci_write_config16(dev, 0xA0, 0xA09A); - pci_write_config16(dev, 0xA2, 0xA09F); - pci_write_config16(dev, 0xA4, 0xA07A); - pci_write_config16(dev, 0xA6, 0xA07A); - pci_write_config16(dev, 0xA8, 0xA07A); - pci_write_config16(dev, 0xAA, 0xA07A); + pci_write_config16(dev, 0xa0, 0xA09A); + pci_write_config16(dev, 0xa2, 0xA09F); + pci_write_config16(dev, 0xa4, 0xA07A); + pci_write_config16(dev, 0xa6, 0xA07A); + pci_write_config16(dev, 0xa8, 0xA07A); + pci_write_config16(dev, 0xaa, 0xA07A); } static void sata_init(struct device *dev) @@ -79,8 +81,18 @@ static void sata_init(struct device *dev) u32 dword; u8 rev_id; void *sata_bar5; - u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; + uint16_t sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; + uint16_t ide_bar0, ide_bar1, ide_bar2, ide_bar3; + uint16_t current_bar; int i, j; + uint8_t nvram; + uint8_t sata_ahci_mode; + uint8_t port_count; + uint8_t max_port_count; + + sata_ahci_mode = 0; + if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) + sata_ahci_mode = !!nvram; device_t sm_dev; /* SATA SMBus Disable */ @@ -94,21 +106,39 @@ static void sata_init(struct device *dev) byte |= (1 << 5); pci_write_config8(sm_dev, 0xad, byte); + /* get rev_id */ + rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; + + if (sata_ahci_mode) { + /* Enable link latency enhancement on A14 and above */ + if (rev_id >= 0x14) { + byte = pci_read_config8(sm_dev, 0xad); + byte &= ~(1 << 5); + pci_write_config8(sm_dev, 0xad, byte); + } + } + + /* Disable combined mode */ + byte = pci_read_config8(sm_dev, 0xad); + byte &= ~(1 << 3); + pci_write_config8(sm_dev, 0xad, byte); + + device_t ide_dev; + /* IDE Device */ + ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + /* RPR 7.2 SATA Initialization */ /* Set the interrupt Mapping to INTG# */ byte = pci_read_config8(sm_dev, 0xaf); byte = 0x6 << 2; pci_write_config8(sm_dev, 0xaf, byte); - /* get rev_id */ - rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; - /* get base address */ sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF); sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; - sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3; + sata_bar3 = pci_read_config16(dev, 0x1c) & ~0x3; sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */ @@ -118,11 +148,16 @@ static void sata_init(struct device *dev) printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */ - /* disable combined mode */ - byte = pci_read_config8(sm_dev, 0xAD); - byte &= ~(1 << 3); - pci_write_config8(sm_dev, 0xAD, byte); - /* Program the 2C to 0x43801002 */ + ide_bar0 = pci_read_config16(ide_dev, 0x10) & ~0x7; + ide_bar1 = pci_read_config16(ide_dev, 0x14) & ~0x3; + ide_bar2 = pci_read_config16(ide_dev, 0x18) & ~0x7; + ide_bar3 = pci_read_config16(ide_dev, 0x1c) & ~0x3; + printk(BIOS_SPEW, "ide_bar0=%x\n", ide_bar0); + printk(BIOS_SPEW, "ide_bar1=%x\n", ide_bar1); + printk(BIOS_SPEW, "ide_bar2=%x\n", ide_bar2); + printk(BIOS_SPEW, "ide_bar3=%x\n", ide_bar3); + + /* Program the Subsystem ID/VID to 0x43801002 */ dword = 0x43801002; pci_write_config32(dev, 0x2c, dword); @@ -136,15 +171,48 @@ static void sata_init(struct device *dev) byte |= (1 << 2); pci_write_config8(dev, 0x40, byte); - /* Set SATA Operation Mode, Set to IDE mode */ + /* Unlock subclass and certain BAR R/O registers */ byte = pci_read_config8(dev, 0x40); byte |= (1 << 0); - byte |= (1 << 4); pci_write_config8(dev, 0x40, byte); - dword = 0x01018f00; - pci_write_config32(dev, 0x8, dword); + /* Disable AHCI enhancement (AMD SP5100 RPR page 54) */ + dword = pci_read_config32(dev, 0x40); + dword |= (1 << 23); + pci_write_config32(dev, 0x40, dword); + + if (sata_ahci_mode) { + /* Force number of ports to 6 + * NOTE: This is not documented in the register + * reference guide, but CIMX needs to do this + * to activate all 6 ports when IDE is disabled. + */ + dword = read32(sata_bar5 + 0x00); + dword &= ~0x7; + dword |= 0x5; + write32(sata_bar5 + 0x00, dword); + } else { + /* Set SATA Operation Mode, Set to IDE mode */ + byte = pci_read_config8(dev, 0x40); + byte |= (1 << 4); + pci_write_config8(dev, 0x40, byte); + + dword = 0x01018f00; + pci_write_config32(dev, 0x8, dword); + } + + /* Get maximum number of ports */ + max_port_count = read32(sata_bar5 + 0x00) & 0x1f; + max_port_count++; + printk(BIOS_SPEW, "Maximum SATA port count supported by silicon: %d\n", max_port_count); + /* Set number of ports */ + dword = CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD; + for (i = max_port_count; i < 32; i++) + dword &= ~(0x1 << i); + write32(sata_bar5 + 0x0c, dword); + + /* Write protect Sub-Class Code */ byte = pci_read_config8(dev, 0x40); byte &= ~(1 << 0); pci_write_config8(dev, 0x40, byte); @@ -177,6 +245,7 @@ static void sata_init(struct device *dev) byte = 0x10; pci_write_config8(dev, 0x46, byte); sb7xx_51xx_setup_sata_phys(dev); + /* Enable the I/O, MM, BusMaster access for SATA */ byte = pci_read_config8(dev, 0x4); byte |= 7 << 0; @@ -187,62 +256,75 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0xC, 0x00004000); #endif - /* RPR7.7 SATA drive detection. */ - /* Use BAR5+0x128,BAR0 for Primary Slave */ - /* Use BAR5+0x1A8,BAR0 for Primary Slave */ - /* Use BAR5+0x228,BAR2 for Secondary Master */ - /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ - /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary master emulation */ - /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */ - - /* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */ - - for (i = 0; i < 4; i++) { - byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); - byte &= 0xF; - if( byte == 0x1 ) { - /* If the drive status is 0x1 then we see it but we aren't talking to it. */ - /* Try to do something about it. */ - printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); + /* Determine port count */ + port_count = 0; + for (i = 0; i < 32; i++) { + if (CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD & (0x1 << i)) + port_count = i; + } + port_count++; + if (port_count > max_port_count) + port_count = max_port_count; + + if (!sata_ahci_mode) { + /* RPR7.7 SATA drive detection. */ + /* Use BAR5+0x128,BAR0 for Primary Slave */ + /* Use BAR5+0x1A8,BAR0 for Primary Slave */ + /* Use BAR5+0x228,BAR2 for Secondary Master */ + /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ + /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */ + /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */ + for (i = 0; i < port_count; i++) { + byte = read8(sata_bar5 + 0x128 + 0x80 * i); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); + byte &= 0xF; + if (byte == 0x1) { + /* If the drive status is 0x1 then we see it but we aren't talking to it. */ + /* Try to do something about it. */ + printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); - /* Read in Port-N Serial ATA Control Register */ - byte = read8(sata_bar5 + 0x12C + 0x80 * i); + /* Read in Port-N Serial ATA Control Register */ + byte = read8(sata_bar5 + 0x12C + 0x80 * i); - /* Set Reset Bit and 1.5g bit */ - byte |= 0x11; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); + /* Set Reset Bit and 1.5g bit */ + byte |= 0x11; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); - /* Wait 1ms */ - mdelay(1); + /* Wait 1ms */ + mdelay(1); - /* Clear Reset Bit */ - byte &= ~0x01; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); + /* Clear Reset Bit */ + byte &= ~0x01; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); - /* Wait 1ms */ - mdelay(1); + /* Wait 1ms */ + mdelay(1); - /* Reread status */ - byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); - byte &= 0xF; - } + /* Reread status */ + byte = read8(sata_bar5 + 0x128 + 0x80 * i); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); + byte &= 0xF; + } - if (byte == 0x3) { - for (j = 0; j < 10; j++) { - if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2)) - break; + if (byte == 0x3) { + for (j = 0; j < 10; j++) { + if (i < 4) + current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2; + else + current_bar = ide_bar0; + if (!sata_drive_detect(i, current_bar)) + break; + } + printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", + (i / 2) ? "Secondary" : "Primary", + (i % 2 ) ? "Slave" : "Master", + (j == 10) ? "not " : "", + (j == 10) ? j : j + 1); + } else { + printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", + (i / 2) ? "Secondary" : "Primary", + (i % 2 ) ? "Slave" : "Master", i); } - printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", - (i / 2) ? "Secondary" : "Primary", - (i % 2 ) ? "Slave" : "Master", - (j == 10) ? "not " : "", - (j == 10) ? j : j + 1); - } else { - printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", - (i / 2) ? "Secondary" : "Primary", - (i % 2 ) ? "Slave" : "Master", i); } } @@ -252,13 +334,15 @@ static void sata_init(struct device *dev) byte |= 1 << 1; write8((sata_bar5 + 0x4), byte); - /* Clear error status */ - write32((sata_bar5 + 0x130), 0xFFFFFFFF); - write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); - write32((sata_bar5 + 0x230), 0xFFFFFFFF); - write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); - write32((sata_bar5 + 0x330), 0xFFFFFFFF); - write32((sata_bar5 + 0x3b0), 0xFFFFFFFF); + if (!sata_ahci_mode) { + /* Clear error status */ + write32((sata_bar5 + 0x130), 0xFFFFFFFF); + write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); + write32((sata_bar5 + 0x230), 0xFFFFFFFF); + write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); + write32((sata_bar5 + 0x330), 0xFFFFFFFF); + write32((sata_bar5 + 0x3b0), 0xFFFFFFFF); + } /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */ @@ -289,3 +373,15 @@ static const struct pci_driver sata0_driver __pci_driver = { .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB700_SATA, }; + +static const struct pci_driver sata1_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_SATA_AHCI, +}; + +static const struct pci_driver sata2_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_SATA_AHCI_AMD, +};

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Properly initialize SB700 SATA PHYs
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11982 -gerrit commit 9a8a3da9a6098ab3a1945e5a6023774bc1690954 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 9 18:57:23 2015 -0500 mainboard/asus/kgpe-d16: Properly initialize SB700 SATA PHYs Change-Id: I5323462dcb8a4e84786be38cc85070eb48d4a31d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/mainboard.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c index 802b855..d71df9e 100644 --- a/src/mainboard/asus/kgpe-d16/mainboard.c +++ b/src/mainboard/asus/kgpe-d16/mainboard.c @@ -72,6 +72,29 @@ static void mainboard_enable(device_t dev) /* get_ide_dma66(); */ } +/* override the default SATA PHY setup */ +void sb7xx_51xx_setup_sata_phys(struct device *dev) +{ + /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ + pci_write_config16(dev, 0x86, 0x2c00); + + /* RPR7.6.2 SATA GENI PHY ports setting */ + pci_write_config32(dev, 0x88, 0x01b48016); + pci_write_config32(dev, 0x8c, 0x01b48016); + pci_write_config32(dev, 0x90, 0x01b48016); + pci_write_config32(dev, 0x94, 0x01b48016); + pci_write_config32(dev, 0x98, 0x01b48016); + pci_write_config32(dev, 0x9c, 0x01b48016); + + /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ + pci_write_config16(dev, 0xa0, 0xa07a); + pci_write_config16(dev, 0xa2, 0xa07a); + pci_write_config16(dev, 0xa4, 0xa07a); + pci_write_config16(dev, 0xa6, 0xa07a); + pci_write_config16(dev, 0xa8, 0xa07a); + pci_write_config16(dev, 0xaa, 0xa07a); +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, };

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Patch set updated for coreboot: southbridge/amd/sb700: Disable broken SATA MSI functionality
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11983 -gerrit commit 572663b131e47341b9ff94bc4325bac071119220 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 9 19:12:35 2015 -0500 southbridge/amd/sb700: Disable broken SATA MSI functionality Change-Id: I4e0a52eb90910604f8640ad7533b5d71be6c8e20 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/early_setup.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 26fcebd..f109896 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -670,6 +670,7 @@ static void sb700_pci_cfg(void) { device_t dev; u8 byte; + uint8_t acpi_s1_supported = 1; /* SMBus Device, BDF:0-20-0 */ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); @@ -722,10 +723,10 @@ static void sb700_pci_cfg(void) byte = pci_read_config8(dev, 0x40); byte |= 1 << 0; pci_write_config8(dev, 0x40, byte); - if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12) - pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */ + if (acpi_s1_supported) + pci_write_config8(dev, 0x34, 0x70); /* Hide D3 power state and MSI capabilities */ else - pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */ + pci_write_config8(dev, 0x61, 0x70); /* Hide MSI capability */ byte &= ~(1 << 0); pci_write_config8(dev, 0x40, byte); }

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coreboot-gerrit November 2015