coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: src/console: Add x86 romstage spinlock option and printk spinlock support
by Timothy Pearson 02 Nov '15

02 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11958 -gerrit commit 5ace6412d3fb355eebe8351a788945bbd7e5022f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon May 18 16:04:10 2015 -0500 src/console: Add x86 romstage spinlock option and printk spinlock support This paves the way for AP printk spinlock on AMD platforms Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/Kconfig | 4 ++++ src/arch/x86/include/arch/smp/spinlock.h | 11 ++++++++++- src/console/printk.c | 15 +++++++++++++++ src/cpu/amd/car/post_cache_as_ram.c | 4 ++++ 4 files changed, 33 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 79d5994..c79a7cc 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -459,6 +459,10 @@ config HAVE_HARD_RESET This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code. +config HAVE_ROMSTAGE_CONSOLE_SPINLOCK + bool + default n + config HAVE_MONOTONIC_TIMER def_bool n help diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 32be2f2..74e532c 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,7 +1,7 @@ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H -#ifndef __PRE_RAM__ +#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) /* * Your basic SMP spinlocks, allowing only a single CPU anywhere @@ -11,9 +11,18 @@ typedef struct { volatile unsigned int lock; } spinlock_t; +#ifdef __PRE_RAM__ +spinlock_t *romstage_console_lock(void); +void initialize_romstage_console_lock(void); +#endif #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } + +#ifndef __PRE_RAM__ #define DECLARE_SPIN_LOCK(x) static spinlock_t x = SPIN_LOCK_UNLOCKED; +#else +#define DECLARE_SPIN_LOCK(x) +#endif /* * Simple spin lock operations. There are two variants, one clears IRQ's diff --git a/src/console/printk.c b/src/console/printk.c index aab7ff5..99f90a8 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -2,6 +2,7 @@ * blatantly copied from linux/kernel/printk.c * * Copyright (C) 1991, 1992 Linus Torvalds + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * */ @@ -13,7 +14,9 @@ #include <stddef.h> #include <trace.h> +#if (!defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) DECLARE_SPIN_LOCK(console_lock) +#endif void do_putchar(unsigned char byte) { @@ -39,7 +42,13 @@ int do_printk(int msg_level, const char *fmt, ...) #endif DISABLE_TRACE; +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) + spin_lock(romstage_console_lock()); +#endif +#else spin_lock(&console_lock); +#endif va_start(args, fmt); i = vtxprintf(wrap_putchar, fmt, args, NULL); @@ -47,7 +56,13 @@ int do_printk(int msg_level, const char *fmt, ...) console_tx_flush(); +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) + spin_unlock(romstage_console_lock()); +#endif +#else spin_unlock(&console_lock); +#endif ENABLE_TRACE; return i; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 61d47a2..4102a66 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -76,6 +76,10 @@ static void prepare_ramstage_region(void *resume_backup_memory) memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); } +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) + initialize_romstage_console_lock(); +#endif + print_car_debug("Done\n"); }

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Patch set updated for coreboot: northbridge/amd/amdfam10: Set DIMM voltage based on SPD data
by Timothy Pearson 02 Nov '15

02 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11957 -gerrit commit e92169d56ab0f9b0c72a3047d5b0500e24faa15b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Sep 5 18:56:05 2015 -0500 northbridge/amd/amdfam10: Set DIMM voltage based on SPD data Change-Id: I67a76cf0e4ebc33fbd7dd151bb68dce1fc6ba680 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/Kconfig | 4 ++++ src/northbridge/amd/amdfam10/acpi.c | 3 +-- src/northbridge/amd/amdfam10/northbridge.c | 30 +++++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 8 ++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 ++++++ 5 files changed, 49 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 3ea1e46..17968b4 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -83,6 +83,10 @@ config DIMM_REGISTERED bool default n +config DIMM_VOLTAGE_SET_SUPPORT + bool + default n + if DIMM_FBDIMM config DIMM_SUPPORT hex diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 5ff38aa..ad54abd 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -303,8 +303,7 @@ void northbridge_acpi_write_vars(device_t device) } else { if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 CBST = (u8) (0x0f); - } - else { + } else { CBST = (u8) (0x00); } } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 2846ed3..2e7fc3a 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1063,6 +1063,36 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, snprintf(string_buffer, sizeof (string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]); t->serial_number = smbios_add_string(t->eos, string_buffer); } + if (IS_ENABLED(CONFIG_DIMM_DDR2)) { + /* JEDEC specifies 1.8V only, so assume that the memory is configured for 1.8V */ + t->minimum_voltage = 1800; + t->maximum_voltage = 1800; + t->configured_voltage = 1800; + } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) { +#if IS_ENABLED(CONFIG_DIMM_DDR3) + /* Find the maximum and minimum supported voltages */ + uint8_t supported_voltages = mem_info->dct_stat[node].DimmSupportedVoltages[slot]; + if (supported_voltages & 0x8) + t->minimum_voltage = 1150; + else if (supported_voltages & 0x4) + t->minimum_voltage = 1250; + else if (supported_voltages & 0x2) + t->minimum_voltage = 1350; + else if (supported_voltages & 0x1) + t->minimum_voltage = 1500; + + if (supported_voltages & 0x1) + t->maximum_voltage = 1500; + else if (supported_voltages & 0x2) + t->maximum_voltage = 1350; + else if (supported_voltages & 0x4) + t->maximum_voltage = 1250; + else if (supported_voltages & 0x8) + t->maximum_voltage = 1150; + + t->configured_voltage = mem_info->dct_stat[node].DimmConfiguredVoltage[slot]; +#endif + } t->memory_error_information_handle = 0xFFFE; /* no error information handle available */ single_len = t->length + smbios_string_table_len(t->eos); len += single_len; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index aaabf9d..ca68900 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -336,6 +336,11 @@ restartinit: goto fatalexit; } +#if IS_ENABLED(DIMM_VOLTAGE_SET_SUPPORT) + printk(BIOS_DEBUG, "mctAutoInitMCT_D: DIMMSetVoltage\n"); + DIMMSetVoltages(pMCTstat, pDCTstatA); /* Set the DIMM voltages (mainboard specific) */ +#endif + printk(BIOS_DEBUG, "mctAutoInitMCT_D: SyncDCTsReady_D\n"); SyncDCTsReady_D(pMCTstat, pDCTstatA); /* Make sure DCTs are ready for accesses.*/ @@ -2128,6 +2133,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->DimmBanks[i] = 1ULL << (((mctRead_SPD(smbaddr, SPD_Density) & 0x70) >> 4) + 3); pDCTstat->DimmWidth[i] = 1ULL << ((mctRead_SPD(smbaddr, SPD_BusWidth) & 0x7) + 3); } + /* Check supported voltage(s) */ + pDCTstat->DimmSupportedVoltages[i] = mctRead_SPD(smbaddr, SPD_Voltage) & 0x7; + pDCTstat->DimmSupportedVoltages[i] ^= 0x1; /* Invert LSB to convert from SPD format to internal bitmap format */ /* Check module type */ byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE) & 0x7; if (byte == JED_RDIMM || byte == JED_MiniRDIMM) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index d403817..146e699 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -202,6 +202,7 @@ #define JED_MiniRDIMM 0x5 /* Mini-RDIMM */ #define SPD_Density 4 /* Bank address bits,SDRAM capacity */ #define SPD_Addressing 5 /* Row/Column address bits */ +#define SPD_Voltage 6 /* Supported voltage bitfield */ #define SPD_Organization 7 /* rank#,Device width */ #define SPD_BusWidth 8 /* ECC, Bus width */ #define JED_ECC 8 /* ECC capability */ @@ -581,6 +582,10 @@ struct DCTStatStruc { /* A per Node structure*/ struct _sDCTStruct s_C_DCTPtr[2]; /* struct _sDCTStruct s_C_DCT1Ptr[8]; */ + /* DIMM supported voltage bitmap ([2:0]: 1.25V, 1.35V, 1.5V) */ + uint8_t DimmSupportedVoltages[MAX_DIMMS_SUPPORTED]; + uint32_t DimmConfiguredVoltage[MAX_DIMMS_SUPPORTED]; /* mV */ + uint8_t DimmRows[MAX_DIMMS_SUPPORTED]; uint8_t DimmCols[MAX_DIMMS_SUPPORTED]; uint8_t DimmRanks[MAX_DIMMS_SUPPORTED]; @@ -901,6 +906,7 @@ u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val); void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct); void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); void mctSMBhub_Init(u32 node); +void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); int mctRead_SPD(u32 smaddr, u32 reg); void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Set DDR3 memory voltage based on SPD data
by Timothy Pearson 02 Nov '15

02 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11956 -gerrit commit 91cfeb0ff4fda4ee0776305288db7bd85700453d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun May 10 04:37:56 2015 -0500 mainboard/asus/kgpe-d16: Set DDR3 memory voltage based on SPD data Change-Id: I21777283ce0fd3c607951204a63ff67dc656c8cc Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/Kconfig | 1 + src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 5 ++ src/mainboard/asus/kgpe-d16/romstage.c | 84 ++++++++++++++++++++++++++++++-- 4 files changed, 86 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index f47e6a1..f5ff81c 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR3 select DIMM_REGISTERED # select QRANK_DIMM_SUPPORT + select DIMM_VOLTAGE_SET_SUPPORT select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_SR5650 select SOUTHBRIDGE_AMD_SB700 diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 38b2ddf..d84c402 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -6,6 +6,7 @@ iommu = Disable nmi = Disable hypertransport_speed_limit = Auto max_mem_clock = DDR3-1600 +minimum_memory_voltage = 1.5V ECC_memory = Enable ECC_redirection = Disable ecc_scrub_rate = 1.28us diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 4120515..c672e09 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -37,6 +37,7 @@ entries 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection 458 4 e 11 hypertransport_speed_limit +462 2 e 12 minimum_memory_voltage 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum @@ -125,6 +126,10 @@ enumerations 11 13 400MHz 11 14 300MHz 11 15 200MHz +12 0 1.5V +12 1 1.35V +12 2 1.25V +12 3 1.15V checksums diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index ddfdc08..e509268 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -131,7 +131,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { */ static void set_ddr3_voltage(uint8_t node, uint8_t index) { uint8_t byte; - uint8_t value; + uint8_t value = 0; if (index == 0) value = 0x0; @@ -157,6 +157,82 @@ static void set_ddr3_voltage(uint8_t node, uint8_t index) { byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd0); byte &= 0x0f; pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd0, byte); + + printk(BIOS_DEBUG, "Node %02d DIMM voltage set to index %02x\n", node, index); +} + +void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA) { + /* This mainboard allows the DIMM voltage to be set per-socket. + * Therefore, for each socket, iterate over all DIMMs to find the + * lowest supported voltage common to all DIMMs on that socket. + */ + uint8_t nvram; + uint8_t dimm; + uint8_t node; + uint8_t socket; + uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */ + uint8_t node_allowed_voltages; + uint32_t set_voltage = 0; + + if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) { + switch (nvram) { + case 2: + allowed_voltages = 0x7; /* Allow 1.25V, 1.35V, and 1.5V */ + break; + case 1: + allowed_voltages = 0x3; /* Allow 1.35V and 1.5V */ + break; + case 0: + default: + allowed_voltages = 0x1; /* Allow 1.5V only */ + break; + } + } + + for (node = 0; node < MAX_NODES_SUPPORTED; node++) { + socket = node / 2; + node_allowed_voltages = allowed_voltages; + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + node; + if (pDCTstat->NodePresent) { + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + if (pDCTstat->DIMMValid & (1 << dimm)) { + node_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; + } + } + } + + if (pDCTstat->NodePresent && (node % 2)) { + /* Set voltages */ + if (node_allowed_voltages & 0x8) { + set_voltage = 1150; + set_ddr3_voltage(socket, 3); + } else if (node_allowed_voltages & 0x4) { + set_voltage = 1250; + set_ddr3_voltage(socket, 2); + } else if (node_allowed_voltages & 0x2) { + set_voltage = 1350; + set_ddr3_voltage(socket, 1); + } else { + set_voltage = 1500; + set_ddr3_voltage(socket, 0); + } + + /* Save final DIMM voltages for SMBIOS use */ + if (pDCTstat->NodePresent) { + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; + } + } + pDCTstat = pDCTstatA + (node - 1); + if (pDCTstat->NodePresent) { + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; + } + } + } + } } static void set_peripheral_control_lines(void) { @@ -351,10 +427,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) die("After soft_reset_x - shouldn't see this message!!!\n"); } - /* Set DDR memory voltage - * FIXME - * This should be set based on the output of the DIMM SPDs - * For now it is locked to 1.5V + /* Set default DDR memory voltage + * This will be overridden later during RAM initialization */ set_lpc_sticky_ctl(1); /* Retain LPC/IMC GPIO configuration during S3 sleep */ if (!s3resume) { /* Avoid supply voltage glitches while the DIMMs are retaining data */

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Patch set updated for coreboot: drivers/pc80: Rework normal / fallback selector code
by Timothy Pearson 02 Nov '15

02 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12289 -gerrit commit 62d320df70ef2aca2a0227e39f229efdff07da43 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Nov 1 02:13:17 2015 -0600 drivers/pc80: Rework normal / fallback selector code Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback path should always be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/pc80/mc146818rtc_early.c | 56 +++++++++++++++++++----------------- src/include/pc80/mc146818rtc.h | 2 ++ src/lib/fallback_boot.c | 25 +++++++++------- 3 files changed, 46 insertions(+), 37 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 421af2f..1de920e 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -41,12 +41,24 @@ static int cmos_chksum_valid(void) #endif } +static inline __attribute__((unused)) int boot_count(uint8_t rtc_byte) +{ + return rtc_byte >> 4; +} -static inline __attribute__((unused)) int last_boot_normal(void) +static inline __attribute__((unused)) uint8_t increment_boot_count(uint8_t rtc_byte) { - unsigned char byte; - byte = cmos_read(RTC_BOOT_BYTE); - return (byte & (1 << 1)); + return rtc_byte + (1 << 4); +} + +static inline __attribute__((unused)) uint8_t boot_use_fallback(uint8_t rtc_byte) +{ + return rtc_byte & ~RTC_BOOT_NORMAL; +} + +static inline __attribute__((unused)) int boot_use_normal(uint8_t rtc_byte) +{ + return rtc_byte & RTC_BOOT_NORMAL; } static inline __attribute__((unused)) int do_normal_boot(void) @@ -54,42 +66,32 @@ static inline __attribute__((unused)) int do_normal_boot(void) unsigned char byte; if (cmos_error() || !cmos_chksum_valid()) { - /* There are no impossible values, no checksums so just - * trust whatever value we have in the the cmos, - * but clear the fallback bit. + /* Invalid CMOS checksum detected! + * Force fallback boot... */ byte = cmos_read(RTC_BOOT_BYTE); - byte &= 0x0c; - byte |= CONFIG_MAX_REBOOT_CNT << 4; + byte &= boot_use_fallback(byte) & 0x0f; + byte |= 0xf << 4; cmos_write(byte, RTC_BOOT_BYTE); } /* The RTC_BOOT_BYTE is now o.k. see where to go. */ byte = cmos_read(RTC_BOOT_BYTE); - if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) - /* Are we in normal mode? */ - if (byte & 1) - byte &= 0x0f; /* yes, clear the boot count */ - - /* Properly set the last boot flag */ - byte &= 0xfc; - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte |= (1<<1); - } - - /* Are we already at the max count? */ - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte += 1 << 4; /* No, add 1 to the count */ - } - else { - byte &= 0xfc; /* Yes, put in fallback mode */ + /* Are we attempting to boot normally? */ + if (byte & RTC_BOOT_NORMAL) { + /* Are we already at the max count? */ + if (boot_count(byte) < CONFIG_MAX_REBOOT_CNT) + byte = increment_boot_count(byte); + else + byte = boot_use_fallback(byte); } /* Save the boot byte */ cmos_write(byte, RTC_BOOT_BYTE); - return (byte & (1<<1)); + /* Return selected code path for this boot attempt */ + return (byte & RTC_BOOT_NORMAL); } unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 0e15273..38f2ad0 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -25,6 +25,8 @@ **********************************************************************/ #define RTC_FREQ_SELECT RTC_REG_A +#define RTC_BOOT_NORMAL 0x1 + /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, * totaling to a max high interval of 2.228 ms. diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index 74572df..b1b37a7 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -8,23 +8,28 @@ static void set_boot_successful(void) { - /* Remember I successfully booted by setting - * the initial boot direction - * to the direction that I booted. - */ - unsigned char index, byte; + uint8_t index, byte; + index = inb(RTC_PORT(0)) & 0x80; index |= RTC_BOOT_BYTE; outb(index, RTC_PORT(0)); byte = inb(RTC_PORT(1)); - byte &= 0xfe; - byte |= (byte & (1 << 1)) >> 1; - /* If we are in normal mode set the boot count to 0 */ - if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) - if(byte & 1) + if (IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) { + /* Set the fallback boot bit to allow for recovery if + * the payload fails to boot. + * It is the responsibility of the payload to reset + * the normal boot bit to 1 if desired + */ + byte &= ~RTC_BOOT_NORMAL; + } else { + /* If we are in normal mode set the boot count to 0 */ + if(byte & RTC_BOOT_NORMAL) byte &= 0x0f; + + } + outb(byte, RTC_PORT(1)); } #else

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Patch set updated for coreboot: drivers/pc80: Rework normal / fallback selector code
by Timothy Pearson 02 Nov '15

02 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12289 -gerrit commit 97beeedf265bca4088c9ac9a598085c637560900 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Nov 1 02:13:17 2015 -0600 drivers/pc80: Rework normal / fallback selector code Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback path should always be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/pc80/mc146818rtc_early.c | 49 +++++++++++++++++++++--------------- src/lib/fallback_boot.c | 25 ++++++++---------- 2 files changed, 40 insertions(+), 34 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 421af2f..2eb4a15 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -12,6 +12,8 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif +#define RTC_BOOT_NORMAL 0x1 + static int cmos_error(void) { unsigned char reg_d; @@ -41,12 +43,28 @@ static int cmos_chksum_valid(void) #endif } +static inline __attribute__((unused)) int boot_count(void) +{ + unsigned char byte; + byte = cmos_read(RTC_BOOT_BYTE); + return byte >> 4; +} + +static inline __attribute__((unused)) uint8_t increment_boot_count(uint8_t rtc_byte) +{ + return rtc_byte + (1 << 4); +} + +static inline __attribute__((unused)) uint8_t boot_use_fallback(uint8_t rtc_byte) +{ + return rtc_byte & ~RTC_BOOT_NORMAL; +} static inline __attribute__((unused)) int last_boot_normal(void) { unsigned char byte; byte = cmos_read(RTC_BOOT_BYTE); - return (byte & (1 << 1)); + return (byte & RTC_BOOT_NORMAL); } static inline __attribute__((unused)) int do_normal_boot(void) @@ -59,7 +77,7 @@ static inline __attribute__((unused)) int do_normal_boot(void) * but clear the fallback bit. */ byte = cmos_read(RTC_BOOT_BYTE); - byte &= 0x0c; + byte &= RTC_BOOT_NORMAL; byte |= CONFIG_MAX_REBOOT_CNT << 4; cmos_write(byte, RTC_BOOT_BYTE); } @@ -67,29 +85,20 @@ static inline __attribute__((unused)) int do_normal_boot(void) /* The RTC_BOOT_BYTE is now o.k. see where to go. */ byte = cmos_read(RTC_BOOT_BYTE); - if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) - /* Are we in normal mode? */ - if (byte & 1) - byte &= 0x0f; /* yes, clear the boot count */ - - /* Properly set the last boot flag */ - byte &= 0xfc; - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte |= (1<<1); - } - - /* Are we already at the max count? */ - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte += 1 << 4; /* No, add 1 to the count */ - } - else { - byte &= 0xfc; /* Yes, put in fallback mode */ + /* Are we attempting to boot normally? */ + if (byte & RTC_BOOT_NORMAL) { + /* Are we already at the max count? */ + if (boot_count() < CONFIG_MAX_REBOOT_CNT) + byte = increment_boot_count(byte); + else + byte = boot_use_fallback(byte); } /* Save the boot byte */ cmos_write(byte, RTC_BOOT_BYTE); - return (byte & (1<<1)); + /* Return selected code path for this boot attempt */ + return (byte & RTC_BOOT_NORMAL); } unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c index 74572df..5f1d078 100644 --- a/src/lib/fallback_boot.c +++ b/src/lib/fallback_boot.c @@ -8,24 +8,21 @@ static void set_boot_successful(void) { - /* Remember I successfully booted by setting - * the initial boot direction - * to the direction that I booted. - */ - unsigned char index, byte; - index = inb(RTC_PORT(0)) & 0x80; - index |= RTC_BOOT_BYTE; - outb(index, RTC_PORT(0)); - - byte = inb(RTC_PORT(1)); - byte &= 0xfe; - byte |= (byte & (1 << 1)) >> 1; + uint8_t index, byte; /* If we are in normal mode set the boot count to 0 */ - if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) + if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) { + index = inb(RTC_PORT(0)) & 0x80; + index |= RTC_BOOT_BYTE; + outb(index, RTC_PORT(0)); + + byte = inb(RTC_PORT(1)); + if(byte & 1) byte &= 0x0f; - outb(byte, RTC_PORT(1)); + + outb(byte, RTC_PORT(1)); + } } #else static void set_boot_successful(void)

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Patch set updated for coreboot: drivers/pc80: Rework normal / fallback selector code
by Timothy Pearson 02 Nov '15

02 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12289 -gerrit commit 960caf3775e1eb2da79260cdab65be667a6ccf0b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Nov 1 02:13:17 2015 -0600 drivers/pc80: Rework normal / fallback selector code Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback path should always be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/pc80/mc146818rtc_early.c | 49 +++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 421af2f..2eb4a15 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -12,6 +12,8 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif +#define RTC_BOOT_NORMAL 0x1 + static int cmos_error(void) { unsigned char reg_d; @@ -41,12 +43,28 @@ static int cmos_chksum_valid(void) #endif } +static inline __attribute__((unused)) int boot_count(void) +{ + unsigned char byte; + byte = cmos_read(RTC_BOOT_BYTE); + return byte >> 4; +} + +static inline __attribute__((unused)) uint8_t increment_boot_count(uint8_t rtc_byte) +{ + return rtc_byte + (1 << 4); +} + +static inline __attribute__((unused)) uint8_t boot_use_fallback(uint8_t rtc_byte) +{ + return rtc_byte & ~RTC_BOOT_NORMAL; +} static inline __attribute__((unused)) int last_boot_normal(void) { unsigned char byte; byte = cmos_read(RTC_BOOT_BYTE); - return (byte & (1 << 1)); + return (byte & RTC_BOOT_NORMAL); } static inline __attribute__((unused)) int do_normal_boot(void) @@ -59,7 +77,7 @@ static inline __attribute__((unused)) int do_normal_boot(void) * but clear the fallback bit. */ byte = cmos_read(RTC_BOOT_BYTE); - byte &= 0x0c; + byte &= RTC_BOOT_NORMAL; byte |= CONFIG_MAX_REBOOT_CNT << 4; cmos_write(byte, RTC_BOOT_BYTE); } @@ -67,29 +85,20 @@ static inline __attribute__((unused)) int do_normal_boot(void) /* The RTC_BOOT_BYTE is now o.k. see where to go. */ byte = cmos_read(RTC_BOOT_BYTE); - if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) - /* Are we in normal mode? */ - if (byte & 1) - byte &= 0x0f; /* yes, clear the boot count */ - - /* Properly set the last boot flag */ - byte &= 0xfc; - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte |= (1<<1); - } - - /* Are we already at the max count? */ - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte += 1 << 4; /* No, add 1 to the count */ - } - else { - byte &= 0xfc; /* Yes, put in fallback mode */ + /* Are we attempting to boot normally? */ + if (byte & RTC_BOOT_NORMAL) { + /* Are we already at the max count? */ + if (boot_count() < CONFIG_MAX_REBOOT_CNT) + byte = increment_boot_count(byte); + else + byte = boot_use_fallback(byte); } /* Save the boot byte */ cmos_write(byte, RTC_BOOT_BYTE); - return (byte & (1<<1)); + /* Return selected code path for this boot attempt */ + return (byte & RTC_BOOT_NORMAL); } unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)

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Patch set updated for coreboot: drivers/pc80: Rework normal / fallback selector code
by Timothy Pearson 02 Nov '15

02 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12289 -gerrit commit 32cbe28e4e5e2ffc8b913d5a423ef35954f4bf58 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Nov 1 02:13:17 2015 -0600 drivers/pc80: Rework normal / fallback selector code Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback path should always be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/pc80/mc146818rtc_early.c | 50 +++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 20 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 421af2f..1bc641e 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -12,6 +12,8 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif +#define RTC_BOOT_NORMAL 0x1 + static int cmos_error(void) { unsigned char reg_d; @@ -41,12 +43,28 @@ static int cmos_chksum_valid(void) #endif } +static inline __attribute__((unused)) int boot_count(void) +{ + unsigned char byte; + byte = cmos_read(RTC_BOOT_BYTE); + return byte >> 4; +} + +static inline __attribute__((unused)) void increment_boot_count(uint8_t &rtc_byte) +{ + rtc_byte += (1 << 4); +} + +static inline __attribute__((unused)) void boot_use_fallback(uint8_t &rtc_byte) +{ + rtc_byte &= ~RTC_BOOT_NORMAL; +} static inline __attribute__((unused)) int last_boot_normal(void) { unsigned char byte; byte = cmos_read(RTC_BOOT_BYTE); - return (byte & (1 << 1)); + return (byte & RTC_BOOT_NORMAL); } static inline __attribute__((unused)) int do_normal_boot(void) @@ -59,7 +77,7 @@ static inline __attribute__((unused)) int do_normal_boot(void) * but clear the fallback bit. */ byte = cmos_read(RTC_BOOT_BYTE); - byte &= 0x0c; + byte &= RTC_BOOT_NORMAL; byte |= CONFIG_MAX_REBOOT_CNT << 4; cmos_write(byte, RTC_BOOT_BYTE); } @@ -67,29 +85,21 @@ static inline __attribute__((unused)) int do_normal_boot(void) /* The RTC_BOOT_BYTE is now o.k. see where to go. */ byte = cmos_read(RTC_BOOT_BYTE); - if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) - /* Are we in normal mode? */ - if (byte & 1) - byte &= 0x0f; /* yes, clear the boot count */ - - /* Properly set the last boot flag */ - byte &= 0xfc; - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte |= (1<<1); - } - - /* Are we already at the max count? */ - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte += 1 << 4; /* No, add 1 to the count */ - } - else { - byte &= 0xfc; /* Yes, put in fallback mode */ + /* Are we attempting to boot normally? */ + if (byte & RTC_BOOT_NORMAL) { + /* Are we already at the max count? */ + if (boot_count() < CONFIG_MAX_REBOOT_CNT) { + increment_boot_count(byte) + } else { + boot_use_fallback(byte); + } } /* Save the boot byte */ cmos_write(byte, RTC_BOOT_BYTE); - return (byte & (1<<1)); + /* Return selected code path for this boot attempt */ + return (byte & RTC_BOOT_NORMAL); } unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)

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Patch set updated for coreboot: drivers/pc80: Rework normal / fallback selector code
by Timothy Pearson 02 Nov '15

02 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12289 -gerrit commit 3bfed20f15080a3689e4b6e1621f72783fc7ff89 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Nov 1 02:13:17 2015 -0600 drivers/pc80: Rework normal / fallback selector code Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback patch should be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/pc80/mc146818rtc_early.c | 50 +++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 20 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 421af2f..1bc641e 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -12,6 +12,8 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif +#define RTC_BOOT_NORMAL 0x1 + static int cmos_error(void) { unsigned char reg_d; @@ -41,12 +43,28 @@ static int cmos_chksum_valid(void) #endif } +static inline __attribute__((unused)) int boot_count(void) +{ + unsigned char byte; + byte = cmos_read(RTC_BOOT_BYTE); + return byte >> 4; +} + +static inline __attribute__((unused)) void increment_boot_count(uint8_t &rtc_byte) +{ + rtc_byte += (1 << 4); +} + +static inline __attribute__((unused)) void boot_use_fallback(uint8_t &rtc_byte) +{ + rtc_byte &= ~RTC_BOOT_NORMAL; +} static inline __attribute__((unused)) int last_boot_normal(void) { unsigned char byte; byte = cmos_read(RTC_BOOT_BYTE); - return (byte & (1 << 1)); + return (byte & RTC_BOOT_NORMAL); } static inline __attribute__((unused)) int do_normal_boot(void) @@ -59,7 +77,7 @@ static inline __attribute__((unused)) int do_normal_boot(void) * but clear the fallback bit. */ byte = cmos_read(RTC_BOOT_BYTE); - byte &= 0x0c; + byte &= RTC_BOOT_NORMAL; byte |= CONFIG_MAX_REBOOT_CNT << 4; cmos_write(byte, RTC_BOOT_BYTE); } @@ -67,29 +85,21 @@ static inline __attribute__((unused)) int do_normal_boot(void) /* The RTC_BOOT_BYTE is now o.k. see where to go. */ byte = cmos_read(RTC_BOOT_BYTE); - if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) - /* Are we in normal mode? */ - if (byte & 1) - byte &= 0x0f; /* yes, clear the boot count */ - - /* Properly set the last boot flag */ - byte &= 0xfc; - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte |= (1<<1); - } - - /* Are we already at the max count? */ - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte += 1 << 4; /* No, add 1 to the count */ - } - else { - byte &= 0xfc; /* Yes, put in fallback mode */ + /* Are we attempting to boot normally? */ + if (byte & RTC_BOOT_NORMAL) { + /* Are we already at the max count? */ + if (boot_count() < CONFIG_MAX_REBOOT_CNT) { + increment_boot_count(byte) + } else { + boot_use_fallback(byte); + } } /* Save the boot byte */ cmos_write(byte, RTC_BOOT_BYTE); - return (byte & (1<<1)); + /* Return selected code path for this boot attempt */ + return (byte & RTC_BOOT_NORMAL); } unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)

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Patch set updated for coreboot: nb/intel/sandybridge/northbridge: Initialize uma_memory_base in all cases
by Patrick Rudolph 02 Nov '15

02 Nov '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11918 -gerrit commit 10cc3f8111bcc7b7a747e67f5d634eec03250de2 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Oct 15 15:33:25 2015 +0200 nb/intel/sandybridge/northbridge: Initialize uma_memory_base in all cases Issue observed: Coreboot stops at: "Not enough MTRRs available!" Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * ATI Radeon HD4780 Problem description: In case the IGD does not claim VGA decode, the code path taken results in an integer overflow as uma_memory_base isn't initialized. The MTRR assignment will fail, because of invalid memory regions. Problem solution: Properly initialize uma_memory_base to prevent possible integer overflow. Final testing results: The system boots again with IGD not claiming VGA decode. Change-Id: I025be23b1defb6155469a3eee66569e49a695e7f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/northbridge.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 76f03f3..5c1f366 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -189,6 +189,7 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); + uma_memory_base = tolud; tomk = tolud >> 10; if (me_base == tolud) { /* ME is from MEBASE-TOM */

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Patch set updated for coreboot: [NEEDS TEST] nb/intel/sandybridge: start PEG link training
by Patrick Rudolph 02 Nov '15

02 Nov '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11917 -gerrit commit aa5a4dbf869a264089f4a72172c8b154d3c859ec Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Oct 15 11:09:15 2015 +0200 [NEEDS TEST] nb/intel/sandybridge: start PEG link training Issue observed: The PCIe Root port shows up in GNU/Linux but no device. Test system: * Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130) * Lenovo T530 (Intel Core i5-3320M CPU) Problem description: The PEG Root port link training on Ivy Bridge needs to be started by hand. (The PEG Root port on Sandy Bridge works out of the box.) Problem solution: The bits are set in early_init to meet PCIe reset timeout of 100msec. The bits should be set in PCI device enable function, but this causes the PCI enumeration to not detect the card, as it's still booting. Adding a fixed delay of 100msec resolves this problem, but this would increase boot time. Tested with: * Nvidia NVS 5400M (PCIe2) * ATI Radeon HD4780 (PCIe2) * Nvidia GeForce 8600 GT (PCIe1) Untested: * PCIe3 devices Final test results: The PEG device shows up under GNU/Linux and can be used without issues. Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/early_init.c | 42 ++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b3a829d..7e5ace6 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -148,6 +148,39 @@ static void sandybridge_setup_graphics(void) MCHBAR32(0x5418) = reg32; } +static void start_peg_link_training(void) +{ + u32 tmp; + u32 deven; + + /* skip on SandyBridge */ + if ((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) & + BASE_REV_MASK) != BASE_REV_IVB) + return; + + deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + + if (deven & DEVEN_PEG10) { + tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG11) { + tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG12) { + tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG60) { + tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5)); + } +} + void sandybridge_early_initialization(int chipset_type) { u32 capid0_a; @@ -174,6 +207,15 @@ void sandybridge_early_initialization(int chipset_type) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); sandybridge_setup_graphics(); + + /* Write magic value to start PEG link training. + * This should be done in PCI device enumeration, but + * the PCIe specification requires to wait at least 100msec + * after reset for devices to come up. + * As we don't want to increase boot time, enable it early and + * assume the PEG is up as soon as PCI enumeration starts. + * TODO: use time stamps to ensure the timings are met */ + start_peg_link_training(); } void northbridge_romstage_finalize(int s3resume)

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coreboot-gerrit November 2015