coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: asrock/e350m1: Add ACPI S3 support
by gerrit＠coreboot.org 02 Nov '15

02 Nov '15

the following patch was just integrated into master: commit 688257409330b9d12455c6997b0f57f128cd207b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 27 14:31:18 2015 +0200 asrock/e350m1: Add ACPI S3 support To store memory configuration in SPI flash currently adds some 150 ms delay in ramstage, visible in timestamps listing at 75:cbmem post. Change-Id: I1160259054b58e9a8df2a105c730e0f4140be1f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12215 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12215 for details. -gerrit

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Patch merged into coreboot/master: asrock/e350m1: Match super-io GPIO configuration with vendor
by gerrit＠coreboot.org 02 Nov '15

02 Nov '15

the following patch was just integrated into master: commit d28474b46d69e683e26443f295ae4a626d7c3b38 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Oct 28 11:08:24 2015 +0200 asrock/e350m1: Match super-io GPIO configuration with vendor Disables mouse ps2 data/clock signals, not connected in hardware. Purpose of other GPIOs is not really known, but match them with superiotool dump taken from vendor bios. Change-Id: I7b549fbd7dd3fa4cbd507d76882b60bc324a4bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12214 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12214 for details. -gerrit

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Patch merged into coreboot/master: superio/nuvoton/nct5572d: Add missing logical devices
by gerrit＠coreboot.org 02 Nov '15

02 Nov '15

the following patch was just integrated into master: commit 3b01cf17d28d895ed2eed52213ed2f590f976567 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 27 18:00:57 2015 +0200 superio/nuvoton/nct5572d: Add missing logical devices While the actual pins behind these devices are not exposed on the chip, the enable registers are implemented in hardware. Allow to turn these LDNs off, like the vendor bios for asrock/e350m1 does. Change-Id: I4d6d5a8de12b09095138cacbad62b2dfbbe54028 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/12213 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See http://review.coreboot.org/12213 for details. -gerrit

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Patch merged into coreboot/master: mainboard/asus/kfsn4-dre_k8: Fix ramstage using Family 10h structs
by gerrit＠coreboot.org 02 Nov '15

02 Nov '15

the following patch was just integrated into master: commit 70460249fd9b4c35d4f844aa6491e7f6def31c42 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Nov 1 02:41:39 2015 -0600 mainboard/asus/kfsn4-dre_k8: Fix ramstage using Family 10h structs Several ramstage files were inadvertently using Family 10h-specfic structures, causing unstable operation. Use the K8-specific structures instead. Change-Id: I64066dfdca83557393499b77726051e25b814381 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12290 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12290 for details. -gerrit

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Patch set updated for coreboot: drivers/pc80: Ensure recovery mode always boots fallback image
by Timothy Pearson 02 Nov '15

02 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12289 -gerrit commit bc4a9f009d121e8baa87f70a01aef23b37bc38d9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Nov 1 02:13:17 2015 -0600 drivers/pc80: Ensure recovery mode always boots fallback image The current fallback / failed boot count checks only look at the value of last_boot when determining whether to execute the normal or fallback image. Furthermore, the normal boot bit is unconditionally set if the failed boot count has not exceeded its threshold, thereby overriding a request from the user to boot into fallback mode if the user does not also set the failed boot count above the failure threshold. Only check the failed boot count if the normal boot bit is set in nvram. NOTE: The existing code did not function as intended when used with recovery jumpers or nvramtool. Even when the user set a recovery jumper or used nvramtool to set the next boot attempt to Fallback, the bootblock would execute the normal code if the failed boot count was below threshold. The only way to recover from this situation was to forcibly power off and on the board repeatedly until the failed boot count rose high enough, or to directly reflash the ROM. Note that clearing the CMOS actually had the opposite effect from what was intended, as it reset the failed boot count and set the normal boot bit. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/pc80/mc146818rtc_early.c | 51 +++++++++++++++++++++++++----------- 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 421af2f..6efb2e8 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -12,6 +12,9 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif +#define RTC_BOOT_TRY_NORMAL 0x1 +#define RTC_BOOT_LAST_WAS_NORMAL_AND_REACHED_PAYLOAD 0x2 + static int cmos_error(void) { unsigned char reg_d; @@ -67,29 +70,47 @@ static inline __attribute__((unused)) int do_normal_boot(void) /* The RTC_BOOT_BYTE is now o.k. see where to go. */ byte = cmos_read(RTC_BOOT_BYTE); + /* If booting past the bootblock is all that is required + * to reset the failed boot checks, then clear the boot + * count. This code must execute before any of the boot + * count checks below to function correctly. + */ if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) - /* Are we in normal mode? */ - if (byte & 1) + /* Are we attempting to boot normally? */ + if (byte & RTC_BOOT_TRY_NORMAL) byte &= 0x0f; /* yes, clear the boot count */ - /* Properly set the last boot flag */ - byte &= 0xfc; - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte |= (1<<1); - } - - /* Are we already at the max count? */ - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte += 1 << 4; /* No, add 1 to the count */ - } - else { - byte &= 0xfc; /* Yes, put in fallback mode */ + /* Are we attempting to boot normally? */ + if (byte & RTC_BOOT_TRY_NORMAL) { + /* Properly set the last boot flag */ + byte &= 0xfc; + if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { + byte |= RTC_BOOT_LAST_WAS_NORMAL_AND_REACHED_PAYLOAD; + } + + /* Are we already at the max count? */ + if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { + byte += 1 << 4; /* No, add 1 to the count */ + } + else { + byte &= 0xfc; /* Yes, put in fallback mode */ + } } /* Save the boot byte */ cmos_write(byte, RTC_BOOT_BYTE); - return (byte & (1<<1)); + /* Return selected code path for this boot attempt + * If a boot path was selected and we successfully reach + * the payload, the last boot state bit will indicate + * which code path was taken. + * + * In other words, RTC_BOOT_LAST_WAS_NORMAL_AND_REACHED_PAYLOAD + * has final and absolute say on which code path to take. + * RTC_BOOT_TRY_NORMAL is only a request to try normal boot if + * possible (i.e. the payload can be reached via normal boot). + */ + return (byte & RTC_BOOT_LAST_WAS_NORMAL_AND_REACHED_PAYLOAD); } unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)

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New patch to review for coreboot: Needs Testing: VGA and GM45 textmode fixes
by Nicky Sielicki 02 Nov '15

02 Nov '15

Nicky Sielicki (me(a)nicky.io) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12293 -gerrit commit def06e20d4e940f302a22028c30b6390ecf75b90 Author: Nicky Sielicki <me(a)nicky.io> Date: Sun Nov 1 16:51:19 2015 -0600 Needs Testing: VGA and GM45 textmode fixes See thread here: http://www.coreboot.org/pipermail/coreboot/2015-October/080523.html VGA Documentation here: http://www.osdever.net/FreeVGA/vga/vga.htm#register Changes in src/drivers/pc80/vga/vga.c: * Ensure CR lock bit isn't set before vga_textmode_init() and vga_set_mode() in src/northbridge/intel/gm45/gma.c * Ensure screen disable sequencer register is unset after textmode init * use sizeof() when looping over u8 cr registers. I'm unsure this would fix GM45 textmode graphics, but it's at least a start. Change-Id: Iae3d393ed4f39164c486672b08deb6187fd269ca Signed-off-by: Nicky Sielicki <me(a)nicky.io> --- src/drivers/pc80/vga/vga.c | 8 ++++++++ src/northbridge/intel/gm45/gma.c | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/drivers/pc80/vga/vga.c b/src/drivers/pc80/vga/vga.c index 740910c..e10b5b4 100644 --- a/src/drivers/pc80/vga/vga.c +++ b/src/drivers/pc80/vga/vga.c @@ -106,6 +106,10 @@ vga_mode_set(int hdisplay, int hblankstart, int hsyncstart, int hsyncend, int vsyncstart, int vsyncend, int vblankend, int vtotal, int stride) { + /* ensure everything is unlocked. + * That's a 0 in the 7th bit of cr 0x11 */ + vga_cr_write(0x11, vga_cr_read(0x11) & (~(0x1 << 7))); + /* htotal: 2080 */ htotal /= 8; htotal -= 5; @@ -291,6 +295,10 @@ vga_line_write(unsigned int line, const char *string) void vga_textmode_init(void) { + /* ensure everything is unlocked. + * That's a 0 in the 7th bit of cr 0x11 */ + vga_cr_write(0x11, vga_cr_read(0x11) & (~(0x1 << 7))); + vga_sr_write(0x00, 0x01); /* clear reset */ vga_sr_write(0x01, 0x00); diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8c97143..084094a 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -144,7 +144,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, }; vga_cr_write(0x11, 0); - for (i = 0; i <= 0x18; i++) + for (i = 0; i < sizeof(cr)/sizeof(u8); i++) vga_cr_write(i, cr[i]); power_port(mmio); @@ -198,6 +198,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); #else vga_textmode_init(); + vga_sr_write(1, vga_sr_read(1) & ~0x20); // Enable screen. #endif /* Find suitable divisors. */

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Patch set updated for coreboot: drivers/pc80: Ensure recovery mode always boots fallback image
by Timothy Pearson 01 Nov '15

01 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12289 -gerrit commit 6bdeb5a35312b3cad4633481f557c8bc1a40d766 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Nov 1 02:13:17 2015 -0600 drivers/pc80: Ensure recovery mode always boots fallback image The current fallback / failed boot count checks only look at the value of last_boot when determining whether to execute the normal or fallback image. Furthermore, the normal boot bit is unconditionally set if the failed boot count has not exceeded its threshold, thereby overriding a request from the user to boot into fallback mode if the user does not also set the failed boot count above the failure threshold. Only check the failed boot count if the normal boot bit is set in nvram. NOTE: The existing code was very badly broken. Even when the user set a recovery jumper (or used nvramtool to set the next boot attempt to Fallback), the bootblock would execute the normal code if the failed boot count was below threshold. The only way to recover from this situation was to forcibly power off and on the board repeatedly until the failed boot count rose high enough, or to directly reflash the ROM. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/pc80/mc146818rtc_early.c | 51 +++++++++++++++++++++++++----------- 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 421af2f..6efb2e8 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -12,6 +12,9 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif +#define RTC_BOOT_TRY_NORMAL 0x1 +#define RTC_BOOT_LAST_WAS_NORMAL_AND_REACHED_PAYLOAD 0x2 + static int cmos_error(void) { unsigned char reg_d; @@ -67,29 +70,47 @@ static inline __attribute__((unused)) int do_normal_boot(void) /* The RTC_BOOT_BYTE is now o.k. see where to go. */ byte = cmos_read(RTC_BOOT_BYTE); + /* If booting past the bootblock is all that is required + * to reset the failed boot checks, then clear the boot + * count. This code must execute before any of the boot + * count checks below to function correctly. + */ if (!IS_ENABLED(CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR)) - /* Are we in normal mode? */ - if (byte & 1) + /* Are we attempting to boot normally? */ + if (byte & RTC_BOOT_TRY_NORMAL) byte &= 0x0f; /* yes, clear the boot count */ - /* Properly set the last boot flag */ - byte &= 0xfc; - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte |= (1<<1); - } - - /* Are we already at the max count? */ - if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { - byte += 1 << 4; /* No, add 1 to the count */ - } - else { - byte &= 0xfc; /* Yes, put in fallback mode */ + /* Are we attempting to boot normally? */ + if (byte & RTC_BOOT_TRY_NORMAL) { + /* Properly set the last boot flag */ + byte &= 0xfc; + if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { + byte |= RTC_BOOT_LAST_WAS_NORMAL_AND_REACHED_PAYLOAD; + } + + /* Are we already at the max count? */ + if ((byte >> 4) < CONFIG_MAX_REBOOT_CNT) { + byte += 1 << 4; /* No, add 1 to the count */ + } + else { + byte &= 0xfc; /* Yes, put in fallback mode */ + } } /* Save the boot byte */ cmos_write(byte, RTC_BOOT_BYTE); - return (byte & (1<<1)); + /* Return selected code path for this boot attempt + * If a boot path was selected and we successfully reach + * the payload, the last boot state bit will indicate + * which code path was taken. + * + * In other words, RTC_BOOT_LAST_WAS_NORMAL_AND_REACHED_PAYLOAD + * has final and absolute say on which code path to take. + * RTC_BOOT_TRY_NORMAL is only a request to try normal boot if + * possible (i.e. the payload can be reached via normal boot). + */ + return (byte & RTC_BOOT_LAST_WAS_NORMAL_AND_REACHED_PAYLOAD); } unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)

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Patch merged into coreboot/master: abuild: allow specifying multiple targets by mainboard descriptor
by gerrit＠coreboot.org 01 Nov '15

01 Nov '15

the following patch was just integrated into master: commit f6dc5443185ea07fd305426a67a1b0aa57003d96 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Oct 31 09:13:26 2015 +0100 abuild: allow specifying multiple targets by mainboard descriptor abuild -t EMULATION_QEMU_UCB_RISCV,EMULATION_SPIKE_UCB_RISCV works now Change-Id: I49d8cd86e21ede724d8daa441b728efa1f6ea1fa Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12281 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12281 for details. -gerrit

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Patch merged into coreboot/master: abuild: Don't keep around old junit reports
by gerrit＠coreboot.org 01 Nov '15

01 Nov '15

the following patch was just integrated into master: commit 5ab5a39d2ed0ea28347218ad5e129a7c8244012c Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Oct 31 08:53:30 2015 +0100 abuild: Don't keep around old junit reports junit reports were kept around (and appended to) in some cases, leading to duplicate reports on jenkins. Drop old per-mainboard reports before building said boards, and do the same for the tools (reported thrice). Change-Id: I74a035587bbf917dca85ba6fc74621c583efe9a2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12280 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12280 for details. -gerrit

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Patch merged into coreboot/master: abuild: allow users to specify multiple boards
by gerrit＠coreboot.org 01 Nov '15

01 Nov '15

the following patch was just integrated into master: commit 0c65dccd3f2d2443459fc00d63f096a94cba2d13 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Oct 31 00:42:50 2015 +0100 abuild: allow users to specify multiple boards Specifying a directory with multiple boards (eg abuild -t google/veyron) makes abuild run through all of them. Change-Id: Ifb60f3a1f0c4a727dc43c48671ea90711ffe5585 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12278 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12278 for details. -gerrit

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coreboot-gerrit November 2015