coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: abuild: change board identifier to a variant of CONFIG_BOARD_*
by gerrit＠coreboot.org 01 Nov '15

01 Nov '15

the following patch was just integrated into master: commit c2050f014d3d9d53766f99849881da4895eceb7c Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Oct 31 00:35:44 2015 +0100 abuild: change board identifier to a variant of CONFIG_BOARD_* Since we now have multiple boards in a single mainboard directory (eg google/veyron), we need some other identifier from which to create output directories and filenames in abuild than the directory name. Use the wildcard part of CONFIG_BOARD_* instead. This changes the semantics of payload.sh handling: it's passed the single new identifier instead of two arguments "vendor" and "board" that constitute the mainboard directory's path. Change-Id: I0dc59c6a1ad1ee51d393fa06b98944a6da342cdf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12277 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12277 for details. -gerrit

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Patch merged into coreboot/master: abuild: change compile_target interface
by gerrit＠coreboot.org 01 Nov '15

01 Nov '15

the following patch was just integrated into master: commit df7cee23c8695ff2a96fe897ebf70c41bda18aa3 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Oct 30 23:49:32 2015 +0100 abuild: change compile_target interface It only takes a single argument now, which is the directory below the coreboot-builds directory. Preparation for future work. The only visible change is in console output. Change-Id: I4b0fe268ccfb69a0403fa5f8b23444c07843386f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12276 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12276 for details. -gerrit

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Patch merged into coreboot/master: abuild: change remove_board interface
by gerrit＠coreboot.org 01 Nov '15

01 Nov '15

the following patch was just integrated into master: commit 35261c0d476eff250a695e97be8cd8ceb406a7d3 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Oct 30 23:25:23 2015 +0100 abuild: change remove_board interface It's passed the mainboard's directory name (below $TARGET) directly in preparation of more rework in that area. Change-Id: I3a82b8673fdea07bc5c957f76f4685c34a805334 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12275 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12275 for details. -gerrit

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Patch merged into coreboot/master: abuild: remove ancient, unused test submission feature
by gerrit＠coreboot.org 01 Nov '15

01 Nov '15

the following patch was just integrated into master: commit 85f4b3c9b3c0ad41c1fc7ca708517b76ef43405b Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Oct 30 23:05:56 2015 +0100 abuild: remove ancient, unused test submission feature Its hardcoded HTTP endpoint is gone since 2007. Change-Id: Ib76814d31b571456d950d45f45912036b6fa82d1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12274 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12274 for details. -gerrit

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Patch merged into coreboot/master: abuild: drop the ability to specify a configuration
by gerrit＠coreboot.org 01 Nov '15

01 Nov '15

the following patch was just integrated into master: commit e6adabdf3a798b0dde19ae739a89662e244de65c Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Oct 30 22:59:30 2015 +0100 abuild: drop the ability to specify a configuration If you already have a configuration, there's no need to run it through abuild. Change-Id: I4dde9a7b96bb0c08ec5c91426a4dd3aa15e74edf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12273 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12273 for details. -gerrit

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New patch to review for coreboot: board-status: Reorder the table categories
by Patrick Georgi 01 Nov '15

01 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12292 -gerrit commit 00f24849cb5627de23fa8ffb1d2d94aa9dc141f3 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sun Nov 1 14:20:15 2015 +0100 board-status: Reorder the table categories Show laptops and servers before desktop boards since that's where both the market and coreboot are the most active these days. Change-Id: I7de63975f3f2ff5e983b19e07558175a58870a1b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/board_status/to-wiki/towiki.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index c1d2394..e46d606 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -58,7 +58,7 @@ cat <<EOF ! align="left" | <span title="Vendor Cooperation Score">VCS<sup>5</sup></span> EOF -for category in desktop server laptop half mini settop "eval" sbc emulation misc unclass; do +for category in laptop server desktop half mini settop "eval" sbc emulation misc unclass; do last_vendor= color=eeeeee case "$category" in

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New patch to review for coreboot: board-status: Update the foreword
by Patrick Georgi 01 Nov '15

01 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12291 -gerrit commit d1a852785c3091531e60d9f9041ce472c3087ffd Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sun Nov 1 14:18:30 2015 +0100 board-status: Update the foreword There's the sentiment that the Supported_Motherboards wiki page is outdated. Point out that the list is current (and drop the table of contents that became a distraction). Change-Id: Ib2363fad0b7f6951b07b2ad0c85148d9bc729b55 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/board_status/to-wiki/foreword.wiki | 45 ++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/util/board_status/to-wiki/foreword.wiki b/util/board_status/to-wiki/foreword.wiki index 925646f..5b1875c 100644 --- a/util/board_status/to-wiki/foreword.wiki +++ b/util/board_status/to-wiki/foreword.wiki @@ -1,28 +1,39 @@ +__NOTOC__ This page was automatically generated. Please do not edit, any edits will be overwritten by an automatic utility. -= coreboot status by mainboard = += Mainboards supported by coreboot = -* This list contains reports of successful coreboot execution, ordered by date. It's shows which boards can actually run with current coreboot versions. +This page shows two representations of the same data: -* Using the precise commit id and config.txt, it's possible to reproduce working coreboot builds (assuming no compiler bugs). +First a list of all mainboards supported by coreboot (current within +one hour) ordered by category. For each mainboard the table shows the +latest user-contributed report of a successful boot on the device. -* By sorting it by date, we encourage developers and users to keep ports current and well-tested. +After that, the page provides a time-ordered list of these contributed +reports, with the newest report first. -* Status data comes from the [http://review.coreboot.org/gitweb?p=board-status.git board status repository]. +Boards without such reports may boot or there may be some maintenance +required. The reports contain the coreboot configuration and precise commit +id, so it is possible to reproduce the build. -* The coreboot tree [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=util/board_status… contains a tool] to generate and push suitable data -as well as the scripts that present the data in wiki format. +We encourage developers and users to contribute reports so we know which +devices are well-tested. We have +[http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=util/board_status;hb=HEAD a tool in the coreboot repository] +to make contributing easy. The data resides in the +[http://review.coreboot.org/gitweb?p=board-status.git board status repository]. +Contributing requires an account on review.coreboot.org -* Board info is automatically generated from Kconfig and board_info.txt files. All boards present in the tree will appear here with varying amount of details. +Sometimes the same board is sold under different names, we've tried to +list all known names but some names might be missing. -* An account on review.coreboot.org is required for sending data. +If the board is not found in the corebootv4's source code, there might +be some form of support that is not ready yet for inclusion in coreboot, +usually people willing to send their patches to coreboot goes through +[http://review.coreboot.org gerrit], so looking there could find some +code for boards that are not yet merged. -* Sometimes the same board is sold under different names, we've tried to list all known names but some names might be missing. - -* Some boards have been removed for various reasons, may be brought back if someone works on them. Consult [[Graveyard]] for details. - -* If the board is not found in the corebootv4's source code, there might be some form of support that is not ready yet for inclusion in coreboot, usually people willing to send their patches to coreboot goes trough [http://review.coreboot.org gerrit], so looking there could find some code for boards that are not yet merged. -* some vendors have their own coreboot trees/fork, like for instance: -** [http://git.xivo.fr/?p=official/xioh/coreboot.git;a=summary xivo's tree] -** [http://git.chromium.org/gitweb/?p=chromiumos/third_party/coreboot.git;a=sum… chrome/chromium's tree] += Vendor trees = +Some vendors have their own coreboot trees/fork, like for instance: +* [http://git.xivo.fr/?p=official/xioh/coreboot.git;a=summary xivo's tree] +* [http://git.chromium.org/gitweb/?p=chromiumos/third_party/coreboot.git;a=sum… chrome/chromium's tree]

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Patch set updated for coreboot: superio/nuvoton/nct5572d: Add missing logical devices
by Kyösti Mälkki 01 Nov '15

01 Nov '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12213 -gerrit commit d5c0090eea36597e44eb085f7b6f58a6348d6204 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 27 18:00:57 2015 +0200 superio/nuvoton/nct5572d: Add missing logical devices While the actual pins behind these devices are not exposed on the chip, the enable registers are implemented in hardware. Allow to turn these LDNs off, like the vendor bios for asrock/e350m1 does. Change-Id: I4d6d5a8de12b09095138cacbad62b2dfbbe54028 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/superio/nuvoton/nct5572d/nct5572d.h | 4 ++++ src/superio/nuvoton/nct5572d/superio.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/superio/nuvoton/nct5572d/nct5572d.h b/src/superio/nuvoton/nct5572d/nct5572d.h index c0623e0..e04abf3 100644 --- a/src/superio/nuvoton/nct5572d/nct5572d.h +++ b/src/superio/nuvoton/nct5572d/nct5572d.h @@ -18,6 +18,8 @@ #define SUPERIO_NUVOTON_NCT5572D /* Logical Device Numbers (LDN). */ +#define NCT5572D_FDC 0x00 +#define NCT5572D_PP 0x01 #define NCT5572D_SP1 0x02 /* Com1 */ #define NCT5572D_IR 0x03 #define NCT5572D_KBC 0x05 @@ -35,8 +37,10 @@ /* virtual LDN for GPIO */ #define NCT5572D_GPIO2 ((0 << 8) | NCT5572D_GPIO235_V) #define NCT5572D_GPIO3 ((1 << 8) | NCT5572D_GPIO235_V) +#define NCT5572D_GPIO4 ((2 << 8) | NCT5572D_GPIO235_V) #define NCT5572D_GPIO5 ((3 << 8) | NCT5572D_GPIO235_V) #define NCT5572D_GPIO6 ((1 << 8) | NCT5572D_GPIO689_V) +#define NCT5572D_GPIO7 ((2 << 8) | NCT5572D_GPIO689_V) #define NCT5572D_GPIO8 ((3 << 8) | NCT5572D_GPIO689_V) #define NCT5572D_GPIO9 ((4 << 8) | NCT5572D_GPIO689_V) diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 688333d..81a8326 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -76,6 +76,8 @@ static struct device_operations ops = { }; static struct pnp_info pnp_dev_info[] = { + { &ops, NCT5572D_FDC}, /* no pins, removed from datasheet */ + { &ops, NCT5572D_PP}, /* no pins, removed from datasheet */ { &ops, NCT5572D_SP1, PNP_IO0 | PNP_IRQ0, {0x0FF8, 0}, }, { &ops, NCT5572D_IR, PNP_IO0 | PNP_IRQ0, {0x0FF8, 0}, }, { &ops, NCT5572D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0FFF, 0}, {0x0FFF, 4}, }, @@ -89,8 +91,10 @@ static struct pnp_info pnp_dev_info[] = { { &ops, NCT5572D_GPIO_PP_OD}, { &ops, NCT5572D_GPIO2}, { &ops, NCT5572D_GPIO3}, + { &ops, NCT5572D_GPIO4}, /* no pins, removed from datasheet */ { &ops, NCT5572D_GPIO5}, { &ops, NCT5572D_GPIO6}, + { &ops, NCT5572D_GPIO7}, /* no pins, removed from datasheet */ { &ops, NCT5572D_GPIO8}, { &ops, NCT5572D_GPIO9}, };

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Patch set updated for coreboot: asrock/e350m1: Add ACPI S3 support
by Kyösti Mälkki 01 Nov '15

01 Nov '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12215 -gerrit commit 4a8846cd8f34e4bd1d02e95796f82f86f5491951 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 27 14:31:18 2015 +0200 asrock/e350m1: Add ACPI S3 support To store memory configuration in SPI flash currently adds some 150 ms delay in ramstage, visible in timestamps listing at 75:cbmem post. Change-Id: I1160259054b58e9a8df2a105c730e0f4140be1f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/asrock/e350m1/Kconfig | 1 + src/mainboard/asrock/e350m1/buildOpts.c | 4 ++-- src/mainboard/asrock/e350m1/romstage.c | 26 +++++++++++++++++++++----- 3 files changed, 24 insertions(+), 7 deletions(-) diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index fa93d13..1c53212 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 041e1dd..140ece4 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -115,7 +115,7 @@ #define AGESA_ENTRY_INIT_LATE TRUE #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE /* @@ -187,7 +187,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = //#define BLDCFG_USE_HT_ASSIST TRUE //#define BLDCFG_USE_ATM_MODE TRUE //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_S3_LATE_RESTORE TRUE //#define BLDCFG_USE_32_BYTE_REFRESH FALSE //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index bf38395..50f3f6b 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -17,6 +17,7 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> +#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -33,6 +34,7 @@ #include <cpu/x86/lapic.h> #include <sb_cimx.h> #include "SBPLATFORM.h" +#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) @@ -77,12 +79,26 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - post_code(0x40); - agesawrapper_amdinitpost(); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); + post_code(0x42); + agesawrapper_amdinitenv(); + amd_initenv(); + + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } post_code(0x50); copy_and_run();

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Patch set updated for coreboot: asrock/e350m1: Match super-io GPIO configuration with vendor
by Kyösti Mälkki 01 Nov '15

01 Nov '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12214 -gerrit commit e12f24cb6a805d9c167f49cd75125cd644a2c8db Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Oct 28 11:08:24 2015 +0200 asrock/e350m1: Match super-io GPIO configuration with vendor Disables mouse ps2 data/clock signals, not connected in hardware. Purpose of other GPIOs is not really known, but match them with superiotool dump taken from vendor bios. Change-Id: I7b549fbd7dd3fa4cbd507d76882b60bc324a4bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/asrock/e350m1/devicetree.cb | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index 3488e44..e8b3ea5 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -72,17 +72,34 @@ chip northbridge/amd/agesa/family14/root_complex io 0x60 = 0x100 irq 0x70 = 0 end - device pnp 2e.7 off end # GIPO689 + device pnp 2e.107 off end # GPIO6 + device pnp 2e.207 off end # GPIO7 + device pnp 2e.307 on # GPIO8 + irq 0x23 = 0x28 + irq 0xe4 = 0xbf + irq 0xed = 0x27 + end + device pnp 2e.407 off end # GPIO9 device pnp 2e.8 off end # WDT - device pnp 2e.9 off end # GPIO235 - device pnp 2e.a on end # ACPI + device pnp 2e.009 on # GPIO2 + irq 0x2a = 0x42 + irq 0xe0 = 0xe3 + end + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe7 = 0x10 + end device pnp 2e.b on # HW Monitor io 0x60 = 0x290 io 0x62 = 0x0000 # SB-TSI currently not implemented irq 0x70 = 5 end device pnp 2e.c off end # PECI - device pnp 2e.d off end # SUSLED + device pnp 2e.d on # SUSLED + irq 0xec = 0x90 + end device pnp 2e.e off # CIRWKUP io 0x60 = 0x0000 irq 0x70 = 0

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coreboot-gerrit November 2015