coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Drop SuperIO smsc/fdc37m60x
by Stefan Reinauer 03 Nov '15

03 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12245 -gerrit commit edf0d3f465160c46faf00447efb0133eea592287 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Oct 28 18:14:38 2015 -0700 Drop SuperIO smsc/fdc37m60x All boards using this SuperIO have been removed from the tree already. Change-Id: I52847bc2fc16b27ac0de0bc7c847221b1e5cb744 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/superio/smsc/Kconfig | 2 - src/superio/smsc/Makefile.inc | 1 - src/superio/smsc/fdc37m60x/Makefile.inc | 17 ------- src/superio/smsc/fdc37m60x/early_serial.c | 73 ------------------------------- src/superio/smsc/fdc37m60x/fdc37m60x.h | 39 ----------------- src/superio/smsc/fdc37m60x/superio.c | 66 ---------------------------- 6 files changed, 198 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 6245766..0bab195 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -19,8 +19,6 @@ config SUPERIO_WANTS_14MHZ_CLOCK config SUPERIO_SMSC_DME1737 bool -config SUPERIO_SMSC_FDC37M60X - bool config SUPERIO_SMSC_FDC37N972 bool config SUPERIO_SMSC_LPC47B272 diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 88d5b6e..9b86745 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -15,7 +15,6 @@ ## subdirs-y += dme1737 -subdirs-y += fdc37m60x subdirs-y += fdc37n972 subdirs-y += lpc47b272 subdirs-y += lpc47b397 diff --git a/src/superio/smsc/fdc37m60x/Makefile.inc b/src/superio/smsc/fdc37m60x/Makefile.inc deleted file mode 100644 index 713bc0a..0000000 --- a/src/superio/smsc/fdc37m60x/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-$(CONFIG_SUPERIO_SMSC_FDC37M60X) += superio.c diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c deleted file mode 100644 index 36a62b0..0000000 --- a/src/superio/smsc/fdc37m60x/early_serial.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include "fdc37m60x.h" - -/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */ -#define FDC37M60X_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define FDC37M60X_CONFIG_POWER_CONTROL 0x22 /* Power Control. */ -#define FDC37M60X_CONFIG_POWER_MGMT 0x23 /* Intelligent Power Mgmt. */ -#define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */ - -#define FDC37M60X_CONFIGURATION_PORT 0x3f0 /* Write-only. */ - -/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) -{ - outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ -static void fdc37m60x_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - /* (1) Enter the configuration state. */ - outb(0x55, FDC37M60X_CONFIGURATION_PORT); - - /* (2) Modify the data of configuration registers. */ - - /* Power on all devices by setting the respective bit. - Bits: 0 (FDC), 3 (PP), 4 (Com1), 5 (Com2). The rest is reserved. */ - fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_CONTROL, 0x39); - - /* Disable intelligent power management. */ - fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_MGMT, 0x00); - - /* Turn on OSC, turn on BRG clock. */ - fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_OSC, 0x04); - - /* Configure serial port 1. */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0x60, 0x03); - fdc37m60x_sio_write(FDC37M60X_SP1, 0x61, 0xf8); /* I/O 0x3f8 */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0x70, 0x04); /* IRQ 4 */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0xf0, 0x00); /* Normal */ - - /* Enable serial port 1. */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0x30, 0x01); - - /* (3) Exit the configuration state. */ - outb(0xaa, FDC37M60X_CONFIGURATION_PORT); -} diff --git a/src/superio/smsc/fdc37m60x/fdc37m60x.h b/src/superio/smsc/fdc37m60x/fdc37m60x.h deleted file mode 100644 index a2eabcf..0000000 --- a/src/superio/smsc/fdc37m60x/fdc37m60x.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_SMSC_FDC37M60X_FDC37M60X_H -#define SUPERIO_SMSC_FDC37M60X_FDC37M60X_H - -/* - * Datasheet: - * - Name: FDC37M60x Enhanced Super I/O Controller with Infrared Support. - * - URL: http://www.smsc.com/main/discfdc.html - * - PDF: http://www.smsc.com/main/tools/discontinued/37m602.pdf - * - Revision: 6/6/97 - */ - -/* Status: Serial port 1 is tested and works (tested on FDC37M602). */ - -/* Note: Logical devices 1, 2, 6, and 9 are reserved. */ - -#define FDC37M60X_FDC 0x00 /* Floppy */ -#define FDC37M60X_PP 0x03 /* Parallel port */ -#define FDC37M60X_SP1 0x04 /* Com1 */ -#define FDC37M60X_SP2 0x05 /* Com2 */ -#define FDC37M60X_KBCK 0x07 /* Keyboard */ -#define FDC37M60X_AUX 0x08 /* Auxiliary I/O */ - -#endif diff --git a/src/superio/smsc/fdc37m60x/superio.c b/src/superio/smsc/fdc37m60x/superio.c deleted file mode 100644 index 57ba0d0..0000000 --- a/src/superio/smsc/fdc37m60x/superio.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include "fdc37m60x.h" - -static void init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case FDC37M60X_FDC: /* TODO. */ - break; - case FDC37M60X_PP: /* TODO. */ - break; - case FDC37M60X_KBCK: - pc_keyboard_init(); - break; - case FDC37M60X_AUX: /* TODO. */ - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -/* TODO: FDC, PP, AUX. */ -static struct pnp_info pnp_dev_info[] = { - { &ops, FDC37M60X_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, - { &ops, FDC37M60X_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, - { &ops, FDC37M60X_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &pnp_ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_smsc_fdc37m60x_ops = { - CHIP_NAME("SMSC FDC37M60X Super I/O") - .enable_dev = enable_dev, -};

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Patch set updated for coreboot: asus/kgpe-d16: fix DIMMSetVoltages
by Felix Held 03 Nov '15

03 Nov '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12297 -gerrit commit 2b2826e6c1deb24026c996772f40e4d4b3a44d2f Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Tue Nov 3 00:59:49 2015 +0100 asus/kgpe-d16: fix DIMMSetVoltages The RAM voltages can be set per socket, which contains two nodes. Only reset the allowed voltages per socket before processing a new socket and not after every node. Change-Id: Ia0e47676c7a3eebd56a17ab6de0e9690bf8cf703 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/mainboard/asus/kgpe-d16/romstage.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 76cbb8e..b8789b3 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -172,7 +172,7 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, uint8_t node; uint8_t socket; uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */ - uint8_t node_allowed_voltages; + uint8_t socket_allowed_voltages; uint32_t set_voltage = 0; if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) { @@ -190,28 +190,36 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, } } + /* unneeded, but makes the compiler happy */ + socket_allowed_voltages = allowed_voltages; + for (node = 0; node < MAX_NODES_SUPPORTED; node++) { socket = node / 2; - node_allowed_voltages = allowed_voltages; struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + node; + + /* reset socket_allowed_voltages before processing each socket */ + if (!(node % 2)) + socket_allowed_voltages = allowed_voltages; + if (pDCTstat->NodePresent) { for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { if (pDCTstat->DIMMValid & (1 << dimm)) { - node_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; + socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; } } } + /* set voltage per socket after processing last contained node */ if (pDCTstat->NodePresent && (node % 2)) { /* Set voltages */ - if (node_allowed_voltages & 0x8) { + if (socket_allowed_voltages & 0x8) { set_voltage = 1150; set_ddr3_voltage(socket, 3); - } else if (node_allowed_voltages & 0x4) { + } else if (socket_allowed_voltages & 0x4) { set_voltage = 1250; set_ddr3_voltage(socket, 2); - } else if (node_allowed_voltages & 0x2) { + } else if (socket_allowed_voltages & 0x2) { set_voltage = 1350; set_ddr3_voltage(socket, 1); } else {

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Patch set updated for coreboot: asus/kgpe-d16: fix DIMMSetVoltages
by Felix Held 03 Nov '15

03 Nov '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12297 -gerrit commit 2d61d81b332df19d1911ff4b686974bb66230575 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Tue Nov 3 00:59:49 2015 +0100 asus/kgpe-d16: fix DIMMSetVoltages The RAM voltages can be set per socket, which contains two nodes. Only reset the allowed voltages per socket before processing a new socket and not after every node. Change-Id: Ia0e47676c7a3eebd56a17ab6de0e9690bf8cf703 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/mainboard/asus/kgpe-d16/romstage.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 76cbb8e..e141b73 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -172,7 +172,7 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, uint8_t node; uint8_t socket; uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */ - uint8_t node_allowed_voltages; + uint8_t socket_allowed_voltages; uint32_t set_voltage = 0; if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) { @@ -192,26 +192,31 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, for (node = 0; node < MAX_NODES_SUPPORTED; node++) { socket = node / 2; - node_allowed_voltages = allowed_voltages; struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + node; + + /* reset socket_allowed_voltages before processing each socket */ + if (!(node % 2)) + socket_allowed_voltages = allowed_voltages; + if (pDCTstat->NodePresent) { for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { if (pDCTstat->DIMMValid & (1 << dimm)) { - node_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; + socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; } } } + /* set voltage per socket after processing last contained node */ if (pDCTstat->NodePresent && (node % 2)) { /* Set voltages */ - if (node_allowed_voltages & 0x8) { + if (socket_allowed_voltages & 0x8) { set_voltage = 1150; set_ddr3_voltage(socket, 3); - } else if (node_allowed_voltages & 0x4) { + } else if (socket_allowed_voltages & 0x4) { set_voltage = 1250; set_ddr3_voltage(socket, 2); - } else if (node_allowed_voltages & 0x2) { + } else if (socket_allowed_voltages & 0x2) { set_voltage = 1350; set_ddr3_voltage(socket, 1); } else {

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New patch to review for coreboot: asus/kgpe-d16: fix DIMMSetVoltages
by Felix Held 03 Nov '15

03 Nov '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12297 -gerrit commit ecaf97e619ed30a61d1dbd34773e009a2f28f081 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Tue Nov 3 00:59:49 2015 +0100 asus/kgpe-d16: fix DIMMSetVoltages The RAM voltages can be set per socket, which contains two nodes. Only reset the allowed voltages per socket before processing a new socket and not after every node. Change-Id: Ia0e47676c7a3eebd56a17ab6de0e9690bf8cf703 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/mainboard/asus/kgpe-d16/romstage.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 76cbb8e..02f5fcd 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -171,8 +171,8 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, uint8_t dimm; uint8_t node; uint8_t socket; - uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */ - uint8_t node_allowed_voltages; + const uint8_t allowed_voltages = 0xf; /* The mainboard VRMs allow 1.15V, 1.25V, 1.35V, and 1.5V */ + uint8_t socket_allowed_voltages; uint32_t set_voltage = 0; if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) { @@ -192,26 +192,31 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, for (node = 0; node < MAX_NODES_SUPPORTED; node++) { socket = node / 2; - node_allowed_voltages = allowed_voltages; struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + node; + + /* reset socket_allowed_voltages before processing each socket */ + if (!(node % 2)) + socket_allowed_voltages = allowed_voltages; + if (pDCTstat->NodePresent) { for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { if (pDCTstat->DIMMValid & (1 << dimm)) { - node_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; + socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; } } } + /* set voltage per socket after processing last contained node */ if (pDCTstat->NodePresent && (node % 2)) { /* Set voltages */ - if (node_allowed_voltages & 0x8) { + if (socket_allowed_voltages & 0x8) { set_voltage = 1150; set_ddr3_voltage(socket, 3); - } else if (node_allowed_voltages & 0x4) { + } else if (socket_allowed_voltages & 0x4) { set_voltage = 1250; set_ddr3_voltage(socket, 2); - } else if (node_allowed_voltages & 0x2) { + } else if (socket_allowed_voltages & 0x2) { set_voltage = 1350; set_ddr3_voltage(socket, 1); } else {

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Patch set updated for coreboot: util/cbmem: remove duplicated cbmem data structure logic.
by Aaron Durbin 03 Nov '15

03 Nov '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11758 -gerrit commit 420c1fc1639d6a5e623de16da962823b64f45b53 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 12:33:01 2015 -0500 util/cbmem: remove duplicated cbmem data structure logic. The cbmem utility shouldn't be using the intra coreboot data structures for obtaining the produced data/information. Instead use the newly added cbmem records in the coreboot tables for pulling out the data one wants by using the generic indexing of coreboot table entries. BUG=chrome-os-partner:43731 BRANCH=None TEST=Interrogated cbmem table of contents with updated code. Change-Id: I51bca7d34baf3b3a856cd5e585c8d5e3d8af1d1c --- util/cbmem/cbmem.c | 203 +++++++++++++++++++++-------------------------------- 1 file changed, 80 insertions(+), 123 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index f1cd03d..3c7f49b 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -57,8 +57,8 @@ static int verbose = 0; /* File handle used to access /dev/mem */ static int mem_fd; -/* IMD root pointer location */ -static uint64_t rootptr = 0; +static uint64_t lbtable_address; +static size_t lbtable_size; /* * calculate ip checksum (16 bit quantities) on a passed in buffer. In case @@ -170,9 +170,57 @@ static void *map_memory_size(u64 physical, size_t size, uint8_t abort_on_failure return v; } -static void *map_memory(u64 physical) +static void *map_lbtable(void) { - return map_memory_size(physical, MAP_BYTES, 1); + if (lbtable_address == 0 || lbtable_size == 0) { + fprintf(stderr, "No coreboot table area found!\n"); + return NULL; + } + + return map_memory_size(lbtable_address, lbtable_size, 1); +} + +static void unmap_lbtable(void) +{ + unmap_memory(); +} + +/* Find the first cbmem entry filling in the details. */ +static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size) +{ + uint8_t *table; + size_t offset; + int ret = -1; + + table = map_lbtable(); + + if (table == NULL) + return -1; + + offset = 0; + + while (offset < lbtable_size) { + struct lb_record *lbr; + struct lb_cbmem_entry *lbe; + + lbr = (void *)(table + offset); + offset += lbr->size; + + if (lbr->tag != LB_TAG_CBMEM_ENTRY) + continue; + + lbe = (void *)lbr; + if (lbe->id != id) + continue; + + *addr = lbe->address; + *size = lbe->entry_size; + ret = 0; + break; + } + + unmap_lbtable(); + return ret; } /* @@ -245,6 +293,11 @@ static int parse_cbtable(u64 address, size_t table_size, uint8_t abort_on_failur found = 1; debug("Found!\n"); + /* Keep reference to lbtable. */ + lbtable_address = address; + lbtable_address += ((uint8_t *)lbtable - (uint8_t *)lbh); + lbtable_size = lbh->table_bytes; + for (j = 0; j < lbh->table_bytes; j += lbr_p->size) { lbr_p = (struct lb_record*) ((char *)lbtable + j); debug(" coreboot table entry 0x%02x\n", lbr_p->tag); @@ -706,44 +759,6 @@ static void dump_cbmem_hex(void) hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size)); } -/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */ -#define DYN_CBMEM_ALIGN_SIZE (4096) -#define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE -#define CBMEM_POINTER_MAGIC 0xc0389481 -#define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC) - -struct cbmem_root_pointer { - uint32_t magic; - /* Relative to upper limit/offset. */ - int32_t root_offset; -} __attribute__((packed)); - -struct dynamic_cbmem_entry { - uint32_t magic; - int32_t start_offset; - uint32_t size; - uint32_t id; -} __attribute__((packed)); - -struct cbmem_root { - uint32_t max_entries; - uint32_t num_entries; - uint32_t flags; - uint32_t entry_align; - int32_t max_offset; - struct dynamic_cbmem_entry entries[0]; -} __attribute__((packed)); - -#define CBMEM_MAGIC 0x434f5245 -#define MAX_CBMEM_ENTRIES 16 - -struct cbmem_entry { - uint32_t magic; - uint32_t id; - uint64_t base; - uint64_t size; -} __attribute__((packed)); - struct cbmem_id_to_name { uint32_t id; const char *name; @@ -772,74 +787,39 @@ void cbmem_print_entry(int n, uint32_t id, uint64_t base, uint64_t size) printf(" %08" PRIx64 "\n", size); } -static void dump_static_cbmem_toc(struct cbmem_entry *entries) +static void dump_cbmem_toc(void) { int i; + uint8_t *table; + size_t offset; - printf("CBMEM table of contents:\n"); - printf(" ID START LENGTH\n"); - - for (i=0; i<MAX_CBMEM_ENTRIES; i++) { - if (entries[i].magic != CBMEM_MAGIC) - break; - cbmem_print_entry(i, entries[i].id, - entries[i].base, entries[i].size); - } -} + table = map_lbtable(); -static void dump_dynamic_cbmem_toc(struct cbmem_root *root) -{ - int i; - debug("CBMEM: max_entries=%d num_entries=%d flags=0x%x, entry_align=0x%x, max_offset=%d\n\n", - root->max_entries, root->num_entries, root->flags, root->entry_align, root->max_offset); + if (table == NULL) + return; printf("CBMEM table of contents:\n"); printf(" ID START LENGTH\n"); - for (i = 0; i < root->num_entries; i++) { - if(root->entries[i].magic != CBMEM_ENTRY_MAGIC) - break; - cbmem_print_entry(i, root->entries[i].id, - rootptr + root->entries[i].start_offset, root->entries[i].size); - } -} - -static void dump_cbmem_toc(void) -{ - uint64_t start; - void *cbmem_area; - struct cbmem_entry *entries; + i = 0; + offset = 0; - if (cbmem.type != LB_MEM_TABLE) { - fprintf(stderr, "No coreboot CBMEM area found!\n"); - return; - } + while (offset < lbtable_size) { + struct lb_record *lbr; + struct lb_cbmem_entry *lbe; - start = unpack_lb64(cbmem.start); + lbr = (void *)(table + offset); + offset += lbr->size; - cbmem_area = map_memory_size(start, unpack_lb64(cbmem.size), 1); - entries = (struct cbmem_entry *)cbmem_area; + if (lbr->tag != LB_TAG_CBMEM_ENTRY) + continue; - if (entries[0].magic == CBMEM_MAGIC) { - dump_static_cbmem_toc(entries); - } else { - rootptr = unpack_lb64(cbmem.start) + unpack_lb64(cbmem.size); - rootptr &= ~(DYN_CBMEM_ALIGN_SIZE - 1); - rootptr -= sizeof(struct cbmem_root_pointer); - unmap_memory(); - struct cbmem_root_pointer *r = - map_memory_size(rootptr, sizeof(*r), 1); - if (r->magic == CBMEM_POINTER_MAGIC) { - struct cbmem_root *root; - uint64_t rootaddr = rootptr + r->root_offset; - unmap_memory(); - root = map_memory_size(rootaddr, ROOT_MIN_SIZE, 1); - dump_dynamic_cbmem_toc(root); - } else - fprintf(stderr, "No valid coreboot CBMEM root pointer found.\n"); + lbe = (void *)lbr; + cbmem_print_entry(i, lbe->id, lbe->address, lbe->entry_size); + i++; } - unmap_memory(); + unmap_lbtable(); } #define COVERAGE_MAGIC 0x584d4153 @@ -871,42 +851,19 @@ static int mkpath(char *path, mode_t mode) static void dump_coverage(void) { - int i, found = 0; uint64_t start; - struct cbmem_entry *entries; + size_t size; void *coverage; unsigned long phys_offset; #define phys_to_virt(x) ((void *)(unsigned long)(x) + phys_offset) - if (cbmem.type != LB_MEM_TABLE) { - fprintf(stderr, "No coreboot table area found!\n"); + if (find_cbmem_entry(CBMEM_ID_COVERAGE, &start, &size)) { + fprintf(stderr, "No coverage information found\n"); return; } - start = unpack_lb64(cbmem.start); - - entries = (struct cbmem_entry *)map_memory(start); - - for (i=0; i<MAX_CBMEM_ENTRIES; i++) { - if (entries[i].magic != CBMEM_MAGIC) - break; - if (entries[i].id == CBMEM_ID_COVERAGE) { - found = 1; - break; - } - } - - if (!found) { - unmap_memory(); - fprintf(stderr, "No coverage information found in" - " CBMEM area.\n"); - return; - } - - start = entries[i].base; - unmap_memory(); /* Map coverage area */ - coverage = map_memory(start); + coverage = map_memory_size(start, size, 1); phys_offset = (unsigned long)coverage - (unsigned long)start; printf("Dumping coverage data...\n");

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Patch merged into coreboot/master: cbmem: add coreboot table records for each cbmem entry
by gerrit＠coreboot.org 03 Nov '15

03 Nov '15

the following patch was just integrated into master: commit 1ca2d864dd09788ab69f461074889bab57a92ae8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 12:26:54 2015 -0500 cbmem: add coreboot table records for each cbmem entry In order to not expose the cbmem data structures to userland that are used by coreboot internally add each of the cbmem entries to a coreboot table record. The payload ABI uses coreboot tables so this just provides a shortcut for cbmem entries which were manually added previously by doing the work on behalf of all entries. A cursor structure and associated functions are added to the imd code for walking the entries in order to be placed in the coreboot tables. Additionally a struct lb_cbmem_entry is added that lists the base address, size, and id of the cbmem entry. BUG=chrome-os-partner:43731 BRANCH=None TEST=Booted glados. View coreboot table entries with cbmem. Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11757 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11757 for details. -gerrit

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Patch set updated for coreboot: cbmem: add coreboot table records for each cbmem entry
by Aaron Durbin 03 Nov '15

03 Nov '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11757 -gerrit commit b7056328460605109a1d17904ba757567b43cb07 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 30 12:26:54 2015 -0500 cbmem: add coreboot table records for each cbmem entry In order to not expose the cbmem data structures to userland that are used by coreboot internally add each of the cbmem entries to a coreboot table record. The payload ABI uses coreboot tables so this just provides a shortcut for cbmem entries which were manually added previously by doing the work on behalf of all entries. A cursor structure and associated functions are added to the imd code for walking the entries in order to be placed in the coreboot tables. Additionally a struct lb_cbmem_entry is added that lists the base address, size, and id of the cbmem entry. BUG=chrome-os-partner:43731 BRANCH=None TEST=Booted glados. View coreboot table entries with cbmem. Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/commonlib/include/commonlib/coreboot_tables.h | 13 +++++++ src/include/cbmem.h | 4 +-- src/include/imd.h | 16 +++++++++ src/lib/coreboot_table.c | 3 ++ src/lib/imd.c | 44 +++++++++++++++++++++++ src/lib/imd_cbmem.c | 43 ++++++++++++++++++++-- 6 files changed, 119 insertions(+), 4 deletions(-) diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 2ed4d7f..5e0c87c 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -308,6 +308,19 @@ struct lb_boot_media_params { uint64_t boot_media_size; }; +/* + * There can be more than one of these records as there is one per cbmem entry. + */ +#define LB_TAG_CBMEM_ENTRY 0x0031 +struct lb_cbmem_entry { + uint32_t tag; + uint32_t size; + + uint64_t address; + uint32_t entry_size; + uint32_t id; +}; + #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 0825f29..efaa44f 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -37,6 +37,7 @@ #ifndef __ASSEMBLER__ #include <stddef.h> #include <stdint.h> +#include <boot/coreboot_tables.h> struct cbmem_entry; @@ -114,12 +115,11 @@ typedef void (* const cbmem_init_hook_t)(int is_recovery); void cbmem_run_init_hooks(int is_recovery); void cbmem_fail_resume(void); -#ifndef __PRE_RAM__ /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); void cbmem_list(void); -#endif /* __PRE_RAM__ */ +void cbmem_add_records_to_cbtable(struct lb_header *header); #if ENV_RAMSTAGE #define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ diff --git a/src/include/imd.h b/src/include/imd.h index 90a0dd5..6575312 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -120,6 +120,9 @@ size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry); /* Returns pointer to region described by entry or NULL on failure. */ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry); +/* Returns id for the imd entry. */ +uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry); + /* Attempt to remove entry from imd. */ int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry); @@ -132,6 +135,13 @@ struct imd_lookup { int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup, size_t size); +struct imd_cursor; +/* Initialize an imd_cursor object to walk the IMD entries. */ +int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor); + +/* Retrieve the next imd entry the cursor is referencing. Returns NULL when + * no more entries exist. */ +const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor); /* * The struct imd is a handle for working with an in-memory directory. @@ -148,4 +158,10 @@ struct imd { struct imdr sm; }; +struct imd_cursor { + size_t current_imdr; + size_t current_entry; + const struct imdr *imdr[2]; +}; + #endif /* _IMD_H_ */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 8ffc698..258a4a5 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -538,6 +538,9 @@ unsigned long write_coreboot_table( lb_boot_media_params(head); + /* Add all cbmem entries into the coreboot tables. */ + cbmem_add_records_to_cbtable(head); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } diff --git a/src/lib/imd.c b/src/lib/imd.c index bbfbced..2ad9cd8 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -623,6 +623,11 @@ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry) return imdr_entry_at(imdr, entry); } +uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry) +{ + return entry->id; +} + int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry) { struct imd_root *r; @@ -698,3 +703,42 @@ int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup, return 0; } + +int imd_cursor_init(const struct imd *imd, struct imd_cursor *cursor) +{ + if (imd == NULL || cursor == NULL) + return -1; + + memset(cursor, 0, sizeof(*cursor)); + + cursor->imdr[0] = &imd->lg; + cursor->imdr[1] = &imd->sm; + + return 0; +} + +const struct imd_entry *imd_cursor_next(struct imd_cursor *cursor) +{ + struct imd_root *r; + const struct imd_entry *e; + + if (cursor->current_imdr >= ARRAY_SIZE(cursor->imdr)) + return NULL; + + r = imdr_root(cursor->imdr[cursor->current_imdr]); + + if (r == NULL) + return NULL; + + if (cursor->current_entry >= r->num_entries) { + /* Try next imdr. */ + cursor->current_imdr++; + cursor->current_entry = 0; + return imd_cursor_next(cursor); + } + + e = &r->entries[cursor->current_entry]; + cursor->current_entry++; + + return e; +} diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 7cc34f5..49faad9 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -263,7 +263,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) return imd_entry_at(imd, cbmem_to_imd(entry)); } -#if ENV_RAMSTAGE void cbmem_add_bootmem(void) { void *base = NULL; @@ -273,10 +272,50 @@ void cbmem_add_bootmem(void) bootmem_add_range((uintptr_t)base, size, LB_MEM_TABLE); } +#if ENV_RAMSTAGE +/* + * -fdata-sections doesn't work so well on read only strings. They all + * get put in the same section even though those strings may never be + * referenced in the final binary. + */ void cbmem_list(void) { static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE }; imd_print_entries(cbmem_get_imd(), lookup, ARRAY_SIZE(lookup)); } -#endif /* __PRE_RAM__ */ +#endif + +void cbmem_add_records_to_cbtable(struct lb_header *header) +{ + struct imd_cursor cursor; + struct imd *imd; + + imd = cbmem_get_imd(); + + if (imd_cursor_init(imd, &cursor)) + return; + + while (1) { + const struct imd_entry *e; + struct lb_cbmem_entry *lbe; + uint32_t id; + + e = imd_cursor_next(&cursor); + + if (e == NULL) + break; + + id = imd_entry_id(imd, e); + /* Don't add these metadata entries. */ + if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL) + continue; + + lbe = (struct lb_cbmem_entry *)lb_new_record(header); + lbe->tag = LB_TAG_CBMEM_ENTRY; + lbe->size = sizeof(*lbe); + lbe->address = (uintptr_t)imd_entry_at(imd, e); + lbe->entry_size = imd_entry_size(imd, e); + lbe->id = id; + } +}

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Patch merged into coreboot/master: cpu/amd: Add initial AMD Family 15h support
by gerrit＠coreboot.org 02 Nov '15

02 Nov '15

the following patch was just integrated into master: commit 730a043fb6cb4dd3cb5af8f8640365727b598648 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Oct 16 13:51:51 2015 -0500 cpu/amd: Add initial AMD Family 15h support TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working * Suspend to RAM (S3) tested and working Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11966 for details. -gerrit

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Patch merged into coreboot/master: cpu/amd/family_10h-family_15h: Use correct label for break state
by gerrit＠coreboot.org 02 Nov '15

02 Nov '15

the following patch was just integrated into master: commit d150006c4a4584bc9933c2d8ff580a54c4f0cc2a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Oct 20 01:17:34 2015 -0500 cpu/amd/family_10h-family_15h: Use correct label for break state Change-Id: I07e517f239807cbe76037308f0beff80c9a6f2ba Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12101 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12101 for details. -gerrit

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Patch merged into coreboot/master: cpu/amd: Move model_10xxx to family_10h-family_15h
by gerrit＠coreboot.org 02 Nov '15

02 Nov '15

the following patch was just integrated into master: commit b30d7ed8f09d4d5d75bf68f3ba74674fe65c4b4f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Oct 16 14:24:06 2015 -0500 cpu/amd: Move model_10xxx to family_10h-family_15h Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/11965 for details. -gerrit

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coreboot-gerrit November 2015