coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

Patch merged into coreboot/master: arch/x86/bootblock_normal: Fix failure to build
by gerrit＠coreboot.org 03 Nov '15

03 Nov '15

the following patch was just integrated into master: commit 82cb7875ff13e97c57d83deabd6350d2a5186ee7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 3 16:04:56 2015 -0600 arch/x86/bootblock_normal: Fix failure to build Fix a function call in the normal path using the original function name and arguments in code that was changed in commit 3bfd7cc6 (drivers/pc80: Rework normal / fallback selector code) This commit reworked most of the fallback / normal code, however the normal code paths were not fully tested by Jenkins, so this was missed. Change-Id: Ied66334977272a13b7a7307ff4d9f34eb22040aa Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12315 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12315 for details. -gerrit

1 0

Patch set updated for coreboot: arch/x86/bootblock_normal: Fix failure to build
by Martin Roth 03 Nov '15

03 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12315 -gerrit commit 36e5f9677a5343f5c66282856930c56b1ff111cd Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 3 16:04:56 2015 -0600 arch/x86/bootblock_normal: Fix failure to build Fix a function call in the normal path using the original function name and arguments in code that was changed in commit 3bfd7cc6 (drivers/pc80: Rework normal / fallback selector code) This commit reworked most of the fallback / normal code, however the normal code paths were not fully tested by Jenkins, so this was missed. Change-Id: Ied66334977272a13b7a7307ff4d9f34eb22040aa Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/arch/x86/bootblock_normal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index bde2535..a4dc3c4 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -27,7 +27,7 @@ static void main(unsigned long bist) * Do not add any other CMOS access in the * bootblock for AP CPUs. */ - boot_mode = last_boot_normal(); + boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); } char *filenames = (char *)walkcbfs("coreboot-stages");

1 0

New patch to review for coreboot: arch/x86/bootblock_normal: Fix failure to build
by Timothy Pearson 03 Nov '15

03 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12315 -gerrit commit 863a677b2bafc4462c37793edf567abed85ddc10 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 3 16:04:56 2015 -0600 arch/x86/bootblock_normal: Fix failure to build Changeset 12289 reworked most of the fallback / normal code, however the normal code paths were not fully tested by Jenkins. Fix a function call in the normal path using the original function name and arguments. Change-Id: Ied66334977272a13b7a7307ff4d9f34eb22040aa Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/arch/x86/bootblock_normal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index bde2535..a4dc3c4 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -27,7 +27,7 @@ static void main(unsigned long bist) * Do not add any other CMOS access in the * bootblock for AP CPUs. */ - boot_mode = last_boot_normal(); + boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); } char *filenames = (char *)walkcbfs("coreboot-stages");

1 0

Patch merged into coreboot/master: drivers/pc80: Rework normal / fallback selector code
by gerrit＠coreboot.org 03 Nov '15

03 Nov '15

the following patch was just integrated into master: commit 3bfd7cc61e73439a2b1ac2d85faa7aaa988969ed Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Nov 1 02:13:17 2015 -0600 drivers/pc80: Rework normal / fallback selector code Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback path should always be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12289 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/12289 for details. -gerrit

1 0

Patch merged into coreboot/master: board-status: Reorder the table categories
by gerrit＠coreboot.org 03 Nov '15

03 Nov '15

the following patch was just integrated into master: commit 2a4f58ac1283e45d1f0cc6102a319b6d442a888d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sun Nov 1 14:20:15 2015 +0100 board-status: Reorder the table categories Show laptops and servers before desktop boards since that's where both the market and coreboot are the most active these days. Change-Id: I7de63975f3f2ff5e983b19e07558175a58870a1b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12292 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12292 for details. -gerrit

1 0

Patch merged into coreboot/master: board-status: Update the foreword
by gerrit＠coreboot.org 03 Nov '15

03 Nov '15

the following patch was just integrated into master: commit e0e7bba2de1122726b29e46b0301016d02286292 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sun Nov 1 14:18:30 2015 +0100 board-status: Update the foreword There's the sentiment that the Supported_Motherboards wiki page is outdated. Point out that the list is current (and drop the table of contents that became a distraction). Change-Id: Ib2363fad0b7f6951b07b2ad0c85148d9bc729b55 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/12291 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12291 for details. -gerrit

1 0

New patch to review for coreboot: ultra40m2: HDA verb configuration
by Jonathan A. Kollasch 03 Nov '15

03 Nov '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12314 -gerrit commit 826bf1491d6be80607d99eef6bc2bc7d327b36b2 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Nov 3 12:03:32 2015 -0600 ultra40m2: HDA verb configuration Change-Id: I93d83ac2e5a123907622505630624805f1128c5a Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/sunw/ultra40m2/hda_verb.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/mainboard/sunw/ultra40m2/hda_verb.c b/src/mainboard/sunw/ultra40m2/hda_verb.c index 31052f2..137196c 100644 --- a/src/mainboard/sunw/ultra40m2/hda_verb.c +++ b/src/mainboard/sunw/ultra40m2/hda_verb.c @@ -19,18 +19,18 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 + 0x10ec0885, // Codec Vendor / Device ID: Realtek ALC889A 0x00000000, // Subsystem ID 0x0000000d, // Number of jacks - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x0000e601 */ - AZALIA_SUBVENDOR(0x0, 0x0000e601), + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x108ee601 */ + AZALIA_SUBVENDOR(0x0, 0x108ee601), /* NID 0x14, FRONT-OUT-L/R */ - AZALIA_PIN_CFG(0x0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), /* NID 0x15, SURR-OUT-L/R */ - AZALIA_PIN_CFG(0x0, 0x15, 0x01011412), + AZALIA_PIN_CFG(0x0, 0x15, 0x01011012), /* NID 0x16, CEN/LFE-OUT */ AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), @@ -39,28 +39,28 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0x0, 0x17, 0x01012014), /* NID 0x18, MIC1-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x18, 0x01a19c30), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19840), /* NID 0x19, MIC2-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c40), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19850), /* NID 0x1a, LINE1-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x1a, 0x01813431), + AZALIA_PIN_CFG(0x0, 0x1a, 0x01813041), /* NID 0x1b, LINE2-L/R, VREFO */ - AZALIA_PIN_CFG(0x0, 0x1b, 0x0221441f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214020), /* NID 0x1c, CD-L/R / GND */ - AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1c, 0x9933014f), /* NID 0x1d, PCBEEP */ - AZALIA_PIN_CFG(0x0, 0x1d, 0x9983013e), + AZALIA_PIN_CFG(0x0, 0x1d, 0x99830142), /* NID 0x1e, S/PDIF-OUT */ - AZALIA_PIN_CFG(0x0, 0x1e, 0x01454120), + AZALIA_PIN_CFG(0x0, 0x1e, 0x014b4130), /* NID 0x1f, S/PDIF-IN */ - AZALIA_PIN_CFG(0x0, 0x1f, 0x01c59150), + AZALIA_PIN_CFG(0x0, 0x1f, 0x01cb9160), }; const u32 pc_beep_verbs[0] = {};

1 0

New patch to review for coreboot: ultra40m2: remove some probably-useless cargo cult GPIO configuration
by Jonathan A. Kollasch 03 Nov '15

03 Nov '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12313 -gerrit commit e39ccb5f9fe4a7dd931b534d5062ea9fd3835b41 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Nov 3 12:31:52 2015 -0600 ultra40m2: remove some probably-useless cargo cult GPIO configuration Change-Id: Ie7ab1ae49f5c9e42dbfe491da05e0fb09692a513 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/sunw/ultra40m2/romstage.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 8fc8304..c20d39f 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -61,8 +61,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+61, 0xf0, 0x05,/* GPIO62 Firewire OHCI disable (active low)? */ #include <southbridge/nvidia/mcp55/early_setup_ss.h>

1 0

New patch to review for coreboot: ultra40m2: add second CPU node devices in devicetree
by Jonathan A. Kollasch 03 Nov '15

03 Nov '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12312 -gerrit commit 78bc3d32e45237325cb08ba1dd447616d14da4c4 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Nov 3 12:29:47 2015 -0600 ultra40m2: add second CPU node devices in devicetree Change-Id: I164a77fdd3521cf5dd4163160b9f75c3970861c4 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/sunw/ultra40m2/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/sunw/ultra40m2/devicetree.cb b/src/mainboard/sunw/ultra40m2/devicetree.cb index bbcf3ee..6b1f3ec 100644 --- a/src/mainboard/sunw/ultra40m2/devicetree.cb +++ b/src/mainboard/sunw/ultra40m2/devicetree.cb @@ -146,6 +146,12 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end end end end

1 0

New patch to review for coreboot: ultra40m2: configure TPM ports
by Jonathan A. Kollasch 03 Nov '15

03 Nov '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12311 -gerrit commit 5f1a31d7bfeee4964a79dc9f3525bc098d492164 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Nov 3 12:26:05 2015 -0600 ultra40m2: configure TPM ports Change-Id: Ie4a645da500f5417cd378079e3eb8a9253065f2d Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/sunw/ultra40m2/devicetree.cb | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/sunw/ultra40m2/devicetree.cb b/src/mainboard/sunw/ultra40m2/devicetree.cb index d61dd17..bbcf3ee 100644 --- a/src/mainboard/sunw/ultra40m2/devicetree.cb +++ b/src/mainboard/sunw/ultra40m2/devicetree.cb @@ -41,8 +41,13 @@ chip northbridge/amd/amdk8/root_complex # Root complex io 0x60 = 0x600 end end + chip drivers/pc80/tpm + device pnp 4e.0 on # Infineon SLB9635TT12 TPM + #io 0x60 = 0x7f0 + end + end # There's also an Akom AK2001 7-segment port 0x80 decoder on - # and Infineon SLB9635TT12 TPM on this LPC bus. + # this LPC bus. end device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015