coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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1544 discussions

New patch to review for coreboot: libpayload: usb: xhci: Workaround to get Intel xHCI reset working more reliably
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12325 -gerrit commit 1a13c9fc08e08af292d64e1276093de96713f315 Author: Rajmohan Mani <rajmohan.mani(a)intel.com> Date: Fri Oct 30 17:00:24 2015 -0700 libpayload: usb: xhci: Workaround to get Intel xHCI reset working more reliably Existing Intel xHCI controllers require a delay of 1 mS, after setting the CMD_RESET bit in command register, before accessing any HC registers. This allows the HC to complete the reset operation and be ready for HC register access. Without this delay, the subsequent HC register access, may result in a system hang, very rarely. Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles (which was not possible without this patch), without any xHCI reset hang in depthcharge. BRANCH=None BUG=None TEST=Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles, without any xHCI reset hang in depthcharge. Change-Id: I8eff5115ca52738bdcf8bc65fbfb2a5f60a0abe1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3e7ea70df36e3bf35a6ee1297640900ee76bfdac Original-Change-Id: Id681a19d0eedb0e2c29e259c5467bcde577e3460 Original-Signed-off-by: Rajmohan Mani <rajmohan.mani(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310022 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/drivers/usb/xhci.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 71272c7..863ba4e 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -328,6 +328,17 @@ xhci_reset(hci_t *const controller) xhci_stop(controller); xhci->opreg->usbcmd |= USBCMD_HCRST; + + /* Existing Intel xHCI controllers require a delay of 1 mS, + * after setting the CMD_RESET bit, and before accessing any + * HC registers. This allows the HC to complete the + * reset operation and be ready for HC register access. + * Without this delay, the subsequent HC register access, + * may result in a system hang very rarely. + */ + if (IS_ENABLED(CONFIG_LP_ARCH_X86)) + mdelay(1); + xhci_debug("Resetting controller... "); if (!xhci_handshake(&xhci->opreg->usbcmd, USBCMD_HCRST, 0, 1000000L)) usb_debug("timeout!\n");

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New patch to review for coreboot: google/chell: Fix USB port assignment
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12324 -gerrit commit e9858fa5c916db0fecb6fe983938db416aa586d2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 30 17:55:05 2015 -0700 google/chell: Fix USB port assignment The PCH pin names in the schematic were incorrectly labeled. BUG=chrome-os-partner:46289 BRANCH=none TEST=build and boot on chell Change-Id: I6153137b7c04d22db5b3f00f5eaf3f400f4c344c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6f362900b0635dc392c63b25a88a7723f22b467a Original-Change-Id: If6f8744f020a35a76647366b247723b03c02991a Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/310061 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index dfa588a..05e37bf 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -54,11 +54,11 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[4]" = "2" register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_MID" # Type-A Port - register "usb2_ports[2]" = "USB2_PORT_FLEX" # Camera + register "usb2_ports[2]" = "USB2_PORT_TYPE_C" # Type-C Port 2 register "usb2_ports[3]" = "USB2_PORT_MID" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID" # SD - register "usb2_ports[5]" = "USB2_PORT_TYPE_C" # Type-C Port 2 + register "usb2_ports[5]" = "USB2_PORT_MID" # Type-A Port + register "usb2_ports[7]" = "USB2_PORT_FLEX" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID" # SD register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2

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New patch to review for coreboot: intel/kunimitsu, google/glados: Enable Fan control support
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12323 -gerrit commit f1de9f7215038a41e1da1f31a338d105eb82e6b7 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Mon Oct 19 14:57:43 2015 +0530 intel/kunimitsu, google/glados: Enable Fan control support This patch enables the Fan thermal participant device in the device tree for thermal active cooling action for DPTF on SKL-U fan based kunimitsu board. This patch defines the _ART table in dptf ASL file. With active cooling policy (_ART), we can control the fan on/off and speed. BRANCH=None BUG=chrome-os-partner:46493 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also, checked the FAN type the cooling devices enumerated in the /sys/class/thermal with sysfs interface. Change-Id: I40c540dad32beefe249f025b570c347d3ad08c36 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 82ae11643ca23e65780006f3890f1d173363b8af Original-Change-Id: If44b358052a677d13c74919f09a3eb89611fccad Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307028 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/acpi/dptf.asl | 3 +++ src/mainboard/intel/kunimitsu/acpi/dptf.asl | 37 +++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/src/mainboard/google/glados/acpi/dptf.asl b/src/mainboard/google/glados/acpi/dptf.asl index aebc7b2..8e96315 100644 --- a/src/mainboard/google/glados/acpi/dptf.asl +++ b/src/mainboard/google/glados/acpi/dptf.asl @@ -45,6 +45,9 @@ /* SKL-Y EC already has a custom charge profile based on temperature. */ #undef DPTF_ENABLE_CHARGER +/* SKL-Y is Fanless design. */ +#undef DPTF_ENABLE_FAN_CONTROL + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl index 73ed77b..2eea804 100644 --- a/src/mainboard/intel/kunimitsu/acpi/dptf.asl +++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl @@ -38,6 +38,7 @@ #define DPTF_TSR2_CRITICAL 70 #define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL /* Charger performance states, board-specific values from charger and EC */ Name (CHPS, Package () { @@ -48,6 +49,42 @@ Name (CHPS, Package () { Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ }) +#ifdef DPTF_ENABLE_FAN_CONTROL +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {100, 0xFFFFFFFF, 4986, 220, 2200}, + Package () {90, 0xFFFFFFFF, 4804, 180, 1800}, + Package () {80, 0xFFFFFFFF, 4512, 145, 1450}, + Package () {70, 0xFFFFFFFF, 4204, 115, 1150}, + Package () {60, 0xFFFFFFFF, 3838, 90, 900}, + Package () {50, 0xFFFFFFFF, 3402, 65, 650}, + Package () {40, 0xFFFFFFFF, 2904, 45, 450}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0, + 0, 0, 0 + } +}) +#endif + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },

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New patch to review for coreboot: intel/skylake: Add Fan control support
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12322 -gerrit commit 5d3fcb9dc09e170b05f59c8fd86f8688d095a482 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Mon Oct 19 14:45:23 2015 +0530 intel/skylake: Add Fan control support This patch adds the ASL file for Fan as cooling device /participant for thermal active cooling action for DPTF on SKL-U fan based kunimitsu board. With active cooling policy (_ART), we can control the fan on/off and speed. BRANCH=None BUG=chrome-os-partner:46493 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also, checked the FAN type the cooling devices enumerated in the /sys/class/thermal with sysfs interface. Change-Id: Iacfd9152e300ec47895c29deab2c9d4361230849 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d37a089b5196f02cb95f16083c416456e96d54a4 Original-Change-Id: I8293bfe2a2bf213b69fbb4223bbfcf508a9cf0bf Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307027 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/acpi/dptf/dptf.asl | 18 ++++++++ src/soc/intel/skylake/acpi/dptf/fan.asl | 72 ++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) diff --git a/src/soc/intel/skylake/acpi/dptf/dptf.asl b/src/soc/intel/skylake/acpi/dptf/dptf.asl index 4f1c564..61f982c 100644 --- a/src/soc/intel/skylake/acpi/dptf/dptf.asl +++ b/src/soc/intel/skylake/acpi/dptf/dptf.asl @@ -29,6 +29,11 @@ Device (DPTF) /* DPPM Cooling Policy */ ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"), + +#ifdef DPTF_ENABLE_FAN_CONTROL + /* DPPM Active Policy */ + ToUUID ("3A95C389-E4B8-4629-A526-C52C88626BAE"), +#endif }) Method (_STA) @@ -71,6 +76,14 @@ Device (DPTF) Return (\_SB.DTRT) } +#ifdef DPTF_ENABLE_FAN_CONTROL + /* _ART : Active Cooling Relationship Table */ + Method (_ART) + { + Return (\_SB.DART) + } +#endif + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ Method (CTOK, 1) { /* 10th of Degrees C */ @@ -90,6 +103,11 @@ Device (DPTF) #include "charger.asl" #endif +#ifdef DPTF_ENABLE_FAN_CONTROL + /* Include Fan Participant */ + #include "fan.asl" +#endif + } Scope (\_SB.PCI0) diff --git a/src/soc/intel/skylake/acpi/dptf/fan.asl b/src/soc/intel/skylake/acpi/dptf/fan.asl new file mode 100644 index 0000000..0501385 --- /dev/null +++ b/src/soc/intel/skylake/acpi/dptf/fan.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Device (TFN1) +{ + Name (_HID, "INT3404") + Name (_UID, 0) + Name (_STR, Unicode("Fan Control")) + + /* _FIF: Fan Information */ + Name (_FIF, Package () + { + 0, // Revision + 1, // Fine Grained Control + 2, // Step Size + 0 // No Low Speed Notification + }) + + /* Return Fan Performance States defined by mainboard */ + Method (_FPS) + { + Return (\_SB.DFPS) + } + + Name (TFST, Package () + { + 0, // Revision + 0x00, // Control + 0x00 // Speed + }) + + /* _FST: Fan current Status */ + Method (_FST, 0, Serialized,,PkgObj) + { + /* Fill in TFST with current control. */ + Store (\_SB.PCI0.LPCB.EC0.FAND, Index (TFST, 1)) + Return (TFST) + } + + /* _FSL: Fan Speed Level */ + Method (_FSL, 1, Serialized) + { + Store (Arg0, \_SB.PCI0.LPCB.EC0.FAND) + Notify (DPTF, 0x83) // Re evaluate _ART + } + + Method (_STA) + { + If (LEqual (\DPTE, One)) + { + Return (0xF) + } Else { + Return (0x0) + } + } +}

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New patch to review for coreboot: nvidia/tegra210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12321 -gerrit commit 9a54d7b30b714b16a3e04347c5f8bebcde3ef4db Author: Joseph Lo <josephl(a)nvidia.com> Date: Wed Oct 28 15:34:22 2015 +0800 nvidia/tegra210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0 The MC/SMMU should be resumed by the kernel. And the unexpected value in the MC_INTSTATUS should be cleared before that. Or it will cause some noisy MC interrupt once we enable the IRQ in the kernel. BUG=chrome-os-partner:46796 BRANCH=none TEST=LP0 suspend/resume test and the EMEM decode/arbitration errors should not be observed on resume. Change-Id: I5b32fa58ebcb8e7db6ffc88e13cca050753f621a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 07cb719caf40b59c5519fcf212c2fb50f006812e Original-Change-Id: I4d34905c04effd54d0d0edf8809e192283db2ca3 Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309248 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic(a)chromium.org> Original-Commit-Queue: Joseph Lo <yushun.lo(a)gmail.com> Original-Tested-by: Joseph Lo <yushun.lo(a)gmail.com> Original-(cherry picked from commit 13cbcaf441bd762af9cf00eff24eb7709db38d95) Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309497 Original-Commit-Ready: Andrew Bresticker <abrestic(a)chromium.org> --- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 000d48d..15477d6 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -335,6 +335,8 @@ enum { static uint32_t *pmc_set_sw_clamp_ptr = (void *)(PMC_CTLR_BASE + 0x47c); /* Memory controller registers. */ +static uint32_t *mc_intstatus_ptr = (void *)(MC_CTLR_BASE); +static uint32_t *mc_intmask_ptr = (void *)(MC_CTLR_BASE + 0x4); static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c); static uint32_t *mc_video_protect_reg_ctrl_ptr = @@ -979,6 +981,13 @@ void lp0_resume(void) write32(pmc_dpd_sample_ptr, 0); udelay(10); + /* Clear the MC_INTSTATUS if MC_INTMASK was 0. */ + if (!read32(mc_intmask_ptr)) { + uint32_t mc_intst_val = read32(mc_intstatus_ptr); + if (mc_intst_val) + write32(mc_intstatus_ptr, mc_intst_val); + } + /* * Set both _ACCESS bits so that kernel/secure code * can reconfig VPR careveout as needed from the TrustZone.

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Patch set updated for coreboot: libpayload: Allow non-default CBFS media
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12232 -gerrit commit fed9bbe447f71a5e9446d58c7023101730c74644 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Oct 23 20:25:03 2015 +0200 libpayload: Allow non-default CBFS media CBFS requests were always fulfilled using the CBFS specified in cbtables. That's a great policy when default requests are sought, but not so great when the user deliberately asked for something else. So check if they want default CBFS media information, otherwise ignore cbtables data. BUG=chromium:445938 BRANCH=none TEST=none Change-Id: I01b63049eebfba6f467808ac84ef77385840c204 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 621c916ab14c0de4bae3dde09c05060c4f3c63c5 Original-Change-Id: Ia4a8848fd7db9d9a2bf9f5c226566fe3936ff543 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308520 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/libcbfs/cbfs_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index ff3c527..14a2001 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -100,7 +100,8 @@ static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end, { const struct cbfs_header *header; - if (lib_sysinfo.cbfs_offset && lib_sysinfo.cbfs_size) { + if (media == CBFS_DEFAULT_MEDIA && + lib_sysinfo.cbfs_offset && lib_sysinfo.cbfs_size) { *offset = lib_sysinfo.cbfs_offset; *cbfs_end = *offset + lib_sysinfo.cbfs_size; return 0;

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Patch set updated for coreboot: fsp1_1: pass ROM_SIZE to FSP for cacheable RO region
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12260 -gerrit commit 3fd5fad1df9ea8bb0ef7eafb33b87362a2ef085b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 29 10:43:21 2015 -0500 fsp1_1: pass ROM_SIZE to FSP for cacheable RO region As vboot verification works on regions outside of CBFS pass the entire ROM_SIZE to FSP for creating a cacheable RO region. Additionally remove the CACHE_ROM_SIZE_OVERRIDE as it doesn't work with non-power of 2 CBFS_SIZE. In practice the entire ROM should be attempted to be cached. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados w/ a 3MiB CBFS_SIZE. Change-Id: I61404c626ab2bcfd039d6eb3c01d9c13a0928446 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 92568c630c48446b1ad9d4f22056f22e0679970c Original-Change-Id: I032e4d615d2b68d3a2e597555eb1b5034a74bf0a Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309770 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/intel/fsp1_1/Kconfig | 9 --------- src/drivers/intel/fsp1_1/cache_as_ram.inc | 4 ++-- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 5936f60..4ae3727 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -80,15 +80,6 @@ config FSP_LOC endif #HAVE_FSP_BIN -config CACHE_ROM_SIZE_OVERRIDE - hex "Cache ROM Size" - default CBFS_SIZE - help - This is the size of the cachable area that is passed into the FSP in - the early initialization. Typically this should be the size of the - CBFS area, but the size must be a power of 2 whereas the CBFS size - does not have this limitation. - config DISPLAY_FAST_BOOT_DATA bool "Display fast boot data" default n diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 1d63376..7d68f32 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -212,8 +212,8 @@ fake_fsp_stack: CAR_init_params: .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ - .long 0xFFFFFFFF - CONFIG_CBFS_SIZE + 1 /* Firmware Location */ - .long CONFIG_CBFS_SIZE /* Total Firmware Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total Firmware Length */ CAR_init_stack: .long CAR_init_done

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Patch set updated for coreboot: skylake: Set Pkg Power clamping bit in Power Limit MSR
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12257 -gerrit commit 130e3258a956a88c1b67aaf2e529be14c7507006 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Oct 15 21:38:21 2015 +0530 skylake: Set Pkg Power clamping bit in Power Limit MSR Setting the Package Power clamping bits in Power Limit MSR (MSR_PKG_POWER_LIMIT 0x610) Allows going below the OS requested P or T state for the time window specified for PL1 or PL2. BRANCH=none BUG=chrome-os-partner:47041 TEST=Built and boot on kunimitsu, load the system with Aquarium WebGL, change the power limit value from default (TDP or 15W) to any lower value note that the Pkg power comes down and also the CPU frequency is lowered. Change-Id: I9c0dd90a6660214ae142418aae8b8c5f6a739896 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b0b527991c2d26da5772700a22ff101eaf9993ef Original-Change-Id: Ia59fcfe2a14cd7f8b1e1b8e967073e67eb452f42 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309556 Original-Tested-by: Charulatha Varadarajan <charuprasanna(a)gmail.com> Original-Tested-by: Charulatha Varadarajan <charulatha.varadarajan(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index a5c60b8..3687380 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -152,6 +152,10 @@ void set_power_limits(u8 power_limit_1_time) /* Set long term power limit to TDP */ limit.lo = 0; limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + + /* Set PL1 Pkg Power clamp bit */ + limit.lo |= PKG_POWER_LIMIT_CLAMP; + limit.lo |= PKG_POWER_LIMIT_EN; limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; @@ -159,6 +163,7 @@ void set_power_limits(u8 power_limit_1_time) /* Set short term power limit to 1.25 * TDP */ limit.hi = 0; limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_EN; /* Power limit 2 time is only programmable on server SKU */

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Patch set updated for coreboot: libpayload: Fix building dwc2 UDC driver with debug enabled
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12258 -gerrit commit 3691b1340b29a2a18a8fe6191cb3c411ae7cb000 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Oct 26 19:48:25 2015 +0100 libpayload: Fix building dwc2 UDC driver with debug enabled hexdump() now takes a pointer instead of an int-containing-an-address. BUG=none BRANCH=none TEST=building with USB_DEBUG works Change-Id: Idd0c43031a212c8f3b6489f533c488805d98d6a9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8660f6091bb124eeabe73302e8c7f1a8e46324f1 Original-Change-Id: I266efcb8b939d6da104ad05a3e79a78065c60beb Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308762 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: yunzhi li <lyz(a)rock-chips.com> --- payloads/libpayload/drivers/udc/dwc2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/udc/dwc2.c b/payloads/libpayload/drivers/udc/dwc2.c index b38a0de..03691e7 100644 --- a/payloads/libpayload/drivers/udc/dwc2.c +++ b/payloads/libpayload/drivers/udc/dwc2.c @@ -563,7 +563,7 @@ static void dwc2_outep_intr(struct usbdev_ctrl *this, dwc2_ep_t *ep) usb_debug("DEPINT_SETUP\n"); writel(DXEPINT_SETUP, &ep->ep_regs->depint); #ifdef USB_DEBUG - hexdump((unsigned int)p->setup_buf, sizeof(dev_req_t)); + hexdump(p->setup_buf, sizeof(dev_req_t)); #endif SIMPLEQ_REMOVE_HEAD(&p->eps[0][0].job_queue, queue); p->eps[0][0].busy = 0;

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Patch set updated for coreboot: libpayload: Avoid confusing usb debug output in dwc2 driver
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12259 -gerrit commit 3859a025fa59a681ae5dd55af977a80a71aa7546 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Oct 26 19:48:25 2015 +0100 libpayload: Avoid confusing usb debug output in dwc2 driver enqueue_packet already runs start_ep_transfer, which enqueues the next job. It's pretty much guaranteed that the port will look busy. BUG=none BRANCH=none TEST=no spurious ep 0-0 busy messages Change-Id: I9cbfa7b51dd37564262295ddbcdd0755da40c05b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8997dbd78dc363334f4e22eaa61f25de1449ffba Original-Change-Id: I8a39713fc1d6f16b80284e0f21dc95685716a9b7 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308763 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: yunzhi li <lyz(a)rock-chips.com> --- payloads/libpayload/drivers/udc/dwc2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/udc/dwc2.c b/payloads/libpayload/drivers/udc/dwc2.c index 03691e7..32d6a5d 100644 --- a/payloads/libpayload/drivers/udc/dwc2.c +++ b/payloads/libpayload/drivers/udc/dwc2.c @@ -519,8 +519,8 @@ static void complete_ep_transfer(struct usbdev_ctrl *this, int endpoint, if (endpoint == 0 && job->xfered_length == 0) dwc2_enqueue_packet(this, 0, 0, p->setup_buf, 8, 0, 0); - - start_ep_transfer(p, endpoint, in_dir); + else + start_ep_transfer(p, endpoint, in_dir); } static void dwc2_outep_intr(struct usbdev_ctrl *this, dwc2_ep_t *ep)

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coreboot-gerrit November 2015