Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12326
-gerrit
commit 0e3e547a4f32e16e7513af9b48f9ae6c6fb302b2
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Wed Nov 4 15:46:00 2015 +0100
nb/intel/sandybridge: Limit GFX workaround to Sandy Bridge
The touched workaround for Sandy Bridge reserves two memory regions that
could cause graphics corruption if mapped by the integrated graphics
device. To the best of our knowledge, the workaround is not needed for
Ivy Bridge revisions.
Tested on kontron/ktqm77 (Ivy Bridge): Booted Linux and checked the
memory regions are not reserved. Couldn't test on Sandy Bridge, due to
lack of hardware.
Change-Id: I4273d1d804b490cf93c23426782eb1ffaf29f7d4
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
src/northbridge/intel/sandybridge/northbridge.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 08a0c9d..bfc5de8 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -124,9 +124,11 @@ static void add_fixed_resources(struct device *dev, int index)
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
#endif
- /* Required for SandyBridge sighting 3715511 */
- bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
- bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ /* Required for SandyBridge sighting 3715511 */
+ bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
+ bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
+ }
/* Reserve IOMMU BARs */
const u32 capid0_a = pci_read_config32(dev, 0xe4);
Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12319
-gerrit
commit d29bc284cd3b3d1dd80591a7221120f9b6578217
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 3 22:04:45 2015 -0600
src: Make maximum reboot count user configurable
In discusson with mrnuke on IRC it was suggested to make the maximum
reboot count a user-configurable variable in Kconfig. The idea
was to allow the user to tweak coreboot to fit his or her general use
case; for example, during development on a laptop a low reboot count
may be desired, while in a production situation a very high reboot
count may reduce maintainance burden. Right now the user would need
to manually edit the Kconfig file of his or her board to modify the
maximum reboot count, which is hardly intuitive.
Change-Id: Ibe54ed14a6500eaa4a25f33f34f3c78216e6ccd6
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
---
src/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/Kconfig b/src/Kconfig
index 865f7f5..ea0499e 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1107,7 +1107,7 @@ config REG_SCRIPT
Internal option that controls whether we compile in register scripts.
config MAX_REBOOT_CNT
- int
+ int "Maximum reboot count"
default 3
help
Internal option that sets the maximum number of bootblock executions allowed
the following patch was just integrated into master:
commit 9d9ce0d6d2ed3e5a2a81407a835a7e8d6490fe1f
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Mon Oct 26 12:59:49 2015 +0100
nb/intel/sandybridge: Add ACPI DMAR table
Add a DMAR table to advertise IOMMU and IRQ remapping capabilities to
the OS.
Tested with kontron/ktqm77. Under Linux, the table is detected and
interrupt remapping is enabled automatically.
Change-Id: Id6ee601a0a8543ed09c6bb8d308a3a3549fc34e5
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Reviewed-on: http://review.coreboot.org/12195
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)google.com>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/12195 for details.
-gerrit
the following patch was just integrated into master:
commit bb9469c450a12b876fca3a8c5e02af97c0ef36a1
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Wed Oct 21 11:49:23 2015 +0200
nb/intel/sandybridge: Enable basic IOMMU support
Sandy Bridge and Ivy Bridge processors have two IOMMU units. One for the
integrated graphics controller and one for all other PCI devices. Assign
resources for both IOMMUs and apply some quirks.
Tested with kontron/ktqm77 and a Muen based system that makes use of the
IOMMUs. Not tested on Sandy Bridge, but register dumps show the same
settings that are applied here.
Change-Id: I43b5e20b750e7529f448acac35de173185678fd9
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Reviewed-on: http://review.coreboot.org/12194
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)google.com>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/12194 for details.
-gerrit
the following patch was just integrated into master:
commit b2dae79301d2bb19e17a4c8960b11a16800574f8
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Mon Oct 26 12:34:02 2015 +0100
sb/intel/bd82x6x: Assign unique bus/dev/fn for I/O APIC + HPETs
Assign unique bus/dev/fn values for the I/O APIC and each HPET. The
values are taken from an example DMAR table. They are used as source-id
for MSI requests and as completer-id for reads from the device' MMIO
space [1, 2]. The former is usefull for source-id verfication during
interrupt remapping.
[1] Intel 6 Series Chipset and Intel C200 Series Chipset
Datasheet
Document-Number: 324645
[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)
Datasheet
Document-Number: 326776
Change-Id: Ib46f8cfb7d966dd1cf2b026f671bc45ffcc43d25
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Reviewed-on: http://review.coreboot.org/12193
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)google.com>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/12193 for details.
-gerrit
the following patch was just integrated into master:
commit bc39b488a5a721521b7256b7a1ac3a4f664b400d
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 3 22:11:51 2015 -0600
mainboard/asus: Increase reboot count on boards with recovery jumper
On server boards with a recovery jumper, having the fallback path
less sensitive to power fluctuations or BMC issues makes sense.
Increase the maximum number of boot attempts before automatic
fallback to 10 on these boards.
Change-Id: Iabe0b0cbf332686db8e9380a8b65a1477173599c
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12320
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See http://review.coreboot.org/12320 for details.
-gerrit
the following patch was just integrated into master:
commit 6c4751d5965c3c8d87b21c39efd66ccc26ff5823
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Mon Oct 26 12:03:54 2015 +0100
ACPI: Add functions for DMAR I/O-APIC and HPET entries
Refactor acpi_create_dmar_drhd_ds_pci() and add similar functions for
I/O-APICs and MSI capable HPETs. We violate the spec [1] here, which
talks about 16-bit source-ids spread over start_bus and path entries.
Intel actually uses bus/dev/fn identification for those devices too,
and so do we.
[1] Intel Virtualization Technology for Directed I/O
Architecture Specification
Document-Number: D51397
Change-Id: I0fce075961762610d44b5552b71e010511871fc2
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Reviewed-on: http://review.coreboot.org/12192
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)google.com>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/12192 for details.
-gerrit
the following patch was just integrated into master:
commit e561f35fa5126e89b568292864acd8b9b95377e0
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Mon Oct 26 11:51:25 2015 +0100
ACPI: Make DMAR flags settable
Add a parameter to acpi_create_dmar() for the flags field and define
flags given by the spec [1].
[1] Intel Virtualization Technology for Directed I/O
Architecture Specification
Document-Number: D51397
Change-Id: I03ae32f13bb0061bd3b9bef607db175d9b0bc5e1
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Reviewed-on: http://review.coreboot.org/12191
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)google.com>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/12191 for details.
-gerrit
Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12326
-gerrit
commit 237bb37c88faf6f617ef2f6e86e9b15dcda24aa2
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Wed Nov 4 15:46:00 2015 +0100
nb/intel/sandybridge: Limit GFX workaround to Sandy Bridge
The touched workaround for Sandy Bridge reserves two memory regions that
could cause graphics corruption if mapped by the integrated graphics
device. To the best of our knowledge, the workaround is not needed for
Ivy Bridge revisions.
Tested on kontron/ktqm77 (Ivy Bridge): Booted Linux and checked the
memory regions are not reserved. Couldn't test on Sandy Bridge, due to
lack of hardware.
Change-Id: I4273d1d804b490cf93c23426782eb1ffaf29f7d4
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
src/northbridge/intel/sandybridge/northbridge.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 09830de..96ddc0b 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -124,9 +124,11 @@ static void add_fixed_resources(struct device *dev, int index)
CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
#endif
- /* Required for SandyBridge sighting 3715511 */
- bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
- bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ /* Required for SandyBridge sighting 3715511 */
+ bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
+ bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
+ }
}
static void pci_domain_set_resources(device_t dev)