coreboot-gerrit November 2015

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Patch set updated for coreboot: superio/windbond: Add WPCD376I device
by Marc Jones 05 Nov '15

05 Nov '15

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12165 -gerrit commit 83c8433756c9d855f5ecd237cbb9c627f9560566 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Wed Sep 16 17:58:35 2015 -0600 superio/windbond: Add WPCD376I device The Winbond WPCD376I is a desktop Super I/O often selected on Intel mainboards. The support is similar to other Winbond and NSC SIOs. Based on output from superiotool -d. Change-Id: Ib4786b410b1d83606e8d79a9f686c14a5d25cadf Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/superio/winbond/Kconfig | 4 ++ src/superio/winbond/Makefile.inc | 1 + src/superio/winbond/wpcd376i/Makefile.inc | 23 +++++++++ src/superio/winbond/wpcd376i/chip.h | 27 ++++++++++ src/superio/winbond/wpcd376i/early_serial.c | 34 +++++++++++++ src/superio/winbond/wpcd376i/superio.c | 79 +++++++++++++++++++++++++++++ src/superio/winbond/wpcd376i/wpcd376i.h | 37 ++++++++++++++ 7 files changed, 205 insertions(+) diff --git a/src/superio/winbond/Kconfig b/src/superio/winbond/Kconfig index a08d5af..2eeb725 100644 --- a/src/superio/winbond/Kconfig +++ b/src/superio/winbond/Kconfig @@ -50,3 +50,7 @@ config SUPERIO_WINBOND_W83697HF config SUPERIO_WINBOND_W83977TF bool select SUPERIO_WINBOND_COMMON_ROMSTAGE + +config SUPERIO_WINBOND_WPCD376I + bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc index 6fd447e..7d5e30d 100644 --- a/src/superio/winbond/Makefile.inc +++ b/src/superio/winbond/Makefile.inc @@ -27,3 +27,4 @@ subdirs-y += w83627thg subdirs-y += w83627uhg subdirs-y += w83697hf subdirs-y += w83977tf +subdirs-y += wpcd376i diff --git a/src/superio/winbond/wpcd376i/Makefile.inc b/src/superio/winbond/wpcd376i/Makefile.inc new file mode 100644 index 0000000..9ff2425 --- /dev/null +++ b/src/superio/winbond/wpcd376i/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2000 AG Electronics Ltd. +## Copyright (C) 2003-2004 Linux Networx +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +romstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += early_serial.c +ramstage-$(CONFIG_SUPERIO_WINBOND_WPCD376I) += superio.c diff --git a/src/superio/winbond/wpcd376i/chip.h b/src/superio/winbond/wpcd376i/chip.h new file mode 100644 index 0000000..d0d5748 --- /dev/null +++ b/src/superio/winbond/wpcd376i/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef SUPERIO_WINBOND_WPCD376I_CHIP_H +#define SUPERIO_WINBOND_WPCD376I_CHIP_H + +struct superio_winbond_wpcd376i_config { +}; +#endif diff --git a/src/superio/winbond/wpcd376i/early_serial.c b/src/superio/winbond/wpcd376i/early_serial.c new file mode 100644 index 0000000..009471d --- /dev/null +++ b/src/superio/winbond/wpcd376i/early_serial.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Jones <marcj303(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Pre-RAM driver for the Winbond WPCD376I Super I/O chip. */ + + +#include <arch/io.h> +#include <device/pnp_def.h> +#include "wpcd376i.h" + +void wpcd376i_enable_serial(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c new file mode 100644 index 0000000..d54c4af --- /dev/null +++ b/src/superio/winbond/wpcd376i/superio.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <drivers/uart/uart8250reg.h> +#include <pc80/keyboard.h> +#include <arch/io.h> +#include <stdlib.h> +#include "chip.h" +#include "wpcd376i.h" + +static void init(device_t dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + + case WPCD376I_FDC: + case WPCD376I_LPT: + case WPCD376I_IR: + case WPCD376I_SP1: + case WPCD376I_SWC: + case WPCD376I_KBCM: + case WPCD376I_GPIO: + break; + + case WPCD376I_KBCK: + pc_keyboard_init(); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, WPCD376I_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, }, + { &ops, WPCD376I_LPT, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, }, + { &ops, WPCD376I_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, WPCD376I_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, WPCD376I_KBCM, PNP_IRQ0, }, + { &ops, WPCD376I_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, + { &ops, WPCD376I_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_winbond_wpcd376i_ops = { + CHIP_NAME("Winbond WPCD376I Super I/O") + .enable_dev = enable_dev, +}; diff --git a/src/superio/winbond/wpcd376i/wpcd376i.h b/src/superio/winbond/wpcd376i/wpcd376i.h new file mode 100644 index 0000000..195b914 --- /dev/null +++ b/src/superio/winbond/wpcd376i/wpcd376i.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef SUPERIO_WINBOND_WPCD376I_WPCD376I_H +#define SUPERIO_WINBOND_WPCD376I_WPCD376I_H + +/* Logical Device Numbers (LDN). */ +#define WPCD376I_FDC 0 /* Floppy */ +#define WPCD376I_LPT 1 /* Parallel port */ +#define WPCD376I_IR 2 /* Infrared port */ +#define WPCD376I_SP1 3 /* UART1 */ +#define WPCD376I_SWC 4 /* System wake-up control */ +#define WPCD376I_KBCM 5 /* PS/2 mouse */ +#define WPCD376I_KBCK 6 /* PS/2 keyboard */ +#define WPCD376I_GPIO 7 /* General Purpose I/O */ + +void wpcd376i_enable_serial(device_t dev, u16 iobase); + +#endif

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Patch set updated for coreboot: Documentation: coreboot Gerrit Etiquette and Guidelines
by Martin Roth 04 Nov '15

04 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12256 -gerrit commit f6977fc224238f2fd4f89f7134cad59b5f068050 Author: Martin Roth <martinroth(a)google.com> Date: Thu Oct 29 12:43:10 2015 -0600 Documentation: coreboot Gerrit Etiquette and Guidelines As the community has grown, so has the need to formalize some of the guidelines that the community lives by. When the community was small, it was easy to communicate these things just from one person to another. Now, with more people joining the community every day, it seems that it's time to write some of these things down, allowing people to understand our policies immediately instead of making them learn our practices as they make mistakes. As it says in the document: The following rules are the requirements for behavior in the coreboot codebase in gerrit. These have mainly been unwritten rules up to this point, and should be familiar to most users who have been active in coreboot for a period of time. Following these rules will help reduce friction in the community. Change-Id: If80e933fcfb04b86fd5efe6423cda448118d7a3c Signed-off-by: Martin Roth <martinroth(a)google.com> --- Documentation/gerrit_guidelines.md | 263 +++++++++++++++++++++++++++++++++++++ 1 file changed, 263 insertions(+) diff --git a/Documentation/gerrit_guidelines.md b/Documentation/gerrit_guidelines.md new file mode 100644 index 0000000..3140ff5 --- /dev/null +++ b/Documentation/gerrit_guidelines.md @@ -0,0 +1,263 @@ +coreboot Gerrit Etiquette and Guidelines +======================================== + +The following rules are the requirements for behavior in the coreboot +codebase in gerrit. These have mainly been unwritten rules up to this +point, and should be familiar to most users who have been active in +coreboot for a period of time. Following these rules will help reduce +friction in the community. + +Note that as with many rules, there are exceptions. Some have been noted +in the 'More Detail' section. If you feel there is an exception not listed +here, please discuss it in the mailing list to get this document updated. +Don't just assume that it's okay, even if someone on IRC says it is. + + +Summary: +-------- +These are the expectations for committing, reviewing, and submitting code +into coreboot git and gerrit. While breaking individual rules may not have +immediate consequences, the coreboot leadership may act on repeated or +flagrant violations with or without notice. + +* Don't violate the licenses. +* Let non-trivial patches sit in a review state for at least 24 hours +before submission. +* Try to coordinate with platform maintainers when making changes to +platforms. +* If you give a patch a -2, you are responsible for giving concrete +recommendations for what could be changed to resolve the issue the patch +addresses. +* Don't modify other people's patches without their consent. +* Be respectful to others when commenting. +* Don’t submit patches that you know will break other platforms. + + +More detail: +------------ +* Don't violate the licenses. If you're submitting code that you didn't +write yourself, make sure the license is compatible with the license of the +project you're submitting the changes to. If you’re submitting code that +you wrote that might be owned by your employer, make sure that your +employer is aware and you are authorized to submit the code. For +clarification, see the Developer's Certificate of Origin in the coreboot +[Signed-off-by policy](http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure). + +* Let non-trivial patches sit in a review state for at least 24 hours +before submission. Remember that there are coreboot developers in timezones +all over the world, and everyone should have a chance to contribute. +Trivial patches would be things like whitespace changes or spelling fixes. +In general, small changes that don’t impact the final binary output. The +24-hour period would start at submission, and would be restarted at any +update which significantly changes any part of the patch. Patches can be +'Fast-tracked' and submitted in under this 24 hour with the agreement of at +least 3 +2 votes. + +* Do not +2 patches that you authored or own, even for something as trivial +as whitespace fixes. When working on your own patches, it’s easy to +overlook something like accidentally updating file permissions or git +submodule commit IDs. Let someone else review the patch. An exception to +this would be if two people worked in the patch together. If both +2 the +patch, that is acceptable, as each is giving a +2 to the other's work. + +* Try to coordinate with platform maintainers and other significant +contributors to the code when making changes to platforms. The platform +maintainers are the users who initially pushed the code for that platform, +as well as users who have made significant changes to a platform. To find +out who maintains a piece of code, please use util/scripts/maintainers.go +or refer to the original author of the code in git log. + +* If you give a patch a -2, you are responsible for giving concrete +recommendations for what could be changed to resolve the issue the patch +addresses. If you feel strongly that a patch should NEVER be merged, you +are responsible for defending your position and listening to other points +of view. Giving a -2 and walking away is not acceptable, and may cause your + -2 to be removed by the coreboot leadership after no less than a week. A + notification that the -2 will be removed unless there is a response will + be sent out at least 2 days before it is removed. + +* Don't modify other people's patches unless you have coordinated this with +the owner of that patch. Not only is this considered rude, but your changes +could be unintentionally lost. An exception to this would be for patches +that have not been updated for more than 90 days. In that case, the patch +can be taken over if the original author does not respond to requests for +updates. Alternatively, a new patch can be pushed with the original +content, and both patches should be updated to reference the other. + +* Be respectful to others when commenting on patches. Comments should +be kept to the code, and should be kept in a polite tone. We are a +worldwide community and English is a difficult language. Assume your +colleagues are intelligent and do not intend disrespect. Resist the urge to +retaliate against perceived verbal misconduct, such behavior is not +conducive to getting patches merged. + +* Don’t submit code that you know will break other platforms. If your patch +affects code that is used by other platforms, it should be compatible with +those platforms. While it would be nice to update any other platforms, you +must at least provide a path that will allow other platforms to continue +working. + + +Recommendations for gerrit activity: +------------------------------------ +These guidelines are less strict than the ones listed above. These are more +of the “good idea” variety. You are requested to follow the below +guidelines, but there will probably be no actual consequences if they’re +not followed. That said, following the recommendations below will speed up +review of your patches, and make the members of the community do less work. + +* Each patch should be kept to one logical change, which should be +described in the title of the patch. Unrelated changes should be split out +into separate patches. Fixing whitespace on a line you’re editing is +reasonable. Fixing whitespace around the code you’re working on should be a +separate ‘cleanup’ patch. Larger patches that touch several areas are fine, +so long as they are one logical change. Adding new chips and doing code +cleanup over wide areas are two examples of this. + +* Test your patches before submitting them to gerrit. It's also appreciated +if you add a line to the commit message describing how the patch was +tested. This prevents people from having to ask whether and how the patch +was tested. Examples of this sort of comment would be ‘TEST=Built +platform’ or ‘Tested by building and booting platform’. Stating that the +patch was not tested is also fine, although you might be asked to do some +testing in cases where that would be reasonable. + +* Take advantage of the lint tools to make sure your patches don’t contain +trivial mistakes. By running ‘make gitconfig’, the lint-stable tools are +automatically put in place and will test your patches before they are +committed. As a violation of these tools will cause the jenkins build test +to fail, it’s to your advantage to test this before pushing to gerrit. + +* Don't submit patch trains longer than around 20 patches unless you +understand how to manage long patch trains. Long patch trains can become +difficult to handle and tie up the build servers for long periods of time +if not managed well. Rebasing a patch train over and over as you fix +earlier patches in the train can hide comments, and make people review the +code multiple times to see if anything has changed between revisions. When +pushing long patch trains, it is recommended to only push the full patch +train once - the initial time, and only to rebase three or four patches at +a time. + +* Run 'make what-jenkins-does' locally on patch trains before submitting. +This helps verify that the patch train won’t tie up the jenkins builders +for no reason if there are failing patches in the train. For running +parallel builds, you can specify the number of cores to use by setting the +the CPUS environment variable. Example: + make what-jenkins-does CPUS=8 + +* Use a topic when pushing a train of patches. This groups the commits +together so people can easily see the connection at the top level of +gerrit. Topics can be set for individual patches in gerrit by going into +the patch and clicking on the icon next to the topic line. Topics can also +be set when you push the patches into gerrit. For example, to push a set of +commits with the the i915-kernel-x60 set, use the command: + git push origin HEAD:refs/for/master/i915-kernel-x60 + +* If one of your patches isn't ready to be merged, make sure it's obvious +that you don't feel it's ready for merge yet. The preferred way to show +this is by marking in the commit message that it’s not ready until X. The +commit message can be updated easily when it’s ready to be pushed. +Examples of this are "WIP: title" or "[NEEDS_TEST]: title". Another way to +mark the patch as not ready would be to give it a -1 or -2 review, but +isn't as obvious as the commit message. These patches can also be pushed as +drafts as shown in the next guideline. + +* When pushing patches that are not for submission, these should be marked +as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as +draft commits, so that only explicitly added reviewers will see them. These +sorts of patches are frequently posted as ideas or RFCs for the community +to look at. To push a draft, use the command: + git push origin HEAD:refs/drafts/master + +* Respond to anyone who has taken the time to review your patches, even if +it's just to say that you disagree. While it may seem annoying to address a +request to fix spelling or 'trivial' issues, it’s generally easy to handle +in gerrit’s built-in editor. If you do use the built-in editor, remember to +get that change to your local copy before re-pushing. It's also acceptable +to add fixes for these sorts of comments to another patch, but it's +recommended that that patch be pushed to gerrit before the initial patch +gets submitted. + +* Consider breaking up large individual patches into smaller patches +grouped by areas. This makes the patches easier to review, but increases +the number of patches. The way you want to handle this is a personal +decision, as long as each patch is still one logical change. + +* If you have an interest in a particular area or mainboard, set yourself +up as a ‘maintainer’ of that area by adding yourself to the MAINTAINERS +file in the coreboot root directory. Eventually, this should automatically +add you as a reviewer when an area that you’re listed as a maintainer is +changed. + +* Submit mainboards that you’re working on to the board-status repo. This +helps others and shows that these mainboards are currently being +maintained. At some point, boards that are not up to date in the +board-status repo will probably end up getting removed from the coreboot +master branch. + +* Abandon patches that are no longer useful, or that you don’t intend to +keep working on to get submitted. + +* Bring attention to patches that you would like reviewed. Add reviewers, +ask for reviewers on IRC or even just rebase it against the current +codebase to bring it to the top of the gerrit list. If you’re not sure who +would be a good reviewer, look in the MAINTAINERS file or git history of +the files that you’ve changed, and add those people. + +* Familiarize yourself with the coreboot [commit message +guidelines](http://www.coreboot.org/Git#Commit_messages), before pushing +patches. This will help to keep annoying requests to fix your commit +message to a minimum. + +* If there have been comments or discussion on a patch, verify that the +comments have been addressed before giving a +2. If you feel that a comment +is invalid, please respond to that comment instead of just ignoring it. + +* Be conscientious when reviewing patches. As a reviewer who approves (+2) +a patch, you are responsible for the patch and the effect it has on the +codebase. In the event that the patch breaks things, you are expected to +be actively involved in the cleanup effort. This means you shouldn’t +2 a +patch just because you trust the author of a patch - Make sure you +understand what the implications of a patch might be, or leave the review +to others. Partial reviews, reviewing code style, for example, can be given +a +1 instead of a +2. This also applies if you think the patch looks good, +but may not have the experience to know if there may be unintended +consequences. + +* If there is still ongoing discussion to a patch, try to wait for a +conclusion to the discussion before submitting it to the tree. If you feel +that someone is just bikeshedding, maybe just state that and give a time +that the patch will be submitted if no new objections are raised. + +* When working with patch trains, for minor requests it’s acceptable to +create a fix addressing a comment in another patch at the end of the patch +train. This minimizes rebases of the patch train while still addressing the +request. For major problems where the change doesn’t work as intended or +breaks other platforms, the change really needs to go into the original +patch. + + +Expectations contributors should have: +-------------------------------------- +* Don't expect that people will review your patch unless you ask them to. +Adding other people as reviewers is the easiest way. Asking for reviews for +individual patches in the IRC channel, or by sending a direct request to an +individual through your favorite messenger is usually the best way to get a +patch reviewed quickly. + +* Don't expect that your patch will be submitted immediately after getting +a +2. As stated previously, non-trivial patches should wait at least 24 +hours before being submitted. That said, if you feel that your patch or +series of patches has been sitting longer than needed, you can ask for it +to be submitted on IRC, or comment that it's ready for submission in the +patch. This will move it to the top of the list where it's more likely to +be noticed and acted upon. + +* Reviews are about the code. It's easy to take it personally when someone +is criticising your code, but the whole idea is to get better code into our +codebase. Again, this also applies in the other direction: review code, +criticize code, but don’t make it personal. + + +Requests for clarification and suggestions for updates to these guidelines +should be sent to the coreboot mailing list at <coreboot(a)coreboot.org>.

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Patch set updated for coreboot: libpayload: xhci: Add delay to get reset working more reliably
by Patrick Georgi 04 Nov '15

04 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12325 -gerrit commit 9bce072cf13125222ca87ce66f41f3a309d02210 Author: Rajmohan Mani <rajmohan.mani(a)intel.com> Date: Fri Oct 30 17:00:24 2015 -0700 libpayload: xhci: Add delay to get reset working more reliably Existing Intel xHCI controllers require a delay of 1 ms, after setting the CMD_RESET bit in command register, before accessing any HC registers. This allows the HC to complete the reset operation and be ready for HC register access. Without this delay, the subsequent HC register access, may result in a system hang, very rarely. Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles (which was not possible without this patch), without any xHCI reset hang in depthcharge. BRANCH=None BUG=None TEST=Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles, without any xHCI reset hang in depthcharge. Change-Id: I8eff5115ca52738bdcf8bc65fbfb2a5f60a0abe1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3e7ea70df36e3bf35a6ee1297640900ee76bfdac Original-Change-Id: Id681a19d0eedb0e2c29e259c5467bcde577e3460 Original-Signed-off-by: Rajmohan Mani <rajmohan.mani(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310022 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/drivers/usb/xhci.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 71272c7..d223d0f 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -328,6 +328,17 @@ xhci_reset(hci_t *const controller) xhci_stop(controller); xhci->opreg->usbcmd |= USBCMD_HCRST; + + /* Existing Intel xHCI controllers require a delay of 1 ms, + * after setting the CMD_RESET bit, and before accessing any + * HC registers. This allows the HC to complete the + * reset operation and be ready for HC register access. + * Without this delay, the subsequent HC register access, + * may result in a system hang very rarely. + */ + if (IS_ENABLED(CONFIG_LP_ARCH_X86)) + mdelay(1); + xhci_debug("Resetting controller... "); if (!xhci_handshake(&xhci->opreg->usbcmd, USBCMD_HCRST, 0, 1000000L)) usb_debug("timeout!\n");

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Patch set updated for coreboot: util/kconfig: fill glob_t with 0 before calling glob
by Stefan Reinauer 04 Nov '15

04 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11711 -gerrit commit b7c2a7c97fca95106c6bec5edfcd6f42d68ed8a2 Author: zbao <fishbaozi(a)gmail.com> Date: Sat Sep 26 06:49:47 2015 -0400 util/kconfig: fill glob_t with 0 before calling glob On mingw, the function glob has some default options which are not compliant with man page. If gl_offs is not set as 0, there may be some slots which is reserved. If gl_pathc or gl_pathv is not set as 0, the result might be appended to the list instead of being added as new ones. Change-Id: I03110c4cdda70578828d6499262a085a81d26313 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/kconfig/zconf.l | 2 +- util/kconfig/zconf.lex.c_shipped | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/util/kconfig/zconf.l b/util/kconfig/zconf.l index b6bed02..0b45c19 100644 --- a/util/kconfig/zconf.l +++ b/util/kconfig/zconf.l @@ -339,7 +339,7 @@ void zconf_nextfile(const char *name) void zconf_nextfiles(const char *wildcard) { - glob_t g; + glob_t g = {0}; char **w; int i; diff --git a/util/kconfig/zconf.lex.c_shipped b/util/kconfig/zconf.lex.c_shipped index cf05b19..72e3a5f 100644 --- a/util/kconfig/zconf.lex.c_shipped +++ b/util/kconfig/zconf.lex.c_shipped @@ -2417,7 +2417,7 @@ void zconf_nextfile(const char *name) void zconf_nextfiles(const char *wildcard) { - glob_t g; + glob_t g = {0}; char **w; int i;

1 0

Patch set updated for coreboot: util/kconfig: fill glob_t with 0 before calling glob
by Stefan Reinauer 04 Nov '15

04 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11711 -gerrit commit 4c3c49655ae0117df898df864d86ee65dcc5c4f2 Author: zbao <fishbaozi(a)gmail.com> Date: Sat Sep 26 06:49:47 2015 -0400 util/kconfig: fill glob_t with 0 before calling glob On mingw, the function glob has some default options which are not compliant with man page. If gl_offs is not set as 0, there may be some slots which is reserved. If gl_pathc or gl_pathv is not set as 0, the result might be appended to the list instead of being added as new ones. Change-Id: I03110c4cdda70578828d6499262a085a81d26313 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/kconfig/zconf.l | 2 +- util/kconfig/zconf.lex.c_shipped | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/util/kconfig/zconf.l b/util/kconfig/zconf.l index b6bed02..0b45c19 100644 --- a/util/kconfig/zconf.l +++ b/util/kconfig/zconf.l @@ -339,7 +339,7 @@ void zconf_nextfile(const char *name) void zconf_nextfiles(const char *wildcard) { - glob_t g; + glob_t g = {0}; char **w; int i; diff --git a/util/kconfig/zconf.lex.c_shipped b/util/kconfig/zconf.lex.c_shipped index cf05b19..99a437b 100644 --- a/util/kconfig/zconf.lex.c_shipped +++ b/util/kconfig/zconf.lex.c_shipped @@ -2421,6 +2421,9 @@ void zconf_nextfiles(const char *wildcard) char **w; int i; + g.gl_pathc = 0; + g.gl_pathv = NULL; + g.gl_offs = 0; if (glob(wildcard, 0, NULL, &g) != 0) { return; }

1 0

Patch set updated for coreboot: mainboard/asus: Add F2A85-M PRO variant to F2A85-M.
by Stefan Reinauer 04 Nov '15

04 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12301 -gerrit commit 605c8fc7a6a6f9e32df3ee475f4f31eb9b7433a8 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Jul 26 19:57:51 2015 +0200 mainboard/asus: Add F2A85-M PRO variant to F2A85-M. Change-Id: I78389dc1fd19a2354daec0484042940cf8b490ae Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c | 1 + src/mainboard/asus/f2a85-m_pro/Kconfig | 93 ++++++++++++++ src/mainboard/asus/f2a85-m_pro/Kconfig.name | 2 + src/mainboard/asus/f2a85-m_pro/Makefile.inc | 26 ++++ src/mainboard/asus/f2a85-m_pro/OptionsIds.h | 1 + src/mainboard/asus/f2a85-m_pro/PlatformGnbPcie.c | 1 + .../asus/f2a85-m_pro/PlatformGnbPcieComplex.h | 1 + src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi/routing.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi/sata.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi/si.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi/superio.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl | 1 + src/mainboard/asus/f2a85-m_pro/acpi_tables.c | 1 + src/mainboard/asus/f2a85-m_pro/board_info.txt | 7 ++ src/mainboard/asus/f2a85-m_pro/buildOpts.c | 1 + src/mainboard/asus/f2a85-m_pro/cmos.layout | 79 ++++++++++++ src/mainboard/asus/f2a85-m_pro/devicetree.cb | 136 +++++++++++++++++++++ src/mainboard/asus/f2a85-m_pro/dsdt.asl | 1 + src/mainboard/asus/f2a85-m_pro/irq_tables.c | 1 + src/mainboard/asus/f2a85-m_pro/mainboard.c | 1 + src/mainboard/asus/f2a85-m_pro/mptable.c | 1 + src/mainboard/asus/f2a85-m_pro/romstage.c | 1 + 28 files changed, 365 insertions(+) diff --git a/src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c b/src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c new file mode 100644 index 0000000..afa69bb --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c @@ -0,0 +1 @@ +#include "../f2a85-m/BiosCallOuts.c" diff --git a/src/mainboard/asus/f2a85-m_pro/Kconfig b/src/mainboard/asus/f2a85-m_pro/Kconfig new file mode 100644 index 0000000..b437ed6 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/Kconfig @@ -0,0 +1,93 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +if BOARD_ASUS_F2A85_M_PRO + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + select HUDSON_DISABLE_IMC + +choice + prompt "DDR3 memory voltage" + default BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_150 + +config BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_135 + bool "1.35V" + help + Set DRR3 memory voltage to 1.35V +config BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_150 + bool "1.50V" + help + Set DRR3 memory voltage to 1.50V +config BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_165 + bool "1.65V" + help + Set DRR3 memory voltage to 1.65V +endchoice + +config BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL + hex + default 0x9e if BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_135 + default 0x0 if BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_150 + default 0x1e if BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_165 + +config MAINBOARD_DIR + string + default asus/f2a85-m_pro + +config MAINBOARD_PART_NUMBER + string + default "F2A85-M_PRO" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS_ID + string + default "1002,9993" + +endif # BOARD_ASUS_F2A85_M_PRO diff --git a/src/mainboard/asus/f2a85-m_pro/Kconfig.name b/src/mainboard/asus/f2a85-m_pro/Kconfig.name new file mode 100644 index 0000000..e4b8dfd --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_F2A85_M_PRO + bool "F2A85-M PRO" diff --git a/src/mainboard/asus/f2a85-m_pro/Makefile.inc b/src/mainboard/asus/f2a85-m_pro/Makefile.inc new file mode 100644 index 0000000..0008d6d --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/Makefile.inc @@ -0,0 +1,26 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/asus/f2a85-m_pro/OptionsIds.h b/src/mainboard/asus/f2a85-m_pro/OptionsIds.h new file mode 100644 index 0000000..c702a9c --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/OptionsIds.h @@ -0,0 +1 @@ +#include "../f2a85-m/OptionsIds.h" diff --git a/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcie.c new file mode 100644 index 0000000..d83a779 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcie.c @@ -0,0 +1 @@ +#include "../f2a85-m/PlatformGnbPcie.c" diff --git a/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..f6f4c9a --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcieComplex.h @@ -0,0 +1 @@ +#include "../f2a85-m/PlatformGnbPcieComplex.h" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl b/src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl new file mode 100644 index 0000000..43c2428 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl @@ -0,0 +1 @@ +#include "../../f2a85-m/acpi/AmdImc.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl new file mode 100644 index 0000000..29c8d69 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl @@ -0,0 +1 @@ +#include "../../f2a85-m/acpi/cpstate.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl b/src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl new file mode 100644 index 0000000..4794311 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl @@ -0,0 +1 @@ +#include "../../f2a85-m/acpi/gpe.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl b/src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl new file mode 100644 index 0000000..f81742e --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl @@ -0,0 +1 @@ +#include "../../f2a85-m/acpi/mainboard.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/routing.asl b/src/mainboard/asus/f2a85-m_pro/acpi/routing.asl new file mode 100644 index 0000000..77a1f8a --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/routing.asl @@ -0,0 +1 @@ +#include "../../f2a85-m/acpi/routing.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/sata.asl b/src/mainboard/asus/f2a85-m_pro/acpi/sata.asl new file mode 100644 index 0000000..46bc2e6 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/sata.asl @@ -0,0 +1 @@ +#include "../../f2a85-m/acpi/sata.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/si.asl b/src/mainboard/asus/f2a85-m_pro/acpi/si.asl new file mode 100644 index 0000000..208e5c4 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/si.asl @@ -0,0 +1 @@ +#include "../../f2a85-m/acpi/si.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl b/src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl new file mode 100644 index 0000000..67e4e2b --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl @@ -0,0 +1 @@ +#include "../../f2a85-m/acpi/sleep.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/superio.asl b/src/mainboard/asus/f2a85-m_pro/acpi/superio.asl new file mode 100644 index 0000000..88a494d --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/superio.asl @@ -0,0 +1 @@ +#include "../../f2a85-m/acpi/superio.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl b/src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl new file mode 100644 index 0000000..3d529e5 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl @@ -0,0 +1 @@ +#include "../../f2a85-m/acpi/thermal.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl b/src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl new file mode 100644 index 0000000..1b3fba0 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl @@ -0,0 +1 @@ +include "../../f2a85-m/acpi/usb_oc.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/acpi_tables.c b/src/mainboard/asus/f2a85-m_pro/acpi_tables.c new file mode 100644 index 0000000..febb723 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/acpi_tables.c @@ -0,0 +1 @@ +#include "../f2a85-m/acpi_tables.c" diff --git a/src/mainboard/asus/f2a85-m_pro/board_info.txt b/src/mainboard/asus/f2a85-m_pro/board_info.txt new file mode 100644 index 0000000..52c5819 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: http://www.asus.com/Motherboards/F2A85M_PRO/ +ROM package: DIP8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: diff --git a/src/mainboard/asus/f2a85-m_pro/buildOpts.c b/src/mainboard/asus/f2a85-m_pro/buildOpts.c new file mode 100644 index 0000000..c9fc086 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/buildOpts.c @@ -0,0 +1 @@ +#include "../f2a85-m/buildOpts.c" diff --git a/src/mainboard/asus/f2a85-m_pro/cmos.layout b/src/mainboard/asus/f2a85-m_pro/cmos.layout new file mode 100644 index 0000000..50750a8 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/cmos.layout @@ -0,0 +1,79 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/f2a85-m_pro/devicetree.cb b/src/mainboard/asus/f2a85-m_pro/devicetree.cb new file mode 100644 index 0000000..4562557 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/devicetree.cb @@ -0,0 +1,136 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 blue + device pci 3.0 off end # unused? + device pci 4.0 on end # PCIE 4x black + device pci 5.0 off end # unused? + device pci 6.0 off end # unused? + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + register hwm_ctl_register = "0xc0" + register hwm_main_ctl_register = "0x33" + register hwm_adc_temp_chan_en_reg = "0x38" + register hwm_fan1_ctl_pwm = "0x00" + register hwm_fan2_ctl_pwm = "0x00" + register hwm_fan3_ctl_pwm = "0x00" + + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x228 #SMI + io 0x62 = 0x300 #Simple I/O + io 0x64 = 0x238 #Phony resource IT8603E does not have it + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 on end # PCIe 0 - onboard PCIe 1x + device pci 15.1 on end # PCIe 1 onboard gigabit + device pci 15.2 off end # unused + device pci 15.3 off end # unused + + end #chip southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/f2a85-m_pro/dsdt.asl b/src/mainboard/asus/f2a85-m_pro/dsdt.asl new file mode 100644 index 0000000..b27b81d --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/dsdt.asl @@ -0,0 +1 @@ +#include "../f2a85-m/dsdt.asl" diff --git a/src/mainboard/asus/f2a85-m_pro/irq_tables.c b/src/mainboard/asus/f2a85-m_pro/irq_tables.c new file mode 100644 index 0000000..7e6c693 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/irq_tables.c @@ -0,0 +1 @@ +#include "../f2a85-m/irq_tables.c" diff --git a/src/mainboard/asus/f2a85-m_pro/mainboard.c b/src/mainboard/asus/f2a85-m_pro/mainboard.c new file mode 100644 index 0000000..d8cc9c8 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/mainboard.c @@ -0,0 +1 @@ +#include "../f2a85-m/mainboard.c" diff --git a/src/mainboard/asus/f2a85-m_pro/mptable.c b/src/mainboard/asus/f2a85-m_pro/mptable.c new file mode 100644 index 0000000..1d0784d --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/mptable.c @@ -0,0 +1 @@ +#include <mainboard/asus/f2a85-m/mptable.c> diff --git a/src/mainboard/asus/f2a85-m_pro/romstage.c b/src/mainboard/asus/f2a85-m_pro/romstage.c new file mode 100644 index 0000000..0062c87 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_pro/romstage.c @@ -0,0 +1 @@ +#include "../f2a85-m/romstage.c"

1 0

Patch set updated for coreboot: libpayload: usb: xhci: Workaround to get Intel xHCI reset working more reliably
by Stefan Reinauer 04 Nov '15

04 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12325 -gerrit commit a5f84f680c7d4d837241a0b1cd6f9a32957f2b54 Author: Rajmohan Mani <rajmohan.mani(a)intel.com> Date: Fri Oct 30 17:00:24 2015 -0700 libpayload: usb: xhci: Workaround to get Intel xHCI reset working more reliably Existing Intel xHCI controllers require a delay of 1 mS, after setting the CMD_RESET bit in command register, before accessing any HC registers. This allows the HC to complete the reset operation and be ready for HC register access. Without this delay, the subsequent HC register access, may result in a system hang, very rarely. Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles (which was not possible without this patch), without any xHCI reset hang in depthcharge. BRANCH=None BUG=None TEST=Verified CherryView / Braswell platforms go through over 1000 warm reboot cycles, without any xHCI reset hang in depthcharge. Change-Id: I8eff5115ca52738bdcf8bc65fbfb2a5f60a0abe1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3e7ea70df36e3bf35a6ee1297640900ee76bfdac Original-Change-Id: Id681a19d0eedb0e2c29e259c5467bcde577e3460 Original-Signed-off-by: Rajmohan Mani <rajmohan.mani(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310022 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/drivers/usb/xhci.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 71272c7..d223d0f 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -328,6 +328,17 @@ xhci_reset(hci_t *const controller) xhci_stop(controller); xhci->opreg->usbcmd |= USBCMD_HCRST; + + /* Existing Intel xHCI controllers require a delay of 1 ms, + * after setting the CMD_RESET bit, and before accessing any + * HC registers. This allows the HC to complete the + * reset operation and be ready for HC register access. + * Without this delay, the subsequent HC register access, + * may result in a system hang very rarely. + */ + if (IS_ENABLED(CONFIG_LP_ARCH_X86)) + mdelay(1); + xhci_debug("Resetting controller... "); if (!xhci_handshake(&xhci->opreg->usbcmd, USBCMD_HCRST, 0, 1000000L)) usb_debug("timeout!\n");

1 0

New patch to review for coreboot: Revert "Drop SuperIO nuvoton/nct6779d"
by Stefan Reinauer 04 Nov '15

04 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12328 -gerrit commit fad456f408a0939d87828d26aa403ea8c0e4bb7e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 4 22:41:47 2015 +0200 Revert "Drop SuperIO nuvoton/nct6779d" This reverts commit 42444f6f53d47604d9a44c9e109b5717efaed74f. Change-Id: Ifaaaad715d94c3c9ff365745aa2e6ee546924f4f --- src/superio/nuvoton/Kconfig | 4 ++ src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/nct6779d/Makefile.inc | 21 ++++++++ src/superio/nuvoton/nct6779d/nct6779d.h | 56 +++++++++++++++++++ src/superio/nuvoton/nct6779d/superio.c | 89 +++++++++++++++++++++++++++++++ 5 files changed, 171 insertions(+) diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index f3dda1a..b1e4a57 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -32,3 +32,7 @@ config SUPERIO_NUVOTON_NCT5104D config SUPERIO_NUVOTON_NCT5572D bool select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT6779D + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 6173d86..bb6f635 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -23,3 +23,4 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d diff --git a/src/superio/nuvoton/nct6779d/Makefile.inc b/src/superio/nuvoton/nct6779d/Makefile.inc new file mode 100644 index 0000000..c8314f7 --- /dev/null +++ b/src/superio/nuvoton/nct6779d/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += superio.c diff --git a/src/superio/nuvoton/nct6779d/nct6779d.h b/src/superio/nuvoton/nct6779d/nct6779d.h new file mode 100644 index 0000000..b464025 --- /dev/null +++ b/src/superio/nuvoton/nct6779d/nct6779d.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef SUPERIO_NUVOTON_NCT6779D_H +#define SUPERIO_NUVOTON_NCT6779D_H + +/* Logical Device Numbers (LDN). */ +#define NCT6779D_PP 0x01 /* Parallel port */ +#define NCT6779D_SP1 0x02 /* Com1 */ +#define NCT6779D_SP2 0x03 /* Com2 & IR */ +#define NCT6779D_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT6779D_CIR 0x06 /* Consumer IR */ +#define NCT6779D_GPIO678_V 0x07 /* GPIO 6/7/8 */ +#define NCT6779D_WDT1_GPIO01_V 0x08 /* WDT1, GPIO 0/1 */ +#define NCT6779D_GPIO12345678_V 0x09 /* GPIO 1/2/3/4/5/6/7/8 */ +#define NCT6779D_ACPI 0x0A /* ACPI */ +#define NCT6779D_HWM_FPLED 0x0B /* Hardware monitor & front LED */ +#define NCT6779D_WDT1 0x0D /* Watchdog timer 1 */ +#define NCT6779D_CIRWKUP 0x0E /* CIR wakeup */ +#define NCT6779D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ +#define NCT6779D_PRT80 0x14 /* Port 80 UART */ +#define NCT6779D_DSLP 0x16 /* Deep sleep */ + + +/* virtual LDN for GPIO */ + +#define NCT6779D_GPIOBASE ((0 << 8) | NCT6779D_WDT1_GPIO01_V) + +#define NCT6779D_GPIO0 ((1 << 8) | NCT6779D_WDT1_GPIO01_V) +#define NCT6779D_GPIO1 ((1 << 8) | NCT6779D_GPIO12345678_V) +#define NCT6779D_GPIO2 ((2 << 8) | NCT6779D_GPIO12345678_V) +#define NCT6779D_GPIO3 ((3 << 8) | NCT6779D_GPIO12345678_V) +#define NCT6779D_GPIO4 ((4 << 8) | NCT6779D_GPIO12345678_V) +#define NCT6779D_GPIO5 ((5 << 8) | NCT6779D_GPIO12345678_V) +#define NCT6779D_GPIO6 ((6 << 8) | NCT6779D_GPIO12345678_V) +#define NCT6779D_GPIO7 ((7 << 8) | NCT6779D_GPIO12345678_V) +#define NCT6779D_GPIO8 ((0 << 8) | NCT6779D_GPIO12345678_V) + +#endif /* SUPERIO_NUVOTON_NCT6779D_H */ diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c new file mode 100644 index 0000000..79a25b7 --- /dev/null +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "nct6779d.h" + + +static void nct6779d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case NCT6779D_KBC: + pc_keyboard_init(); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6779d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, NCT6779D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, NCT6779D_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6779D_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6779D_ACPI}, + { &ops, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ffe, 0}, {0x0ffe, 4}, }, + { &ops, NCT6779D_WDT1}, + { &ops, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6779D_GPIO_PP_OD}, + { &ops, NCT6779D_PRT80}, + { &ops, NCT6779D_DSLP}, + { &ops, NCT6779D_GPIOBASE, PNP_IO0, {0x0ff8, 0}, }, + { &ops, NCT6779D_GPIO0}, + { &ops, NCT6779D_GPIO1}, + { &ops, NCT6779D_GPIO2}, + { &ops, NCT6779D_GPIO3}, + { &ops, NCT6779D_GPIO4}, + { &ops, NCT6779D_GPIO5}, + { &ops, NCT6779D_GPIO6}, + { &ops, NCT6779D_GPIO7}, + { &ops, NCT6779D_GPIO8}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6779d_ops = { + CHIP_NAME("NUVOTON NCT6779D Super I/O") + .enable_dev = enable_dev, +};

1 0

Patch merged into coreboot/master: buildgcc: change -j variable name from BUILDJOBS to CPUS
by gerrit＠coreboot.org 04 Nov '15

04 Nov '15

the following patch was just integrated into master: commit 11bee4019af70e666f14779f298ac2220aec59c3 Author: Martin Roth <martinroth(a)google.com> Date: Tue Oct 27 14:17:11 2015 -0600 buildgcc: change -j variable name from BUILDJOBS to CPUS The buildgcc makefile was using the variable 'BUILDJOBS' to pass the number of cores to use for the build into buildgcc. This is changed to 'CPUS' to match the variable name for the what-jenkins-does target. Change-Id: I373c4988e9f096ca2e142afdd5e94d7d806891e3 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/12299 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/12299 for details. -gerrit

1 0

New patch to review for coreboot: Kconfig: Remove obsolete Kconfig symbols from google/intel boards
by Martin Roth 04 Nov '15

04 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12327 -gerrit commit 36d54566b9922fae350dbeeecfd35c4fc711bcce Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 4 11:52:41 2015 -0700 Kconfig: Remove obsolete Kconfig symbols from google/intel boards - CACHE_ROM is no longer used in the coreboot code. It was removed in commit 4337020b (Remove CACHE_ROM.) - CAR_MIGRATION is also no longer used in coreboot code - it was removed in commit cbf5bdfe (CBMEM: Always select CAR_MIGRATION) - MARK_GRAPHICS_MEM_WRCOMB was removed in commit 30fe6120 (MTRR: Mark all prefetchable resources as WRCOMB) Change-Id: I8b33a08c256f6b022e57e9af60d0629d9a3ffac8 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/chell/Kconfig | 2 -- src/mainboard/google/cyan/Kconfig | 2 +- src/mainboard/google/glados/Kconfig | 2 -- src/mainboard/google/lars/Kconfig | 2 -- src/mainboard/intel/kunimitsu/Kconfig | 2 -- src/mainboard/intel/sklrvp/Kconfig | 2 -- src/soc/intel/skylake/Kconfig | 2 -- 7 files changed, 1 insertion(+), 13 deletions(-) diff --git a/src/mainboard/google/chell/Kconfig b/src/mainboard/google/chell/Kconfig index a419cf5..c7e2a18 100644 --- a/src/mainboard/google/chell/Kconfig +++ b/src/mainboard/google/chell/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 - select CACHE_ROM select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_LPC @@ -16,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select MARK_GRAPHICS_MEM_WRCOMB select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index e4dc322..7a3a11a 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -57,7 +57,7 @@ config VBOOT_REFCODE_INDEX hex default 0x3 -if !CONFIG_GOP_SUPPORT +if !GOP_SUPPORT config VGA_BIOS_FILE string default "3rdparty/blobs/mainboard/intel/strago/vgabios_c0.bin" if C0_DISP_SUPPORT diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index b0d4535..2dd3bdd 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 - select CACHE_ROM select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_LPC @@ -16,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select MARK_GRAPHICS_MEM_WRCOMB select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index d9381e7..4026863 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 - select CACHE_ROM select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_LPC @@ -16,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select MARK_GRAPHICS_MEM_WRCOMB select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 9447f8e..03c31f0 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 - select CACHE_ROM select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_LPC @@ -16,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select MARK_GRAPHICS_MEM_WRCOMB select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE diff --git a/src/mainboard/intel/sklrvp/Kconfig b/src/mainboard/intel/sklrvp/Kconfig index 4fd181f..73b866a 100644 --- a/src/mainboard/intel/sklrvp/Kconfig +++ b/src/mainboard/intel/sklrvp/Kconfig @@ -3,13 +3,11 @@ if BOARD_INTEL_SKLRVP config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ROMSIZE_KB_16384 - select CACHE_ROM select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select MARK_GRAPHICS_MEM_WRCOMB select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select PCIEXP_L1_SUB_STATE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index b67faab..3de9b54 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -14,8 +14,6 @@ config CPU_SPECIFIC_OPTIONS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE - select CACHE_ROM - select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_MICROCODE_IN_CBFS

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coreboot-gerrit November 2015