coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: AMD bettong: Fix the interrupt routing.
by Patrick Georgi 05 Nov '15

05 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11374 -gerrit commit a9283086143f98d2aa0173d71c140cdcd27b4615 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 19:33:53 2015 +0800 AMD bettong: Fix the interrupt routing. The plugged devices on PCIe should use IOAPIC2 instead of standard IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1. The unchanged code worked because the OS uses MSI instead APIC. To test that, boot linux with parameter pci=nomsi and see if the devices like NIC work well as they do without the booting parameter. Change-Id: I893e73f2aab3227381e44406fa285613e4ba2904 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/acpi/routing.asl | 88 ++++++++++++++++------ .../amd/pi/00660F01/acpi/northbridge.asl | 35 +++++++++ 2 files changed, 98 insertions(+), 25 deletions(-) diff --git a/src/mainboard/amd/bettong/acpi/routing.asl b/src/mainboard/amd/bettong/acpi/routing.asl index 51f0205..bcf0e90 100644 --- a/src/mainboard/amd/bettong/acpi/routing.asl +++ b/src/mainboard/amd/bettong/acpi/routing.asl @@ -105,12 +105,9 @@ Name(APR0, Package(){ Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 17 }, - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 17}, /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, 0, 19 }, @@ -144,10 +141,10 @@ Name(PS4, Package(){ }) Name(APS4, Package(){ /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, }) /* GPP 0 */ @@ -158,10 +155,10 @@ Name(PS5, Package(){ Package(){0x0000FFFF, 3, INTA, 0 }, }) Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, }) /* GPP 1 */ @@ -172,10 +169,10 @@ Name(PS6, Package(){ Package(){0x0000FFFF, 3, INTB, 0 }, }) Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, }) /* GPP 2 */ @@ -186,10 +183,10 @@ Name(PS7, Package(){ Package(){0x0000FFFF, 3, INTC, 0 }, }) Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, }) /* GPP 3 */ @@ -200,9 +197,50 @@ Name(PS8, Package(){ Package(){0x0000FFFF, 3, INTD, 0 }, }) Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 18 }, + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, }) +/* GFX 2 */ +Name(PSA, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APSA, Package(){ + Package(){0x0000FFFF, 0, 0, 52 }, + Package(){0x0000FFFF, 1, 0, 53 }, + Package(){0x0000FFFF, 2, 0, 54 }, + Package(){0x0000FFFF, 3, 0, 55 }, +}) + +/* GFX 3 */ +Name(PSB, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APSB, Package(){ + Package(){0x0000FFFF, 0, 0, 27 }, + Package(){0x0000FFFF, 1, 0, 24 }, + Package(){0x0000FFFF, 2, 0, 25 }, + Package(){0x0000FFFF, 3, 0, 26 }, +}) + +/* GFX 4 */ +Name(PSC, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APSC, Package(){ + Package(){0x0000FFFF, 0, 0, 31 }, + Package(){0x0000FFFF, 1, 0, 28 }, + Package(){0x0000FFFF, 2, 0, 29 }, + Package(){0x0000FFFF, 3, 0, 30 }, +}) diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index 4e6d13e..cde5182 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -94,3 +94,38 @@ Device(PBR8) { Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ + +/* GFX 1 */ +Device(PBR9) { + Name(_ADR, 0x00030002) +} /* end PBR8 */ + +/* GFX 2 */ +Device(PBRA) { + Name(_ADR, 0x00030003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSA) } /* APIC mode */ + Return (PSA) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +/* GFX 3 */ +Device(PBRB) { + Name(_ADR, 0x00030004) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSB) } /* APIC mode */ + Return (PSB) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +/* GFX 4 */ +Device(PBRC) { + Name(_ADR, 0x00030005) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSC) } /* APIC mode */ + Return (PSC) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */

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Patch set updated for coreboot: amd/pi/Makefile: Remove cp option '-u'
by Patrick Georgi 05 Nov '15

05 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11601 -gerrit commit 1732518d15475c45812bca4dc58272a2fa8ed737 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Sep 11 09:11:49 2015 -0400 amd/pi/Makefile: Remove cp option '-u' "-u" is only for GNU cp. Cp of BSD and Solaris don't take this option. It is not necessary to compare the files before copying. Change-Id: I60cf57991275db0e075278f77a95ca5b8b941c7f Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/vendorcode/amd/pi/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index a3d7fc1..b95fc5c 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -83,7 +83,7 @@ define create_agesa_cp_template $(agesa_src_path)/$(notdir $2): $2 $(agesa_src_path) @printf " AGESA Copying $$(notdir $2) => $$(@D)\n" if [ ! -r $(agesa_src_path)/$(notdir $2) ]; then \ - cp -uf $2 $$(@D); \ + cp -f $2 $$(@D); \ fi $(agesa_obj_path)/$1.libagesa.o: $(agesa_src_path)/$(notdir $2) $(obj)/config.h $(src)/include/kconfig.h $(agesa_obj_path)

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Patch set updated for coreboot: AMD Bettong: Enable S4 feature for Windows 7
by Zheng Bao 05 Nov '15

05 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11373 -gerrit commit ead415ec96f058d21dd7b8fc7d8ae87405158c9a Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 20:25:59 2015 +0800 AMD Bettong: Enable S4 feature for Windows 7 PMIOxEE is for setting USB3 power rail. Set it to S0, otherwise going into hibernation can not be wake up. Change-Id: I692497bad24d745738d670897e725a568c1db114 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/arch/x86/acpi.c | 6 ++++++ src/arch/x86/include/arch/acpi.h | 2 ++ src/mainboard/amd/bettong/romstage.c | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 55995c9..c540b5c 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1005,6 +1005,12 @@ int acpi_is_wakeup_s3(void) return (acpi_slp_type == 3); } +int acpi_is_wakeup_s4(void) +{ + acpi_handoff_wakeup(); + return (acpi_slp_type == 4); +} + void acpi_fail_wakeup(void) { if (acpi_slp_type == 3 || acpi_slp_type == 2) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 66e1100..87810b6 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -596,12 +596,14 @@ static inline int acpi_is_wakeup_s3(void) #else int acpi_is_wakeup(void); int acpi_is_wakeup_s3(void); +int acpi_is_wakeup_s4(void); #endif #else #define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } +static inline int acpi_is_wakeup_s4(void) { return 0; } #endif #endif /* __ASM_ACPI_H */ diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 9f94d7b..6399804 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <arch/acpi.h> +#include <arch/io.h> #include <arch/stages.h> #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> @@ -78,6 +79,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) prepare_for_resume(); } + if (s3resume || acpi_is_wakeup_s4()) { + outb(0xEE, PM_INDEX); + outb(0x8, PM_DATA); + } + post_code(0x50); copy_and_run();

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Patch set updated for coreboot: buildgcc: Search the cksum command without checking OS type
by Zheng Bao 05 Nov '15

05 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11483 -gerrit commit 065590b983e64b7cfd3a589435ba6a55581d6071 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 20:08:50 2015 +0800 buildgcc: Search the cksum command without checking OS type The checksum command might appear to be unpredictable only by checking the OS. Just list the candidates, sorted by possibility. Change-Id: Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/crossgcc/buildgcc | 42 ++++++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 321854f..a444099 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -146,24 +146,30 @@ searchtool() fi fi fi - if [ "$(echo $1 | cut -b -3)" = "sha" ]; then - if [ $UNAME = "FreeBSD" ]; then - if [ -x "$(which sha1 2>/dev/null)" ]; then - echo sha1 - return - fi - fi - if [ $UNAME = "NetBSD" ]; then - if [ -x "$(which cksum 2>/dev/null)" ]; then - echo cksum -a $(echo $1 | sed -e 's,sum,,') - return - fi - fi - if [ $UNAME = "Darwin" ]; then - if [ -x "$(which openssl 2>/dev/null)" ]; then - echo openssl $(echo $1 | sed -e 's,sum,,') - return - fi + if echo $1 | grep -q "sum" ; then + algor=$(echo $1 | sed -e 's,sum,,') #algor=sha1 + if [ -x "$(which $1 2>/dev/null)" ]; then + #sha1sum [file] + echo $1 + return + elif [ -x "$(which shasum 2>/dev/null)" ]; then + #shasum -a 1 [file] + echo shasum -a $(echo $algor | cut -c 4-) + return + elif [ -x "$(which $algor 2>/dev/null)" ]; then + #sha1 [file] + echo $algor + return + elif [ -x "$(which openssl 2>/dev/null)" ]; then + #openssl sha1 [file] + echo openssl $algor + return + elif [ -x "$(which cksum 2>/dev/null)" ]; then + #cksum -a sha1 [file] + #cksum has special options in NetBSD. Actually, NetBSD will use the second case above. + echo "buildgcc" | cksum -a $algor > /dev/null 2>/dev/null && \ + echo cksum -a $algor + return fi fi please_install $1

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Patch set updated for coreboot: AMD bettong: Fix the interrupt routine.
by Zheng Bao 05 Nov '15

05 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11374 -gerrit commit 8992c30cd77337669f77fc92e209ab4deed9deeb Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 19:33:53 2015 +0800 AMD bettong: Fix the interrupt routine. The plugged devices on PCIe should use IOAPIC2 instead of standard IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1. The unchanged code worked because the OS uses MSI instead APIC. To test that, boot linux with parameter pci=nomsi and see if the devices like NIC work well as they do without the booting parameter. Change-Id: I893e73f2aab3227381e44406fa285613e4ba2904 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/acpi/routing.asl | 88 ++++++++++++++++------ .../amd/pi/00660F01/acpi/northbridge.asl | 35 +++++++++ 2 files changed, 98 insertions(+), 25 deletions(-) diff --git a/src/mainboard/amd/bettong/acpi/routing.asl b/src/mainboard/amd/bettong/acpi/routing.asl index 51f0205..bcf0e90 100644 --- a/src/mainboard/amd/bettong/acpi/routing.asl +++ b/src/mainboard/amd/bettong/acpi/routing.asl @@ -105,12 +105,9 @@ Name(APR0, Package(){ Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 17 }, - Package(){0x0016FFFF, 0, 0, 18 }, - Package(){0x0016FFFF, 1, 0, 17 }, - /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ - Package(){0x0010FFFF, 0, 0, 0x12}, - Package(){0x0010FFFF, 1, 0, 0x11}, + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 17}, /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, 0, 19 }, @@ -144,10 +141,10 @@ Name(PS4, Package(){ }) Name(APS4, Package(){ /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, }) /* GPP 0 */ @@ -158,10 +155,10 @@ Name(PS5, Package(){ Package(){0x0000FFFF, 3, INTA, 0 }, }) Name(APS5, Package(){ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, }) /* GPP 1 */ @@ -172,10 +169,10 @@ Name(PS6, Package(){ Package(){0x0000FFFF, 3, INTB, 0 }, }) Name(APS6, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, }) /* GPP 2 */ @@ -186,10 +183,10 @@ Name(PS7, Package(){ Package(){0x0000FFFF, 3, INTC, 0 }, }) Name(APS7, Package(){ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, }) /* GPP 3 */ @@ -200,9 +197,50 @@ Name(PS8, Package(){ Package(){0x0000FFFF, 3, INTD, 0 }, }) Name(APS8, Package(){ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 18 }, + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, }) +/* GFX 2 */ +Name(PSA, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APSA, Package(){ + Package(){0x0000FFFF, 0, 0, 52 }, + Package(){0x0000FFFF, 1, 0, 53 }, + Package(){0x0000FFFF, 2, 0, 54 }, + Package(){0x0000FFFF, 3, 0, 55 }, +}) + +/* GFX 3 */ +Name(PSB, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APSB, Package(){ + Package(){0x0000FFFF, 0, 0, 27 }, + Package(){0x0000FFFF, 1, 0, 24 }, + Package(){0x0000FFFF, 2, 0, 25 }, + Package(){0x0000FFFF, 3, 0, 26 }, +}) + +/* GFX 4 */ +Name(PSC, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APSC, Package(){ + Package(){0x0000FFFF, 0, 0, 31 }, + Package(){0x0000FFFF, 1, 0, 28 }, + Package(){0x0000FFFF, 2, 0, 29 }, + Package(){0x0000FFFF, 3, 0, 30 }, +}) diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index 4e6d13e..cde5182 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -94,3 +94,38 @@ Device(PBR8) { Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ + +/* GFX 1 */ +Device(PBR9) { + Name(_ADR, 0x00030002) +} /* end PBR8 */ + +/* GFX 2 */ +Device(PBRA) { + Name(_ADR, 0x00030003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSA) } /* APIC mode */ + Return (PSA) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +/* GFX 3 */ +Device(PBRB) { + Name(_ADR, 0x00030004) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSB) } /* APIC mode */ + Return (PSB) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +/* GFX 4 */ +Device(PBRC) { + Name(_ADR, 0x00030005) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSC) } /* APIC mode */ + Return (PSC) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */

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Patch set updated for coreboot: xcompile: Redirect the objdump stderr to /dev/null
by Zheng Bao 05 Nov '15

05 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11681 -gerrit commit 754637536da99fb849fcb938ac1c7044b6f3073b Author: zbao <fishbaozi(a)gmail.com> Date: Fri Sep 18 06:17:09 2015 -0700 xcompile: Redirect the objdump stderr to /dev/null On system with clang, "as" is available but "objdump" is not by default. So if ${gccprefix} is empty, "as" can run successfully and the "objdump" below might report error. Mask that output. Change-Id: I9940f069f66e097973ed6138cf3c696087fa5531 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 76c3698..a8134a0 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -111,7 +111,7 @@ testas() { 2>/dev/null || return 1 # Check output content type. - local obj_type="$(LANG=C LC_ALL= ${gccprefix}objdump -p $obj_file)" + local obj_type="$(LANG=C LC_ALL= ${gccprefix}objdump -p $obj_file 2>/dev/null)" local obj_arch="$(expr "$obj_type" : '.*format $.[a-z0-9-]*$')" [ "$obj_arch" = "$full_arch" ] || return 1

1 0

Patch set updated for coreboot: hudson/Makefile: Remove the dd argument "status"
by Zheng Bao 05 Nov '15

05 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11745 -gerrit commit b7519b9e58b558eb800bd1a928dd848c8392ba1a Author: zbao <fishbaozi(a)gmail.com> Date: Wed Sep 30 04:22:04 2015 -0700 hudson/Makefile: Remove the dd argument "status" My dd on Macos doesn't take "status=xx". Darwin Kernel Version 13.0.0: cy660Ta,9hor6pr 2013 02:42:04 (MSK) root:xnu-2422.1.72_by_bronya_sinetek_anv_rc7/ BUILD/obj/RELEASE_X86_64 Change-Id: I7f7bf68967c61524811aa038b064ea706dadd366 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 00d150f..547ed52 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -136,7 +136,7 @@ $(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM $(HUDSON_PSP_DIRECTORY_POSITION); do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done > $@.tmp; \ - dd if=$@.tmp of=$@ conv=notrunc status=noxfer 2>/dev/null; \ + dd if=$@.tmp of=$@ conv=notrunc >/dev/null 2>/dev/null; \ rm $@.tmp ifeq ($(CONFIG_HUDSON_FWM), y) @@ -408,7 +408,7 @@ apu/smuscs-position := $(SMUSCS_POS) apu/smuscs-type := raw #9 -cbfs-files-y += apu/pspsecuredebug +#cbfs-files-y += apu/pspsecuredebug apu/pspsecuredebug-file := $(CONFIG_PSPSECUREDEBUG_FILE) apu/pspsecuredebug-position := $(PSPSECUREDEBUG_POS) apu/pspsecuredebug-type := raw

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Patch set updated for coreboot: AMD/Bettong: Set on-board eMMC as SD 2.0 for rev F
by Zheng Bao 05 Nov '15

05 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11748 -gerrit commit 1d1241be59642f77091465733e55586f7c49660d Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 6 19:06:41 2015 -0400 AMD/Bettong: Set on-board eMMC as SD 2.0 for rev F The on-board eMMC is designed as 2.0. If it is set as 3.0, it can not be detected. Change-Id: I9fd913f76535e65c1672924ebdeba3d35dea59cc Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/BiosCallOuts.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index ad8dc40..83a1f19 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -31,6 +31,7 @@ #include "hudson.h" #include <stdlib.h> #include "BiosCallOuts.h" +#include "board_rev.h" static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); @@ -90,6 +91,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ /* sata configuration */ + /* SD configuration */ + /* Rev F has an on-board eMMC, which only support SD 2.0 */ + if (get_board_id() == 'F') { + FchParams_env->Sd.SdConfig = SdVer2; + } } printk(BIOS_DEBUG, "Done\n");

1 0

Patch set updated for coreboot: AMD/bettong: Add UART support (WIP)
by Zheng Bao 05 Nov '15

05 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11749 -gerrit commit 07dbcd17ffc8eed04b62d7cfbe83dde5227c2c88 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 18:34:19 2015 +0800 AMD/bettong: Add UART support (WIP) The function delay in uart8250mem.c is not enough for hudson. Need a seprate patch to fix that. Select HUDSON_UART to enable this feature. Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/romstage.c | 27 ++++++++++++ src/southbridge/amd/pi/hudson/Kconfig | 16 +++++++ src/southbridge/amd/pi/hudson/Makefile.inc | 5 +++ src/southbridge/amd/pi/hudson/acpi/uart.asl | 65 +++++++++++++++++++++++++++++ src/southbridge/amd/pi/hudson/uart.c | 47 +++++++++++++++++++++ 5 files changed, 160 insertions(+) diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 9f94d7b..81e3812 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/stages.h> +#include <arch/io.h> #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> @@ -23,6 +24,10 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> +#include <delay.h> + +#define ACPI_MMIO_BASE ((void *)0xFED80000) +#define AOAC_BASE 0x1E00 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -30,6 +35,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif +#if CONFIG_DRIVERS_UART_8250MEM + u8 byte; + msr_t msr; +#endif amd_initmmio(); @@ -39,6 +48,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x30); post_code(0x31); +#if CONFIG_DRIVERS_UART_8250MEM + msr = rdmsr(0x1B); + msr.lo |= 1 << 11; + wrmsr(0x1B, msr); + byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2); + byte |= 1 << 3; + write8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2, byte); + byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x62); + byte |= 1 << 3; + write8(ACPI_MMIO_BASE + AOAC_BASE + 0x62, byte); + write8(ACPI_MMIO_BASE + 0xD00 + 0x89, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8A, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8E, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8F, 0); + + udelay(2000); + write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); /* reset UART */ +#endif console_init(); } diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c720791..94a313d 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -227,3 +227,19 @@ config AZ_PIN bit 5,4 - pin 2 bit 7,6 - pin 3 endif + +config HUDSON_UART + bool "UART controller on Kern." + default n + depends on SOUTHBRIDGE_AMD_PI_KERN + select DRIVERS_UART_8250MEM + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + help + There are two UART controllers in Kern. + The UART registers are memory-mapped. UART + controller 0 registers range from FEDC_6000h + to FEDC_6FFFh. UART controller 1 registers + range from FEDC_8000h to FEDC_8FFFh. + + diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 00d150f..2c2458c 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -50,6 +50,11 @@ romstage-y += imc.c ramstage-y += imc.c endif +ifeq ($(CONFIG_HUDSON_UART), y) +romstage-y += uart.c +ramstage-y += uart.c +endif + smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c diff --git a/src/southbridge/amd/pi/hudson/acpi/uart.asl b/src/southbridge/amd/pi/hudson/acpi/uart.asl new file mode 100644 index 0000000..ae7baa4 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/acpi/uart.asl @@ -0,0 +1,65 @@ + Scope(\_SB.FUR0) + { + Device(UART) + { + Name(_HID, "UTK0001") + Name(_CID, "UARTTest") + Name(_UID, Zero) + Method(_CRS, 0, NotSerialized) + { + Name(RBUF, Buffer(0x22) + { + 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35, + 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00, + 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F, + 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x30, 0x00, + 0x79, 0x00 + }) + Return(RBUF) + } + Method(_STA, 0, NotSerialized) + { + If(LEqual(MWTT, Zero)) + { + Return(0x0F) + } + Else + { + Return(Zero) + } + } + } + } +/* + Scope(\_SB.FUR1) + { + Device(UART) + { + Name(_HID, "UTK0001") + Name(_CID, "UARTTest") + Name(_UID, One) + Method(_CRS, 0, NotSerialized) + { + Name(RBUF, Buffer(0x22) + { + 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35, + 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00, + 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F, + 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x31, 0x00, + 0x79, 0x00 + }) + Return(RBUF) + } + Method(_STA, 0, NotSerialized) + { + If(LEqual(MWTT, Zero)) + { + Return(0x0F) + } + Else + { + Return(Zero) + } + } + } + } diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c new file mode 100644 index 0000000..ba35fbf --- /dev/null +++ b/src/southbridge/amd/pi/hudson/uart.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + + +#include <boot/coreboot_tables.h> +#include <console/console.h> /* for __console definition */ +#include <console/uart.h> +#include <drivers/uart/uart8250reg.h> + +#define ACPI_MMIO_BASE 0xFED80000 +#define AOAC_BASE 0x1E00 +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1)); +} + +unsigned int uart_platform_refclk(void) +{ + return 48000000; +} + +#ifdef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + serial.regwidth = 4; + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

1 0

Patch set updated for coreboot: AMD/bettong: Add UART support (WIP)
by Zheng Bao 05 Nov '15

05 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11749 -gerrit commit 0438c73f04296429b71f1aaa36ef8afbd9d34637 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Nov 5 18:34:19 2015 +0800 AMD/bettong: Add UART support (WIP) The function delay in uart8250mem.c is not enough for hudson. Need a seprate patch to fix that. Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/bettong/romstage.c | 27 ++++++++++++ src/southbridge/amd/pi/hudson/Kconfig | 16 +++++++ src/southbridge/amd/pi/hudson/Makefile.inc | 5 +++ src/southbridge/amd/pi/hudson/acpi/uart.asl | 65 +++++++++++++++++++++++++++++ src/southbridge/amd/pi/hudson/uart.c | 47 +++++++++++++++++++++ 5 files changed, 160 insertions(+) diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 9f94d7b..81e3812 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/stages.h> +#include <arch/io.h> #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> @@ -23,6 +24,10 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> +#include <delay.h> + +#define ACPI_MMIO_BASE ((void *)0xFED80000) +#define AOAC_BASE 0x1E00 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -30,6 +35,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif +#if CONFIG_DRIVERS_UART_8250MEM + u8 byte; + msr_t msr; +#endif amd_initmmio(); @@ -39,6 +48,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x30); post_code(0x31); +#if CONFIG_DRIVERS_UART_8250MEM + msr = rdmsr(0x1B); + msr.lo |= 1 << 11; + wrmsr(0x1B, msr); + byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2); + byte |= 1 << 3; + write8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2, byte); + byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x62); + byte |= 1 << 3; + write8(ACPI_MMIO_BASE + AOAC_BASE + 0x62, byte); + write8(ACPI_MMIO_BASE + 0xD00 + 0x89, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8A, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8E, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8F, 0); + + udelay(2000); + write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); /* reset UART */ +#endif console_init(); } diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c720791..94a313d 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -227,3 +227,19 @@ config AZ_PIN bit 5,4 - pin 2 bit 7,6 - pin 3 endif + +config HUDSON_UART + bool "UART controller on Kern." + default n + depends on SOUTHBRIDGE_AMD_PI_KERN + select DRIVERS_UART_8250MEM + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + help + There are two UART controllers in Kern. + The UART registers are memory-mapped. UART + controller 0 registers range from FEDC_6000h + to FEDC_6FFFh. UART controller 1 registers + range from FEDC_8000h to FEDC_8FFFh. + + diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 00d150f..2c2458c 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -50,6 +50,11 @@ romstage-y += imc.c ramstage-y += imc.c endif +ifeq ($(CONFIG_HUDSON_UART), y) +romstage-y += uart.c +ramstage-y += uart.c +endif + smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c diff --git a/src/southbridge/amd/pi/hudson/acpi/uart.asl b/src/southbridge/amd/pi/hudson/acpi/uart.asl new file mode 100644 index 0000000..ae7baa4 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/acpi/uart.asl @@ -0,0 +1,65 @@ + Scope(\_SB.FUR0) + { + Device(UART) + { + Name(_HID, "UTK0001") + Name(_CID, "UARTTest") + Name(_UID, Zero) + Method(_CRS, 0, NotSerialized) + { + Name(RBUF, Buffer(0x22) + { + 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35, + 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00, + 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F, + 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x30, 0x00, + 0x79, 0x00 + }) + Return(RBUF) + } + Method(_STA, 0, NotSerialized) + { + If(LEqual(MWTT, Zero)) + { + Return(0x0F) + } + Else + { + Return(Zero) + } + } + } + } +/* + Scope(\_SB.FUR1) + { + Device(UART) + { + Name(_HID, "UTK0001") + Name(_CID, "UARTTest") + Name(_UID, One) + Method(_CRS, 0, NotSerialized) + { + Name(RBUF, Buffer(0x22) + { + 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35, + 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00, + 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F, + 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x31, 0x00, + 0x79, 0x00 + }) + Return(RBUF) + } + Method(_STA, 0, NotSerialized) + { + If(LEqual(MWTT, Zero)) + { + Return(0x0F) + } + Else + { + Return(Zero) + } + } + } + } diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c new file mode 100644 index 0000000..ba35fbf --- /dev/null +++ b/src/southbridge/amd/pi/hudson/uart.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + + +#include <boot/coreboot_tables.h> +#include <console/console.h> /* for __console definition */ +#include <console/uart.h> +#include <drivers/uart/uart8250reg.h> + +#define ACPI_MMIO_BASE 0xFED80000 +#define AOAC_BASE 0x1E00 +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1)); +} + +unsigned int uart_platform_refclk(void) +{ + return 48000000; +} + +#ifdef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + serial.regwidth = 4; + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

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coreboot-gerrit November 2015