coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 3d4492d Makefile: clang - ramp up some more warnings
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8136 -gerrit commit 3d4492d3080fb546a7c5f92371043a679d9a7b5d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 14:58:31 2015 +1100 Makefile: clang - ramp up some more warnings Change-Id: I5262cba22d262f5d74d1edd958b59c2695271293 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6ef9838..ce2b727 100644 --- a/Makefile +++ b/Makefile @@ -119,7 +119,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # this means the triple is i386-linux-elf instead of i386-none-elf CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 # Tone down some clang warnings -CFLAGS_x86_32 += -Wno-unused-variable -Wno-unused-function -Wno-tautological-compare -Wno-shift-overflow +CFLAGS_x86_32 += -Wno-unused-variable -Wno-tautological-compare -Wno-shift-overflow CC_x86_32:=clang HOSTCC := clang

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Patch set updated for coreboot: eb4c703 soc/intel/broadwell/spi_loading.c: Remove dead code
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8168 -gerrit commit eb4c70395062d8bc4e1208e9d2685d25883603bf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 8 02:05:21 2015 +1100 soc/intel/broadwell/spi_loading.c: Remove dead code I would appear from commit a6354a1 that this is now dead code. Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/spi_loading.c | 67 ----------------------------------- 2 files changed, 68 deletions(-) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 43be95e..feead00 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -52,7 +52,6 @@ smm-y += smihandler.c ramstage-y += smmrelocate.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += spi_loading.c ramstage-y += stage_cache.c romstage-y += stage_cache.c ramstage-y += systemagent.c diff --git a/src/soc/intel/broadwell/spi_loading.c b/src/soc/intel/broadwell/spi_loading.c deleted file mode 100644 index 9454d03..0000000 --- a/src/soc/intel/broadwell/spi_loading.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -}

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Patch set updated for coreboot: ba76944 Re-factor 'to_flash_offset()' into 'spi_flash.h'
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8165 -gerrit commit ba76944f5f143e95992cfb4cbc798bea993de12c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:09:50 2014 +1000 Re-factor 'to_flash_offset()' into 'spi_flash.h' Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by Clang complaining that the function 'to_flash_offset' is unused. Change-Id: Ie2a8ac3cddac1cd87f1197efcd1bc9eb3189136e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/intel/fsp/fastboot_cache.c | 13 ++----------- src/include/spi_flash.h | 8 ++++++++ src/northbridge/intel/haswell/mrccache.c | 7 +------ src/northbridge/intel/sandybridge/mrccache.c | 7 +------ src/soc/intel/common/nvm.c | 10 ++-------- src/soc/intel/fsp_baytrail/nvm.c | 13 ++----------- 6 files changed, 16 insertions(+), 42 deletions(-) diff --git a/src/drivers/intel/fsp/fastboot_cache.c b/src/drivers/intel/fsp/fastboot_cache.c index 64982d8..907e143 100644 --- a/src/drivers/intel/fsp/fastboot_cache.c +++ b/src/drivers/intel/fsp/fastboot_cache.c @@ -31,15 +31,6 @@ #include <lib.h> // hexdump #include "fsp_util.h" -#ifndef CONFIG_VIRTUAL_ROM_SIZE -#error "CONFIG_VIRTUAL_ROM_SIZE must be set." -#endif - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -205,7 +196,7 @@ void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -213,7 +204,7 @@ void update_mrc_cache(void *unused) /* 4. write mrc data with flash->write() */ printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); } diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 7e430d0..0d8331e 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -76,4 +76,12 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, return flash->erase(flash, offset, len); } +#if !defined(__PRE_RAM__) +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + u32 size = CONFIG_VIRTUAL_ROM_SIZE ? CONFIG_VIRTUAL_ROM_SIZE : flash->size; + return ((u32)p + size); +} +#endif /* !defined(__PRE_RAM__) */ + #endif /* _SPI_FLASH_H_ */ diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index a921e04..88af789 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -228,7 +223,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..664fb7f 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -227,7 +222,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 791422f..54b3baf 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -46,12 +46,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -70,7 +64,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - return flash->erase(flash, to_flash_offset(start), size); + return flash->erase(flash, to_flash_offset(flash, start), size); } /* Write data to NVM. Returns 0 on success < 0 on error. */ @@ -78,5 +72,5 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - return flash->write(flash, to_flash_offset(start), size, data); + return flash->write(flash, to_flash_offset(flash, start), size, data); } diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c index 0224463..d1e5223 100644 --- a/src/soc/intel/fsp_baytrail/nvm.c +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -47,15 +47,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ -#ifndef CONFIG_ROM_SIZE -#error CONFIG_ROM_SIZE must be set. -#endif - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -74,7 +65,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + flash->erase(flash, to_flash_offset(flash, start), size); return 0; } @@ -83,6 +74,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + flash->write(flash, to_flash_offset(flash, start), size, data); return 0; }

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Patch set updated for coreboot: 0fb3580 southbridge/intel/lynxpoint/me_9.x.c: Avoid unused func warn
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8157 -gerrit commit 0fb3580cba89627ceec2e070b1a28aea00e4a0fb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 7 15:53:00 2015 +1100 southbridge/intel/lynxpoint/me_9.x.c: Avoid unused func warn Put a guard around this function to avoid compiler warnings pretaining to unused functions when a false branch is hit on a guard further down the file. Change-Id: Ie4955ee9df6904c38848f46226b53be37d9fa239 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/intel/lynxpoint/me_9.x.c | 52 +++++++++++++++++--------------- 1 file changed, 28 insertions(+), 24 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index dfed6de..935e2b8 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -374,6 +374,9 @@ static int mei_recv_msg(void *header, int header_bytes, return mei_wait_for_me_ready(); } +#if IS_ENABLED (CONFIG_DEBUG_INTEL_ME) + +#if defined(__SMM__) static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, void *req_data, int req_bytes, void *rsp_data, int rsp_bytes) @@ -411,30 +414,7 @@ static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, return 0; } - -static inline int mei_sendrecv_icc(struct icc_header *icc, - void *req_data, int req_bytes, - void *rsp_data, int rsp_bytes) -{ - struct icc_header icc_rsp; - - /* Send header */ - if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, - icc, sizeof(*icc), req_bytes ? 0 : 1) < 0) - return -1; - - /* Send data if available */ - if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, - req_data, req_bytes) < 0) - return -1; - - /* Read header and data, if needed */ - if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp), - rsp_data, rsp_bytes) < 0) - return -1; - - return 0; -} +#endif /* CONFIG_DEBUG_INTEL_ME || __SMM__ */ /* * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read @@ -636,6 +616,30 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ +static inline int mei_sendrecv_icc(struct icc_header *icc, + void *req_data, int req_bytes, + void *rsp_data, int rsp_bytes) +{ + struct icc_header icc_rsp; + + /* Send header */ + if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, + icc, sizeof(*icc), req_bytes ? 0 : 1) < 0) + return -1; + + /* Send data if available */ + if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, + req_data, req_bytes) < 0) + return -1; + + /* Read header and data, if needed */ + if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp), + rsp_data, rsp_bytes) < 0) + return -1; + + return 0; +} + static int me_icc_set_clock_enables(u32 mask) { struct icc_clock_enables_msg clk = {

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Patch set updated for coreboot: 60246b8 mainboard/lenovo/x201/romstage.c: Avoid unused func warning
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8158 -gerrit commit 60246b8d7bbe7cbb990b4797a1a0476e1034a467 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 7 15:55:32 2015 +1100 mainboard/lenovo/x201/romstage.c: Avoid unused func warning Change-Id: I646dddd39e61b59358b29a49239c0a1de77c7e55 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/x201/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 64011b1..535c373 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -167,10 +167,14 @@ static inline u32 read_acpi32(u32 addr) return inl(DEFAULT_PMBASE | addr); } +// Used for reverse engining purposes +// avoid unused func compiler warn +#if 0 static inline u16 read_acpi16(u32 addr) { return inw(DEFAULT_PMBASE | addr); } +#endif static void set_fsb_frequency(void) {

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Patch set updated for coreboot: 6be60cf Makefile: clang - ramp up some more warnings
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8136 -gerrit commit 6be60cfc0265457c3d65cd9a153173e744c5a15e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 14:58:31 2015 +1100 Makefile: clang - ramp up some more warnings Change-Id: I5262cba22d262f5d74d1edd958b59c2695271293 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6ef9838..ce2b727 100644 --- a/Makefile +++ b/Makefile @@ -119,7 +119,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # this means the triple is i386-linux-elf instead of i386-none-elf CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 # Tone down some clang warnings -CFLAGS_x86_32 += -Wno-unused-variable -Wno-unused-function -Wno-tautological-compare -Wno-shift-overflow +CFLAGS_x86_32 += -Wno-unused-variable -Wno-tautological-compare -Wno-shift-overflow CC_x86_32:=clang HOSTCC := clang

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Patch set updated for coreboot: 3f34e3d soc/intel/broadwell/spi_loading.c: Remove dead code
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8168 -gerrit commit 3f34e3db0352ac600e7c149748d665f579842538 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 8 02:05:21 2015 +1100 soc/intel/broadwell/spi_loading.c: Remove dead code I would appear from commit a6354a1 that this is now dead code. Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/spi_loading.c | 67 ----------------------------------- 2 files changed, 68 deletions(-) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 43be95e..feead00 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -52,7 +52,6 @@ smm-y += smihandler.c ramstage-y += smmrelocate.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += spi_loading.c ramstage-y += stage_cache.c romstage-y += stage_cache.c ramstage-y += systemagent.c diff --git a/src/soc/intel/broadwell/spi_loading.c b/src/soc/intel/broadwell/spi_loading.c deleted file mode 100644 index 9454d03..0000000 --- a/src/soc/intel/broadwell/spi_loading.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -}

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Patch set updated for coreboot: d7f36ad mainboard/packardbell/ms2290/romstage.c: Comment unused func
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8167 -gerrit commit d7f36ad295a2c26690dd930d8dbdd57486c1a924 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 8 01:57:43 2015 +1100 mainboard/packardbell/ms2290/romstage.c: Comment unused func Take unused reverse eng function out of build by wrapping in #if 0. Change-Id: I816b3ea08a8858fc03e4455c1d7711265e63cba4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/packardbell/ms2290/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index a366d38..f702e9f 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -163,10 +163,13 @@ static inline u32 read_acpi32(u32 addr) return inl(DEFAULT_PMBASE | addr); } +// unused func - used for RE +#if 0 static inline u16 read_acpi16(u32 addr) { return inw(DEFAULT_PMBASE | addr); } +#endif #include <cpu/intel/romstage.h> void main(unsigned long bist)

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Patch set updated for coreboot: d6363bd Re-factor 'to_flash_offset()' into 'spi_flash.h'
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8165 -gerrit commit d6363bdce5c4602ac6a463f952101fd624c00fdd Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:09:50 2014 +1000 Re-factor 'to_flash_offset()' into 'spi_flash.h' Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by Clang complaining that the function 'to_flash_offset' is unused. Change-Id: Ie2a8ac3cddac1cd87f1197efcd1bc9eb3189136e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/intel/fsp/fastboot_cache.c | 13 ++----------- src/include/spi_flash.h | 11 +++++++++++ src/northbridge/intel/haswell/mrccache.c | 7 +------ src/northbridge/intel/sandybridge/mrccache.c | 7 +------ src/soc/intel/common/nvm.c | 10 ++-------- src/soc/intel/fsp_baytrail/nvm.c | 13 ++----------- 6 files changed, 19 insertions(+), 42 deletions(-) diff --git a/src/drivers/intel/fsp/fastboot_cache.c b/src/drivers/intel/fsp/fastboot_cache.c index 64982d8..907e143 100644 --- a/src/drivers/intel/fsp/fastboot_cache.c +++ b/src/drivers/intel/fsp/fastboot_cache.c @@ -31,15 +31,6 @@ #include <lib.h> // hexdump #include "fsp_util.h" -#ifndef CONFIG_VIRTUAL_ROM_SIZE -#error "CONFIG_VIRTUAL_ROM_SIZE must be set." -#endif - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -205,7 +196,7 @@ void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -213,7 +204,7 @@ void update_mrc_cache(void *unused) /* 4. write mrc data with flash->write() */ printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); } diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 7e430d0..fa97ad5 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -76,4 +76,15 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, return flash->erase(flash, offset, len); } +#if !defined(__PRE_RAM__) +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { +#if IS_ENABLED (CONFIG_VIRTUAL_ROM_SIZE) + return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); +#else + return ((u32)p + flash->size); +#endif /* defined(CONFIG_VIRTUAL_ROM_SIZE) */ +} +#endif /* !defined(__PRE_RAM__) */ + #endif /* _SPI_FLASH_H_ */ diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index a921e04..88af789 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -228,7 +223,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..664fb7f 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -227,7 +222,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 791422f..54b3baf 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -46,12 +46,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -70,7 +64,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - return flash->erase(flash, to_flash_offset(start), size); + return flash->erase(flash, to_flash_offset(flash, start), size); } /* Write data to NVM. Returns 0 on success < 0 on error. */ @@ -78,5 +72,5 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - return flash->write(flash, to_flash_offset(start), size, data); + return flash->write(flash, to_flash_offset(flash, start), size, data); } diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c index 0224463..d1e5223 100644 --- a/src/soc/intel/fsp_baytrail/nvm.c +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -47,15 +47,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ -#ifndef CONFIG_ROM_SIZE -#error CONFIG_ROM_SIZE must be set. -#endif - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -74,7 +65,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + flash->erase(flash, to_flash_offset(flash, start), size); return 0; } @@ -83,6 +74,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + flash->write(flash, to_flash_offset(flash, start), size, data); return 0; }

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New patch to review for coreboot: 5c45219 soc/intel/broadwell/spi_loading.c: Remove dead code
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8168 -gerrit commit 5c452192e2283a5585a40cf9251a404953567fc6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 8 02:05:21 2015 +1100 soc/intel/broadwell/spi_loading.c: Remove dead code I would appear from commit a6354a1 that this is now dead code. Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/spi_loading.c | 67 ----------------------------------- 2 files changed, 68 deletions(-) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 43be95e..feead00 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -52,7 +52,6 @@ smm-y += smihandler.c ramstage-y += smmrelocate.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += spi_loading.c ramstage-y += stage_cache.c romstage-y += stage_cache.c ramstage-y += systemagent.c diff --git a/src/soc/intel/broadwell/spi_loading.c b/src/soc/intel/broadwell/spi_loading.c deleted file mode 100644 index 9454d03..0000000 --- a/src/soc/intel/broadwell/spi_loading.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -}

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coreboot-gerrit January 2015