coreboot-gerrit January 2015

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New patch to review for coreboot: cb3a75f vboot2: implement vb2ex_read_resource
by Marc Jones 07 Jan '15

07 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8161 -gerrit commit cb3a75f5c660d450a8f67be3cb2071bd8cd2ef8c Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Jun 30 08:28:17 2014 -0700 vboot2: implement vb2ex_read_resource TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I633f9dddbf8b2f25797aacc246bcebaafb02bea4 Original-Reviewed-on: https://chromium-review.googlesource.com/206063 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> (cherry picked from commit 1f215672de31847cc647e83d2c04633b7f8dfa33) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I57f449b052132b300f7bca4351871c539a7a8694 --- src/vendorcode/google/chromeos/vboot_main.c | 55 +++++++++++++++++++---------- 1 file changed, 37 insertions(+), 18 deletions(-) diff --git a/src/vendorcode/google/chromeos/vboot_main.c b/src/vendorcode/google/chromeos/vboot_main.c index 9779d35..907afd7 100644 --- a/src/vendorcode/google/chromeos/vboot_main.c +++ b/src/vendorcode/google/chromeos/vboot_main.c @@ -31,6 +31,23 @@ struct vboot_region { int32_t size; }; +static void locate_region(const char *name, struct vboot_region *region) +{ + region->size = find_fmap_entry(name, (void **)&region->offset_addr); + VBDEBUG("Located %s @%x\n", name, region->offset_addr); +} + +static int is_slot_a(struct vb2_context *ctx) +{ + return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); +} + +static int in_ro(void) +{ + /* TODO: Implement */ + return 1; +} + /* exports */ void vb2ex_printf(const char *func, const char *fmt, ...) @@ -57,27 +74,29 @@ int vb2ex_read_resource(struct vb2_context *ctx, void *buf, uint32_t size) { - VBDEBUG("Reading resource\n"); - return VB2_ERROR_UNKNOWN; -} + struct vboot_region region; + + switch (index) { + case VB2_RES_GBB: + locate_region("GBB", &region); + break; + case VB2_RES_FW_VBLOCK: + if (is_slot_a(ctx)) + locate_region("VBLOCK_A", &region); + else + locate_region("VBLOCK_B", &region); + break; + default: + return VB2_ERROR_EX_READ_RESOURCE_INDEX; + } -/* locals */ + if (offset + size > region.size) + return VB2_ERROR_EX_READ_RESOURCE_SIZE; -static void locate_region(const char *name, struct vboot_region *region) -{ - region->size = find_fmap_entry(name, (void **)&region->offset_addr); - VBDEBUG("Located %s @%x\n", name, region->offset_addr); -} + if (vboot_get_region(region.offset_addr + offset, size, buf) == NULL) + return VB2_ERROR_UNKNOWN; -static int is_slot_a(struct vb2_context *ctx) -{ - return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); -} - -static int in_ro(void) -{ - /* TODO: Implement */ - return 1; + return VB2_SUCCESS; } static void reboot(void)

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New patch to review for coreboot: f6322e5 vboot2: implement select_firmware for pre-romstage verification
by Marc Jones 07 Jan '15

07 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8160 -gerrit commit f6322e5179057a8ca8d54c195b0544cbb167c7bc Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Jun 19 19:16:24 2014 -0700 vboot2: implement select_firmware for pre-romstage verification This patch has a basic structure of vboot2 integration. It supports only Nyans, which have bootblock architecture and romstage architecture are compatible from linker's perspective. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I4bbd4d0452604943b376bef20ea8a258820810aa Original-Reviewed-on: https://chromium-review.googlesource.com/204522 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> (cherry picked from commit a6bce0cbed34def60386f3d9aece59e739740c58) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I63ddfbf463c8a83120828ec8ab994f8146f90001 --- src/arch/arm/Makefile.inc | 12 + src/arch/arm/armv7/Makefile.inc | 12 + src/arch/arm/bootblock.ld | 1 + src/arch/arm/libgcc/Makefile.inc | 4 + src/console/Makefile.inc | 4 + src/include/reset.h | 1 + src/lib/Makefile.inc | 6 + src/mainboard/google/nyan_blaze/Makefile.inc | 2 + src/mainboard/google/nyan_blaze/romstage.c | 4 + src/soc/nvidia/tegra124/Kconfig | 11 + src/soc/nvidia/tegra124/Makefile.inc | 8 + src/soc/nvidia/tegra124/verstage.c | 8 +- src/vendorcode/google/chromeos/Makefile.inc | 26 +++ src/vendorcode/google/chromeos/chromeos.h | 9 +- src/vendorcode/google/chromeos/vboot_handoff.c | 7 + src/vendorcode/google/chromeos/vboot_main.c | 311 +++++++++++++++++++++++++ 16 files changed, 423 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index ba7fb60..3d3569c 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -68,6 +68,18 @@ $(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(boo endif # CONFIG_ARCH_BOOTBLOCK_ARM ############################################################################### +# verification stage +############################################################################### + +verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c +verstage-y += div0.c +verstage-y += eabi_compat.c +verstage-y += memset.S +verstage-y += memcpy.S +verstage-y += memmove.S +verstage-y += stages.c + +############################################################################### # romstage ############################################################################### diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 7e67178..0919a93 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -46,6 +46,18 @@ bootblock-S-ccopts += $(armv7_asm_flags) endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 +################################################################################ +## verification stage +################################################################################ + +verstage-c-ccopts += $(armv7_flags) +verstage-S-ccopts += $(armv7_asm_flags) +verstage-y += cache.c +verstage-y += cpu.S +verstage-y += exception.c +verstage-y += exception_asm.S +verstage-y += mmu.c + ############################################################################### # romstage ############################################################################### diff --git a/src/arch/arm/bootblock.ld b/src/arch/arm/bootblock.ld index 150bf2d..c1a6ccf 100644 --- a/src/arch/arm/bootblock.ld +++ b/src/arch/arm/bootblock.ld @@ -50,6 +50,7 @@ SECTIONS } : to_load = 0xff preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + verstage_preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; /DISCARD/ : { *(.comment) diff --git a/src/arch/arm/libgcc/Makefile.inc b/src/arch/arm/libgcc/Makefile.inc index a1d325d..5e8858a 100644 --- a/src/arch/arm/libgcc/Makefile.inc +++ b/src/arch/arm/libgcc/Makefile.inc @@ -25,6 +25,10 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y) bootblock-y += $(libgcc_files) endif +ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) +verstage-y += $(libgcc_files) +endif + ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y) romstage-y += $(libgcc_files) endif diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index d339500..b9cafae 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -6,6 +6,10 @@ ramstage-y += die.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c +verstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c +verstage-y += console.c +verstage-y += die.c + romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c diff --git a/src/include/reset.h b/src/include/reset.h index 9f117db..9430ffe 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -7,5 +7,6 @@ void hard_reset(void); #define hard_reset() do {} while(0) #endif void soft_reset(void); +void cpu_reset(void); #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 0501091..3ce9acf 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -24,6 +24,12 @@ bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c bootblock-y += memchr.c bootblock-y += memcmp.c +verstage-y += delay.c +verstage-y += cbfs.c +verstage-y += memcmp.c +verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c + + romstage-y += memchr.c romstage-y += memcmp.c $(foreach arch,$(ARCH_SUPPORTED),\ diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index b66cd55..02b3977 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -32,6 +32,8 @@ bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c +verstage-y += reset.c + romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 4e02365..480abd6 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -228,7 +228,11 @@ static void __attribute__((noinline)) romstage(void) cbmemc_reinit(); #endif +#if CONFIG_VBOOT2_VERIFY_FIRMWARE + // vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS); +#else vboot_verify_firmware(romstage_handoff_find_or_add()); +#endif timestamp_add(TS_START_COPYRAM, timestamp_get()); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index ea946e6..d9264fe 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -46,10 +46,12 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" + default 0x1e000 if VBOOT2_VERIFY_FIRMWARE default 0x18000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" + default 0x1e080 if VBOOT2_VERIFY_FIRMWARE default 0x18080 config SYS_SDRAM_BASE @@ -62,6 +64,7 @@ config BOOTBLOCK_BASE config ROMSTAGE_BASE hex + default 0x4002d000 if VBOOT2_VERIFY_FIRMWARE default 0x4002c000 config RAMSTAGE_BASE @@ -94,6 +97,14 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00017fe0 +config VBOOT_WORK_BUFFER_ADDRESS + hex "memory address of vboot work buffer" + default 0x40018000 + +config VBOOT_WORK_BUFFER_SIZE + hex "size of vboot work buffer" + default 0x00004000 + config TEGRA124_MODEL_TD570D bool "TD570D" diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index b306412..4b0ec96 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -21,6 +21,14 @@ bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c endif verstage-y += verstage.c +verstage-y += cbfs.c +verstage-y += dma.c +verstage-y += monotonic_timer.c +verstage-y += spi.c +verstage-y += timer.c +verstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +verstage-y += ../tegra/gpio.c +verstage-y += ../tegra/pinmux.c romstage-y += cbfs.c romstage-y += cbmem.c diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 234a89d..d85fc5c 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -1,9 +1,15 @@ #include "verstage.h" +#include <vendorcode/google/chromeos/chromeos.h> /** * Stage entry point */ void vboot_main(void) { - for(;;); + /* Stub to force arm_init_caches to the top, before any stack/memory + * accesses */ + asm volatile ("bl arm_init_caches" + ::: "r0","r1","r2","r3","r4","r5","ip"); + + select_firmware(); } diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 12d35b6..cb3d9a6 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -95,7 +95,33 @@ $(VB_LIB): endif ifeq ($(CONFIG_VBOOT2_VERIFY_FIRMWARE),y) +VB_SOURCE := vboot_reference VERSTAGE_LIB = $(obj)/vendorcode/google/chromeos/verstage.a + +INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include +INCLUDES += -I$(VB_SOURCE)/firmware/include +verstage-y += vboot_main.c fmap.c chromeos.c + +VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y)) +VB2_LIB = $(obj)/external/vboot_reference/vboot_fw2.a +VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%,$(filter-out -include $(src)/include/kconfig.h, $(CFLAGS_verstage))) +VBOOT_CFLAGS += $(verstage-c-ccopts) +VBOOT_CFLAGS += -include $(top)/src/include/kconfig.h -Wno-missing-prototypes +VBOOT_CFLAGS += -DVBOOT_DEBUG + +$(VB2_LIB): $(obj)/config.h + @printf " MAKE $(subst $(obj)/,,$(@))\n" + $(Q)FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ + CC="$(CC_verstage)" \ + CFLAGS="$(VBOOT_CFLAGS)" VBOOT2="y" \ + make -C $(VB_SOURCE) \ + BUILD=$(top)/$(dir $(VB2_LIB)) \ + V=$(V) \ + fwlib2 + mv $@ $@.tmp + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY_verstage) --prefix-symbols=verstage_ $@.tmp $@ + $(VERSTAGE_LIB): $$(verstage-objs) @printf " AR $(subst $(obj)/,,$(@))\n" $(AR_verstage) rc $@.tmp $(verstage-objs) diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index a2ecac8..a799528 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -46,7 +46,7 @@ struct romstage_handoff; /* TODO(shawnn): Remove these CONFIGs and define default weak functions * that can be overridden in the platform / MB code. */ -#if CONFIG_VBOOT_VERIFY_FIRMWARE +#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE /* * This is a dual purpose routine. If dest is non-NULL the region at * offset_addr will be read into the area pointed to by dest. If dest @@ -67,7 +67,8 @@ static inline int vboot_get_handoff_info(void **addr, uint32_t *size) return -1; } static inline int vboot_skip_display_init(void) { return 0; } -#endif +#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE */ + int vboot_get_sw_write_protect(void); #include "gnvs.h" @@ -85,4 +86,8 @@ static inline void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) {} static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} #endif /* CONFIG_CHROMEOS_RAMOOPS */ +#if CONFIG_VBOOT2_VERIFY_FIRMWARE +void select_firmware(void); +#endif + #endif diff --git a/src/vendorcode/google/chromeos/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot_handoff.c index 7ef2c7e..7ea21ea 100644 --- a/src/vendorcode/google/chromeos/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot_handoff.c @@ -105,6 +105,12 @@ int __attribute((weak)) vboot_get_sw_write_protect(void) return 0; } +#if CONFIG_VBOOT2_VERIFY_FIRMWARE + +void *vboot_get_payload(int *len) { return NULL; } + +#else /* CONFIG_VBOOT2_VERIFY_FIRMWARE */ + static void *vboot_get_payload(size_t *len) { struct vboot_handoff *vboot_handoff; @@ -131,6 +137,7 @@ static void *vboot_get_payload(size_t *len) return (void *)fwc->address; } +#endif static int vboot_locate_payload(struct payload *payload) { diff --git a/src/vendorcode/google/chromeos/vboot_main.c b/src/vendorcode/google/chromeos/vboot_main.c new file mode 100644 index 0000000..9779d35 --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_main.c @@ -0,0 +1,311 @@ +#include <2api.h> +#include <2struct.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> +#include <console/vtxprintf.h> +#include <reset.h> +#include <string.h> + +#include "chromeos.h" +#include "fmap.h" + +#define VBDEBUG(format, args...) \ + printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) +#define TODO_BLOCK_SIZE 8192 +#define MAX_PARSED_FW_COMPONENTS 5 +#define ROMSTAGE_INDEX 2 + +struct component_entry { + uint32_t offset; + uint32_t size; +} __attribute__((packed)); + +struct components { + uint32_t num_components; + struct component_entry entries[MAX_PARSED_FW_COMPONENTS]; +} __attribute__((packed)); + +struct vboot_region { + uintptr_t offset_addr; + int32_t size; +}; + +/* exports */ + +void vb2ex_printf(const char *func, const char *fmt, ...) +{ + va_list args; + + printk(BIOS_INFO, "VB2:%s() ", func); + va_start(args, fmt); + printk(BIOS_INFO, fmt, args); + va_end(args); + + return; +} + +int vb2ex_tpm_clear_owner(struct vb2_context *ctx) +{ + VBDEBUG("Clearing owner\n"); + return VB2_ERROR_UNKNOWN; +} + +int vb2ex_read_resource(struct vb2_context *ctx, + enum vb2_resource_index index, + uint32_t offset, + void *buf, + uint32_t size) +{ + VBDEBUG("Reading resource\n"); + return VB2_ERROR_UNKNOWN; +} + +/* locals */ + +static void locate_region(const char *name, struct vboot_region *region) +{ + region->size = find_fmap_entry(name, (void **)&region->offset_addr); + VBDEBUG("Located %s @%x\n", name, region->offset_addr); +} + +static int is_slot_a(struct vb2_context *ctx) +{ + return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); +} + +static int in_ro(void) +{ + /* TODO: Implement */ + return 1; +} + +static void reboot(void) +{ + cpu_reset(); +} + +static void recovery(void) +{ + void *entry; + + if (!in_ro()) + reboot(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); + if (entry != (void *)-1) + stage_exit(entry); + + for(;;); +} + +static int hash_body(struct vb2_context *ctx, struct vboot_region *fw_main) +{ + uint32_t expected_size; + uint8_t block[TODO_BLOCK_SIZE]; + size_t block_size = sizeof(block); + uintptr_t offset; + int rv; + + expected_size = fw_main->size; + offset= fw_main->offset_addr; + + /* Start the body hash */ + rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size); + if (rv) { + return rv; + } + + /* Extend over the body */ + while (expected_size) { + void *b; + if (block_size > expected_size) + block_size = expected_size; + + b = vboot_get_region(offset, block_size, block); + if (b == NULL) + return VB2_ERROR_UNKNOWN; + rv = vb2api_extend_hash(ctx, b, block_size); + if (rv) + return rv; + + expected_size -= block_size; + offset+= block_size; + } + + /* Check the result */ + rv = vb2api_check_hash(ctx); + if (rv) { + return rv; + } + + return VB2_SUCCESS; +} + +static int locate_fw_components(struct vb2_context *ctx, + struct vboot_region *fw_main, + struct components *fw_info) +{ + if (is_slot_a(ctx)) + locate_region("FW_MAIN_A", fw_main); + else + locate_region("FW_MAIN_B", fw_main); + if (fw_main->size < 0) + return 1; + + if (vboot_get_region(fw_main->offset_addr, + sizeof(*fw_info), fw_info) == NULL) + return 1; + return 0; +} + +static struct cbfs_stage *load_stage(struct vb2_context *ctx, + int stage_index, + struct vboot_region *fw_main, + struct components *fw_info) +{ + struct cbfs_stage *stage; + uint32_t fc_addr; + uint32_t fc_size; + + /* Check for invalid address. */ + fc_addr = fw_main->offset_addr + fw_info->entries[stage_index].offset; + fc_size = fw_info->entries[stage_index].size; + if (fc_addr == 0 || fc_size == 0) { + VBDEBUG("romstage address invalid.\n"); + return NULL; + } + + /* Loading to cbfs cache. This stage data must be retained until it's + * decompressed. */ + stage = vboot_get_region(fc_addr, fc_size, NULL); + + if (stage == NULL) { + VBDEBUG("Unable to load a stage.\n"); + return NULL; + } + + return stage; +} + +static void enter_stage(struct cbfs_stage *stage) +{ + /* Stages rely the below clearing so that the bss is initialized. */ + memset((void *) (uintptr_t)stage->load, 0, stage->memlen); + + if (cbfs_decompress(stage->compression, + (unsigned char *)stage + sizeof(*stage), + (void *) (uintptr_t) stage->load, + stage->len)) + return; + + VBDEBUG("Jumping to entry @%llx.\n", stage->entry); + stage_exit((void *)(uintptr_t)stage->entry); +} + +/** + * Save non-volatile and/or secure data if needed. + */ +static void save_if_needed(struct vb2_context *ctx) +{ + if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { + VBDEBUG("Saving nvdata\n"); + //save_vbnv(ctx->nvdata); + ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; + } + if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { + VBDEBUG("Saving secdata\n"); + //antirollback_write_space_firmware(ctx); + ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED; + } +} + +void __attribute__((noinline)) select_firmware(void) +{ + struct vb2_context ctx; + uint8_t *workbuf = (uint8_t *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS; + struct vboot_region fw_main; + struct components fw_info; + struct cbfs_stage *stage; + int rv; + + console_init(); + + /* Set up context */ + memset(&ctx, 0, sizeof(ctx)); + ctx.workbuf = workbuf; + ctx.workbuf_size = CONFIG_VBOOT_WORK_BUFFER_SIZE; + memset(ctx.workbuf, 0, ctx.workbuf_size); + + /* Read nvdata from a non-volatile storage */ + //read_vbnv(ctx.nvdata); + + /* Read secdata from TPM. Initialize TPM if secdata not found. We don't + * check the return value here because vb2api_fw_phase1 will catch + * invalid secdata and tell us what to do (=reboot). */ + //antirollback_read_space_firmware(&ctx); + + //if (get_developer_mode_switch()) + // ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; + //if (get_recovery_mode_switch()) { + // clear_recovery_mode_switch(); + // ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; + //} + + /* Do early init */ + VBDEBUG("Phase 1\n"); + rv = vb2api_fw_phase1(&ctx); + if (rv) { + VBDEBUG("Recovery requested (%x)\n", rv); + /* If we need recovery mode, leave firmware selection now */ + save_if_needed(&ctx); + recovery(); + } + + /* Determine which firmware slot to boot */ + VBDEBUG("Phase 2\n"); + rv = vb2api_fw_phase2(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + save_if_needed(&ctx); + reboot(); + } + + /* Try that slot */ + VBDEBUG("Phase 3\n"); + rv = vb2api_fw_phase3(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + save_if_needed(&ctx); + reboot(); + } + + VBDEBUG("Phase 4\n"); + rv = locate_fw_components(&ctx, &fw_main, &fw_info); + if (rv) { + VBDEBUG("Failed to locate firmware components\n"); + reboot(); + } + rv = hash_body(&ctx, &fw_main); + stage = load_stage(&ctx, ROMSTAGE_INDEX, &fw_main, &fw_info); + if (stage == NULL) { + VBDEBUG("Failed to load stage\n"); + reboot(); + } + save_if_needed(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + reboot(); + } + + /* TODO: Do we need to lock secdata? */ + VBDEBUG("Locking TPM\n"); + + /* Load next stage and jump to it */ + VBDEBUG("Jumping to rw-romstage @%llx\n", stage->entry); + enter_stage(stage); + + /* Shouldn't reach here */ + VBDEBUG("Halting\n"); + for(;;); +}

1 0

New patch to review for coreboot: 0997785 vboot2: add verstage
by Marc Jones 07 Jan '15

07 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8159 -gerrit commit 09977850361376f438b96223a078bfad51e3e7da Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Jun 19 19:09:47 2014 -0700 vboot2: add verstage Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I42b2b3854a24ef6cda2316eb741ca379f41516e0 --- Makefile.inc | 9 ++++++++- src/arch/arm/Kconfig | 4 ++++ src/arch/arm/Makefile.inc | 2 +- src/arch/arm/armv7/Kconfig | 4 ++++ src/soc/nvidia/tegra124/Kconfig | 1 + src/soc/nvidia/tegra124/Makefile.inc | 2 ++ src/soc/nvidia/tegra124/bootblock.c | 9 ++++++++- src/soc/nvidia/tegra124/verstage.c | 9 +++++++++ src/soc/nvidia/tegra124/verstage.h | 2 ++ src/vendorcode/google/chromeos/Kconfig | 8 ++++++++ src/vendorcode/google/chromeos/Makefile.inc | 9 +++++++++ toolchain.inc | 2 +- 12 files changed, 57 insertions(+), 4 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index b0289c0..0c6aafa 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -75,7 +75,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock smm smmstub cpu_microcode +classes-y := ramstage romstage bootblock smm smmstub cpu_microcode verstage # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ @@ -128,6 +128,8 @@ ramstage-postprocess=$(foreach d,$(sort $(dir $(1))), \ $(eval $(d)ramstage.o: $(call files-in-dir,$(d),$(1)); $$(LD_ramstage) -o $$@ -r $$^ ) \ $(eval ramstage-objs:=$(d)ramstage.o $(filter-out $(call files-in-dir,$(d),$(1)),$(ramstage-objs)))) +verstage-c-ccopts:=-D__PRE_RAM__ -D__VER_STAGE__ +verstage-S-ccopts:=-D__PRE_RAM__ -D__VER_STAGE__ romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ ifeq ($(CONFIG_TRACE),y) @@ -162,6 +164,7 @@ endif ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) +verstage-c-deps:=$$(OPTION_TABLE_H) bootblock-c-deps:=$$(OPTION_TABLE_H) smm-c-deps:=$$(OPTION_TABLE_H) @@ -374,6 +377,10 @@ $(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_romstage) -MMD $(CFLAGS_romstage) $(CPPFLAGS_romstage) $(romstage-c-ccopts) -c -o $@ $< +$(obj)/%.verstage.o $(abspath $(obj))/%.verstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_verstage) -MMD $(CFLAGS_verstage) $(verstage-c-ccopts) -c -o $@ $< + $(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) -MMD $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) $(bootblock-c-ccopts) -c -o $@ $< diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 156c8c2..f73ad27 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -3,6 +3,10 @@ config ARCH_BOOTBLOCK_ARM default n select ARCH_ARM +config ARCH_VERSTAGE_ARM + bool + default n + config ARCH_ROMSTAGE_ARM bool default n diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 5698f38..ba7fb60 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -61,7 +61,7 @@ bootblock-y += memcpy.S bootblock-y += memmove.S bootblock-y += div0.c -$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) +$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $$(VERSTAGE_LIB) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm/bootblock.ld diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig index f8e0205..aa188e2 100644 --- a/src/arch/arm/armv7/Kconfig +++ b/src/arch/arm/armv7/Kconfig @@ -2,6 +2,10 @@ config ARCH_BOOTBLOCK_ARMV7 def_bool n select ARCH_BOOTBLOCK_ARM +config ARCH_VERSTAGE_ARMV7 + def_bool n + select ARCH_VERSTAGE_ARM + config ARCH_ROMSTAGE_ARMV7 def_bool n select ARCH_ROMSTAGE_ARM diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 195261e..ea946e6 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -2,6 +2,7 @@ config SOC_NVIDIA_TEGRA124 bool default n select ARCH_BOOTBLOCK_ARMV4 + select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 792bb99..b306412 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -20,6 +20,8 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c endif +verstage-y += verstage.c + romstage-y += cbfs.c romstage-y += cbmem.c romstage-y += clock.c diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 2857a90..0456b48 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -23,10 +23,13 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/nvidia/tegra/apbmisc.h> - #include "pinmux.h" #include "power.h" +#if CONFIG_VBOOT2_VERIFY_FIRMWARE +#include "verstage.h" +#endif + void main(void) { void *entry; @@ -72,7 +75,11 @@ void main(void) power_enable_cpu_rail(); power_ungate_cpu(); +#if CONFIG_VBOOT2_VERIFY_FIRMWARE + entry = (void *)verstage_vboot_main; +#else entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); +#endif if (entry) clock_cpu0_config_and_reset(entry); diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c new file mode 100644 index 0000000..234a89d --- /dev/null +++ b/src/soc/nvidia/tegra124/verstage.c @@ -0,0 +1,9 @@ +#include "verstage.h" + +/** + * Stage entry point + */ +void vboot_main(void) +{ + for(;;); +} diff --git a/src/soc/nvidia/tegra124/verstage.h b/src/soc/nvidia/tegra124/verstage.h new file mode 100644 index 0000000..a0bac34 --- /dev/null +++ b/src/soc/nvidia/tegra124/verstage.h @@ -0,0 +1,2 @@ +void vboot_main(void); +void verstage_vboot_main(void); diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 8156758..62d991b 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -85,6 +85,14 @@ config VBOOT_VERIFY_FIRMWARE Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the ramstage and boot loader. +config VBOOT2_VERIFY_FIRMWARE + bool "Firmware Verification with vboot2" + default n + depends on CHROMEOS + help + Enabling VBOOT2_VERIFY_FIRMWARE will use vboot2 to verify the romstage + and boot loader. + config EC_SOFTWARE_SYNC bool "Enable EC software sync" default n diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index e17f50c..12d35b6 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -93,3 +93,12 @@ $(VB_LIB): fwlib endif + +ifeq ($(CONFIG_VBOOT2_VERIFY_FIRMWARE),y) +VERSTAGE_LIB = $(obj)/vendorcode/google/chromeos/verstage.a +$(VERSTAGE_LIB): $$(verstage-objs) + @printf " AR $(subst $(obj)/,,$(@))\n" + $(AR_verstage) rc $@.tmp $(verstage-objs) + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY_verstage) --prefix-symbols=verstage_ $@.tmp $@ +endif diff --git a/toolchain.inc b/toolchain.inc index e6f530a..40fff39 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -51,7 +51,7 @@ HOSTCXX:=CCC_CXX="$(HOSTCXX)" $(CXX) ROMCC=CCC_CC="$(ROMCC_BIN)" $(CC) endif -COREBOOT_STANDARD_STAGES := bootblock romstage ramstage +COREBOOT_STANDARD_STAGES := bootblock verstage romstage ramstage ARCHDIR-i386 := x86 ARCHDIR-x86_32 := x86

1 0

Patch set updated for coreboot: 5edfd12 CBMEM: Always use DYNAMIC_CBMEM
by Kyösti Mälkki 07 Jan '15

07 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7851 -gerrit commit 5edfd12545975931745475ae7630584cc0e34d10 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 28 11:24:19 2014 +0200 CBMEM: Always use DYNAMIC_CBMEM Drop the implementation of statically allocated high memory region for CBMEM. There is no longer the need to explicitly select DYNAMIC_CBMEM, it is the only remaining choice. Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 10 +- src/arch/x86/boot/cbmem.c | 21 -- src/arch/x86/boot/tables.c | 9 +- src/cpu/allwinner/a10/Kconfig | 1 - src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 1 - src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/haswell/romstage.c | 5 +- src/cpu/ti/am335x/Kconfig | 1 - src/include/cbmem.h | 31 --- src/include/rmodule.h | 2 - src/lib/Makefile.inc | 13 +- src/lib/cbmem.c | 288 ---------------------- src/lib/rmodule.c | 8 +- src/mainboard/emulation/qemu-armv7/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 - src/mainboard/emulation/qemu-q35/Kconfig | 1 - src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 1 - src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/nehalem/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 4 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 2 - src/soc/nvidia/tegra124/Kconfig | 1 - src/soc/samsung/exynos5250/Kconfig | 1 - src/soc/samsung/exynos5420/Kconfig | 1 - src/soc/ucb/riscv/Kconfig | 1 - 30 files changed, 7 insertions(+), 408 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 560f9e5..e5dc26b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,14 +159,6 @@ config INCLUDE_CONFIG_FILE config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT -config DYNAMIC_CBMEM - bool - default n - help - Instead of reserving a static amount of CBMEM space the CBMEM - area grows dynamically. CBMEM can be used both in romstage (after - memory initialization) and ramstage. - config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" default n @@ -200,7 +192,7 @@ config RELOCATABLE_MODULES loaded anywhere and all the relocations are handled automatically. config RELOCATABLE_RAMSTAGE - depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM && EARLY_CBMEM_INIT) + depends on (RELOCATABLE_MODULES && EARLY_CBMEM_INIT) bool "Build the ramstage to be relocatable in 32-bit address space." default n help diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 1036adc..762d246 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -26,21 +26,6 @@ #include <console/cbmem_console.h> #include <timestamp.h> -#if !CONFIG_DYNAMIC_CBMEM -void get_cbmem_table(uint64_t *base, uint64_t *size) -{ - uint64_t top_of_ram = get_top_of_ram(); - - if (top_of_ram >= HIGH_MEMORY_SIZE) { - *base = top_of_ram - HIGH_MEMORY_SIZE; - *size = HIGH_MEMORY_SIZE; - } else { - *base = 0; - *size = 0; - } -} -#endif /* !DYNAMIC_CBMEM */ - #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) @@ -52,11 +37,7 @@ void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) void set_top_of_ram(uint64_t ramtop) { backup_top_of_ram(ramtop); -#if !CONFIG_DYNAMIC_CBMEM - cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); -#else cbmem_set_top((void*)(uintptr_t)ramtop); -#endif } #endif /* !__PRE_RAM__ */ @@ -66,13 +47,11 @@ unsigned long __attribute__((weak)) get_top_of_ram(void) return 0; } -#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM) void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ return (void *)get_top_of_ram(); } -#endif #endif /* LATE_CBMEM_INIT */ diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index c2265ea..712f66f 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -101,11 +101,8 @@ void write_tables(void) #endif /* CONFIG_GENERATE_MP_TABLE */ #if CONFIG_HAVE_ACPI_TABLES -#if CONFIG_DYNAMIC_CBMEM #define MAX_ACPI_SIZE (144 * 1024) -#else -#define MAX_ACPI_SIZE (45 * 1024) -#endif + post_code(0x9c); /* Write ACPI tables to F segment and high tables area */ @@ -199,11 +196,7 @@ void write_tables(void) /* FIXME: The high_table_base parameter is not reference when tables are high, * or high_table_pointer >1 MB. */ -#if CONFIG_DYNAMIC_CBMEM u64 fixme_high_tables_base = 0; -#else - u64 fixme_high_tables_base = (u32)get_cbmem_toc(); -#endif /* Also put a forwarder entry into 0-4K */ new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index b7b435f..2bf32ec 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select CPU_HAS_BOOTBLOCK_INIT - select DYNAMIC_CBMEM # The "eGON.BT0" header takes 32 bytes config BOOTBLOCK_BASE diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 9b0edfc..e9cbe43 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select BROKEN_CAR_MIGRATE - select DYNAMIC_CBMEM config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 2f891ad..5cd4c65 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select BROKEN_CAR_MIGRATE - select DYNAMIC_CBMEM choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 0597363..37ae5b3 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -18,7 +18,6 @@ config CPU_SPECIFIC_OPTIONS select SMM_MODULES select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE - select DYNAMIC_CBMEM select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 1af5259..50150cf 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -75,14 +75,11 @@ static inline u32 *stack_push(u32 *stack, u32 value) static unsigned long choose_top_of_stack(void) { unsigned long stack_top; -#if CONFIG_DYNAMIC_CBMEM + /* cbmem_add() does a find() before add(). */ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, ROMSTAGE_RAM_STACK_SIZE); stack_top += ROMSTAGE_RAM_STACK_SIZE; -#else - stack_top = CONFIG_RAMTOP; -#endif return stack_top; } diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index eb60ad1..fae527d 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -6,7 +6,6 @@ config CPU_TI_AM335X select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select CPU_HAS_BOOTBLOCK_INIT - select DYNAMIC_CBMEM bool default n diff --git a/src/include/cbmem.h b/src/include/cbmem.h index c2e7314..ca7a5f4 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -118,8 +118,6 @@ struct cbmem_id_to_name { struct cbmem_entry; -#if CONFIG_DYNAMIC_CBMEM - /* * The dynamic cbmem infrastructure allows for growing cbmem dynamically as * things are added. It requires an external function, cbmem_top(), to be @@ -171,35 +169,6 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry); -#else /* !CONFIG_DYNAMIC_CBMEM */ - -/* Allocation with static CBMEM is resolved at build time. We start - * with 128kB and conditionally add some of the most greedy CBMEM - * table entries. - */ -#define _CBMEM_SZ_MINIMAL ( 128 * 1024 ) - -#define _CBMEM_SZ_TOTAL \ - (_CBMEM_SZ_MINIMAL + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE + \ - HIGH_MEMORY_SAVE + HIGH_MEMORY_SCRATCH) - -#define HIGH_MEMORY_SIZE ALIGN_UP(_CBMEM_SZ_TOTAL, 0x10000) - -#ifndef __PRE_RAM__ -void cbmem_late_set_table(uint64_t base, uint64_t size); -#endif - -void get_cbmem_table(uint64_t *base, uint64_t *size); -struct cbmem_entry *get_cbmem_toc(void); - -static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id) -{ - return NULL; -} -#endif /* CONFIG_DYNAMIC_CBMEM */ - -/* Common API between cbmem and dynamic cbmem. */ - /* Returns 0 if old cbmem was recovered. Recovery is only attempted if * s3resume is non-zero. */ int cbmem_recovery(int s3resume); diff --git a/src/include/rmodule.h b/src/include/rmodule.h index d229cf8..76b855a 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -54,7 +54,6 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, /* Support for loading rmodule stages. This API is only available when * using dynamic cbmem because it uses the dynamic cbmem API to obtain * the backing store region for the stage. */ -#if CONFIG_DYNAMIC_CBMEM struct cbfs_stage; struct cbmem_entry; @@ -70,7 +69,6 @@ struct rmod_stage_load { /* Both of the following functions return 0 on success, -1 on error. */ int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage); int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl); -#endif struct rmodule { void *location; diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e35116b..c3658d2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -74,17 +74,8 @@ ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -# The CBMEM implementations are chosen based on CONFIG_DYNAMIC_CBMEM. -ifeq ($(CONFIG_DYNAMIC_CBMEM),y) -ramstage-y += dynamic_cbmem.c -romstage-y += dynamic_cbmem.c -else -ramstage-y += cbmem.c -romstage-y += cbmem.c -endif # CONFIG_DYNAMIC_CBMEM - -romstage-y += cbmem_common.c -ramstage-y += cbmem_common.c +romstage-y += cbmem_common.c dynamic_cbmem.c +ramstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += hexdump.c romstage-y += hexdump.c diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c deleted file mode 100644 index d5f89a1..0000000 --- a/src/lib/cbmem.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ - -#include <types.h> -#include <string.h> -#include <bootmem.h> -#include <bootstate.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/early_variables.h> -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) -#include <arch/acpi.h> -#endif - -// The CBMEM TOC reserves 512 bytes to keep -// the other entries somewhat aligned. -// Increase if MAX_CBMEM_ENTRIES exceeds 21 -#define CBMEM_TOC_RESERVED 512 -#define MAX_CBMEM_ENTRIES 16 -#define CBMEM_MAGIC 0x434f5245 - -struct cbmem_entry { - u32 magic; - u32 id; - u64 base; - u64 size; -} __attribute__((packed)); - -#ifndef __PRE_RAM__ -static uint64_t cbmem_base = 0; -static uint64_t cbmem_size = 0; -#endif - -static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) -{ - if (base && size && s) { - printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", - base, base + size - 1, s); - } -} - -static void cbmem_locate_table(uint64_t *base, uint64_t *size) -{ -#ifdef __PRE_RAM__ - get_cbmem_table(base, size); -#else - if (!(cbmem_base && cbmem_size)) { - get_cbmem_table(&cbmem_base, &cbmem_size); - cbmem_trace_location(cbmem_base, cbmem_size, __FUNCTION__); - } - *base = cbmem_base; - *size = cbmem_size; -#endif -} - -struct cbmem_entry *get_cbmem_toc(void) -{ - uint64_t base, size; - cbmem_locate_table(&base, &size); - return (struct cbmem_entry *)(unsigned long)base; -} - -#if !defined(__PRE_RAM__) -void cbmem_late_set_table(uint64_t base, uint64_t size) -{ - cbmem_trace_location(base, size, __FUNCTION__); - cbmem_base = base; - cbmem_size = size; -} -#endif - -/** - * cbmem is a simple mechanism to do some kind of book keeping of the coreboot - * high tables memory. This is a small amount of memory which is "stolen" from - * the system memory for coreboot purposes. Usually this memory is used for - * - the coreboot table - * - legacy tables (PIRQ, MP table) - * - ACPI tables - * - suspend/resume backup memory - */ - -static void cbmem_initialize_empty(void) -{ - uint64_t baseaddr, size; - struct cbmem_entry *cbmem_toc; - - cbmem_locate_table(&baseaddr, &size); - cbmem_trace_location(baseaddr, size, __FUNCTION__); - - if (!(baseaddr && size)) { - printk(BIOS_CRIT, "Unable to set location for CBMEM.\n"); - return; - } - - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); - - cbmem_toc[0] = (struct cbmem_entry) { - .magic = CBMEM_MAGIC, - .id = CBMEM_ID_FREESPACE, - .base = baseaddr + CBMEM_TOC_RESERVED, - .size = size - CBMEM_TOC_RESERVED - }; -} - -static int cbmem_check_toc(void) -{ - uint64_t baseaddr, size; - struct cbmem_entry *cbmem_toc; - - cbmem_locate_table(&baseaddr, &size); - cbmem_trace_location(baseaddr, size, __FUNCTION__); - - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - - return (cbmem_toc[0].magic == CBMEM_MAGIC); -} - -void *cbmem_add(u32 id, u64 size) -{ - struct cbmem_entry *cbmem_toc; - int i; - void *p; - - /* - * This could be a restart, check if the section is there already. It - * is remotely possible that the dram contents persisted over the - * bootloader upgrade AND the same section now needs more room, but - * this is quite a remote possibility and it is ignored here. - */ - p = cbmem_find(id); - if (p) { - printk(BIOS_NOTICE, - "CBMEM section %x: using existing location at %p.\n", - id, p); - return p; - } - - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) { - return NULL; - } - - if (cbmem_toc[0].magic != CBMEM_MAGIC) { - printk(BIOS_ERR, "ERROR: CBMEM was not initialized yet.\n"); - return NULL; - } - - /* Will the entry fit at all? */ - if (size > cbmem_toc[0].size) { - printk(BIOS_ERR, "ERROR: Not enough memory for table %x\n", id); - return NULL; - } - - /* Align size to 512 byte blocks */ - - size = ALIGN(size, 512) < cbmem_toc[0].size ? - ALIGN(size, 512) : cbmem_toc[0].size; - - /* Now look for the first free/usable TOC entry */ - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - if (cbmem_toc[i].id == CBMEM_ID_NONE) - break; - } - - if (i >= MAX_CBMEM_ENTRIES) { - printk(BIOS_ERR, "ERROR: No more CBMEM entries available.\n"); - return NULL; - } - - printk(BIOS_DEBUG, "Adding CBMEM entry as no. %d\n", i); - - cbmem_toc[i] = (struct cbmem_entry) { - .magic = CBMEM_MAGIC, - .id = id, - .base = cbmem_toc[0].base, - .size = size - }; - - cbmem_toc[0].base += size; - cbmem_toc[0].size -= size; - - return (void *)(uintptr_t)cbmem_toc[i].base; -} - -void *cbmem_find(u32 id) -{ - struct cbmem_entry *cbmem_toc; - int i; - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) - return NULL; - - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - if (cbmem_toc[i].id == id) - return (void *)(unsigned long)cbmem_toc[i].base; - } - - return (void *)NULL; -} - -/* Returns True if it was not initialized before. */ -int cbmem_recovery(int is_wakeup) -{ - int found = cbmem_check_toc(); - int wipe = 0; - - /* CBMEM TOC is wiped clean when we are not waking up from S3 - * suspend. Boards with EARLY_CBMEM_INIT do this in romstage, - * boards without EARLY_CBMEM_INIT do this in ramstage. - */ -#if defined(__PRE_RAM__) && CONFIG_EARLY_CBMEM_INIT - wipe = 1; -#endif -#if !defined(__PRE_RAM__) && !CONFIG_EARLY_CBMEM_INIT - wipe = 1; -#endif - - if (!is_wakeup && wipe) - cbmem_initialize_empty(); - - if (is_wakeup && !found) { - cbmem_initialize_empty(); - cbmem_fail_resume(); - } - - /* Complete migration to CBMEM. */ - cbmem_run_init_hooks(); - - return !found; -} - -#ifndef __PRE_RAM__ -static void init_cbmem_post_device(void *unused) -{ -#if CONFIG_HAVE_ACPI_RESUME - cbmem_recovery(acpi_is_wakeup()); -#else - cbmem_recovery(0); -#endif -} - -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, - init_cbmem_post_device, NULL), -}; - -void cbmem_add_bootmem(void) -{ - bootmem_add_range(cbmem_base, cbmem_size, LB_MEM_TABLE); -} - -void cbmem_list(void) -{ - struct cbmem_entry *cbmem_toc; - int i; - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) - return; - - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - - if (cbmem_toc[i].magic != CBMEM_MAGIC) - continue; - cbmem_print_entry(i, cbmem_toc[i].id, cbmem_toc[i].base, - cbmem_toc[i].size); - } -} -#endif diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 908297b..5c6df02 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <assert.h> +#include <cbmem.h> +#include <cbfs_core.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -249,10 +251,6 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, return region_alignment - sizeof(struct rmodule_header); } -#if CONFIG_DYNAMIC_CBMEM -#include <cbmem.h> -#include <cbfs_core.h> - int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) { struct rmodule rmod_stage; @@ -307,5 +305,3 @@ int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl) return rmodule_stage_load(rsl, stage); } - -#endif /* DYNAMIC_CBMEM */ diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 7e24a20..b275e88 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARM_ROMSTAGE_ARMV7 select ARM_RAMSTAGE_ARMV7 select BOARD_ROMSIZE_KB_4096 - select DYNAMIC_CBMEM config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index b002c21..406612e 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 - select DYNAMIC_CBMEM select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 4931523..08d563f 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -130,10 +130,6 @@ static void cpu_pci_domain_read_resources(struct device *dev) "debugcon"); } -#if !CONFIG_DYNAMIC_CBMEM - set_top_of_ram(tomk * 1024); -#endif - if (q35 && ((tomk * 1024) < 0xb0000000)) { /* * Reserve the region between top-of-ram and the diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 3949937..fcc750c 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 - select DYNAMIC_CBMEM select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index fa08acc..a804fd3 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select DYNAMIC_CBMEM select INTEL_INT15 select VGA select INTEL_EDID diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index fac7329..096c80f 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -27,7 +27,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_DEBUG_RAM_SETUP select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select IOMMU select VGA select INTEL_EDID diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index c578011..8a0cb5b 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER select VGA diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index b49f331..ca5ffa5 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,7 +22,6 @@ config NORTHBRIDGE_INTEL_NEHALEM select CPU_INTEL_MODEL_2065X select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select VGA select INTEL_EDID select TSC_MONOTONIC_TIMER diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 647b4fb..11370f5 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -22,7 +22,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX select PER_DEVICE_ACPI_TABLES @@ -31,7 +30,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES @@ -41,7 +39,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_306AX select PER_DEVICE_ACPI_TABLES @@ -50,7 +47,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index bcaa1ff..28dc7d7 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS - select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index b93216e..2c5ebd3 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS - select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index b61fac3..081ea09 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -30,8 +30,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_BOOTBLOCK_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select DYNAMIC_CBMEM - select BROKEN_CAR_MIGRATE select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 195261e..89d07c5 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA124 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE - select DYNAMIC_CBMEM select ARM_BOOTBLOCK_CUSTOM select ARM_LPAE diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 8d7c867..9cbd37f 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -5,7 +5,6 @@ config CPU_SAMSUNG_EXYNOS5250 select CPU_HAS_BOOTBLOCK_INIT select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select DYNAMIC_CBMEM bool default n diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 904091e..c9f2ec6 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -6,7 +6,6 @@ config CPU_SAMSUNG_EXYNOS5420 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select RELOCATABLE_MODULES - select DYNAMIC_CBMEM bool default n diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index be4a675..d1e4ba7 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -3,7 +3,6 @@ config SOC_UCB_RISCV select ARCH_BOOTBLOCK_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV - select DYNAMIC_CBMEM bool default n

1 0

Patch set updated for coreboot: 2d03988 CBMEM: Tag chipsets with LATE_CBMEM_INIT
by Kyösti Mälkki 07 Jan '15

07 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7850 -gerrit commit 2d03988806d41af3e1363ff8051227843b879bf7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 18 22:22:04 2014 +0200 CBMEM: Tag chipsets with LATE_CBMEM_INIT In preparation to remove the static CBMEM allocator, tag the chipsets that still do not implement get_top_of_ram() for romstage. LATE_CBMEM_INIT also implies BROKEN_CAR_MIGRATE. Change-Id: Iad359db2e65ac15c54ff6e9635429628e4db6fde Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 15 ++++++++------- src/arch/x86/boot/cbmem.c | 2 +- src/northbridge/amd/agesa/Kconfig | 1 + src/northbridge/amd/amdfam10/Kconfig | 1 + src/northbridge/amd/amdk8/Kconfig | 1 + src/northbridge/amd/gx2/Kconfig | 1 + src/northbridge/amd/lx/Kconfig | 1 + src/northbridge/amd/pi/Kconfig | 1 + src/northbridge/dmp/vortex86ex/Kconfig | 1 + src/northbridge/intel/e7501/Kconfig | 1 + src/northbridge/intel/e7505/Kconfig | 1 + src/northbridge/intel/i3100/Kconfig | 1 + src/northbridge/intel/i440bx/Kconfig | 1 + src/northbridge/intel/i440lx/Kconfig | 1 + src/northbridge/intel/i5000/Kconfig | 1 + src/northbridge/intel/i82810/Kconfig | 1 + src/northbridge/intel/i82830/Kconfig | 1 + src/northbridge/intel/i855/Kconfig | 1 + src/northbridge/intel/sch/Kconfig | 1 + src/northbridge/rdc/r8610/Kconfig | 1 + src/northbridge/via/cn700/Kconfig | 1 + src/northbridge/via/cx700/Kconfig | 1 + src/northbridge/via/vx800/Kconfig | 1 + src/northbridge/via/vx900/Kconfig | 1 + 24 files changed, 31 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 4b10e17..92714d5 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -157,16 +157,17 @@ config INCLUDE_CONFIG_FILE (empty) 0x8e480 null 3610440 config EARLY_CBMEM_INIT - bool - default n + def_bool !LATE_CBMEM_INIT + +config LATE_CBMEM_INIT + def_bool n help - Make coreboot initialize the CBMEM structures while running in ROM - stage. This is useful when the ROM stage wants to communicate - some, for instance, execution timestamps. It needs support in - romstage.c and should be enabled by the board's Kconfig. + Enable this in chipset's Kconfig if northbridge does not implement + early get_top_of_ram() call for romstage. CBMEM tables will be + allocated late in ramstage, after PCI devices resources are known. config BROKEN_CAR_MIGRATE - def_bool !EARLY_CBMEM_INIT + def_bool LATE_CBMEM_INIT help Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and manage CAR migration on S3 resume path only. Couple boards use diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 34309c2..af42edd 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -56,7 +56,7 @@ void set_top_of_ram(uint64_t ramtop) } #endif /* !__PRE_RAM__ */ -#if CONFIG_BROKEN_CAR_MIGRATE || !defined(__PRE_RAM__) +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) unsigned long __attribute__((weak)) get_top_of_ram(void) { printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 68551fb..8fd8bfd 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_AMD_AGESA bool default CPU_AMD_AGESA + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 0789ac3..13b912e 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 8bee5ca..65dc173 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -24,6 +24,7 @@ config NORTHBRIDGE_AMD_AMDK8 select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDK8 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/gx2/Kconfig b/src/northbridge/amd/gx2/Kconfig index dc347c4..1fe33f8 100644 --- a/src/northbridge/amd/gx2/Kconfig +++ b/src/northbridge/amd/gx2/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_AMD_GX2 bool select GEODE_VSA + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_GX2 diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index d74d715..abc3e4c 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_AMD_LX bool select GEODE_VSA + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_LX diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 8af4872..2b8e356 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_AMD_PI bool default CPU_AMD_PI + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI diff --git a/src/northbridge/dmp/vortex86ex/Kconfig b/src/northbridge/dmp/vortex86ex/Kconfig index 7bf5235..74239ad 100644 --- a/src/northbridge/dmp/vortex86ex/Kconfig +++ b/src/northbridge/dmp/vortex86ex/Kconfig @@ -19,3 +19,4 @@ config NORTHBRIDGE_DMP_VORTEX86EX bool + select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/e7501/Kconfig b/src/northbridge/intel/e7501/Kconfig index 88c0b45..763b96e 100644 --- a/src/northbridge/intel/e7501/Kconfig +++ b/src/northbridge/intel/e7501/Kconfig @@ -2,4 +2,5 @@ config NORTHBRIDGE_INTEL_E7501 bool select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index ff7f5a5..e755852 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT config HW_SCRUBBER bool diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 079004b..cb0bd38 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I3100 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_INTEL_I3100 config DIMM_MAP_LOGICAL diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 902eb73..c5cc43e 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_INTEL_I440BX bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT config SDRAMPWR_4DIMM bool diff --git a/src/northbridge/intel/i440lx/Kconfig b/src/northbridge/intel/i440lx/Kconfig index a88a7a1..1ccaac6 100644 --- a/src/northbridge/intel/i440lx/Kconfig +++ b/src/northbridge/intel/i440lx/Kconfig @@ -20,4 +20,5 @@ config NORTHBRIDGE_INTEL_I440LX bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig index f7344ca..3bd685a 100644 --- a/src/northbridge/intel/i5000/Kconfig +++ b/src/northbridge/intel/i5000/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_I5000 select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT if NORTHBRIDGE_INTEL_I5000 diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig index 79fe36a..723f751 100644 --- a/src/northbridge/intel/i82810/Kconfig +++ b/src/northbridge/intel/i82810/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_INTEL_I82810 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT choice prompt "Onboard graphics" diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig index 20b31a2..662840f 100644 --- a/src/northbridge/intel/i82830/Kconfig +++ b/src/northbridge/intel/i82830/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_INTEL_I82830 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT choice prompt "Onboard graphics" diff --git a/src/northbridge/intel/i855/Kconfig b/src/northbridge/intel/i855/Kconfig index f5c2890..44becf6 100644 --- a/src/northbridge/intel/i855/Kconfig +++ b/src/northbridge/intel/i855/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_INTEL_I855 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT choice prompt "Onboard graphics" diff --git a/src/northbridge/intel/sch/Kconfig b/src/northbridge/intel/sch/Kconfig index b8dad72..f495e6a 100644 --- a/src/northbridge/intel/sch/Kconfig +++ b/src/northbridge/intel/sch/Kconfig @@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_SCH bool select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT if NORTHBRIDGE_INTEL_SCH diff --git a/src/northbridge/rdc/r8610/Kconfig b/src/northbridge/rdc/r8610/Kconfig index 85461b7..e93a3e6 100644 --- a/src/northbridge/rdc/r8610/Kconfig +++ b/src/northbridge/rdc/r8610/Kconfig @@ -1,2 +1,3 @@ config NORTHBRIDGE_RDC_R8610 bool + select LATE_CBMEM_INIT diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig index 34c330e..15c86eb 100644 --- a/src/northbridge/via/cn700/Kconfig +++ b/src/northbridge/via/cn700/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_VIA_CN700 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT # TODO: Values are from the CX700 datasheet, not sure if this matches CN700. # TODO: What should be the per-chipset default value here? diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig index 8f6e337..03014eb 100644 --- a/src/northbridge/via/cx700/Kconfig +++ b/src/northbridge/via/cx700/Kconfig @@ -5,6 +5,7 @@ config NORTHBRIDGE_VIA_CX700 select HAVE_HARD_RESET select IOAPIC select SMP + select LATE_CBMEM_INIT # TODO: What should be the per-chipset default value here? choice diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index 48ea456..a59fc41 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -2,4 +2,5 @@ config NORTHBRIDGE_VIA_VX800 bool select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS + select LATE_CBMEM_INIT diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 9fe5909..617074f 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_VIA_VX900 select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select LATE_CBMEM_INIT if NORTHBRIDGE_VIA_VX900

1 0

Patch set updated for coreboot: 7428a29 CBMEM console: Fix CAR migration step
by Kyösti Mälkki 07 Jan '15

07 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8032 -gerrit commit 7428a296ea859dbd606f8f2e8db9a9beb551ceb2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 18:34:59 2014 +0200 CBMEM console: Fix CAR migration step With the change it becomes irrelevant if memcpy() car.global_data or cbmemc_reinit() is done first. Change-Id: Ie479eef346c959e97dcc55861ccb0db1321fb7b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/include/arch/early_variables.h | 1 + src/arch/arm64/include/arch/early_variables.h | 1 + src/arch/riscv/include/arch/early_variables.h | 1 + src/arch/x86/include/arch/early_variables.h | 6 +++++ src/cpu/x86/car.c | 32 +++++++++++++++++++++++++++ src/lib/cbmem_console.c | 2 +- 6 files changed, 42 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 5b58baa..cb0872e 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -25,6 +25,7 @@ #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) +#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) static inline void car_migrate_variables(void) { } diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 3d9fa26..4b7c05b 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -29,6 +29,7 @@ #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) +#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) static inline void car_migrate_variables(void) { } diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h index 3a1f20d..f9516a4 100644 --- a/src/arch/riscv/include/arch/early_variables.h +++ b/src/arch/riscv/include/arch/early_variables.h @@ -29,6 +29,7 @@ #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) +#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) static inline void car_migrate_variables(void) { } diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index f76c048..2d5ae85 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -39,9 +39,14 @@ asm(".previous"); /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); +/* Get and update a CAR_GLOBAL pointing elsewhere in car.global_data*/ +void *car_sync_var_ptr(void *var); + /* Get and set a primitive type global variable. */ #define car_get_var(var) \ *(typeof(var) *)car_get_var_ptr(&(var)) +#define car_sync_var(var) \ + *(typeof (var) *)car_sync_var_ptr(&(var)) #define car_set_var(var, val) \ do { car_get_var(var) = (val); } while(0) @@ -49,6 +54,7 @@ void *car_get_var_ptr(void *var); #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) +#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) #endif diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index c9cc6d6..e757f09 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -73,6 +73,38 @@ void *car_get_var_ptr(void *var) return &migrated_base[offset]; } +/* + * Update a CAR_GLOBAL variable var, originally pointing to CAR region, + * with the address in migrated CAR region in DRAM. + */ +void *car_sync_var_ptr(void *var) +{ + void ** mig_var = car_get_var_ptr(var); + void * _car_start = &_car_data_start; + void * _car_end = &_car_data_end; + + /* Not moved or migrated yet. */ + if (mig_var == var) + return mig_var; + + /* It's already pointing outside car.global_data. */ + if (*mig_var < _car_start || *mig_var > _car_end) + return mig_var; + +#if !IS_ENABLED(CONFIG_PLATFORM_USES_FSP) + /* Keep console buffer in CAR until cbmemc_reinit() moves it. */ + if (*mig_var == _car_end) + return mig_var; +#endif + + /* Move the pointer by the same amount the variable storing it was + * moved by. + */ + *mig_var += (char *)mig_var - (char *)var; + + return mig_var; +} + static void do_car_migrate_variables(void) { void *migrated_base; diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 997bb7d..a8195a6 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -65,7 +65,7 @@ static u8 static_console[STATIC_CONSOLE_SIZE]; static inline struct cbmem_console *current_console(void) { - return car_get_var(cbmem_console_p); + return car_sync_var(cbmem_console_p); } static inline void current_console_set(struct cbmem_console *new_console_p)

1 0

Patch set updated for coreboot: f7a4f2d CBMEM: Add timestamp_reinit()
by Kyösti Mälkki 07 Jan '15

07 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8033 -gerrit commit f7a4f2d14f041b56605399cbc5d05c75269c8013 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 19 10:17:46 2014 +0200 CBMEM: Add timestamp_reinit() This avoids the need for separate timestamp_reinit() calls made via CAR_MIGRATE() that is not implemented for ARM. Change-Id: Ia683162f3cb5d3cb3d4b7983a4b7e13306b0cfc8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 4 ++++ src/lib/cbmem_common.c | 4 ++++ src/lib/hardwaremain.c | 2 -- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index b53745b..34309c2 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -23,6 +23,7 @@ /* FIXME: Remove after CBMEM_INIT_HOOKS. */ #include <cpu/x86/gdt.h> #include <console/cbmem_console.h> +#include <timestamp.h> #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) @@ -79,6 +80,9 @@ void cbmem_run_init_hooks(void) /* Relocate CBMEM console. */ cbmemc_reinit(); + /* Relocate timestamps stash. */ + timestamp_reinit(); + move_gdt(); #endif } diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 0389c9d..129aa09 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -22,6 +22,7 @@ /* FIXME: Remove after CBMEM_INIT_HOOKS. */ #include <console/cbmem_console.h> +#include <timestamp.h> #ifndef __PRE_RAM__ @@ -56,6 +57,9 @@ void __attribute__((weak)) cbmem_run_init_hooks(void) { /* Relocate CBMEM console. */ cbmemc_reinit(); + + /* Relocate timestamps stash. */ + timestamp_reinit(); } void __attribute__((weak)) cbmem_fail_resume(void) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index e01247b..d43ff46 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -181,8 +181,6 @@ static boot_state_t bs_post_device(void *arg) dev_finalize(); timestamp_add_now(TS_DEVICE_DONE); - timestamp_reinit(); - return BS_OS_RESUME_CHECK; }

1 0

Patch set updated for coreboot: d56e12b cbmem: [NOTFORMERGE] CBMEM_INIT_HOOK() API
by Kyösti Mälkki 07 Jan '15

07 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7878 -gerrit commit d56e12b6ea67dde06f214261b1d867de8a069dc3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jan 7 04:48:43 2015 +0200 cbmem: [NOTFORMERGE] CBMEM_INIT_HOOK() API Squashed two changes from chromium.git. cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API There are several use cases for performing a certain task when CBMEM is first set up (usually to migrate some data into it that was previously kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them differently: timestamp migration is called explicitly from cbmem_initialize(), certain x86-chipset-specific tasks use the CAR_MIGRATION() macro to register a hook, and the CBMEM console is migrated through a direct call from romstage (on non-x86 and SandyBridge boards). This patch decouples the CAR_MIGRATION() hook mechanism from cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer description of what it really does. All of the above use cases are ported to this new, consistent model, allowing us to have one less line of boilerplate in non-CAR romstages. BRANCH=None BUG=None TEST=Built and booted on Nyan_Blaze and Falco with and without CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after boot (and the resume log after S3 resume on Falco). Compiled for Parrot, Stout and Lumpy. Original-Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232612 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> cbmem: Extend hooks to ramstage, fix timestamp synching Commit 7dd5bbd71 (cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API) inadvertently broke ramstage timestamps since timestamp_sync() was no longer called there. Oops. This patch fixes the issue by extending the CBMEM_INIT_HOOK() mechanism to the cbmem_initialize() call in ramstage. The macro is split into explicit ROMSTAGE_/RAMSTAGE_ versions to make the behavior as clear as possible and prevent surprises (although just using a single macro and relying on the Makefiles to link an object into all appropriate stages would also work). This allows us to get rid of the explicit cbmemc_reinit() in ramstage (which I somehow accounted for in the last patch without realizing that timestamps work exactly the same way...), and replace the older and less flexible cbmem_arch_init() mechanism. Also added a size assertion for the pre-RAM CBMEM console to memlayout that could prevent a very unlikely buffer overflow I just noticed. BRANCH=None BUG=None TEST=Booted on Pinky and Falco, confirmed that ramstage timestamps once again show up. Compile-tested for Rambi and Samus. Original-Change-Id: If907266c3f20dc3d599b5c968ea5b39fe5c00e9c Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233533 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I1be89bafacfe85cba63426e2d91f5d8d4caa1800 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/include/arch/early_variables.h | 1 - src/arch/arm64/include/arch/early_variables.h | 1 - src/arch/x86/boot/cbmem.c | 22 ----- src/arch/x86/boot/gdt.c | 3 +- src/arch/x86/include/arch/early_variables.h | 14 --- src/arch/x86/init/romstage.ld | 9 +- src/cpu/x86/car.c | 21 +---- src/drivers/usb/ehci_debug.c | 2 +- src/include/cbmem.h | 20 ++++- src/include/cpu/x86/gdt.h | 3 - src/include/timestamp.h | 2 - src/lib/cbmem_common.c | 20 ++--- src/lib/cbmem_console.c | 6 +- src/lib/ramstage.ld | 117 +++++++++++++++++++++++++ src/lib/rmodule.ld | 3 + src/lib/romstage.ld | 62 +++++++++++++ src/lib/timestamp.c | 7 +- src/soc/intel/baytrail/romstage/romstage.c | 2 +- src/soc/intel/broadwell/romstage/power_state.c | 2 +- 19 files changed, 227 insertions(+), 90 deletions(-) diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 97bc0cd..f7266d4 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -22,7 +22,6 @@ #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 97bc0cd..f7266d4 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -22,7 +22,6 @@ #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 762d246..414782a 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -20,12 +20,6 @@ #include <cbmem.h> #include <arch/acpi.h> -/* FIXME: Remove after CBMEM_INIT_HOOKS. */ -#include <arch/early_variables.h> -#include <cpu/x86/gdt.h> -#include <console/cbmem_console.h> -#include <timestamp.h> - #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) @@ -55,22 +49,6 @@ void *cbmem_top(void) #endif /* LATE_CBMEM_INIT */ -void cbmem_run_init_hooks(void) -{ - /* Migrate car.global_data. */ - car_migrate_variables(); - -#if !defined(__PRE_RAM__) - /* Relocate CBMEM console. */ - cbmemc_reinit(); - - /* Relocate timestamps stash. */ - timestamp_reinit(); - - move_gdt(); -#endif -} - /* Something went wrong, our high memory area got wiped */ void cbmem_fail_resume(void) { diff --git a/src/arch/x86/boot/gdt.c b/src/arch/x86/boot/gdt.c index 7b64af7..b4cfbee 100644 --- a/src/arch/x86/boot/gdt.c +++ b/src/arch/x86/boot/gdt.c @@ -32,7 +32,7 @@ struct gdtarg { /* Copy GDT to new location and reload it. * FIXME: We only do this for BSP CPU. */ -void move_gdt(void) +static void move_gdt(void) { void *newgdt; u16 num_gdt_bytes = (u32)&gdt_end - (u32)&gdt; @@ -55,3 +55,4 @@ void move_gdt(void) __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg)); printk(BIOS_DEBUG, "ok\n"); } +RAMSTAGE_CBMEM_INIT_HOOK(move_gdt) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 2d5ae85..0f3c4f8 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -29,12 +29,6 @@ asm(".previous"); #endif #if defined(__PRE_RAM__) -#define CAR_MIGRATE_ATTR __attribute__ ((used,section (".car.migrate"))) - -/* Call migrate_fn_() when CAR globals are migrated. */ -#define CAR_MIGRATE(migrate_fn_) \ - static void (* const migrate_fn_ ## _ptr)(void) CAR_MIGRATE_ATTR = \ - migrate_fn_; /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); @@ -51,18 +45,10 @@ void *car_sync_var_ptr(void *var); do { car_get_var(var) = (val); } while(0) #else -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) #endif -#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) -/* Migrate the CAR variables to memory. */ -void car_migrate_variables(void); -#else -static inline void car_migrate_variables(void) { } -#endif - #endif diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 99bcc8e..3ade87f 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -31,15 +31,14 @@ SECTIONS _rom = .; *(.rom.text); *(.rom.data); + . = ALIGN(4); + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; *(.rodata); *(.rodata.*); *(.rom.data.*); . = ALIGN(16); - _car_migrate_start = .; - *(.car.migrate); - LONG(0); - _car_migrate_end = .; - . = ALIGN(16); _erom = .; } diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index cca9afd..4957b46 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -23,10 +23,6 @@ #include <cbmem.h> #include <arch/early_variables.h> -typedef void (* const car_migration_func_t)(void); - -extern car_migration_func_t _car_migrate_start; - extern char _car_data_start[]; extern char _car_data_end[]; @@ -127,22 +123,9 @@ static void do_car_migrate_variables(void) car_migrated = ~0; } -static void do_car_migrate_hooks(void) -{ - car_migration_func_t *migrate_func; - /* Call all the migration functions. */ - migrate_func = &_car_migrate_start; - while (*migrate_func != NULL) { - (*migrate_func)(); - migrate_func++; - } -} - -void car_migrate_variables(void) +static void car_migrate_variables(void) { if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) do_car_migrate_variables(); - - if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) - do_car_migrate_hooks(); } +ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 83c23a3..f89ea2f 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -683,7 +683,7 @@ static void migrate_ehci_debug(void) memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info)); car_set_var(glob_dbg_info_p, dbg_info_cbmem); } -CAR_MIGRATE(migrate_ehci_debug); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_ehci_debug); #endif int dbgp_ep_is_active(struct dbgp_pipe *pipe) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca7a5f4..68a03ad 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -179,16 +179,32 @@ void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); -void cbmem_run_init_hooks(void); void cbmem_fail_resume(void); +typedef void (* const cbmem_init_hook_t)(void); +void cbmem_run_init_hooks(void); + #ifndef __PRE_RAM__ /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); void cbmem_list(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); -#endif /* __PRE_RAM__ */ +#endif + +#ifndef __PRE_RAM__ +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ + static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ + section(".rodata.cbmem_init_hooks"))) = init_fn_; +#else /* __PRE_RAM__ */ +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ + static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ + section(".rodata.cbmem_init_hooks"))) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#endif /* !__PRE_RAM__ */ /* These are for compatibility with old boards only. Any new chipset and board * must implement cbmem_top() for both romstage and ramstage to support diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h index 260b158..43a80fe 100644 --- a/src/include/cpu/x86/gdt.h +++ b/src/include/cpu/x86/gdt.h @@ -28,7 +28,4 @@ extern char _secondary_gdt_addr[]; extern char _secondary_start[]; extern char _secondary_start_end[]; -/* Defined in src/arch/x86/boot/gdt.c */ -void move_gdt(void); - #endif /* CPU_X86_GDT */ diff --git a/src/include/timestamp.h b/src/include/timestamp.h index ba73135..2be3217 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -64,12 +64,10 @@ enum timestamp_id { void timestamp_init(uint64_t base); void timestamp_add(enum timestamp_id id, uint64_t ts_time); void timestamp_add_now(enum timestamp_id id); -void timestamp_reinit(void); #else #define timestamp_init(base) #define timestamp_add(id, time) #define timestamp_add_now(id) -#define timestamp_reinit() #endif /* Implemented by the architecture code */ diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 129aa09..6509c3f 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -20,10 +20,6 @@ #include <cbmem.h> #include <stdlib.h> -/* FIXME: Remove after CBMEM_INIT_HOOKS. */ -#include <console/cbmem_console.h> -#include <timestamp.h> - #ifndef __PRE_RAM__ static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; @@ -52,14 +48,16 @@ void cbmem_print_entry(int n, u32 id, u64 base, u64 size) #endif /* !__PRE_RAM__ */ -/* FIXME: Replace with CBMEM_INIT_HOOKS API. */ -void __attribute__((weak)) cbmem_run_init_hooks(void) -{ - /* Relocate CBMEM console. */ - cbmemc_reinit(); +extern cbmem_init_hook_t _cbmem_init_hooks; +extern cbmem_init_hook_t _ecbmem_init_hooks; - /* Relocate timestamps stash. */ - timestamp_reinit(); +void cbmem_run_init_hooks(void) +{ + cbmem_init_hook_t *init_hook_ptr = &_cbmem_init_hooks; + while (init_hook_ptr != &_ecbmem_init_hooks) { + (*init_hook_ptr)(); + init_hook_ptr++; + } } void __attribute__((weak)) cbmem_fail_resume(void) diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 0c2722c..7f13292 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -208,7 +208,7 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p, new_cons_p->buffer_cursor = cursor; } -void cbmemc_reinit(void) +static void cbmemc_reinit(void) { struct cbmem_console *cbm_cons_p = NULL; int flags = CBMEMC_APPEND; @@ -227,5 +227,5 @@ void cbmemc_reinit(void) init_console_ptr(cbm_cons_p, CONFIG_CONSOLE_CBMEM_BUFFER_SIZE, flags); } -/* Call cbmemc_reinit() at CAR migration time. */ -CAR_MIGRATE(cbmemc_reinit) +ROMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld new file mode 100644 index 0000000..732c8e9 --- /dev/null +++ b/src/lib/ramstage.ld @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file is included inside a SECTIONS block */ + +/* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ +.text : { + _program = .; + _ramstage = .; + _text = .; + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; +} : to_load + +#ifdef CONFIG_COVERAGE +.ctors : { + . = ALIGN(0x100); + __CTOR_LIST__ = .; + KEEP(*(.ctors)); + LONG(0); + LONG(0); + __CTOR_END__ = .; +} +#endif + +/* TODO: align data sections to cache lines? (is that really useful?) */ +.rodata : { + _rodata = .; + . = ALIGN(8); + + /* If any changes are made to the driver start/symbols or the + * section names the equivalent changes need to made to + * rmodule.ld. */ + console_drivers = .; + KEEP(*(.rodata.console_drivers)); + econsole_drivers = . ; + . = ALIGN(8); + pci_drivers = . ; + KEEP(*(.rodata.pci_driver)); + epci_drivers = . ; + cpu_drivers = . ; + KEEP(*(.rodata.cpu_driver)); + ecpu_drivers = . ; + _bs_init_begin = .; + KEEP(*(.bs_init)); + _bs_init_end = .; + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; + + *(.rodata) + *(.rodata.*) + /* kevinh/Ispiri - Added an align, because the objcopy tool + * incorrectly converts sections that are not long word aligned. + */ + . = ALIGN(8); + + _erodata = .; +} + +.data : { + /* Move to different cache line to avoid false sharing with .rodata. */ + . = ALIGN(64); /* May not be actual line size, not that important. */ + _data = .; + *(.data) + *(.data.*) + _edata = .; +} + +.bss . : { + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + _ebss = .; +} + +.heap . : { + _heap = .; + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . += CONFIG_HEAP_SIZE ; + . = ALIGN(4); + _eheap = .; + _eramstage = .; + _eprogram = .; +} + +/* Discard the sections we don't need/want */ + +/DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) +} diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f3e7cba..ad2c852 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -48,6 +48,9 @@ SECTIONS _bs_init_begin = .; *(.bs_init) _bs_init_end = .; + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; . = ALIGN(8); diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld new file mode 100644 index 0000000..bbad333 --- /dev/null +++ b/src/lib/romstage.ld @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file is included inside a SECTIONS block */ + +.text . : { + _program = .; + _romstage = .; + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); +} : to_load + +.data . : { + . = ALIGN(8); + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; + *(.rodata); + *(.rodata.*); + *(.data); + *(.data.*); + . = ALIGN(8); +} + +.bss . : { + . = ALIGN(8); + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + _ebss = .; + _eromstage = .; + _eprogram = .; +} + +/* Discard the sections we don't need/want */ +/DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.eh_frame); +} diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 67635f8..f94aaf7 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -143,7 +143,7 @@ void timestamp_init(uint64_t base) #endif } -void timestamp_reinit(void) +static void timestamp_reinit(void) { if (!boot_cpu()) return; @@ -158,5 +158,6 @@ void timestamp_reinit(void) timestamp_do_sync(); } -/* Call timestamp_reinit at CAR migration time. */ -CAR_MIGRATE(timestamp_reinit) +/* Call timestamp_reinit CBMEM init hooks. */ +ROMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index ac5afab..98987ff 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -164,7 +164,7 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) static struct chipset_power_state *fill_power_state(void) { diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 6e333c1..5871ad9 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -50,7 +50,7 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) /* Return 0, 3, or 5 to indicate the previous sleep state. */ static int prev_sleep_state(struct chipset_power_state *ps)

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Patch set updated for coreboot: 40f2335 CBMEM: Implement cbmem_run_init_hooks() stub
by Kyösti Mälkki 07 Jan '15

07 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7876 -gerrit commit 40f2335f1d1ee73c34d7ffbb60f6cd698b9d2b24 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 18 18:30:29 2014 +0200 CBMEM: Implement cbmem_run_init_hooks() stub Until we completely can unify early_variables, use this to handle CBMEM update hooks for both romstage and ramstage. Change-Id: I100ebc0e35e1b7091b4f287ca37f539fd7c9fa7a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/tables.c | 8 -------- src/arch/arm64/tables.c | 4 ---- src/arch/riscv/tables.c | 8 -------- src/arch/x86/boot/cbmem.c | 18 ++++++++++++------ src/arch/x86/boot/tables.c | 8 -------- src/include/cbmem.h | 8 +++----- src/lib/cbmem.c | 2 +- src/lib/cbmem_common.c | 9 +++++++++ src/lib/dynamic_cbmem.c | 4 ++-- 9 files changed, 27 insertions(+), 42 deletions(-) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index a2b7b9b..09385b6 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -29,14 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void cbmem_arch_init(void) -{ -} - -void cbmem_fail_resume(void) -{ -} - void write_tables(void) { unsigned long table_pointer, new_table_pointer; diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index ce7ad5a..f71c215 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -29,10 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void cbmem_arch_init(void) -{ -} - struct lb_memory *write_tables(void) { unsigned long table_pointer, new_table_pointer; diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 6300f7b..124a659 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -29,10 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void cbmem_arch_init(void) -{ -} - // WTF. this does not agre with the prototype! static struct lb_memory *wtf_write_tables(void) { @@ -70,7 +66,3 @@ void write_tables(void) { wtf_write_tables(); } - -void cbmem_fail_resume(void) -{ -} diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 8b2b6da..bbf70a2 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -20,6 +20,9 @@ #include <cbmem.h> #include <arch/acpi.h> +/* FIXME: Remove after CBMEM_INIT_HOOKS. */ +#include <cpu/x86/gdt.h> + #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) { @@ -69,16 +72,19 @@ void *cbmem_top(void) #endif /* DYNAMIC_CBMEM */ +void cbmem_run_init_hooks(void) +{ #if !defined(__PRE_RAM__) + move_gdt(); +#endif +} -/* ACPI resume needs to be cleared in the fail-to-recover case, but that - * condition is only handled during ramstage. */ +/* Something went wrong, our high memory area got wiped */ void cbmem_fail_resume(void) { -#if CONFIG_HAVE_ACPI_RESUME - /* Something went wrong, our high memory area got wiped */ +#if !defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + /* ACPI resume needs to be cleared in the fail-to-recover case, but that + * condition is only handled during ramstage. */ acpi_fail_wakeup(); #endif } - -#endif /* !__PRE_RAM__ */ diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 8685ed4..c2265ea 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <cpu/cpu.h> -#include <cpu/x86/gdt.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <arch/pirq_routing.h> @@ -31,13 +30,6 @@ #include <cbmem.h> #include <smbios.h> - -void cbmem_arch_init(void) -{ - /* defined in gdt.c */ - move_gdt(); -} - void write_tables(void) { unsigned long low_table_start, low_table_end; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7de6e56..88d2bfe 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -213,17 +213,15 @@ void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); +void cbmem_run_init_hooks(void); +void cbmem_fail_resume(void); + #ifndef __PRE_RAM__ /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); void cbmem_list(void); -void cbmem_arch_init(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); -void cbmem_fail_resume(void); -#else -static inline void cbmem_arch_init(void) {} -static inline void cbmem_fail_resume(void) {} #endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 0b24ad2..5f834b7 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -243,7 +243,7 @@ int cbmem_recovery(int is_wakeup) cbmem_fail_resume(); } - cbmem_arch_init(); + cbmem_run_init_hooks(); car_migrate_variables(); return !found; } diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index a800173..b430015 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -47,3 +47,12 @@ void cbmem_print_entry(int n, u32 id, u64 base, u64 size) } #endif /* !__PRE_RAM__ */ + +/* FIXME: Replace with CBMEM_INIT_HOOKS API. */ +void __attribute__((weak)) cbmem_run_init_hooks(void) +{ +} + +void __attribute__((weak)) cbmem_fail_resume(void) +{ +} diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 5eddbca..ce4e625 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -171,7 +171,7 @@ void cbmem_initialize_empty(void) printk(BIOS_DEBUG, "CBMEM: root @ %p %d entries.\n", root, root->max_entries); - cbmem_arch_init(); + cbmem_run_init_hooks(); /* Migrate cache-as-ram variables. */ car_migrate_variables(); @@ -249,7 +249,7 @@ int cbmem_initialize(void) root->locked = 1; #endif - cbmem_arch_init(); + cbmem_run_init_hooks(); /* Migrate cache-as-ram variables. */ car_migrate_variables();

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Patch set updated for coreboot: f9b63f7 CBMEM: Move cbmemc_reinit()
by Kyösti Mälkki 07 Jan '15

07 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7859 -gerrit commit f9b63f7cb055b99e7e7f9ee03bb1566a11a63ad5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 19:29:02 2014 +0200 CBMEM: Move cbmemc_reinit() This replaces need for separate cbmemc_reinit() calls made via CAR_MIGRATE() and in ramstage. Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 4 ++++ src/lib/cbmem.c | 2 -- src/lib/cbmem_common.c | 5 +++++ src/lib/dynamic_cbmem.c | 2 -- src/mainboard/google/nyan/romstage.c | 5 ----- src/mainboard/google/nyan_big/romstage.c | 5 ----- src/mainboard/google/nyan_blaze/romstage.c | 5 ----- src/mainboard/via/epia-m850/romstage.c | 1 - src/soc/intel/fsp_baytrail/romstage/romstage.c | 1 - 9 files changed, 9 insertions(+), 21 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index bbf70a2..b53745b 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -22,6 +22,7 @@ /* FIXME: Remove after CBMEM_INIT_HOOKS. */ #include <cpu/x86/gdt.h> +#include <console/cbmem_console.h> #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) @@ -75,6 +76,9 @@ void *cbmem_top(void) void cbmem_run_init_hooks(void) { #if !defined(__PRE_RAM__) + /* Relocate CBMEM console. */ + cbmemc_reinit(); + move_gdt(); #endif } diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 5f834b7..ba6560c 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -23,7 +23,6 @@ #include <bootstate.h> #include <cbmem.h> #include <console/console.h> -#include <console/cbmem_console.h> #include <arch/early_variables.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) #include <arch/acpi.h> @@ -256,7 +255,6 @@ static void init_cbmem_post_device(void *unused) #else cbmem_recovery(0); #endif - cbmemc_reinit(); } BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index b430015..0389c9d 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -20,6 +20,9 @@ #include <cbmem.h> #include <stdlib.h> +/* FIXME: Remove after CBMEM_INIT_HOOKS. */ +#include <console/cbmem_console.h> + #ifndef __PRE_RAM__ static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; @@ -51,6 +54,8 @@ void cbmem_print_entry(int n, u32 id, u64 base, u64 size) /* FIXME: Replace with CBMEM_INIT_HOOKS API. */ void __attribute__((weak)) cbmem_run_init_hooks(void) { + /* Relocate CBMEM console. */ + cbmemc_reinit(); } void __attribute__((weak)) cbmem_fail_resume(void) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index ce4e625..a5f2fc2 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -21,7 +21,6 @@ #include <bootmem.h> #include <console/console.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> @@ -426,7 +425,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) static void init_cbmem_pre_device(void *unused) { cbmem_initialize(); - cbmemc_reinit(); } BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index b6e3635..8912d13 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -31,7 +31,6 @@ #include <cpu/x86/bist.h> #include <string.h> #include <timestamp.h> -#include <console/cbmem_console.h> #include <northbridge/via/vx900/early_vx900.h> #include <northbridge/via/vx900/raminit.h> diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index ad42e73..b0b8133 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -43,7 +43,6 @@ #include <version.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> -#include <console/cbmem_console.h> /* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ uint32_t chipset_prev_sleep_state(uint32_t clear)

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