coreboot-gerrit January 2015

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New patch to review for coreboot: d723035 northbridg/via/vx900: Doxygen fixes
by Martin Roth 07 Jan '15

07 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8154 -gerrit commit d7230356eb8f5f33e11ada8963a4e2f52e106bd5 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jan 6 10:20:42 2015 -0700 northbridg/via/vx900: Doxygen fixes - @todo has to be lowercase for doxygen - Fix some parameters that had changed in the code. - The @file entries needed to be more specific. Change-Id: Icdce08735f581609cd25cce41e986c71435368a4 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/northbridge/via/vx900/chrome9hd.c | 2 +- src/northbridge/via/vx900/early_smbus.c | 3 ++- src/northbridge/via/vx900/lpc.c | 2 +- src/northbridge/via/vx900/northbridge.c | 2 +- src/northbridge/via/vx900/pcie.c | 2 +- src/northbridge/via/vx900/sata.c | 2 +- src/northbridge/via/vx900/traf_ctrl.c | 2 +- 7 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index b9fed6f..326fda1 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -53,7 +53,7 @@ * the IGP is able to use it. GRUB2 and linux are capable of getting a usable * text console, which uses the monitor's native resolution (even 1920x1080). * The graphical console (linux) does not work properly. - * @TODO + * @todo * 1. Figure out what sequence we need to do to get the VGA BIOS running * properly. Use the code provided by VIA and compare their sequence to ours, * fill in any missing steps, etc. diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c index f006ce4..0398562 100644 --- a/src/northbridge/via/vx900/early_smbus.c +++ b/src/northbridge/via/vx900/early_smbus.c @@ -48,7 +48,8 @@ static void smbus_delays(int delays) /** * Read a byte from the SMBus. * - * @param dimm The address location of the DIMM on the SMBus. + * @param smbus_dev The PCI address of the SMBus device . + * @param addr The address location of the DIMM on the SMBus. * @param offset The offset the data is located at. */ u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index ac5e4c8..76280d8 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -30,7 +30,7 @@ #include "chip.h" /** - * @file lpc.c + * @file vx900/lpc.c * * STATUS: * We do a fair bit of setup, and most of it seems to work fairly well. There diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index f9c225d..daff180 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -36,7 +36,7 @@ static uint64_t uma_memory_base = 0; static uint64_t uma_memory_size = 0; /** - * @file northbridge.c + * @file vx900/northbridge.c * * STATUS: Pretty good * One thing that needs to be thoroughly tested is the remap above 4G logic. diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c index 109e5c9..96664e0 100644 --- a/src/northbridge/via/vx900/pcie.c +++ b/src/northbridge/via/vx900/pcie.c @@ -26,7 +26,7 @@ #include "vx900.h" /** - * @file pcie.c + * @file vx900/pcie.c * * STATUS: * We do part of the sequence to initialize the PCIE link. The problem is that diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c index 63295e5..4b831be 100644 --- a/src/northbridge/via/vx900/sata.c +++ b/src/northbridge/via/vx900/sata.c @@ -24,7 +24,7 @@ #include "vx900.h" /** - * @file sata.c + * @file vx900/sata.c * * STATUS: Pretty good * The only issue is the SATA EPHY configuration. We do not know if it is board diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index 2e73ea4..5183391 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -28,7 +28,7 @@ #include "chip.h" /** - * @file traf_ctrl.c + * @file vx900/traf_ctrl.c * * STATUS: * The same issues with the IOAPIC pointe in lpc.c also apply here.

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New patch to review for coreboot: a248203 northbridge/amd: Doxygen fixes
by Martin Roth 07 Jan '15

07 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8153 -gerrit commit a248203e99c22201c47c4defa868361de26de025 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jan 6 10:27:39 2015 -0700 northbridge/amd: Doxygen fixes - Add missing parameter names in several files - remove parameter types in several files - remove lines from doxygen documentation. These should be outside the doxygen comments. - Some of the comments shouldn't have been doxygen style. Turn these into regular non-doxygen comments. Change-Id: Ieccfe237385efee007b48308d58eb0a6a12f5bfa Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/northbridge/amd/amdfam10/misc_control.c | 2 +- src/northbridge/amd/amdht/h3finit.c | 44 +-- src/northbridge/amd/amdht/h3ncmn.c | 420 ++++++++++++------------- src/northbridge/amd/amdk8/get_sblk_pci1234.c | 2 +- src/northbridge/amd/amdk8/misc_control.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c | 30 +- src/northbridge/amd/cimx/rd890/NbPlatform.h | 6 +- src/northbridge/intel/i82810/raminit.c | 2 +- src/northbridge/intel/i945/raminit.c | 1 + 9 files changed, 247 insertions(+), 262 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 244dc3c..7c50074 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -39,7 +39,7 @@ /** * @brief Read resources for AGP aperture * - * @param + * @param dev * * There is only one AGP aperture resource needed. The resoruce is added to * the northbridge of BSP. diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 764d298..ff57033 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -119,8 +119,8 @@ * Returns the number of nodes in the compressed graph * * Parameters: - * @param[in] u8 graph = a compressed graph - * @param[out] u8 results = the number of nodes in the graph + * @param[in] graph = a compressed graph + * @param[out] results = the number of nodes in the graph * --------------------------------------------------------------------------------------- */ static u8 graphHowManyNodes(u8 *graph) @@ -138,10 +138,10 @@ static u8 graphHowManyNodes(u8 *graph) * Relies on rule that directly connected nodes always route requests directly. * * Parameters: - * @param[in] u8 graph = the graph to examine - * @param[in] u8 nodeA = the node number of the first node - * @param[in] u8 nodeB = the node number of the second node - * @param[out] BOOL results = true if nodeA connects to nodeB false if not + * @param[in] graph = the graph to examine + * @param[in] nodeA = the node number of the first node + * @param[in] nodeB = the node number of the second node + * @param[out] results = true if nodeA connects to nodeB false if not * --------------------------------------------------------------------------------------- */ static BOOL graphIsAdjacent(u8 *graph, u8 nodeA, u8 nodeB) @@ -190,10 +190,10 @@ static u8 graphGetRsp(u8 *graph, u8 nodeA, u8 nodeB) * it is the responsibility of the caller to apply any permutation needed. * * Parameters: - * @param[in] u8 graph = the graph to examine - * @param[in] u8 nodeA = the node number of the first node - * @param[in] u8 nodeB = the node number of the second node - * @param[out] u8 results = The request route node + * @param[in] graph = the graph to examine + * @param[in] nodeA = the node number of the first node + * @param[in] nodeB = the node number of the second node + * @param[out] results = The request route node * --------------------------------------------------------------------------------------- */ static u8 graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) @@ -213,10 +213,10 @@ static u8 graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) * nodeB towards * * Parameters: - * @param[in] u8 graph = the graph to examine - * @param[in] u8 nodeA = the node number of the first node - * @param[in] u8 nodeB = the node number of the second node - * OU u8 results = the broadcast routes for nodeA from nodeB + * @param[in] graph = the graph to examine + * @param[in] nodeA = the node number of the first node + * @param[in] nodeB = the node number of the second node + * OU results = the broadcast routes for nodeA from nodeB * --------------------------------------------------------------------------------------- */ static u8 graphGetBc(u8 *graph, u8 nodeA, u8 nodeB) @@ -273,19 +273,21 @@ static void routeFromBSP(u8 targetNode, u8 actualTarget, sMainData *pDat) pDat->nb->writeRoutingTable(predecessorNode, actualTarget, predecessorLink, pDat->nb); } -/*---------------------------------------------------------------------------------------- - * u8 +/*---------------------------------------------------------------------------*/ + +/** + * u8 * convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) * * Description: * Return the link on source node which connects to target node * * Parameters: - * @param[in] u8 srcNode = the source node - * @param[in] u8 targetNode = the target node to find the link to - * @param[in] sMainData* pDat = our global state - * @param[out] u8 results = the link on source which connects to target - * --------------------------------------------------------------------------------------- + * @param[in] srcNode = the source node + * @param[in] targetNode = the target node to find the link to + * @param[in] pDat = our global state + * @return the link on source which connects to target + * */ static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) { diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index e83f872..da7e6ae 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -89,7 +89,7 @@ *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** ***************************************************************************/ -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * SBDFO * makeLinkBase(u8 currentNode, u8 currentLink) @@ -99,12 +99,10 @@ * PCI config address for a link. * * Parameters: - * @param[in] u8 node = the node this link is on - * @param[in] u8 link = the link - * @param[out] SBDFO result = the pci config address + * @param[in] node = the node this link is on + * @param[in] link = the link * - * --------------------------------------------------------------------------------------- - */ + *****************************************************************************/ static SBDFO makeLinkBase(u8 node, u8 link) { SBDFO linkBase; @@ -125,7 +123,7 @@ static SBDFO makeLinkBase(u8 node, u8 link) return linkBase; } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * void * setHtControlRegisterBits(SBDFO reg, u8 hiBit, u8 loBit, u32 *pValue) @@ -137,13 +135,12 @@ static SBDFO makeLinkBase(u8 node, u8 link) * NOTE: This routine is called for IO Devices as well as CPUs! * * Parameters: - * @param[in] SBDFO reg = the PCI config address the control register - * @param[in] u8 hiBit = the high bit number - * @param[in] u8 loBit = the low bit number - * @param[in] u8 pValue = the value to write to that bit range. Bit 0 => loBit. + * @param[in] reg = the PCI config address the control register + * @param[in] hiBit = the high bit number + * @param[in] loBit = the low bit number + * @param[in] pValue = the value to write to that bit range. Bit 0 => loBit. * - * --------------------------------------------------------------------------------------- - */ + *****************************************************************************/ static void setHtControlRegisterBits(SBDFO reg, u8 hiBit, u8 loBit, u32 *pValue) { u32 temp, mask; @@ -164,7 +161,7 @@ static void setHtControlRegisterBits(SBDFO reg, u8 hiBit, u8 loBit, u32 *pValue) AmdPCIWrite(reg, &temp); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * writeRoutingTable(u8 node, u8 target, u8 Link, cNorthBridge *nb) @@ -180,13 +177,12 @@ static void setHtControlRegisterBits(SBDFO reg, u8 hiBit, u8 loBit, u32 *pValue) * response paths. * * Parameters: - * @param[in] u8 node = the node that will have it's routing tables modified. - * @param[in] u8 target = For routing to node target - * @param[in] u8 Link = Link from node to target - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] node = the node that will have it's routing tables modified. + * @param[in] target = For routing to node target + * @param[in] link = Link from node to target + * @param[in] *nb = this northbridge * - * --------------------------------------------------------------------------------------- - */ + *****************************************************************************/ static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb) { @@ -204,7 +200,7 @@ static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb) #endif } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) @@ -213,12 +209,11 @@ static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb) * Modifies the NodeID register on the target node * * Parameters: - * @param[in] u8 node = the node that will have its NodeID altered. - * @param[in] u8 nodeID = the new value for NodeID - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] node = the node that will have its NodeID altered. + * @param[in] nodeID = the new value for NodeID + * @param[in] *nb = this northbridge * - * --------------------------------------------------------------------------------------- - */ + *****************************************************************************/ static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) { @@ -232,7 +227,7 @@ static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) 2, 0, &temp); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * readDefLnk(u8 node, cNorthBridge *nb) @@ -242,15 +237,14 @@ static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) * from node * * Parameters: - * @param[in] u8 node = the node that will have its NodeID altered. - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 result = The HyperTransport link where the request to + * @param[in] node = the node that will have its NodeID altered. + * @param[in] *nb = this northbridge + * @return The HyperTransport link where the request to * read the default link came from. Since this * code is running on the BSP, this should be the link * pointing back towards the BSP. * - * --------------------------------------------------------------------------------------- - */ + *****************************************************************************/ static u8 readDefLnk(u8 node, cNorthBridge *nb) { @@ -271,7 +265,7 @@ static u8 readDefLnk(u8 node, cNorthBridge *nb) return (u8)deflink; } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * enableRoutingTables(u8 node, cNorthBridge *nb) @@ -280,11 +274,10 @@ static u8 readDefLnk(u8 node, cNorthBridge *nb) * Turns routing tables on for a given node * * Parameters: - * @param[in] u8 node = the node that will have it's routing tables enabled - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] node = the node that will have it's routing tables enabled + * @param[in] *nb = this northbridge * - * --------------------------------------------------------------------------------------- - */ + *****************************************************************************/ static void enableRoutingTables(u8 node, cNorthBridge *nb) { @@ -299,7 +292,7 @@ static void enableRoutingTables(u8 node, cNorthBridge *nb) } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static BOOL * verifyLinkIsCoherent(u8 node, u8 Link, cNorthBridge *nbk) @@ -308,10 +301,10 @@ static void enableRoutingTables(u8 node, cNorthBridge *nb) * Verify that the link is coherent, connected, and ready * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] u8 link = the link on that Node to examine - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 result = true - The link has the following status + * @param[in] node = the node that will be examined + * @param[in] link = the link on that Node to examine + * @param[in] *nb = this northbridge + * @return true - The link has the following status * linkCon=1, Link is connected * InitComplete=1, Link initialization is complete * NC=0, Link is coherent @@ -319,8 +312,7 @@ static void enableRoutingTables(u8 node, cNorthBridge *nb) * LinkConPend=0 Link connection is not pending * false- The link has some other status * - * --------------------------------------------------------------------------------------- - */ + *****************************************************************************/ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) { @@ -343,7 +335,7 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) #endif /* HT_BUILD_NC_ONLY */ } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static bool * readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb) @@ -362,15 +354,15 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) * 10 1 0 3 No 1 * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] u8 link = the link on that node to examine - * @param[in] u8 sMainData = access to call back routine - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 result = true - the link is not connected or has hard error - * false- if the link is connected + * @param[in] node = the node that will be examined + * @param[in] link = the link on that node to examine + * @param[in] *pDat = access to call back routine + * @param[in] *nb = this northbridge + * @return true - the link is not connected or has hard error + * false- if the link is connected * - * --------------------------------------------------------------------------------------- - */ + *****************************************************************************/ + static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb) { u32 before, after, unconnected, crc; @@ -434,7 +426,7 @@ static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBrid } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static u8 * readToken(u8 node, cNorthBridge *nb) @@ -446,12 +438,11 @@ static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBrid * using it will have no ill-effects during HyperTransport initialization. * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 result = the Token read from the node + * @param[in] node = the node that will be examined + * @param[in] *nb = this northbridge + * @return the Token read from the node * - * --------------------------------------------------------------------------------------- - */ + *****************************************************************************/ static u8 readToken(u8 node, cNorthBridge *nb) { u32 temp; @@ -470,7 +461,7 @@ static u8 readToken(u8 node, cNorthBridge *nb) } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * writeToken(u8 node, u8 Value, cNorthBridge *nb) @@ -483,11 +474,11 @@ static u8 readToken(u8 node, cNorthBridge *nb) * Limiting use to 4 bits makes code GH to rev F compatible. * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] node = the node that will be examined + * @param value + * @param[in] *nb = this northbridge * - * --------------------------------------------------------------------------------------- - */ + *****************************************************************************/ static void writeToken(u8 node, u8 value, cNorthBridge *nb) { u32 temp = value; @@ -502,7 +493,7 @@ static void writeToken(u8 node, u8 value, cNorthBridge *nb) 19, 16, &temp); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static u8 * fam0FGetNumCoresOnNode(u8 node, cNorthBridge *nb) @@ -511,9 +502,9 @@ static void writeToken(u8 node, u8 value, cNorthBridge *nb) * Return the number of cores (1 based count) on node. * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 result = the number of cores + * @param[in] node = the node that will be examined + * @param[in] *nb = this northbridge + * @return = the number of cores * * --------------------------------------------------------------------------------------- */ @@ -534,7 +525,7 @@ static u8 fam0FGetNumCoresOnNode(u8 node, cNorthBridge *nb) return (u8)(temp+1); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static u8 * fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) @@ -543,11 +534,11 @@ static u8 fam0FGetNumCoresOnNode(u8 node, cNorthBridge *nb) * Return the number of cores (1 based count) on node. * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 result = the number of cores + * @param[in] node = the node that will be examined + * @param[in] *nb = this northbridge + * @return = the number of cores + * * - * --------------------------------------------------------------------------------------- */ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) { @@ -583,7 +574,7 @@ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) return (u8)(temp+1); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * setTotalNodesAndCores(u8 node, u8 totalNodes, u8 totalCores, cNorthBridge *nb) @@ -592,10 +583,10 @@ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) * Write the total number of cores and nodes to the node * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] u8 totalNodes = the total number of nodes - * @param[in] u8 totalCores = the total number of cores - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] node = the node that will be examined + * @param[in] totalNodes = the total number of nodes + * @param[in] totalCores = the total number of cores + * @param[in] *nb = this northbridge * * --------------------------------------------------------------------------------------- */ @@ -621,7 +612,7 @@ static void setTotalNodesAndCores(u8 node, u8 totalNodes, u8 totalCores, cNorthB AmdPCIWriteBits(nodeIDReg, 6, 4, &temp); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * limitNodes(u8 node, cNorthBridge *nb) @@ -630,8 +621,8 @@ static void setTotalNodesAndCores(u8 node, u8 totalNodes, u8 totalCores, cNorthB * Limit coherent config accesses to cpus as indicated by nodecnt. * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] node = the node that will be examined + * @param[in] *nb = this northbridge * * --------------------------------------------------------------------------------------- */ @@ -647,7 +638,7 @@ static void limitNodes(u8 node, cNorthBridge *nb) 15, 15, &temp); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * writeFullRoutingTable(u8 node, u8 target, u8 reqLink, u8 rspLink, u32 BClinks, cNorthBridge *nb) @@ -657,12 +648,12 @@ static void limitNodes(u8 node, cNorthBridge *nb) * link, and broadcast links provided. * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] u8 target = the target node for these routes - * @param[in] u8 reqLink = the link for requests to target - * @param[in] u8 rspLink = the link for responses to target - * @param[in] u32 bClinks = the broadcast links - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] node = the node that will be examined + * @param[in] target = the target node for these routes + * @param[in] reqLink = the link for requests to target + * @param[in] rspLink = the link for responses to target + * @param[in] bClinks = the broadcast links + * @param[in] *nb = this northbridge * * --------------------------------------------------------------------------------------- */ @@ -696,7 +687,7 @@ static void writeFullRoutingTable(u8 node, u8 target, u8 reqLink, u8 rspLink, u3 #endif /* HT_BUILD_NC_ONLY */ } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static u32 * makeKey(u8 currentNode) @@ -708,8 +699,8 @@ static void writeFullRoutingTable(u8 node, u8 target, u8 reqLink, u8 rspLink, u3 * same as the BSP's. * * Parameters: - * @param[in] u8 node = the node - * @param[out] u32 result = the key value + * @param[in] node = the node + * @return = the key value * * --------------------------------------------------------------------------------------- */ @@ -732,7 +723,7 @@ static u32 makeKey(u8 node) } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static BOOL * isCompatible(u8 currentNode, cNorthBridge *nb) @@ -743,9 +734,9 @@ static u32 makeKey(u8 node) * same as the BSP's. * * Parameters: - * @param[in] u8 node = the node - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] BOOL result = true: the new is compatible, false: it is not + * @param[in] node = the node + * @param[in] *nb = this northbridge + * @return = true: the new is compatible, false: it is not * * --------------------------------------------------------------------------------------- */ @@ -754,7 +745,7 @@ static BOOL isCompatible(u8 node, cNorthBridge *nb) return (makeKey(node) == nb->compatibleKey); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static BOOL * fam0fIsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) @@ -764,10 +755,10 @@ static BOOL isCompatible(u8 node, cNorthBridge *nb) * Return whether the current configuration exceeds the capability. * * Parameters: - * @param[in] u8 node = the node - * @param[in,out] sMainData *pDat = sysMpCap (updated) and NodesDiscovered - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] BOOL result = true: system is capable of current config. + * @param[in] node = the node + * @param[in,out] *pDat = sysMpCap (updated) and NodesDiscovered + * @param[in] *nb = this northbridge + * @return true: system is capable of current config. * false: system is not capable of current config. * * --------------------------------------------------------------------------------------- @@ -808,7 +799,7 @@ static BOOL fam0fIsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) #endif } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static BOOL * fam10IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) @@ -818,10 +809,10 @@ static BOOL fam0fIsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) * Return whether the current configuration exceeds the capability. * * Parameters: - * @param[in] u8 node = the node - * @param[in,out] sMainData *pDat = sysMpCap (updated) and NodesDiscovered - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] BOOL result = true: system is capable of current config. + * @param[in] node = the node + * @param[in,out] *pDat = sysMpCap (updated) and NodesDiscovered + * @param[in] *nb = this northbridge + * @return true: system is capable of current config. * false: system is not capable of current config. * * --------------------------------------------------------------------------------------- @@ -861,7 +852,7 @@ static BOOL fam10IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) #endif } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * fam0fStopLink(u8 currentNode, u8 currentLink, cNorthBridge *nb) @@ -870,9 +861,9 @@ static BOOL fam10IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) * Disable a cHT link on node by setting F0x[E4, C4, A4, 84][TransOff, EndOfChain]=1 * * Parameters: - * @param[in] u8 node = the node this link is on - * @param[in] u8 link = the link to stop - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] node = the node this link is on + * @param[in] link = the link to stop + * @param[in] *nb = this northbridge * * --------------------------------------------------------------------------------------- */ @@ -892,7 +883,7 @@ static void fam0fStopLink(u8 node, u8 link, cNorthBridge *nb) #endif } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * commonVoid() @@ -909,7 +900,7 @@ static void commonVoid(void) { } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static BOOL * commonReturnFalse() @@ -918,8 +909,8 @@ static void commonVoid(void) * Return False. * * Parameters: - * @param[out] BOOL result = false - * --------------------------------------------------------------------------------------- + * @return = false + * */ static BOOL commonReturnFalse(void) { @@ -931,7 +922,7 @@ static BOOL commonReturnFalse(void) *** Northbridge access routines *** ***************************************************************************/ -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static u8 * readSbLink(cNorthBridge *nb) @@ -940,8 +931,8 @@ static BOOL commonReturnFalse(void) * Return the link to the Southbridge * * Parameters: - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 results = the link to the southbridge + * @param[in] *nb = this northbridge + * @return the link to the southbridge * * --------------------------------------------------------------------------------------- */ @@ -957,7 +948,7 @@ static u8 readSbLink(cNorthBridge *nb) return (u8)temp; } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static BOOL * verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) @@ -966,10 +957,10 @@ static u8 readSbLink(cNorthBridge *nb) * Verify that the link is non-coherent, connected, and ready * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] u8 link = the Link on that node to examine - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 results = true - The link has the following status + * @param[in] node = the node that will be examined + * @param[in] link = the Link on that node to examine + * @param[in] *nb = this northbridge + * @return = true - The link has the following status * LinkCon=1, Link is connected * InitComplete=1,Link initilization is complete * NC=1, Link is coherent @@ -995,7 +986,7 @@ static BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_NONCOHERENT; } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) @@ -1004,13 +995,13 @@ static BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) * Configure and enable config access to a non-coherent chain for the given bus range. * * Parameters: - * @param[in] u8 cfgRouteIndex = the map entry to set - * @param[in] u8 secBus = The secondary bus number to use - * @param[in] u8 subBus = The subordinate bus number to use - * @param[in] u8 targetNode = The node that shall be the recipient of the traffic - * @param[in] u8 targetLink = The link that shall be the recipient of the traffic - * @param[in] sMainData* pDat = our global state - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] cfgMapIndex = the map entry to set + * @param[in] secBus = The secondary bus number to use + * @param[in] subBus = The subordinate bus number to use + * @param[in] targetNode = The node that shall be the recipient of the traffic + * @param[in] targetLink = The link that shall be the recipient of the traffic + * @param[in] pDat = our global state + * @param[in] *nb = this northbridge * * --------------------------------------------------------------------------------------- */ @@ -1041,7 +1032,7 @@ static void ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNod &temp); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) @@ -1050,16 +1041,15 @@ static void ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNod * Configure and enable config access to a non-coherent chain for the given bus range. * * Parameters: - * @param[in] u8 cfgMapIndex = the map entry to set - * @param[in] u8 secBus = The secondary bus number to use - * @param[in] u8 subBus = The subordinate bus number to use - * @param[in] u8 targetNode = The node that shall be the recipient of the traffic - * @param[in] u8 targetLink = The link that shall be the recipient of the traffic - * @param[in] sMainData* pDat = our global state - * @param[in] cNorthBridge *nb = this northbridge - * - * --------------------------------------------------------------------------------------- - */ + * @param[in] cfgMapIndex = the map entry to set + * @param[in] secBus = The secondary bus number to use + * @param[in] subBus = The subordinate bus number to use + * @param[in] targetNode = The node that shall be the recipient of the traffic + * @param[in] targetLink = The link that shall be the recipient of the traffic + * @param[in] pDat = our global state + * @param[in] *nb = this northbridge + * + ******************************************************************************/ static void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) { u8 curNode; @@ -1094,8 +1084,7 @@ static void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode *** Link Optimization *** ***************************************************************************/ -/**---------------------------------------------------------------------------------------- - * +/** * static u8 * convertBitsToWidth(u8 value, cNorthBridge *nb) * @@ -1103,12 +1092,11 @@ static void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode * Given the bits set in the register field, return the width it represents * * Parameters: - * @param[in] u8 value = The bits for the register - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 results = The width + * @param[in] value = The bits for the register + * @param[in] *nb = this northbridge + * @return The width * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ static u8 convertBitsToWidth(u8 value, cNorthBridge *nb) { switch(value) { @@ -1121,7 +1109,7 @@ static u8 convertBitsToWidth(u8 value, cNorthBridge *nb) return 0; // shut up GCC. } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static u8 * convertWidthToBits(u8 value, cNorthBridge *nb) @@ -1130,12 +1118,11 @@ static u8 convertBitsToWidth(u8 value, cNorthBridge *nb) * Translate a desired width setting to the bits to set in the register field * * Parameters: - * @param[in] u8 value = The width - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 results = The bits for the register + * @param[in] value = The width + * @param[in] *nb = this northbridge + * @return The bits for the register * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ static u8 convertWidthToBits(u8 value, cNorthBridge *nb) { switch (value) { @@ -1148,7 +1135,7 @@ static u8 convertWidthToBits(u8 value, cNorthBridge *nb) return 0; // shut up GCC } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static u16 * ht1NorthBridgeFreqMask(u8 NodeID, cNorthBridge *nb) @@ -1158,19 +1145,18 @@ static u8 convertWidthToBits(u8 value, cNorthBridge *nb) * northbridge frequency. * * Parameters: - * @param[in] u8 node = Result could (later) be for a specific node - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u16 results = Frequency mask + * @param[in] node = Result could (later) be for a specific node + * @param[in] *nb = this northbridge + * @return Frequency mask * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) { /* only up to HT1 speeds */ return (HT_FREQUENCY_LIMIT_HT1_ONLY); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static u16 * fam10NorthBridgeFreqMask(u8 NodeID, cNorthBridge *nb) @@ -1180,12 +1166,11 @@ static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) * northbridge frequency. * * Parameters: - * @param[in] u8 node = Result could (later) be for a specific node - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u16 results = Frequency mask + * @param[in] node = Result could (later) be for a specific node + * @param[in] *nb = this northbridge + * @return = Frequency mask * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ static u16 fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) { u8 nbCOF; @@ -1225,7 +1210,7 @@ static u16 fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) return (fixEarlySampleFreqCapability(supported)); } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * gatherLinkData(sMainData *pDat, cNorthBridge *nb) @@ -1235,11 +1220,10 @@ static u16 fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) * capabilities. * * Parameters: - * @param[in,out] sMainData* pDat = our global state, port list - * @param[in] cNorthBridge *nb = this northbridge + * @param[in,out] pDat = our global state, port list + * @param[in] *nb = this northbridge * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) { u8 i; @@ -1301,7 +1285,7 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) } } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * setLinkData(sMainData *pDat, cNorthBridge *nb) @@ -1311,11 +1295,10 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) * port list data structure. * * Parameters: - * @param[in] sMainData* pDat = our global state, port list - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] pDat = our global state, port list + * @param[in] *nb = this northbridge * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ static void setLinkData(sMainData *pDat, cNorthBridge *nb) { u8 i; @@ -1534,7 +1517,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) } } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * void * fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8 rsp, u8 prb) @@ -1545,15 +1528,14 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) * family 10h and family 0fh northbridges. * * Parameters: - * @param[in] u8 node = The node to set allocations on - * @param[in] u8 link = the link to set allocations on - * @param[in] u8 req = non-posted Request Command Buffers - * @param[in] u8 preq = Posted Request Command Buffers - * @param[in] u8 rsp = Response Command Buffers - * @param[in] u8 prb = Probe Command Buffers - * - * --------------------------------------------------------------------------------------- - */ + * @param[in] node = The node to set allocations on + * @param[in] link = the link to set allocations on + * @param[in] req = non-posted Request Command Buffers + * @param[in] preq = Posted Request Command Buffers + * @param[in] rsp = Response Command Buffers + * @param[in] prb = Probe Command Buffers + * + ******************************************************************************/ #ifndef HT_BUILD_NC_ONLY static void fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8 rsp, u8 prb) @@ -1579,7 +1561,7 @@ static void fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8 } #endif /* HT_BUILD_NC_ONLY */ -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * void * fam0fWriteHTLinkDatBufferAlloc(u8 node, u8 link, u8 reqD, u8 preqD, u8 rspD) @@ -1590,14 +1572,13 @@ static void fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8 * family 10h and family 0fh northbridges. * * Parameters: - * @param[in] u8 node = The node to set allocations on - * @param[in] u8 link = the link to set allocations on - * @param[in] u8 reqD = non-posted Request Data Buffers - * @param[in] u8 preqD = Posted Request Data Buffers - * @param[in] u8 rspD = Response Data Buffers + * @param[in] node = The node to set allocations on + * @param[in] link = the link to set allocations on + * @param[in] reqD = non-posted Request Data Buffers + * @param[in] preqD = Posted Request Data Buffers + * @param[in] rspD = Response Data Buffers * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ #ifndef HT_BUILD_NC_ONLY static void fam0fWriteHTLinkDatBufferAlloc(u8 node, u8 link, u8 reqD, u8 preqD, u8 rspD) @@ -1620,7 +1601,7 @@ static void fam0fWriteHTLinkDatBufferAlloc(u8 node, u8 link, u8 reqD, u8 preqD, } #endif /* HT_BUILD_NC_ONLY */ -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) @@ -1629,12 +1610,11 @@ static void fam0fWriteHTLinkDatBufferAlloc(u8 node, u8 link, u8 reqD, u8 preqD, * Set the traffic distribution register for the links provided. * * Parameters: - * @param[in] u32 links01 = coherent links from node 0 to 1 - * @param[in] u32 links10 = coherent links from node 1 to 0 - * @param[in] cNorthBridge* nb = this northbridge + * @param[in] links01 = coherent links from node 0 to 1 + * @param[in] links10 = coherent links from node 1 to 0 + * @param[in] nb = this northbridge * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY @@ -1676,7 +1656,7 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * #endif /* HT_BUILD_NC_ONLY */ } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) @@ -1687,12 +1667,11 @@ static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * * perform the buffer tunings on the links required for this config. * * Parameters: - * @param[in] u32 links01 = coherent links from node 0 to 1 - * @param[in] u32 links01 = coherent links from node 1 to 0 - * @param[in] cNorthBridge* nb = this northbridge + * @param[in] links01 = coherent links from node 0 to 1 + * @param[in] links10 = coherent links from node 1 to 0 + * @param[in] nb = this northbridge * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ static void ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY @@ -1785,7 +1764,7 @@ static void ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * #endif /* HT_BUILD_NC_ONLY */ } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) @@ -1795,12 +1774,11 @@ static void ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * * which require adjustments and apply any standard workarounds to this node. * * Parameters: - * @param[in] u8 node = the node to - * @param[in] sMainData *pDat = coherent links from node 0 to 1 - * @param[in] cNorthBridge* nb = this northbridge + * @param[in] node = the node to + * @param[in] *pDat = coherent links from node 0 to 1 + * @param[in] nb = this northbridge * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY @@ -1982,7 +1960,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) #endif /* HT_BUILD_NC_ONLY */ } -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * static void * fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) @@ -1992,12 +1970,11 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) * which require adjustments and apply any standard workarounds to this node. * * Parameters: - * @param[in] u8 node = the node to tune - * @param[in] sMainData *pDat = global state - * @param[in] cNorthBridge* nb = this northbridge + * @param[in] node = the node to tune + * @param[in] *pDat = global state + * @param[in] nb = this northbridge * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ static void fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) { u32 temp; @@ -2070,7 +2047,7 @@ static void fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) * */ -/**---------------------------------------------------------------------------------------- +/***************************************************************************//** * * void * newNorthBridge(u8 node, cNorthBridge *nb) @@ -2082,11 +2059,10 @@ static void fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) * is provided by nb. * * Parameters: - * @param[in] node u8 = create a northbridge interface for this node. - * @param[out] cNorthBridge* nb = the caller's northbridge structure to initialize. + * @param node + * @param[out] nb = the caller's northbridge structure to initialize. * - * --------------------------------------------------------------------------------------- - */ + ******************************************************************************/ void newNorthBridge(u8 node, cNorthBridge *nb) { u32 match; diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 2db726c..cbbc394 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -69,7 +69,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) #endif -/** +/* * Why we need the pci1234[] array * * It will keep the sequence of HT devices in the HT link registers even when a diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index cab56c2..956692d 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -24,7 +24,7 @@ /** * @brief Read resources for AGP aperture * - * @param + * @param dev * * There is only one AGP aperture resource needed. The resource is added to * the northbridge of BSP. diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c index 42696f6..214313a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c @@ -43,12 +43,14 @@ * * This function set Rtt_Nom for registered DDR3 dimms on targeted dimm. * + * @param *pMCTData * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * dimm - targeted dimm - * wl - current mode, either write levelization mode or normal mode - * MemClkFreq - current frequency + * @param dimm - targeted dimm + * @param wl - current mode, either write levelization mode or normal mode + * @param MemClkFreq - current frequency + * @param rank * - * @return tempW1 - Rtt_Nom + * @return tempW1 - Rtt_Nom */ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) { @@ -154,10 +156,12 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d * * This function set Rtt_Nom for registered DDR3 dimms on non-targeted dimm. * + * @param *pMCTData * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * dimm - non-targeted dimm - * wl - current mode, either write levelization mode or normal mode - * MemClkFreq - current frequency + * @param dimm - non-targeted dimm + * @param wl - current mode, either write levelization mode or normal mode + * @param MemClkFreq - current frequency + * @param rank * * @return tempW1 - Rtt_Nom */ @@ -176,13 +180,16 @@ static u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u * * This function set Rtt_Wr for registered DDR3 dimms. * + * @param pMCTData * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * dimm - targeted dimm - * wl - current mode, either write levelization mode or normal mode - * MemClkFreq - current frequency + * @param dimm - targeted dimm + * @param wl - current mode, either write levelization mode or normal mode + * @param MemClkFreq - current frequency + * @param rank * * @return tempW1 - Rtt_Wr */ + static u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) { u32 tempW1; @@ -238,8 +245,9 @@ static u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BO * * This function set WrLvOdt for registered DDR3 dimms. * + * @param *pMCTData * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * dimm - targeted dimm + * @param dimm - targeted dimm * * @return WrLvOdt */ diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h index 20f7974..5b24224 100644 --- a/src/northbridge/amd/cimx/rd890/NbPlatform.h +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -80,10 +80,8 @@ // CIMX configuration parameters //#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 -/** - * PCIEX_BASE_ADDRESS - Define PCIE base address - * - * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 +/* + * PCIEX_BASE_ADDRESS - Define PCIE base address */ #ifdef MOVE_PCIEBAR_TO_F0000000 #define PCIEX_BASE_ADDRESS 0xF7000000 diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index 904c960..b451803 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -134,7 +134,7 @@ SDRAM configuration functions. /** * Send the specified RAM command to all DIMMs. * - * @param The RAM command to send to the DIMM(s). + * @param command The RAM command to send to the DIMM(s). */ static void do_ram_command(u8 command) { diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e9b6e3f..0a60112 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -3049,6 +3049,7 @@ static void sdram_setup_processor_side(void) /** * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 + * @param spd_addresses pointer to a list of SPD addresses */ void sdram_initialize(int boot_path, const u8 *spd_addresses) {

1 0

Patch set updated for coreboot: b41c7f4 Doxygen: add a "simple" output config and make target
by Martin Roth 07 Jan '15

07 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8068 -gerrit commit b41c7f4290111497b914259d2d30979975997016 Author: Martin Roth <gaumless(a)gmail.com> Date: Mon Dec 29 14:56:19 2014 -0700 Doxygen: add a "simple" output config and make target This is a doxygen target I'm using for cleaning up the coreboot doxygen output. It runs in about a minute instead of.... a lot longer, and only generates documentation for the coreboot/src directory, excluding vendorcode. It was requested that the comments be stripped to make it easier to read. This was done through the following command (split for gerrit): head -n 1 Doxyfile.coreboot_simple > Doxyfile.tmp ; cat Doxyfile.coreboot_simple | sed 's|^\s*#.*$||' | sed '/^$/d' | sed 's|[[:space:]]\+$||' >> Doxyfile.tmp ; mv Doxyfile.tmp Doxyfile.coreboot_simple I'm including the command here because any time the file is updated with the doxygen wizard, it will need to be run again. It might be desirable to turn this into a script in the documentation directory. Change-Id: Ic0cbbcd21aa647e80a037481546bdcd2aab8949e Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile | 5 +- documentation/Doxyfile.coreboot_simple | 259 +++++++++++++++++++++++++++++++++ 2 files changed, 263 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6ef9838..017ca47 100644 --- a/Makefile +++ b/Makefile @@ -263,6 +263,9 @@ doxy: doxygen doxygen: $(DOXYGEN) documentation/Doxyfile.coreboot +doxygen_simple: + $(DOXYGEN) documentation/Doxyfile.coreboot_simple + doxyclean: doxygen-clean doxygen-clean: rm -rf $(DOXYGEN_OUTPUT_DIR) @@ -279,4 +282,4 @@ clean-cscope: distclean: clean rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile -.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean doxygen doxy +.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean doxygen doxy doxygen_simple diff --git a/documentation/Doxyfile.coreboot_simple b/documentation/Doxyfile.coreboot_simple new file mode 100644 index 0000000..2135d96 --- /dev/null +++ b/documentation/Doxyfile.coreboot_simple @@ -0,0 +1,259 @@ +# Doxyfile 1.8.8 +DOXYFILE_ENCODING = UTF-8 +PROJECT_NAME = coreboot +PROJECT_NUMBER = +PROJECT_BRIEF = "coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers." +PROJECT_LOGO = documentation/coreboot_logo.png +OUTPUT_DIRECTORY = doxygen +CREATE_SUBDIRS = YES +ALLOW_UNICODE_NAMES = NO +OUTPUT_LANGUAGE = English +BRIEF_MEMBER_DESC = YES +REPEAT_BRIEF = YES +ABBREVIATE_BRIEF = +ALWAYS_DETAILED_SEC = YES +INLINE_INHERITED_MEMB = NO +FULL_PATH_NAMES = YES +STRIP_FROM_PATH = +STRIP_FROM_INC_PATH = +SHORT_NAMES = NO +JAVADOC_AUTOBRIEF = YES +QT_AUTOBRIEF = NO +MULTILINE_CPP_IS_BRIEF = NO +INHERIT_DOCS = YES +SEPARATE_MEMBER_PAGES = NO +TAB_SIZE = 8 +ALIASES = +TCL_SUBST = +OPTIMIZE_OUTPUT_FOR_C = YES +OPTIMIZE_OUTPUT_JAVA = NO +OPTIMIZE_FOR_FORTRAN = NO +OPTIMIZE_OUTPUT_VHDL = NO +EXTENSION_MAPPING = +MARKDOWN_SUPPORT = YES +AUTOLINK_SUPPORT = YES +BUILTIN_STL_SUPPORT = NO +CPP_CLI_SUPPORT = NO +SIP_SUPPORT = NO +IDL_PROPERTY_SUPPORT = YES +DISTRIBUTE_GROUP_DOC = NO +SUBGROUPING = YES +INLINE_GROUPED_CLASSES = NO +INLINE_SIMPLE_STRUCTS = NO +TYPEDEF_HIDES_STRUCT = NO +LOOKUP_CACHE_SIZE = 0 +EXTRACT_ALL = YES +EXTRACT_PRIVATE = NO +EXTRACT_PACKAGE = NO +EXTRACT_STATIC = YES +EXTRACT_LOCAL_CLASSES = YES +EXTRACT_LOCAL_METHODS = NO +EXTRACT_ANON_NSPACES = NO +HIDE_UNDOC_MEMBERS = NO +HIDE_UNDOC_CLASSES = NO +HIDE_FRIEND_COMPOUNDS = NO +HIDE_IN_BODY_DOCS = NO +INTERNAL_DOCS = NO +CASE_SENSE_NAMES = YES +HIDE_SCOPE_NAMES = NO +SHOW_INCLUDE_FILES = YES +SHOW_GROUPED_MEMB_INC = NO +FORCE_LOCAL_INCLUDES = NO +INLINE_INFO = YES +SORT_MEMBER_DOCS = YES +SORT_BRIEF_DOCS = NO +SORT_MEMBERS_CTORS_1ST = NO +SORT_GROUP_NAMES = NO +SORT_BY_SCOPE_NAME = NO +STRICT_PROTO_MATCHING = NO +GENERATE_TODOLIST = YES +GENERATE_TESTLIST = YES +GENERATE_BUGLIST = YES +GENERATE_DEPRECATEDLIST= YES +ENABLED_SECTIONS = +MAX_INITIALIZER_LINES = 30 +SHOW_USED_FILES = YES +SHOW_FILES = YES +SHOW_NAMESPACES = YES +FILE_VERSION_FILTER = +LAYOUT_FILE = +CITE_BIB_FILES = +QUIET = YES +WARNINGS = YES +WARN_IF_UNDOCUMENTED = YES +WARN_IF_DOC_ERROR = YES +WARN_NO_PARAMDOC = YES +WARN_FORMAT = "$file:$line: $text" +WARN_LOGFILE = +INPUT = src \ + documentation +INPUT_ENCODING = UTF-8 +FILE_PATTERNS = +RECURSIVE = YES +EXCLUDE = src/vendorcode +EXCLUDE_SYMLINKS = NO +EXCLUDE_PATTERNS = +EXCLUDE_SYMBOLS = +EXAMPLE_PATH = +EXAMPLE_PATTERNS = +EXAMPLE_RECURSIVE = NO +IMAGE_PATH = +INPUT_FILTER = +FILTER_PATTERNS = +FILTER_SOURCE_FILES = NO +FILTER_SOURCE_PATTERNS = +USE_MDFILE_AS_MAINPAGE = +SOURCE_BROWSER = YES +INLINE_SOURCES = NO +STRIP_CODE_COMMENTS = NO +REFERENCED_BY_RELATION = YES +REFERENCES_RELATION = YES +REFERENCES_LINK_SOURCE = YES +SOURCE_TOOLTIPS = YES +USE_HTAGS = NO +VERBATIM_HEADERS = YES +ALPHABETICAL_INDEX = YES +COLS_IN_ALPHA_INDEX = 5 +IGNORE_PREFIX = +GENERATE_HTML = YES +HTML_OUTPUT = html +HTML_FILE_EXTENSION = .html +HTML_HEADER = +HTML_FOOTER = +HTML_STYLESHEET = +HTML_EXTRA_STYLESHEET = +HTML_EXTRA_FILES = +HTML_COLORSTYLE_HUE = 220 +HTML_COLORSTYLE_SAT = 100 +HTML_COLORSTYLE_GAMMA = 80 +HTML_TIMESTAMP = NO +HTML_DYNAMIC_SECTIONS = NO +HTML_INDEX_NUM_ENTRIES = 100 +GENERATE_DOCSET = NO +DOCSET_FEEDNAME = "Doxygen documentation" +DOCSET_BUNDLE_ID = org.doxygen.Project +DOCSET_PUBLISHER_ID = org.doxygen.Publisher +DOCSET_PUBLISHER_NAME = Publisher +GENERATE_HTMLHELP = NO +CHM_FILE = +HHC_LOCATION = +GENERATE_CHI = NO +CHM_INDEX_ENCODING = +BINARY_TOC = NO +TOC_EXPAND = NO +GENERATE_QHP = NO +QCH_FILE = +QHP_NAMESPACE = org.doxygen.Project +QHP_VIRTUAL_FOLDER = doc +QHP_CUST_FILTER_NAME = +QHP_CUST_FILTER_ATTRS = +QHP_SECT_FILTER_ATTRS = +QHG_LOCATION = +GENERATE_ECLIPSEHELP = NO +ECLIPSE_DOC_ID = org.doxygen.Project +DISABLE_INDEX = NO +GENERATE_TREEVIEW = YES +ENUM_VALUES_PER_LINE = 4 +TREEVIEW_WIDTH = 250 +EXT_LINKS_IN_WINDOW = NO +FORMULA_FONTSIZE = 10 +FORMULA_TRANSPARENT = YES +USE_MATHJAX = NO +MATHJAX_FORMAT = HTML-CSS +MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest +MATHJAX_EXTENSIONS = +MATHJAX_CODEFILE = +SEARCHENGINE = YES +SERVER_BASED_SEARCH = NO +EXTERNAL_SEARCH = NO +SEARCHENGINE_URL = +SEARCHDATA_FILE = searchdata.xml +EXTERNAL_SEARCH_ID = +EXTRA_SEARCH_MAPPINGS = +GENERATE_LATEX = NO +LATEX_OUTPUT = latex +LATEX_CMD_NAME = latex +MAKEINDEX_CMD_NAME = makeindex +COMPACT_LATEX = NO +PAPER_TYPE = a4wide +EXTRA_PACKAGES = +LATEX_HEADER = +LATEX_FOOTER = +LATEX_EXTRA_FILES = +PDF_HYPERLINKS = NO +USE_PDFLATEX = NO +LATEX_BATCHMODE = NO +LATEX_HIDE_INDICES = NO +LATEX_SOURCE_CODE = NO +LATEX_BIB_STYLE = plain +GENERATE_RTF = NO +RTF_OUTPUT = rtf +COMPACT_RTF = NO +RTF_HYPERLINKS = NO +RTF_STYLESHEET_FILE = +RTF_EXTENSIONS_FILE = +GENERATE_MAN = NO +MAN_OUTPUT = man +MAN_EXTENSION = .3 +MAN_SUBDIR = +MAN_LINKS = NO +GENERATE_XML = NO +XML_OUTPUT = xml +XML_PROGRAMLISTING = YES +GENERATE_DOCBOOK = NO +DOCBOOK_OUTPUT = docbook +DOCBOOK_PROGRAMLISTING = NO +GENERATE_AUTOGEN_DEF = NO +GENERATE_PERLMOD = NO +PERLMOD_LATEX = NO +PERLMOD_PRETTY = YES +PERLMOD_MAKEVAR_PREFIX = +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = YES +EXPAND_ONLY_PREDEF = YES +SEARCH_INCLUDES = YES +INCLUDE_PATH = +INCLUDE_FILE_PATTERNS = +PREDEFINED = __attribute__(x)= +EXPAND_AS_DEFINED = +SKIP_FUNCTION_MACROS = YES +TAGFILES = +GENERATE_TAGFILE = +ALLEXTERNALS = NO +EXTERNAL_GROUPS = YES +EXTERNAL_PAGES = YES +PERL_PATH = /usr/bin/perl +CLASS_DIAGRAMS = YES +MSCGEN_PATH = +DIA_PATH = +HIDE_UNDOC_RELATIONS = NO +HAVE_DOT = NO +DOT_NUM_THREADS = 0 +DOT_FONTNAME = Helvetica +DOT_FONTSIZE = 10 +DOT_FONTPATH = +CLASS_GRAPH = YES +COLLABORATION_GRAPH = YES +GROUP_GRAPHS = YES +UML_LOOK = YES +UML_LIMIT_NUM_FIELDS = 10 +TEMPLATE_RELATIONS = NO +INCLUDE_GRAPH = YES +INCLUDED_BY_GRAPH = YES +CALL_GRAPH = YES +CALLER_GRAPH = YES +GRAPHICAL_HIERARCHY = YES +DIRECTORY_GRAPH = YES +DOT_IMAGE_FORMAT = png +INTERACTIVE_SVG = NO +DOT_PATH = +DOTFILE_DIRS = +MSCFILE_DIRS = +DIAFILE_DIRS = +PLANTUML_JAR_PATH = +DOT_GRAPH_MAX_NODES = 50 +MAX_DOT_GRAPH_DEPTH = 0 +DOT_TRANSPARENT = NO +DOT_MULTI_TARGETS = YES +GENERATE_LEGEND = YES +DOT_CLEANUP = YES

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New patch to review for coreboot: 49794fe nyan*: I2C: Fix bus clear BC_TERMINATE naming.
by Marc Jones 06 Jan '15

06 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8152 -gerrit commit 49794feec2139566667c2f02b2a2f22ad42032de Author: Tom Warren <twarren(a)nvidia.com> Date: Wed Jul 2 09:25:35 2014 -0700 nyan*: I2C: Fix bus clear BC_TERMINATE naming. In the original fix for the 'Lost arb' we were seeing on Nyan* during reboot stress testing, I had the name of BC_TERMINATE's bit setting wrong. Fix this to use the IMMEDIATE (1) setting. The setting didn't change, just the name. According to Julius this is the optimal setting for bus clear in this instance. Also widened the SCLK_THRESHOLD mask to 8 bits as per spec. BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Tested on nyan. Built for nyan and nyan_big. Original-Change-Id: I19588690924b83431d9f4d3d2eb64f4947849a33 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206409 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 76e08d0cb0fb87e2c75d3086930f272b645ecf4e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If187ddf53660feaceab96efe44a3aadad60c43ff --- src/soc/nvidia/tegra/i2c.c | 4 ++-- src/soc/nvidia/tegra/i2c.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 542d4f0..6f9142c 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -37,9 +37,9 @@ static void do_bus_clear(int bus) // 1. Reset the I2C controller (already done) // 2. Set the # of clock pulses required (using default of 9) // 3. Select STOP condition (using default of 1 = STOP) - // 4. Set TERMINATE condition (1 = THRESHOLD) + // 4. Set TERMINATE condition (1 = IMMEDIATE) bc = read32(&regs->bus_clear_config); - bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_THRESHOLD; + bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE; write32(bc, &regs->bus_clear_config); // 4.1 Set MSTR_CONFIG_LOAD and wait for clear write32(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load); diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h index 4b1bddd..9d7de14 100644 --- a/src/soc/nvidia/tegra/i2c.h +++ b/src/soc/nvidia/tegra/i2c.h @@ -115,9 +115,9 @@ enum { enum { I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT = 16, I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_MASK = - 0x7f << I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT, + 0xff << I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT, I2C_BUS_CLEAR_CONFIG_BC_STOP_COND_STOP = 0x1 << 2, - I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_THRESHOLD = 0x1 << 1, + I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE = 0x1 << 1, I2C_BUS_CLEAR_CONFIG_BC_ENABLE = 0x1 << 0, I2C_BUS_CLEAR_STATUS_CLEARED = 0x1 << 0,

1 0

New patch to review for coreboot: 0e63e0c tegra124: fix and fine tune the warm boot code
by Marc Jones 06 Jan '15

06 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8151 -gerrit commit 0e63e0c8faa8603212776ae6e4ed7be6e2ad55ec Author: Joseph Lo <josephl(a)nvidia.com> Date: Fri Jun 27 11:22:41 2014 +0800 tegra124: fix and fine tune the warm boot code We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same as PLLP. But that is incorrect, BootROM had switched it to pllp_out2 with the rate 204MHz. So actually the warm boot procedure was running at the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz. And the CPU complex power on sequences were different with what we used in kernel and Coreboot. Fix up the sequence as below. * enable CPU clk * power on CPU complex * remove I/O clamps * remove CPU reset Update the time of the CPU complex power on function for record. * power_on_partition(PARTID_CRAIL): 528 uSec * power_on_partition(PARTID_CONC): 0 uSec * power_on_partition(PARTID_CE0): 4 uSec Finally, removing the redundant routine of a flow controller event with (20 | MSEC_EVENT | MODE_STOP). BUG=chrome-os-partner:29394 BRANCH=none TEST=manually test LP0 with lid switch quickly and make sure the last write to restore register successfully Original-Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8 Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205901 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Commit-Queue: Jimmy Zhang <jimmzhang(a)nvidia.com> (cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If21d17dc888b2c289970163e4f695423173ca03d --- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 27 +++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 0b519d6..9b1a4b5 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -419,6 +419,13 @@ static void config_tsc(void) setbits32(TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG, sysctr_cntcr_ptr); } +static void enable_cpu_clocks(void) +{ + // Enable the CPU complex clock. + write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); + write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); +} + /* Function unit configuration. */ @@ -505,15 +512,15 @@ static void power_on_main_cpu(void) * Note that PMC_CPUPWRGOOD_TIMER is running at pclk. * * We need to reprogram PMC_CPUPWRGOOD_TIMER based on the current pclk - * which is at 408Mhz (pclk = sclk = pllp_out0) after reset. Multiply - * PMC_CPUPWRGOOD_TIMER by 408M / 32K. + * which is at 204Mhz (pclk = sclk = pllp_out2) after BootROM. Multiply + * PMC_CPUPWRGOOD_TIMER by 204M / 32K. * * Save the original PMC_CPUPWRGOOD_TIMER register which we need to * restore after the CPU is powered up. */ uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); - write32(orig_timer * (408000000 / 32768), + write32(orig_timer * (204000000 / 32768), pmc_ctlr_cpupwrgood_timer_ptr); if (wakeup_on_lp()) { @@ -525,10 +532,6 @@ static void power_on_main_cpu(void) power_on_partition(PARTID_CE0); } - // Give I/O signals time to stablize. - write32(20 | EVENT_MSEC | FLOW_MODE_STOP, - flow_ctlr_halt_cop_events_ptr); - // Restore the original PMC_CPUPWRGOOD_TIMER. write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); } @@ -575,12 +578,6 @@ void lp0_resume(void) ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); - // Enable the CPU complex clock. - write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); - write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); - - clear_cpu_resets(); - config_tsc(); // Disable VPR. @@ -588,8 +585,12 @@ void lp0_resume(void) write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, mc_video_protect_reg_ctrl_ptr); + enable_cpu_clocks(); + power_on_main_cpu(); + clear_cpu_resets(); + // Halt the AVP. while (1) write32(FLOW_MODE_STOP | EVENT_JTAG,

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New patch to review for coreboot: d1ff594 Primitive memory test
by Marc Jones 06 Jan '15

06 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8150 -gerrit commit d1ff594a9b13486eebe35a9638613f6af497ac4f Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Feb 13 13:07:50 2014 -0800 Primitive memory test This adds a generic primitive memory test. We should look into using tests in src/lib/ramtest.c, but they seem to rely too heavily on x86 asm and this test has been useful on multiple ARM platforms. BUG=none BRANCH=none TEST=builds and runs on nyan Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: Ia0fb4e12bc59bf708be13faf63c346b531eb3aed Original-Reviewed-on: https://chromium-review.googlesource.com/186309 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit e7625c15415eaf6053ce32b67d9d6ab18d776f5f) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Conflicts: src/lib/Makefile.inc Change-Id: I34e7aedfd167199fd5db4cd4a766b2b80ddda79b --- src/include/lib.h | 3 +++ src/lib/Makefile.inc | 2 ++ src/lib/primitive_memtest.c | 65 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) diff --git a/src/include/lib.h b/src/include/lib.h index 772a66f..0cb2c0c 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -39,6 +39,9 @@ int ram_check_nodie(unsigned long start, unsigned long stop); int ram_check_noprint_nodie(unsigned long start, unsigned long stop); void quick_ram_check(void); +/* Defined in primitive_memtest.c */ +int primitive_memtest(uintptr_t base, uintptr_t size); + /* Defined in src/lib/stack.c */ int checkstack(void *top_of_stack, int core); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 0501091..76dc18c 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -33,6 +33,8 @@ romstage-$(CONFIG_I2C_TPM) += delay.c romstage-y += cbfs.c cbfs_core.c romstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c +romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c +ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) diff --git a/src/lib/primitive_memtest.c b/src/lib/primitive_memtest.c new file mode 100644 index 0000000..d59d25f --- /dev/null +++ b/src/lib/primitive_memtest.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <inttypes.h> +#include <lib.h> +#include <console/console.h> + +int primitive_memtest(uintptr_t base, uintptr_t size) +{ + uintptr_t *p; + uintptr_t i; + int bad = 0; + + printk(BIOS_SPEW, "Performing primitive memory test.\n"); + printk(BIOS_SPEW, "DRAM start: 0x%08x, DRAM size: 0x%08x", base, size); + for(i = base; i < base + (size - 1) - sizeof(p); i += sizeof(p)) { + if (i % 0x100000 == 0) { + if ((i % 0x800000) == 0) + printk(BIOS_SPEW, "\n"); + else if (i != 0) + printk(BIOS_SPEW, " "); + printk(BIOS_SPEW, "0x%08x", i); + } + p = (uintptr_t *)i; + *p = i; + } + + printk(BIOS_SPEW, "\n\nReading back DRAM content"); + for(i = base; i < base + (size - 1) - sizeof(p); i += sizeof(p)) { + if (i % 0x100000 == 0) { + if ((i % 0x800000) == 0) + printk(BIOS_SPEW, "\n"); + else if (i != 0) + printk(BIOS_SPEW, " "); + printk(BIOS_SPEW, "0x%08x", i); + } + + p = (uintptr_t *)i; + if (*p != i) { + printk(BIOS_SPEW, "\n0x%08zx: got 0x%zx\n", i, *p); + bad++; + } + } + + printk(BIOS_SPEW, "\n"); + printk(BIOS_SPEW, "%d errors\n", bad); + + return bad; +}

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New patch to review for coreboot: 214400d storm: Reserve memory from 0x4000_0000-0x414f_ffff
by Marc Jones 06 Jan '15

06 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8149 -gerrit commit 214400d04beb9904f9e49cff884e45737eded866 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jul 2 13:50:57 2014 -0700 storm: Reserve memory from 0x4000_0000-0x414f_ffff This marks the bottom chunk of memory, which is used by various IP blocks, as reserved so that Depthcharge does not attempt to wipe it. BUG=chrome-os-partner:30067 BRANCH=storm TEST=Built and booted for storm, depthcharge shows: Wipe memory regions: [0x00000041500000, 0x00000051000000) [0x000000510006a0, 0x00000053000000) [0x00000054141260, 0x0000007fffd000) Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I8f782f16d13620b705e1b3fbeca21dc8705b7e77 Original-Reviewed-on: https://chromium-review.googlesource.com/206516 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit f66f553f1594c481a74b7f40b4b1088600b1a70a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I82d118abc86052f5e32f6195a4efd04fe315be5a --- src/soc/qualcomm/ipq806x/soc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/soc.c b/src/soc/qualcomm/ipq806x/soc.c index 53f5716..6421ccd 100644 --- a/src/soc/qualcomm/ipq806x/soc.c +++ b/src/soc/qualcomm/ipq806x/soc.c @@ -22,10 +22,16 @@ #include <console/console.h> #include <device/device.h> + +#define RESERVED_SIZE_KB (0x01500000 / KiB) + static void soc_read_resources(device_t dev) { - ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, - CONFIG_DRAM_SIZE_MB * (1 << 10)); + /* Reserve bottom 0x150_0000 bytes for NSS, SMEM, etc. */ + reserved_ram_resource(dev, 0, + CONFIG_SYS_SDRAM_BASE/KiB, RESERVED_SIZE_KB); + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB + RESERVED_SIZE_KB, + (CONFIG_DRAM_SIZE_MB * KiB) - RESERVED_SIZE_KB); } static void soc_init(device_t dev)

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New patch to review for coreboot: a7ba630 storm: Increase DRAM size to 1024MB
by Marc Jones 06 Jan '15

06 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8148 -gerrit commit a7ba6306240f0509a2eb17b45302d4087d040c3d Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jun 27 13:30:21 2014 -0700 storm: Increase DRAM size to 1024MB BUG=chrome-os-partner:29871 BRANCH=storm TEST=builds and boots (sort of) Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I82e1792152d17d689e129c9941e8972221bde366 Original-Reviewed-on: https://chromium-review.googlesource.com/206011 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 8995fde9bdfb8af8fb86525fd67a61614881f78e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ice4a5382903b0ab6e085c39d05c46601373080eb --- src/mainboard/google/storm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 1063f83..5e34802 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -38,7 +38,7 @@ config MAINBOARD_PART_NUMBER config DRAM_SIZE_MB int - default 512 + default 1024 config DRAM_DMA_START hex

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New patch to review for coreboot: 46e7a96 storm: USB fixes for proto0
by Marc Jones 06 Jan '15

06 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8147 -gerrit commit 46e7a9675048253327145076d66d36c2194b134e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 24 07:26:03 2014 -0700 storm: USB fixes for proto0 The actual storm device has a single USB interface, which needs to be explicitly turned on using GPIO51. BUG=chrome-os-partner:29871 TEST=verified that depthcharge finds and boots a kernel from USB stick Original-Change-Id: Iaf868812c96e1e3289b9403855c4cc8f87c1e368 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205329 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> (cherry picked from commit aa22376ffac22309a298dfa844e7f61c97d57d3e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ic0f34622e61a65a0540c0f3fca26fb057fa85fb7 --- src/mainboard/google/storm/mainboard.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 301e645..d5adf2d 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -21,6 +21,7 @@ #include <boot/coreboot_tables.h> #include <device/device.h> #include <soc/qualcomm/ipq806x/include/clock.h> +#include <soc/qualcomm/ipq806x/include/gpio.h> #include <soc/qualcomm/ipq806x/include/usb.h> /* convenient shorthand (in MB) */ @@ -32,12 +33,15 @@ #define DMA_START (CONFIG_DRAM_DMA_START / MiB) #define DMA_SIZE (CONFIG_DRAM_DMA_SIZE / MiB) +#define USB_ENABLE_GPIO 51 + static void setup_usb(void) { + gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO, + GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE); usb_clock_config(); setup_usb_host1(); - setup_usb_host2(); } static void setup_mmu(void)

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New patch to review for coreboot: a57f454 spi: Add Spansion flash S25FL128P
by Marc Jones 06 Jan '15

06 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8146 -gerrit commit a57f454e2f832865304f6e9b874219875324c697 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Jun 23 09:16:18 2014 -0700 spi: Add Spansion flash S25FL128P Storm devices use more recent Spansion flash, add its description to the table of supported devices. BUG=chrome-os-partner:29871 TEST=the updated firmware boots all the way to depthcharge Original-Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205182 Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> (cherry picked from commit ea7bb1cf65b7130164b869fef09c55138100206b) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1e0136a5c575951b4e464aab0f380f19e886a84f --- src/drivers/spi/spansion.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index c7e31fe..d8a1754 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -140,6 +140,14 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .nr_sectors = 64, .name = "S25FL032P", }, + { + .idcode1 = SPSN_ID_S25FL128P, + .idcode2 = SPSN_EXT_ID_S25FLXXS_64KB, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 256, + .name = "25FS128S", + }, }; static int spansion_write(struct spi_flash *flash,

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coreboot-gerrit January 2015