coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

1 participants
1236 discussions

Patch merged into coreboot/master: 9c2aa69 asrock/e350m1, lenovo/x2x0 Kconfig: fix indentation
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit 9c2aa697258c2aaaa9d4956ff5c7986036aff977 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Jan 4 16:23:41 2015 +0100 asrock/e350m1, lenovo/x2x0 Kconfig: fix indentation Change-Id: Ide09e129fd9400eb20f9b7bb3cd0e5d6d271e372 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/8176 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8176 for details. -gerrit

1 0

Patch set updated for coreboot: 7c186b2 ACPI: Fix S3 handoff state to ramstage
by Kyösti Mälkki 09 Jan '15

09 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8172 -gerrit commit 7c186b21168fe8fdb367aa823ab6b23ca35bf80c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 07:33:50 2015 +0200 ACPI: Fix S3 handoff state to ramstage Global acpi_slp_type is now declared static. The change also guarantees it will always be initialized before. Change-Id: I0f074bb80f06f6f0ddf4212cd8872e94ae57f949 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 17 +++------ src/arch/x86/include/arch/acpi.h | 22 +++++------- .../intel/fsp_sandybridge/northbridge.c | 15 +++----- src/northbridge/intel/gm45/northbridge.c | 31 ++++++++-------- src/northbridge/intel/haswell/northbridge.c | 11 +++--- src/northbridge/intel/i945/northbridge.c | 17 +++------ src/northbridge/intel/nehalem/northbridge.c | 15 +++----- src/northbridge/intel/sandybridge/northbridge.c | 15 +++----- src/northbridge/intel/sch/northbridge.c | 17 +++------ src/soc/intel/baytrail/ramstage.c | 42 ++++++++++++---------- src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/baytrail/xhci.c | 4 +-- src/soc/intel/broadwell/lpc.c | 4 +-- src/soc/intel/broadwell/me.c | 4 +-- src/soc/intel/broadwell/ramstage.c | 41 +++++++++++---------- src/soc/intel/broadwell/refcode.c | 11 +----- src/soc/intel/broadwell/systemagent.c | 22 ------------ src/soc/intel/fsp_baytrail/ramstage.c | 33 +++++++++-------- src/southbridge/amd/sb700/lpc.c | 17 ++++----- src/southbridge/intel/i82371eb/smbus.c | 11 ------ src/southbridge/intel/i82371eb/wakeup.c | 3 +- src/southbridge/via/vt8237r/lpc.c | 10 +++--- 22 files changed, 141 insertions(+), 223 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 61f0954..b5c22a4 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -854,22 +854,13 @@ void acpi_resume(void *wake_vec) acpi_jump_to_wakeup(wake_vec); } -/* This is to be filled by SB code - startup value what was found. */ -u8 acpi_slp_type = 0; - -int __attribute__((weak)) acpi_get_sleep_type(void) -{ - return 0; -} +/* This is filled with acpi_is_wakeup() call early in ramstage. */ +static int acpi_slp_type = -1; static void acpi_handoff_wakeup(void) { - static int once = 0; - if (once) - return; - - acpi_slp_type = acpi_get_sleep_type(); - once = 1; + if (acpi_slp_type < 0) + acpi_slp_type = acpi_get_sleep_type(); } int acpi_is_wakeup(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 502c826..e748e95 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -559,14 +559,10 @@ unsigned long acpi_fill_hest(acpi_hest_t *hest); void acpi_save_gnvs(u32 gnvs_address); -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -/* 0 = S0, 1 = S1 ...*/ -extern u8 acpi_slp_type; - -int acpi_is_wakeup(void); -int acpi_is_wakeup_s3(void); -int acpi_is_wakeup_early(void); +/* cpu/intel/speedstep/acpi.c */ +void generate_cpu_entries(void); +/* For ACPI S3 resume support. */ void acpi_fail_wakeup(void); void acpi_resume(void *wake_vec); void acpi_prepare_resume_backup(void); @@ -575,19 +571,19 @@ void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr); +/* Returns 0 = S0, 1 = S1 ... */ int acpi_get_sleep_type(void); -#endif /* IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) */ - -/* cpu/intel/speedstep/acpi.c */ -void generate_cpu_entries(void); static inline int acpi_s3_resume_allowed(void) { return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); } -#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -#define acpi_slp_type 0 +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +int acpi_is_wakeup(void); +int acpi_is_wakeup_s3(void); +int acpi_is_wakeup_early(void); +#else static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_early(void) { return 0; } diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index b9ecdfa..1834ced 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -329,24 +329,20 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); } -static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; + return 0; } -#endif } static struct pci_operations intel_pci_ops = { @@ -358,7 +354,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index fc54a8c..51515f4 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -220,28 +220,27 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; +int acpi_get_sleep_type(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + switch (pci_read_config32(dev, D0F0_SKPAD)) { + case SKPAD_NORMAL_BOOT_MAGIC: + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + case SKPAD_ACPI_S3_MAGIC: + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + default: + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } +} static void enable_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..498cd0b 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -433,24 +433,22 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); if (handoff == NULL) { printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; + return 0; } else if (handoff->s3_resume) { printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; + return 3; } else { printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; + return 0; } -#endif } static struct pci_operations intel_pci_ops = { @@ -462,7 +460,6 @@ static struct device_operations mc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 1aaeb3b..d4e5ef2 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -232,25 +232,21 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -#if CONFIG_HAVE_ACPI_RESUME -static void northbridge_init(struct device *dev) +int acpi_get_sleep_type(void) { + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; + return 0; } } -#endif static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, @@ -261,9 +257,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, -#if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, -#endif .scan_bus = 0, .ops_pci = &intel_pci_ops, }; diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 2c4b1ff..21900e5 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -283,24 +283,20 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; + return 0; } -#endif } static struct pci_operations intel_pci_ops = { @@ -312,7 +308,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7159700..b96ce8b 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -412,24 +412,20 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; + return 0; } -#endif } static struct pci_operations intel_pci_ops = { @@ -441,7 +437,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index be4785e..7138ba0 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -250,25 +250,21 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -#if CONFIG_HAVE_ACPI_RESUME -static void northbridge_init(struct device *dev) +int acpi_get_sleep_type(void) { + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; + return 0; } } -#endif static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, @@ -278,9 +274,6 @@ static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, -#if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, -#endif .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..ab54049 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -130,13 +130,6 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) { @@ -163,25 +156,36 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) gnvs->pm1i); } +int acpi_get_sleep_type(void) +{ + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } +} + static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 5274b03..f6462fa 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -215,7 +215,7 @@ static void sc_init(device_t dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) com1_configure_resume(dev); } diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..19339e4 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -184,7 +184,7 @@ static void xhci_route_all(device_t dev) /* Route ports to XHCI controller */ reg_script_run_on_dev(dev, xhci_route_all_script); - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) return; /* Reset enabled USB3 ports */ @@ -222,7 +222,7 @@ static void xhci_init(device_t dev) }; /* Initialize XHCI controller for boot or resume path */ - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 394a9d7..c670440 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -394,7 +394,7 @@ static void pch_cg_init(device_t dev) static void pch_set_acpi_mode(void) { #if CONFIG_HAVE_SMI_HANDLER - if (acpi_slp_type != 3) { + if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); @@ -551,7 +551,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (acpi_slp_type != 3 && gnvs) + if (!acpi_is_wakeup_s3() && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); } diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 2bdb1ed..9fc6a41 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -830,13 +830,11 @@ static void intel_me_init(device_t dev) static void intel_me_enable(device_t dev) { -#if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { dev->enabled = 0; pch_disable_devfn(dev); } -#endif } static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 0563064..38f7b5d 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -54,31 +54,36 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) gnvs->pm1i); } -static inline void set_acpi_sleep_type(int val) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } } static void s3_resume_prepare(void) { - global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; + global_nvs_t *gnvs; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); - return; - } + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + if (gnvs == NULL) + return; - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void broadwell_init_pre_device(void *chip_info) diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index a745101..d66d036 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -30,15 +30,6 @@ #include <broadwell/pei_wrapper.h> #include <broadwell/ramstage.h> -static inline int is_s3_resume(void) -{ -#if CONFIG_HAVE_ACPI_RESUME - return acpi_slp_type == 3; -#else - return 0; -#endif -} - static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) { return (struct ramstage_cache *)&c->program[c->size]; @@ -136,7 +127,7 @@ static pei_wrapper_entry_t load_reference_code(void) }; int ret; - if (is_s3_resume()) { + if (acpi_is_wakeup_s3()) { return load_refcode_from_cache(); } diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 74c43f2..2e0a492 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -412,27 +412,6 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -451,7 +430,6 @@ static struct device_operations systemagent_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &systemagent_init, - .enable = &systemagent_enable, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..0b3db41 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -125,31 +125,34 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } - -static inline void set_acpi_sleep_type(int val) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } } static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - set_acpi_sleep_type(3); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); } void baytrail_init_pre_device(void) diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 8ebc765..658e954 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -29,7 +29,6 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> -#include <arch/acpi.h> #include <cbmem.h> #include <cpu/amd/powernow.h> #include "sb700.h" @@ -80,19 +79,15 @@ static void lpc_init(device_t dev) #endif pci_write_config8(dev, 0x78, byte); - /* hack, but the whole sb700 startup lacks any device which - is doing the acpi init */ -#if CONFIG_HAVE_ACPI_RESUME - { - u16 tmp = inw(ACPI_PM1_CNT_BLK); - acpi_slp_type = ((tmp & (7 << 10)) >> 10); - printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); - } -#endif - cmos_check_update_date(); } +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + return ((tmp & (7 << 10)) >> 10); +} + void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index d236cfa..6341751 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -31,11 +31,6 @@ #include "i82371eb.h" #include "smbus.h" -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -int acpi_get_sleep_type(void); -#endif - static void pwrmgt_enable(struct device *dev) { struct southbridge_intel_i82371eb_config *sb = dev->chip_info; @@ -92,12 +87,6 @@ static void pwrmgt_enable(struct device *dev) outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); -#if CONFIG_HAVE_ACPI_RESUME - /* this reads PMCNTRL, so we have to call it before writing the - * default value */ - acpi_slp_type = acpi_get_sleep_type(); -#endif - /* set PMCNTRL default */ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); } diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index dd4a28f..f9ca385 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -19,12 +19,11 @@ */ #include <stdint.h> +#include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> #include "i82371eb.h" -int acpi_get_sleep_type(void); - /* * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 * diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 92eaa39..d3e3d32 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -244,10 +244,6 @@ static void setup_pm(device_t dev) /* SCI is generated for RTC/pwrBtn/slpBtn. */ tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; - printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); -#endif /* All SMI on, both IDE buses ON, PSON rising edge. */ outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c); @@ -258,6 +254,12 @@ static void setup_pm(device_t dev) outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); } +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; +} + static void vt8237r_init(struct device *dev) { u8 enables;

1 0

Patch set updated for coreboot: d8218b2 cpu/amd/pi: Use acpi_is_wakeup()
by Kyösti Mälkki 09 Jan '15

09 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8171 -gerrit commit d8218b24dc6d563524f1e8667679695c55f90d34 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:44:30 2015 +0200 cpu/amd/pi: Use acpi_is_wakeup() Propagate commit 9107e53 from amd/agesa and fix some related #includes under cpu/amd/pi. Change test to return true on S2 wakeup too. In S2 CPU would have been powered down so MTRR recovery is required. Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00730F01/model_16_init.c | 8 ++------ src/cpu/amd/pi/heapmanager.c | 2 +- src/cpu/amd/pi/s3_resume.c | 2 +- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 8053fd1..336618a 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -33,9 +33,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam16.h> #include <arch/acpi.h> -#if CONFIG_HAVE_ACPI_RESUME -#include <cpu/amd/agesa/s3_resume.h> -#endif +#include <cpu/amd/pi/s3_resume.h> static void model_16_init(device_t dev) { @@ -72,10 +70,8 @@ static void model_16_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) + if (acpi_is_wakeup()) restore_mtrr(); -#endif x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index d2c3931..aa251e0 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -1,7 +1,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/pi/BiosCallOuts.h> #include "heapManager.h" #include <cbmem.h> diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index fc619f7..bc82964 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <string.h> #include "Porting.h" -#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/pi/BiosCallOuts.h> #include "s3_resume.h" /* The size needs to be 4k aligned, which is the sector size of most flashes. */

1 0

Patch merged into coreboot/master: 1d7f5c5 macbook21 lenovo/xx: Fix inw() in SMI handlers
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit 1d7f5c5c37c37ff4f9792803147dc94482cf71ae Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 12:06:35 2015 +0200 macbook21 lenovo/xx: Fix inw() in SMI handlers Missing base may have enabled SMI for all GPI inputs. Change-Id: I1157afaccccb17d325a4efdb1f270a27f9a299ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8169 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8169 for details. -gerrit

1 0

Patch set updated for coreboot: 62346e0 lenovo/t530: Fix VGA device ID
by Philipp Deppenwiese 09 Jan '15

09 Jan '15

Philipp Deppenwiese (zaolin(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8178 -gerrit commit 62346e0f010ab9e6102557363248a4bf0491b571 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Fri Jan 9 00:57:21 2015 +0100 lenovo/t530: Fix VGA device ID * Fix VGA device ID * Disable native VGA init default option On many notebooks variants out there are different displays which are not covered by a static display definition inside the devicetree. Please don't make this a default option as long as nobody implements a dynamic resolution via EDID. Change-Id: I3cffe9d832edbbea79cabca639d9d920b7ffcf9a Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/lenovo/t530/Kconfig | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 2dcfa90..550f66f 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select IVYBRIDGE_LVDS - select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX # Workaround for EC/KBC IRQ1. @@ -60,7 +59,11 @@ config DRAM_RESET_GATE_GPIO config VGA_BIOS_FILE string - default "pci8086,0106.rom" + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex

1 0

New patch to review for coreboot: 54c50c2 lenovo/t530: Fix VGA device ID and disable native VGA init default option
by Philipp Deppenwiese 09 Jan '15

09 Jan '15

Philipp Deppenwiese (zaolin(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8178 -gerrit commit 54c50c266e81f230f26fd813a7aae873adfbd572 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Fri Jan 9 00:57:21 2015 +0100 lenovo/t530: Fix VGA device ID and disable native VGA init default option On many notebooks variants out there are different displays which are not covered by a static display definition inside the devicetree. Please don't make this a default option as long as nobody implements a dynamic resolution via EDID. Change-Id: I3cffe9d832edbbea79cabca639d9d920b7ffcf9a Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/lenovo/t530/Kconfig | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 2dcfa90..550f66f 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select IVYBRIDGE_LVDS - select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX # Workaround for EC/KBC IRQ1. @@ -60,7 +59,11 @@ config DRAM_RESET_GATE_GPIO config VGA_BIOS_FILE string - default "pci8086,0106.rom" + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex

1 0

New patch to review for coreboot: 1e542c3 m4a785/Kconfig: Add vgabios pci id
by Nicolas Reinecke 08 Jan '15

08 Jan '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8177 -gerrit commit 1e542c3848ef2dcc8c6308a7a628296ac53a84f2 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Jan 4 16:26:08 2015 +0100 m4a785/Kconfig: Add vgabios pci id Change-Id: I5ad91faec9c97f34c8ca48eee9198237e9ea8336 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/asus/m4a785-m/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index 5162e16..3abeb0b 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -61,4 +61,8 @@ config AMD_UCODE_PATCH_FILE string default "mc_patch_010000b6.h" +config VGA_BIOS_ID + string + default "1002,9710" + endif

1 0

New patch to review for coreboot: 9536887 asrock/e350m1, lenovo/x2x0 Kconfig: fix indentation
by Nicolas Reinecke 08 Jan '15

08 Jan '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8176 -gerrit commit 9536887aa7e9565aacc36168aa4f3c48bc558b29 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Jan 4 16:23:41 2015 +0100 asrock/e350m1, lenovo/x2x0 Kconfig: fix indentation Change-Id: Ide09e129fd9400eb20f9b7bb3cd0e5d6d271e372 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/asrock/e350m1/Kconfig | 48 ++++++++++++++++++------------------- src/mainboard/lenovo/x220/Kconfig | 4 ++-- src/mainboard/lenovo/x230/Kconfig | 4 ++-- 3 files changed, 28 insertions(+), 28 deletions(-) diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 9ef46c4..5992035 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -20,50 +20,50 @@ if BOARD_ASROCK_E350M1 config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_AGESA_FAMILY14 - select NORTHBRIDGE_AMD_AGESA_FAMILY14 - select SOUTHBRIDGE_AMD_CIMX_SB800 + def_bool y + select CPU_AMD_AGESA_FAMILY14 + select NORTHBRIDGE_AMD_AGESA_FAMILY14 + select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_NUVOTON_NCT5572D select SB_SUPERIO_HWM - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA config MAINBOARD_DIR - string - default asrock/e350m1 + string + default asrock/e350m1 config MAINBOARD_PART_NUMBER - string - default "E350M1" + string + default "E350M1" config HW_MEM_HOLE_SIZEK - hex - default 0x200000 + hex + default 0x200000 config MAX_CPUS - int - default 2 + int + default 2 config HW_MEM_HOLE_SIZE_AUTO_INC - bool - default n + bool + default n config IRQ_SLOT_COUNT - int - default 11 + int + default 11 config ONBOARD_VGA_IS_PRIMARY bool default y config VGA_BIOS_ID - string - default "1002,9802" + string + default "1002,9802" config DRIVERS_PS2_KEYBOARD bool diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 20e9527..7814919 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -49,8 +49,8 @@ config MAX_CPUS default 8 config USBDEBUG_HCD_INDEX - int - default 2 + int + default 2 config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 1a1e018..8599ceb 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -49,8 +49,8 @@ config MAX_CPUS default 8 config USBDEBUG_HCD_INDEX - int - default 2 + int + default 2 config DRAM_RESET_GATE_GPIO int

1 0

New patch to review for coreboot: 2afaaca src/mainboard: Doxygen fixes
by Martin Roth 08 Jan '15

08 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8175 -gerrit commit 2afaaca6a1510d869d344969d56837b1ce39dca8 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jan 6 21:09:57 2015 -0700 src/mainboard: Doxygen fixes - Remove @param command for #define - this isn't valid. - Rename duplicate @section names - All of the renamed @sections have other @section names in the same file. - Remove blank @brief and @param commands - Doxygen seems to REALLY dislike this... - Add a missing @param name. Change-Id: Iba99ec68b37bbb5c375b7256363d16228031d771 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/mainboard/amd/torpedo/Oem.h | 2 -- src/mainboard/amd/torpedo/platform_cfg.h | 18 ++++++----------- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 28 +-------------------------- 3 files changed, 7 insertions(+), 41 deletions(-) diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 915182e..f078858 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -34,8 +34,6 @@ /** * PCIEX_BASE_ADDRESS - Define PCIE base address - * - * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 */ #ifdef MOVE_PCIEBAR_TO_F0000000 #define PCIEX_BASE_ADDRESS 0xF7000000 diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 311214c..6ff1476 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -128,7 +128,7 @@ // #endif /** - * @section GecShadowRomBase + * @section GecShadowRomAddress */ #ifndef GEC_ROM_SHADOW_ADDRESS #define GEC_ROM_SHADOW_ADDRESS 0xFED61000 @@ -191,7 +191,7 @@ // #endif /** - * @section SataController + * @section InChipSataController * @li 0 - Disable * @li 1 - Enable */ @@ -200,7 +200,7 @@ #endif /** - * @section SataIdeCombMdPriSecOpt + * @section SataIdeCombModeChannel * @li 0 - Primary * @li 1 - Secondary<TD></TD> * Sata Controller set as primary or @@ -221,7 +221,7 @@ #endif /** - * @section SataIdeCombinedMode + * @section SataCombineMode * @li 0 - Disable * @li 1 - Enable * Sata IDE Controller set to Combined Mode @@ -738,12 +738,6 @@ #define IDE_DISUNUSED_IDE_S_CHANNEL 0 /** - * @section IdeDisUnusedIdeSChannel - * @li 0 - Disable - * @li 1 - Enable - */ - -/** * @section SataEspPort0 * @li 0 - Disable * @li 1 - Enable @@ -1219,10 +1213,10 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_cfg); * * @param[in] func Southbridge CIMx Function ID. * @param[in] data Southbridge Input Data. - * @param[in] sb_cfg Southbridge configuration structure pointer. + * @param[in] config Southbridge configuration structure pointer. * */ -u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg); +u32 sb900_callout_entry(u32 func, u32 data, void* config); // definition for function in gpio.c void gpioEarlyInit (void); diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 4b92877..6e70f3a 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -277,12 +277,6 @@ static int int15_handler(void) #endif /* ############################################################################################# */ - /** - * @brief - * - * @param - */ - static u8 calc_trange(u8 t_min, u8 t_max) { u8 prev; @@ -341,7 +335,6 @@ static void cable_detect(void) /** * @brief Detect the ADT7475 device * - * @param */ static const char * adt7475_detect( void ) { @@ -427,7 +420,6 @@ static void pm_init( void ) /** * @brief Setup thermal config on SINA Mainboard * - * @param */ static void set_thermal_config(void) @@ -604,12 +596,6 @@ static void set_thermal_config(void) } - /** - * @brief - * - * @param - */ - static void patch_mmio_nonposted( void ) { unsigned reg, index; @@ -649,12 +635,6 @@ static void patch_mmio_nonposted( void ) } } - /** - * @brief - * - * @param - */ - struct { unsigned int bus; unsigned int devfn; @@ -691,12 +671,6 @@ static void update_subsystemid( device_t dev ) } } - /** - * @brief - * - * @param - */ - static void detect_hw_variant( device_t dev ) { @@ -806,7 +780,7 @@ static void smm_lock( void ) /** * @brief Init * - * @param the root device + * @param dev - the root device */ static void mainboard_init(device_t dev)

1 0

New patch to review for coreboot: c2622c3 src/include: Doxygen fixes
by Martin Roth 08 Jan '15

08 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8174 -gerrit commit c2622c3157d29d22092792b1c51557a5e31a4f21 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jan 6 21:05:23 2015 -0700 src/include: Doxygen fixes - Join doxygen file command with the file description - Give extended file location so doxygen knows which early_sbmus.h the file is. (I don't get this either, but it fixes the warning) Change-Id: Ia91fb1ac1e9687e1a5a5cb5234696b3c24d4cd24 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/include/console/post_codes.h | 5 ++++- src/include/device/early_smbus.h | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 9f9b788..b2db2da 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -20,7 +20,9 @@ /** * @file post_codes.h - * + */ + +/* * This aims to be a central point for POST codes used throughout coreboot. * All POST codes should be declared here as macros, and post_code() should * be used with the macros instead of hardcoded values. This allows us to @@ -40,6 +42,7 @@ * without any explanation or effort on part of the maintainers. * */ + #ifndef POST_CODES_H #define POST_CODES_H diff --git a/src/include/device/early_smbus.h b/src/include/device/early_smbus.h index 5e15bb1..437a569 100644 --- a/src/include/device/early_smbus.h +++ b/src/include/device/early_smbus.h @@ -18,7 +18,7 @@ */ /** - * @file early_smbus.h + * @file device/early_smbus.h * * This file defines a common API for accessing the SMBus during early * initialization. It defines the prototypes for common SMBus functions. The

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2015