coreboot-gerrit January 2015

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New patch to review for coreboot: b5a761b macbook21 lenovo/xx: Fix inw() in SMI handlers
by Kyösti Mälkki 08 Jan '15

08 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8169 -gerrit commit b5a761ba4d018e0c10e6b79ef8525d9b57cc77b9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 12:06:35 2015 +0200 macbook21 lenovo/xx: Fix inw() in SMI handlers Missing base may have enabled SMI for all GPI inputs. Change-Id: I1157afaccccb17d325a4efdb1f270a27f9a299ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/apple/macbook21/smihandler.c | 2 +- src/mainboard/lenovo/t420s/smihandler.c | 2 +- src/mainboard/lenovo/t520/smihandler.c | 2 +- src/mainboard/lenovo/t530/smihandler.c | 2 +- src/mainboard/lenovo/t60/smihandler.c | 2 +- src/mainboard/lenovo/x201/smihandler.c | 2 +- src/mainboard/lenovo/x220/smihandler.c | 2 +- src/mainboard/lenovo/x230/smihandler.c | 2 +- src/mainboard/lenovo/x60/smihandler.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index ab039dd..449e367 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -69,7 +69,7 @@ int mainboard_smi_apmc(u8 data) switch(data) { case APM_CNT_ACPI_ENABLE: /* route H8SCI to SCI */ - outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index dd8878f..6c80573 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -130,7 +130,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index c81825e..bb3ad78 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -125,7 +125,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index 5bcde1c..6f6cca1 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -130,7 +130,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 130ad96..36495dc 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -173,7 +173,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index ad3911c..7af613b 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -173,7 +173,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 5bcde1c..6f6cca1 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -130,7 +130,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index 5bcde1c..6f6cca1 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -130,7 +130,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index 090f037..ccc328e 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -179,7 +179,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02;

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Patch set updated for coreboot: 83abf6e intel SMI handlers: Refactor GPI SMI/SCI routing
by Kyösti Mälkki 08 Jan '15

08 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7967 -gerrit commit 83abf6e23107a551affa3efd730e60e21c252154 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 29 11:32:27 2014 +0200 intel SMI handlers: Refactor GPI SMI/SCI routing For lenovo/x201, this also changes GPI_ROUT (0xb8-0xbb) programming to change GPI1 between SCI/SMI modes, while previous programming was for GPI12. Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/apple/macbook21/smihandler.c | 22 +++----------- src/mainboard/google/parrot/smihandler.c | 43 ++------------------------- src/mainboard/lenovo/t420s/smihandler.c | 26 ++++------------ src/mainboard/lenovo/t520/smihandler.c | 37 +++++------------------ src/mainboard/lenovo/t530/smihandler.c | 37 +++++------------------ src/mainboard/lenovo/t60/smihandler.c | 24 ++++----------- src/mainboard/lenovo/x201/smihandler.c | 37 +++++------------------ src/mainboard/lenovo/x220/smihandler.c | 37 +++++------------------ src/mainboard/lenovo/x230/smihandler.c | 38 +++++------------------ src/mainboard/lenovo/x60/smihandler.c | 24 ++++----------- src/mainboard/packardbell/ms2290/smihandler.c | 24 +++++---------- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/bd82x6x/pch.h | 6 ++++ src/southbridge/intel/bd82x6x/smihandler.c | 36 ++++++++++++++++++++++ src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +- src/southbridge/intel/i82801gx/i82801gx.h | 7 +++++ src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 36 ++++++++++++++++++++++ src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/ibexpeak/pch.h | 6 ++++ src/southbridge/intel/ibexpeak/smihandler.c | 36 ++++++++++++++++++++++ src/southbridge/intel/lynxpoint/lpc.c | 2 +- 22 files changed, 197 insertions(+), 289 deletions(-) diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index 449e367..4e4a4b6 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -27,6 +27,8 @@ #include <pc80/mc146818rtc.h> #include <delay.h> +#define GPE_H8SCI 12 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -58,30 +60,14 @@ int mainboard_io_trap_handler(int smif) int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); - - if (!pmbase) - return 0; - switch(data) { case APM_CNT_ACPI_ENABLE: /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); break; default: break; diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 4a189f8..1d1b23c 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -29,44 +29,6 @@ #include <ec/compal/ene932/ec.h> #include "ec.h" -/* Power Management PCI Configuration Registers - * Bus 0, Device 31, Function 0, Offset 0xB8 - * 00 = No Effect - * 01 = SMI# - * 10 = SCI - * 11 = NMI - */ -#define GPI_ROUT 0x8000F8B8 -#define GPI_IS_SMI 0x01 -#define GPI_IS_SCI 0x02 - -static void set_lid_gpi_mode(u32 mode) -{ - u32 reg32 = 0; - u16 reg16 = 0; - - /* read the GPI register, clear the lid GPI's mode, write the new mode - * and write out the register. - */ - outl(GPI_ROUT, 0xcf8); - reg32 = inl(0xcfc); - reg32 &= ~(0x03 << (EC_LID_GPI * 2)); - reg32 |= (mode << (EC_LID_GPI * 2)); - outl(GPI_ROUT, 0xcf8); - outl(reg32, 0xcfc); - - /* Set or Disable Lid GPE as SMI source in the ALT_GPI_SMI_EN register. */ - reg16 = inw(smm_get_pmbase() + ALT_GP_SMI_EN); - if (mode == GPI_IS_SCI) { - reg16 &= ~(1 << EC_LID_GPI); - } else { - reg16 |= (1 << EC_LID_GPI); - } - outw(reg16, smm_get_pmbase() + ALT_GP_SMI_EN); - - return; -} - int mainboard_io_trap_handler(int smif) { printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif); @@ -200,8 +162,7 @@ int mainboard_smi_apmc(u8 apmc) ec_kbc_write_ib(0xE8); /* Set LID GPI to generate SCIs */ - set_lid_gpi_mode(GPI_IS_SCI); - + gpi_route_interrupt(EC_LID_GPI, GPI_IS_SCI); break; case APMC_ACPI_DIS: printk(BIOS_DEBUG, "APMC: ACPI_DIS\n"); @@ -211,7 +172,7 @@ int mainboard_smi_apmc(u8 apmc) ec_kbc_write_ib(0xE9); /* Set LID GPI to generate SMIs */ - set_lid_gpi_mode(GPI_IS_SMI); + gpi_route_interrupt(EC_LID_GPI, GPI_IS_SMI); break; } return 0; diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index 6c80573..430b306 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_H8SCI 12 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -130,11 +133,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -143,12 +142,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -179,16 +173,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index bb3ad78..18fac5d 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_H8SCI 12 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -103,7 +106,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -111,25 +114,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -138,12 +128,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -174,16 +159,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index 6f6cca1..fe7cd65 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_H8SCI 12 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -116,25 +119,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -143,12 +133,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -179,16 +164,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 36495dc..d3ada43 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -28,6 +28,8 @@ #include "dock.h" #include "smi.h" +#define GPE_H8SCI 12 + #define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */ /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler @@ -154,41 +156,25 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi) { - if (gpi & (1 << 12)) + if (gpi & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); - - if (!pmbase) - return 0; - switch(data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); break; default: break; diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 7af613b..de40cea 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -34,6 +34,9 @@ #include "dock.h" #include "smi.h" +#define GPE_H8SCI 1 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -137,7 +140,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 1)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -145,15 +148,6 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "APMC: FINALIZE\n"); @@ -173,11 +167,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -186,12 +176,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -207,16 +192,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 6f6cca1..fe7cd65 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_H8SCI 12 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -116,25 +119,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -143,12 +133,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -179,16 +164,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index 6f6cca1..f8b723b 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -33,6 +33,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> + +#define GPE_H8SCI 12 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +112,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -116,25 +120,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -143,12 +134,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -179,16 +165,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index ccc328e..054400e 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -31,6 +31,8 @@ #include "dock.h" #include "smi.h" +#define GPE_H8SCI 12 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -160,30 +162,18 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi) { - if (gpi & (1 << 12)) + if (gpi & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); - - if (!pmbase) - return 0; - switch(data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -192,11 +182,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index f04ff90..eda17f3 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -31,6 +31,9 @@ #include <pc80/mc146818rtc.h> #include <delay.h> +/* This GPI is not confirmed. */ +#define MS2290_ENABLE_GPI12 1 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -69,15 +72,6 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "APMC: FINALIZE\n"); @@ -94,16 +88,12 @@ int mainboard_smi_apmc(u8 data) mainboard_finalized = 1; break; case APM_CNT_ACPI_ENABLE: - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + if (MS2290_ENABLE_GPI12) + gpi_route_interrupt(12, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + if (MS2290_ENABLE_GPI12) + gpi_route_interrupt(12, GPI_IS_SMI); break; default: break; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 11b765a..98f13be 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -167,7 +167,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7cde7bc..c0a6c56 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -66,6 +66,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void gpi_route_interrupt(u8 gpi, u8 mode); #if CONFIG_ELOG void pch_log_state(void); #endif @@ -142,7 +143,12 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ + #define GPIO_ROUT 0xb8 +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 45612d0..8f69af9 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -75,6 +75,42 @@ void tseg_relocate(void **ptr) } #endif +static void alt_gpi_mask(u16 clr, u16 set) +{ + u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); + alt_gp &= ~clr; + alt_gp |= set; + outw(alt_gp, pmbase + ALT_GP_SMI_EN); +} + +static void gpe0_mask(u32 clr, u32 set) +{ + u32 gpe0 = inl(pmbase + GPE0_EN); + gpe0 &= ~clr; + gpe0 |= set; + outl(gpe0, pmbase + GPE0_EN); +} + +void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + if (gpi >= 16) + return; + + alt_gpi_mask(1 << gpi, 0); + gpe0_mask(1 << (gpi+16), 0); + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); + + if (mode == GPI_IS_SCI) + gpe0_mask(0, 1 << (gpi+16)); + else if (mode == GPI_IS_SMI) + alt_gpi_mask(0, 1 << gpi); +} + /** * @brief read and clear PM1_STS * @return PM1_STS register diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index f9961f9..6b95d08 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -185,7 +185,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index ee13b7d..c436209 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -41,6 +41,7 @@ #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); +void gpi_route_interrupt(u8 gpi, u8 mode); #else void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); @@ -74,6 +75,12 @@ int southbridge_detect_s3_resume(void); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 +#define GPIO_ROUT 0xb8 +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 6b9d11e..aae0be6 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -158,7 +158,7 @@ static void i82801gx_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void i82801gx_power_options(device_t dev) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index e2505ce..fb439c6 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -50,6 +50,42 @@ u8 smm_initialized = 0; */ global_nvs_t *gnvs = (global_nvs_t *)0x0; +static void alt_gpi_mask(u16 clr, u16 set) +{ + u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); + alt_gp &= ~clr; + alt_gp |= set; + outw(alt_gp, pmbase + ALT_GP_SMI_EN); +} + +static void gpe0_mask(u32 clr, u32 set) +{ + u32 gpe0 = inl(pmbase + GPE0_EN); + gpe0 &= ~clr; + gpe0 |= set; + outl(gpe0, pmbase + GPE0_EN); +} + +void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + if (gpi >= 16) + return; + + alt_gpi_mask(1 << gpi, 0); + gpe0_mask(1 << (gpi+16), 0); + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); + + if (mode == GPI_IS_SCI) + gpe0_mask(0, 1 << (gpi+16)); + else if (mode == GPI_IS_SMI) + alt_gpi_mask(0, 1 << gpi); +} + /** * @brief read and clear PM1_STS * @return PM1_STS register diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2124711..7ccc00b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -166,7 +166,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index bd94689..4840a1a 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -67,6 +67,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void gpi_route_interrupt(u8 gpi, u8 mode); #if CONFIG_ELOG void pch_log_state(void); #endif @@ -129,7 +130,12 @@ void southbridge_configure_default_intmap(void); #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ + #define GPIO_ROUT 0xb8 +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e2032ad..95530c4 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -75,6 +75,42 @@ void tseg_relocate(void **ptr) } #endif +static void alt_gpi_mask(u16 clr, u16 set) +{ + u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); + alt_gp &= ~clr; + alt_gp |= set; + outw(alt_gp, pmbase + ALT_GP_SMI_EN); +} + +static void gpe0_mask(u32 clr, u32 set) +{ + u32 gpe0 = inl(pmbase + GPE0_EN); + gpe0 &= ~clr; + gpe0 |= set; + outl(gpe0, pmbase + GPE0_EN); +} + +void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + if (gpi >= 16) + return; + + alt_gpi_mask(1 << gpi, 0); + gpe0_mask(1 << (gpi+16), 0); + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); + + if (mode == GPI_IS_SCI) + gpe0_mask(0, 1 << (gpi+16)); + else if (mode == GPI_IS_SMI) + alt_gpi_mask(0, 1 << gpi); +} + /** * @brief read and clear PM1_STS * @return PM1_STS register diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 563cb0a..c551c8b 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -175,7 +175,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev)

1 0

Patch set updated for coreboot: 66444b5 arm: Change MMIO function parameter order to match x86
by Kevin Paul Herbert 07 Jan '15

07 Jan '15

Kevin Paul Herbert (kph(a)meraki.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7924 -gerrit commit 66444b5ee2c28f7613c9895dacec314c42b6b95f Author: Kevin Paul Herbert <kph(a)meraki.net> Date: Wed Dec 24 20:49:42 2014 -0800 arm: Change MMIO function parameter order to match x86 x86 defines the I/O accessors write8/write16/write32 as writeN(addr, val) while ARM defined them as writeN(val, addr). Change ARM to be the same as x86. Change-Id: I26606e7487405fe1d6bb495573a3a7c0967acf64 Signed-off-by: Kevin Paul Herbert <kph(a)meraki.net> --- src/arch/arm/include/arch/io.h | 4 +- src/arch/arm/include/armv4/arch/arch_io.h | 6 +- src/arch/arm/include/armv7/arch/arch_io.h | 6 +- src/cpu/allwinner/a10/clock.c | 12 +-- src/cpu/allwinner/a10/gpio.c | 2 +- src/cpu/allwinner/a10/pinmux.c | 4 +- src/cpu/allwinner/a10/raminit.c | 28 +++---- src/cpu/allwinner/a10/timer.c | 6 +- src/cpu/allwinner/a10/twi.c | 14 ++-- src/cpu/allwinner/a10/uart.c | 12 +-- src/cpu/ti/am335x/uart.c | 52 ++++++------ src/mainboard/cubietech/cubieboard/bootblock.c | 14 ++-- src/soc/nvidia/tegra/apbmisc.c | 4 +- src/soc/nvidia/tegra/gpio.c | 4 +- src/soc/nvidia/tegra/i2c.c | 12 +-- src/soc/nvidia/tegra/pingroup.c | 2 +- src/soc/nvidia/tegra/pinmux.c | 2 +- src/soc/nvidia/tegra/usb.c | 64 ++++----------- src/soc/nvidia/tegra124/clock.c | 105 +++++++++---------------- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 92 +++++++++++----------- src/soc/nvidia/tegra124/power.c | 6 +- src/soc/nvidia/tegra124/spi.c | 23 +++--- src/soc/nvidia/tegra124/uart.c | 19 +++-- src/soc/qualcomm/ipq806x/clock.c | 29 +++---- src/soc/qualcomm/ipq806x/include/iomap.h | 2 +- src/soc/qualcomm/ipq806x/usb.c | 79 ++++++------------- src/soc/samsung/exynos5420/dmc_init_ddr3.c | 4 +- src/soc/samsung/exynos5420/dp_lowlevel.c | 2 +- src/soc/samsung/exynos5420/i2c.c | 12 +-- 29 files changed, 255 insertions(+), 366 deletions(-) diff --git a/src/arch/arm/include/arch/io.h b/src/arch/arm/include/arch/io.h index e537297..0320264 100644 --- a/src/arch/arm/include/arch/io.h +++ b/src/arch/arm/include/arch/io.h @@ -32,9 +32,9 @@ * re-factor all code to specify the data length intended. */ #define readb(a) read8(a) -#define writeb(v,a) write8(v,a) +#define writeb(v,a) write8(a,v) #define readl(a) read32(a) -#define writel(v,a) write32(v,a) +#define writel(v,a) write32(a,v) /* * Clear and set bits in one shot. These macros can be used to clear and diff --git a/src/arch/arm/include/armv4/arch/arch_io.h b/src/arch/arm/include/armv4/arch/arch_io.h index 72653da..cf5a9e1 100644 --- a/src/arch/arm/include/armv4/arch/arch_io.h +++ b/src/arch/arm/include/armv4/arch/arch_io.h @@ -40,17 +40,17 @@ static inline uint32_t read32(const void *addr) return *(volatile uint32_t *)addr; } -static inline void write8(uint8_t val, void *addr) +static inline void write8(void *addr, uint8_t val) { *(volatile uint8_t *)addr = val; } -static inline void write16(uint16_t val, void *addr) +static inline void write16(void *addr, uint16_t val) { *(volatile uint16_t *)addr = val; } -static inline void write32(uint32_t val, void *addr) +static inline void write32(void *addr, uint32_t val) { *(volatile uint32_t *)addr = val; } diff --git a/src/arch/arm/include/armv7/arch/arch_io.h b/src/arch/arm/include/armv7/arch/arch_io.h index 360fa64..53eafc6 100644 --- a/src/arch/arm/include/armv7/arch/arch_io.h +++ b/src/arch/arm/include/armv7/arch/arch_io.h @@ -44,21 +44,21 @@ static inline uint32_t read32(const void *addr) return *(volatile uint32_t *)addr; } -static inline void write8(uint8_t val, void *addr) +static inline void write8(void *addr, uint8_t val) { dmb(); *(volatile uint8_t *)addr = val; dmb(); } -static inline void write16(uint16_t val, void *addr) +static inline void write16(void *addr, uint16_t val) { dmb(); *(volatile uint16_t *)addr = val; dmb(); } -static inline void write32(uint32_t val, void *addr) +static inline void write32(void *addr, uint32_t val) { dmb(); *(volatile uint32_t *)addr = val; diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c index f189aea..c73566a 100644 --- a/src/cpu/allwinner/a10/clock.c +++ b/src/cpu/allwinner/a10/clock.c @@ -28,7 +28,7 @@ void a1x_periph_clock_enable(enum a1x_clken periph) addr = (void *)A1X_CCM_BASE + (periph >> 5); reg32 = read32(addr); reg32 |= 1 << (periph & 0x1f); - write32(reg32, addr); + write32(addr, reg32); } /** @@ -44,7 +44,7 @@ void a1x_periph_clock_disable(enum a1x_clken periph) addr = (void *)A1X_CCM_BASE + (periph >> 5); reg32 = read32(addr); reg32 &= ~(1 << (periph & 0x1f)); - write32(reg32, addr); + write32(addr, reg32); } /** @@ -88,7 +88,7 @@ void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p) reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) | PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p)); reg32 |= PLL5_PLL_ENABLE; - write32(reg32, &ccm->pll5_cfg); + write32(&ccm->pll5_cfg, reg32); } /** @@ -166,7 +166,7 @@ static void cpu_clk_src_switch(u32 clksel_bits) reg32 = read32(&ccm->cpu_ahb_apb0_cfg); reg32 &= ~CPU_CLK_SRC_MASK; reg32 |= clksel_bits & CPU_CLK_SRC_MASK; - write32(reg32, &ccm->cpu_ahb_apb0_cfg); + write32(&ccm->cpu_ahb_apb0_cfg, reg32); } static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp) @@ -179,7 +179,7 @@ static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp) reg32 |= ((axi - 1) << 0) & AXI_DIV_MASK; reg32 |= (ahb_exp << 4) & AHB_DIV_MASK; reg32 |= (apb0_exp << 8) & APB0_DIV_MASK; - write32(reg32, &ccm->cpu_ahb_apb0_cfg); + write32(&ccm->cpu_ahb_apb0_cfg, reg32); } static void spin_delay(u32 loops) @@ -262,7 +262,7 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz) change_sys_divisors(axi, ahb_exp, apb0_exp); /* Configure PLL1 at the desired frequency */ - write32(pll1_table[i].pll1_cfg, &ccm->pll1_cfg); + write32(&ccm->pll1_cfg, pll1_table[i].pll1_cfg); spin_delay(8); cpu_clk_src_switch(CPU_CLK_SRC_PLL1); diff --git a/src/cpu/allwinner/a10/gpio.c b/src/cpu/allwinner/a10/gpio.c index 5fca2d7..95854e5 100644 --- a/src/cpu/allwinner/a10/gpio.c +++ b/src/cpu/allwinner/a10/gpio.c @@ -76,7 +76,7 @@ void gpio_write(u8 port, u32 val) if ((port > GPS)) return; - write32(val, &gpio->port[port].dat); + write32(&gpio->port[port].dat, val); } /** diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c index de87440..f5ed19a 100644 --- a/src/cpu/allwinner/a10/pinmux.c +++ b/src/cpu/allwinner/a10/pinmux.c @@ -33,7 +33,7 @@ void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func) reg32 = read32(&gpio->port[port].cfg[reg]); reg32 &= ~(0xf << bit); reg32 |= (pad_func & 0xf) << bit; - write32(reg32, &gpio->port[port].cfg[reg]); + write32(&gpio->port[port].cfg[reg], reg32); } /** @@ -74,6 +74,6 @@ void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func) reg32 &= ~(0xf << bit); reg32 |= (pad_func & 0xf) << bit; } - write32(reg32, &gpio->port[port].cfg[reg]); + write32(&gpio->port[port].cfg[reg], reg32); } } diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c index de24e03..28fd408 100644 --- a/src/cpu/allwinner/a10/raminit.c +++ b/src/cpu/allwinner/a10/raminit.c @@ -118,7 +118,7 @@ static void mctl_configure_hostport(void) u32 i; for (i = 0; i < 32; i++) - write32(hpcr_value[i], &dram->hpcr[i]); + write32(&dram->hpcr[i], hpcr_value[i]); } static void mctl_setup_dram_clock(u32 clk) @@ -333,9 +333,9 @@ static void dramc_set_autorefresh_cycle(u32 clk) tmp_val = tmp_val * 9 - 200; reg32 |= tmp_val << 8; reg32 |= 0x8 << 24; - write32(reg32, &dram->drr); + write32(&dram->drr, reg32); } else { - write32(0x0, &dram->drr); + write32(&dram->drr, 0x0); } } @@ -360,7 +360,7 @@ unsigned long dramc_init(struct dram_para *para) a1x_gate_dram_clock_output(); /* select dram controller 1 */ - write32(DRAM_CSEL_MAGIC, &dram->csel); + write32(&dram->csel, DRAM_CSEL_MAGIC); mctl_itm_disable(); mctl_enable_dll0(para->tpr3); @@ -390,7 +390,7 @@ unsigned long dramc_init(struct dram_para *para) reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1); reg32 |= DRAM_DCR_CMD_RANK_ALL; reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE); - write32(reg32, &dram->dcr); + write32(&dram->dcr, reg32); /* dram clock on */ a1x_ungate_dram_clock_output(); @@ -405,21 +405,21 @@ unsigned long dramc_init(struct dram_para *para) reg32 = ((para->zq) >> 8) & 0xfffff; reg32 |= ((para->zq) & 0xff) << 20; reg32 |= (para->zq) & 0xf0000000; - write32(reg32, &dram->zqcr0); + write32(&dram->zqcr0, reg32); /* set I/O configure register */ reg32 = 0x00cc0000; reg32 |= (para->odt_en) & 0x3; reg32 |= ((para->odt_en) & 0x3) << 30; - write32(reg32, &dram->iocr); + write32(&dram->iocr, reg32); /* set refresh period */ dramc_set_autorefresh_cycle(para->clock); /* set timing parameters */ - write32(para->tpr0, &dram->tpr0); - write32(para->tpr1, &dram->tpr1); - write32(para->tpr2, &dram->tpr2); + write32(&dram->tpr0, para->tpr0); + write32(&dram->tpr1, para->tpr1); + write32(&dram->tpr2, para->tpr2); if (para->type == DRAM_MEMORY_TYPE_DDR3) { reg32 = DRAM_MR_BURST_LENGTH(0x0); @@ -430,11 +430,11 @@ unsigned long dramc_init(struct dram_para *para) reg32 |= DRAM_MR_CAS_LAT(para->cas); reg32 |= DRAM_MR_WRITE_RECOVERY(0x5); } - write32(reg32, &dram->mr); + write32(&dram->mr, reg32); - write32(para->emr1, &dram->emr); - write32(para->emr2, &dram->emr2); - write32(para->emr3, &dram->emr3); + write32(&dram->emr, para->emr1); + write32(&dram->emr2, para->emr2); + write32(&dram->emr3, para->emr3); /* set DQS window mode */ clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c index 7d5d141..5082114 100644 --- a/src/cpu/allwinner/a10/timer.c +++ b/src/cpu/allwinner/a10/timer.c @@ -24,13 +24,13 @@ void init_timer(void) { u32 reg32; /* Load the timer rollover value */ - write32(0xffffffff, &tmr0->interval); + write32(&tmr0->interval, 0xffffffff); /* Configure the timer to run from 24MHz oscillator, no prescaler */ reg32 = TIMER_CTRL_PRESC_DIV_EXP(0); reg32 |= TIMER_CTRL_CLK_SRC_OSC24M; reg32 |= TIMER_CTRL_RELOAD; reg32 |= TIMER_CTRL_TMR_EN; - write32(reg32, &tmr0->ctrl); + write32(&tmr0->ctrl, reg32); } void udelay(unsigned usec) @@ -61,6 +61,6 @@ void udelay(unsigned usec) */ u8 a1x_get_cpu_chip_revision(void) { - write32(0, &timer_module->cpu_cfg); + write32(&timer_module->cpu_cfg, 0); return (read32(&timer_module->cpu_cfg) >> 6) & 0x3; } diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c index d6a0127..2e516c6 100644 --- a/src/cpu/allwinner/a10/twi.c +++ b/src/cpu/allwinner/a10/twi.c @@ -42,7 +42,7 @@ static void configure_clock(struct a1x_twi *twi, u32 speed_hz) /* Pre-divide the clock by 8 */ n = 3; m = (apb_clk >> n) / speed_hz; - write32(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk); + write32(&twi->clk, TWI_CLK_M(m) | TWI_CLK_N(n)); } void a1x_twi_init(u8 bus, u32 speed_hz) @@ -53,9 +53,9 @@ void a1x_twi_init(u8 bus, u32 speed_hz) configure_clock(twi, speed_hz); /* Enable the I²C bus */ - write32(TWI_CTL_BUS_EN, &twi->ctl); + write32(&twi->ctl, TWI_CTL_BUS_EN); /* Issue soft reset */ - write32(1, &twi->reset); + write32(&twi->reset, 1); while (i-- && read32(&twi->reset)) udelay(1); @@ -63,12 +63,12 @@ void a1x_twi_init(u8 bus, u32 speed_hz) static void clear_interrupt_flag(struct a1x_twi *twi) { - write32(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl); + write32(&twi->ctl, read32(&twi->ctl) & ~TWI_CTL_INT_FLAG); } static void i2c_send_data(struct a1x_twi *twi, u8 data) { - write32(data, &twi->data); + write32(&twi->data, data); clear_interrupt_flag(twi); } @@ -90,7 +90,7 @@ static void i2c_send_start(struct a1x_twi *twi) reg32 = read32(&twi->ctl); reg32 &= ~TWI_CTL_INT_FLAG; reg32 |= TWI_CTL_M_START; - write32(reg32, &twi->ctl); + write32(&twi->ctl, reg32); /* M_START is automatically cleared after condition is transmitted */ i = TWI_TIMEOUT; @@ -106,7 +106,7 @@ static void i2c_send_stop(struct a1x_twi *twi) reg32 = read32(&twi->ctl); reg32 &= ~TWI_CTL_INT_FLAG; reg32 |= TWI_CTL_M_STOP; - write32(reg32, &twi->ctl); + write32(&twi->ctl, reg32); } static int i2c_read(unsigned bus, unsigned chip, unsigned addr, diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index 407bd86..3c02867 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -22,10 +22,10 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit div = (u16) uart_baudrate_divisor(baud_rate, uart_platform_refclk(), 16); /* Enable access to Divisor Latch register */ - write32(UART8250_LCR_DLAB, &uart->lcr); + write32(&uart->lcr, UART8250_LCR_DLAB); /* Set baudrate */ - write32((div >> 8) & 0xff, &uart->dlh); - write32(div & 0xff, &uart->dll); + write32(&uart->dlh, (div >> 8) & 0xff); + write32(&uart->dll, div & 0xff); /* Set line control */ reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK; switch (parity) { @@ -40,12 +40,12 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit default: break; } - write32(reg32, &uart->lcr); + write32(&uart->lcr, reg32); } static void a10_uart_enable_fifos(struct a10_uart *uart) { - write32(UART8250_FCR_FIFO_EN, &uart->fcr); + write32(&uart->fcr, UART8250_FCR_FIFO_EN); } static int tx_fifo_full(struct a10_uart *uart) @@ -83,7 +83,7 @@ static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data) { while (tx_fifo_full(uart)) ; - return write32(data, &uart->thr); + return write32(&uart->thr, data); } diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 5756834..4518ff8 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -42,88 +42,88 @@ static void am335x_uart_init(struct am335x_uart *uart, uint16_t div) uint16_t lcr_orig, efr_orig, mcr_orig; /* reset the UART */ - write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc); + write16(&uart->sysc, uart->sysc | SYSC_SOFTRESET); while (!(read16(&uart->syss) & SYSS_RESETDONE)) ; /* 1. switch to register config mode B */ lcr_orig = read16(&uart->lcr); - write16(0xbf, &uart->lcr); + write16(&uart->lcr, 0xbf); /* * 2. Set EFR ENHANCED_EN bit. To access this bit, registers must * be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1. */ efr_orig = read16(&uart->efr); - write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + write16(&uart->efr, efr_orig | EFR_ENHANCED_EN); /* 3. Switch to register config mode A */ - write16(0x80, &uart->lcr); + write16(&uart->lcr, 0x80); /* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */ mcr_orig = read16(&uart->mcr); - write16(mcr_orig | MCR_TCR_TLR, &uart->mcr); + write16(&uart->mcr, mcr_orig | MCR_TCR_TLR); /* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */ - write16(FCR_FIFO_EN, &uart->fcr); + write16(&uart->fcr, FCR_FIFO_EN); /* 6. Switch to configuration mode B */ - write16(0xbf, &uart->lcr); + write16(&uart->lcr, 0xbf); /* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */ /* 9. Restore original EFR value */ - write16(efr_orig, &uart->efr); + write16(&uart->efr, efr_orig); /* 10. Switch to config mode A */ - write16(0x80, &uart->lcr); + write16(&uart->lcr, 0x80); /* 11. Restore original MCR value */ - write16(mcr_orig, &uart->mcr); + write16(&uart->mcr, mcr_orig); /* 12. Restore original LCR value */ - write16(lcr_orig, &uart->lcr); + write16(&uart->lcr, lcr_orig); /* Protocol, baud rate and interrupt settings */ /* 1. Disable UART access to DLL and DLH registers */ - write16(read16(&uart->mdr1) | 0x7, &uart->mdr1); + write16(&uart->mdr1, read16(&uart->mdr1) | 0x7); /* 2. Switch to config mode B */ - write16(0xbf, &uart->lcr); + write16(&uart->lcr, 0xbf); /* 3. Enable access to IER[7:4] */ - write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + write16(&uart->efr, efr_orig | EFR_ENHANCED_EN); /* 4. Switch to operational mode */ - write16(0x0, &uart->lcr); + write16(&uart->lcr, 0x0); /* 5. Clear IER */ - write16(0x0, &uart->ier); + write16(&uart->ier, 0x0); /* 6. Switch to config mode B */ - write16(0xbf, &uart->lcr); + write16(&uart->lcr, 0xbf); /* 7. Set dll and dlh to the desired values (table 19-25) */ - write16((div >> 8), &uart->dlh); - write16((div & 0xff), &uart->dll); + write16(&uart->dlh, (div >> 8)); + write16(&uart->dll, (div & 0xff)); /* 8. Switch to operational mode to access ier */ - write16(0x0, &uart->lcr); + write16(&uart->lcr, 0x0); /* 9. Clear ier to disable all interrupts */ - write16(0x0, &uart->ier); + write16(&uart->ier, 0x0); /* 10. Switch to config mode B */ - write16(0xbf, &uart->lcr); + write16(&uart->lcr, 0xbf); /* 11. Restore efr */ - write16(efr_orig, &uart->efr); + write16(&uart->efr, efr_orig); /* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */ - write16(0x3, &uart->lcr); + write16(&uart->lcr, 0x3); /* 13. Load the new UART mode */ - write16(0x0, &uart->mdr1); + write16(&uart->mdr1, 0x0); } /* @@ -145,7 +145,7 @@ static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data) { while (!(read16(&uart->lsr) & LSR_TXFIFOE)); - return write8(data, &uart->thr); + return write8(&uart->thr, data); } unsigned int uart_platform_refclk(void) diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 360f914..e4a0313 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -38,12 +38,12 @@ static void cubieboard_set_sys_clock(void) struct a10_ccm *ccm = (void *)A1X_CCM_BASE; /* Switch CPU clock to main oscillator */ - write32(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg); + write32(&ccm->cpu_ahb_apb0_cfg, CPU_AHB_APB0_DEFAULT); /* Configure the PLL1. The value is the same one used by u-boot * P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz */ - write32(0xa1005000, &ccm->pll1_cfg); + write32(&ccm->pll1_cfg, 0xa1005000); /* FIXME: Delay to wait for PLL to lock */ u32 wait = 1000; @@ -53,7 +53,7 @@ static void cubieboard_set_sys_clock(void) reg32 = read32(&ccm->cpu_ahb_apb0_cfg); reg32 &= ~CPU_CLK_SRC_MASK; reg32 |= CPU_CLK_SRC_PLL1; - write32(reg32, &ccm->cpu_ahb_apb0_cfg); + write32(&ccm->cpu_ahb_apb0_cfg, reg32); } static void cubieboard_setup_clocks(void) @@ -62,12 +62,12 @@ static void cubieboard_setup_clocks(void) cubieboard_set_sys_clock(); /* Configure the clock source for APB1. This drives our UART */ - write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0), - &ccm->apb1_clk_div_cfg); + write32(&ccm->apb1_clk_div_cfg, + APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0)); /* Configure the clock for SD0 */ - write32(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) - | SDx_RAT_M(1), &ccm->sd0_clk_cfg); + write32(&ccm->sd0_clk_cfg, + SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1)); /* Enable clock to SD0 */ a1x_periph_clock_enable(A1X_CLKEN_MMC0); diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c index 5983d54..9034c97 100644 --- a/src/soc/nvidia/tegra/apbmisc.c +++ b/src/soc/nvidia/tegra/apbmisc.c @@ -26,10 +26,10 @@ static struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE; void enable_jtag(void) { - write32(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl); + write32(&misc->pp_config_ctl, PP_CONFIG_CTL_JTAG); } void clamp_tristate_inputs(void) { - write32(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global); + write32(&misc->pp_pinmux_global, PP_PINMUX_CLAMP_INPUTS); } diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index b10cded..833020d 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -98,8 +98,8 @@ static void gpio_write_port(int index, size_t offset, u32 mask, u32 value) u32 new_reg = (reg & ~mask) | (value & mask); if (new_reg != reg) { - write32(new_reg, (u8 *)&gpio_banks[bank] + offset + - port * sizeof(u32)); + write32((u8 *)&gpio_banks[bank] + offset + port * sizeof(u32), + new_reg); } } diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 26c2559..d563bf0 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -40,9 +40,9 @@ static void do_bus_clear(int bus) // 4. Set TERMINATE condition (1 = THRESHOLD) bc = read32(&regs->bus_clear_config); bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_THRESHOLD; - write32(bc, &regs->bus_clear_config); + write32(&regs->bus_clear_config, bc); // 4.1 Set MSTR_CONFIG_LOAD and wait for clear - write32(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load); + write32(&regs->config_load, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE); for (i = 0; i < timeout_ms * 10 && (read32(&regs->config_load) & I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE); i++) { printk(BIOS_DEBUG, "%s: wait for MSTR_CONFIG_LOAD to clear\n", @@ -50,7 +50,7 @@ static void do_bus_clear(int bus) udelay(100); } // 5. Set ENABLE to start the bus clear op - write32(bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE, &regs->bus_clear_config); + write32(&regs->bus_clear_config, bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE); for (i = 0; i < timeout_ms * 10 && (read32(&regs->bus_clear_config) & I2C_BUS_CLEAR_CONFIG_BC_ENABLE); i++) { printk(BIOS_DEBUG, "%s: wait for bus clear completion\n", @@ -74,7 +74,7 @@ static int tegra_i2c_send_recv(int bus, int read, rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT; while (header_words && tx_empty) { - write32(*headers++, &regs->tx_packet_fifo); + write32(&regs->tx_packet_fifo, *headers++); header_words--; tx_empty--; } @@ -96,7 +96,7 @@ static int tegra_i2c_send_recv(int bus, int read, int todo = MIN(data_len, sizeof(word)); memcpy(&word, data, todo); - write32(word, &regs->tx_packet_fifo); + write32(&regs->tx_packet_fifo, word); data_len -= todo; data += sizeof(word); tx_empty--; @@ -203,5 +203,5 @@ void i2c_init(unsigned bus) { struct tegra_i2c_regs * const regs = tegra_i2c_info[bus].base; - write32(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg); + write32(&regs->cnfg, I2C_CNFG_PACKET_MODE_EN); } diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c index 858cb44..332e05a 100644 --- a/src/soc/nvidia/tegra/pingroup.c +++ b/src/soc/nvidia/tegra/pingroup.c @@ -26,7 +26,7 @@ static uint32_t *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE; void pingroup_set_config(int group_index, uint32_t config) { - write32(config, &pingroup_regs[group_index]); + write32(&pingroup_regs[group_index], config); } uint32_t pingroup_get_config(int group_index) diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c index 6e4b3ff..f28b026 100644 --- a/src/soc/nvidia/tegra/pinmux.c +++ b/src/soc/nvidia/tegra/pinmux.c @@ -26,7 +26,7 @@ static uint32_t *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE; void pinmux_set_config(int pin_index, uint32_t config) { - write32(config, &pinmux_regs[pin_index]); + write32(&pinmux_regs[pin_index], config); } uint32_t pinmux_get_config(int pin_index) diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index e0455ed..9bd639e 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -35,61 +35,27 @@ void usb_setup_utmip(struct usb_ctlr *usb) udelay(1); /* Take stuff out of pwrdn and add some magic numbers from U-Boot */ - write32(0x8 << 25 | /* HS slew rate [10:4] */ - 0x3 << 22 | /* HS driver output 'SETUP' [6:4] */ - 0 << 21 | /* LS bias selection */ - 0 << 18 | /* PDZI pwrdn */ - 0 << 16 | /* PD2 pwrdn */ - 0 << 14 | /* PD pwrdn */ - 1 << 13 | /* (rst) HS receiver terminations */ - 0x1 << 10 | /* (rst) LS falling slew rate */ - 0x1 << 8 | /* (rst) LS rising slew rate */ - 0x4 << 0 | /* HS driver output 'SETUP' [3:0] */ - 0, &usb->utmip.xcvr0); - write32(0x7 << 18 | /* Termination range adjustment */ - 0 << 4 | /* PDDR pwrdn */ - 0 << 2 | /* PDCHRP pwrdn */ - 0 << 0 | /* PDDISC pwrdn */ - 0, &usb->utmip.xcvr1); - write32(1 << 19 | /* FS send initial J before sync(?) */ - 1 << 16 | /* (rst) Allow stuff error on SoP */ - 1 << 9 | /* (rst) Check disc only on EoP */ - 0, &usb->utmip.tx); - write32(0x2 << 30 | /* (rst) Keep pattern on active */ - 1 << 28 | /* (rst) Realign inertia on pkt */ - 0x1 << 24 | /* (rst) edges-1 to move sampling */ - 0x3 << 21 | /* (rst) squelch delay on EoP */ - 0x11 << 15 | /* cycles until IDLE */ - 0x10 << 10 | /* elastic input depth */ - 0, &usb->utmip.hsrx0); + write32(&usb->utmip.xcvr0, + 0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0); + write32(&usb->utmip.xcvr1, 0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0); + write32(&usb->utmip.tx, 1 << 19 | 1 << 16 | 1 << 9 | 0); + write32(&usb->utmip.hsrx0, + 0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0); /* U-Boot claims the USBD values for these are used across all UTMI+ * PHYs. That sounds so horribly wrong that I'm not going to implement * it, but keep it in mind if we're ever not using the USBD port. */ - write32(0x1 << 24 | /* HS disconnect detect level [2] */ - 1 << 23 | /* (rst) IDPD value */ - 1 << 22 | /* (rst) IDPD select */ - 1 << 11 | /* (rst) OTG pwrdn */ - 0 << 10 | /* bias pwrdn */ - 0x1 << 2 | /* HS disconnect detect level [1:0] */ - 0x2 << 0 | /* HS squelch detect level */ - 0, &usb->utmip.bias0); + write32(&usb->utmip.bias0, + 0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0); - write32(khz / 2200 << 3 | /* bias pwrdn cycles (20us?) */ - 1 << 2 | /* (rst) VBUS wakeup pwrdn */ - 0 << 0 | /* PDTRK pwrdn */ - 0, &usb->utmip.bias1); + write32(&usb->utmip.bias1, khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0); - write32(0xffff << 16 | /* (rst) */ - 25 * khz / 10 << 0 | /* TODO: what's this, really? */ - 0, &usb->utmip.debounce); + write32(&usb->utmip.debounce, 0xffff << 16 | 25 * khz / 10 << 0 | 0); udelay(1); setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ - write32(1 << 12 | /* UTMI+ enable */ - 0 << 11 | /* UTMI+ reset */ - 0, &usb->suspend_ctrl); + write32(&usb->suspend_ctrl, 1 << 12 | 0 << 11 | 0); } /* @@ -105,7 +71,7 @@ void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type) { int timeout = 1000; - write32(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */ + write32(&usb->ehci_usbcmd, 1 << 1); /* Host Controller Reset */ /* TODO: Resets are long, find way to parallelize... or just use XHCI */ while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1)) /* wait for HC to reset */; @@ -115,7 +81,7 @@ void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type) return; } - write32(3 << 0, &usb->usb_mode); /* Controller mode: HOST */ - write32(type << 29, &usb->lpm_ctrl); /* Parallel transceiver selct */ - write32(0x10 << 16, &usb->tx_fill_tuning); /* Tx FIFO Burst thresh */ + write32(&usb->usb_mode, 3 << 0); /* Controller mode: HOST */ + write32(&usb->lpm_ctrl, type << 29); /* Parallel transceiver selct */ + write32(&usb->tx_fill_tuning, 0x10 << 16); /* Tx FIFO Burst thresh */ } diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index af2f96a..48bf765 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -184,11 +184,11 @@ void clock_init_arm_generic_timer(void) __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); // Record the system timer frequency. - write32(freq, &sysctr->cntfid0); + write32(&sysctr->cntfid0, freq); // Enable the system counter. uint32_t cntcr = read32(&sysctr->cntcr); cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; - write32(cntcr, &sysctr->cntcr); + write32(&sysctr->cntcr, cntcr); } #define SOR0_CLK_SEL0 (1 << 14) @@ -241,25 +241,14 @@ static void init_utmip_pll(void) clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); - write32(80 << 16 | /* (rst) phy_divn */ - 1 << 8 | /* (rst) phy_divm */ - 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */ + write32(&clk_rst->utmip_pll_cfg0, 80 << 16 | 1 << 8 | 0); /* 960MHz * 1 / 80 == 12 MHz */ - write32(CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ - 0 << 16 | /* PLLU pwrdn */ - 0 << 14 | /* pll_enable pwrdn */ - 0 << 12 | /* pll_active pwrdn */ - CEIL_DIV(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */ - 0, &clk_rst->utmip_pll_cfg1); + write32(&clk_rst->utmip_pll_cfg1, + CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0); /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ - write32(0 << 24 | /* SAMP_D/XDEV pwrdn */ - CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ - CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ - 0 << 4 | /* SAMP_C/USB3 pwrdn */ - 0 << 2 | /* SAMP_B/XHOST pwrdn */ - 0 << 0 | /* SAMP_A/USBD pwrdn */ - 0, &clk_rst->utmip_pll_cfg2); + write32(&clk_rst->utmip_pll_cfg2, + 0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0); setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ } @@ -396,8 +385,8 @@ clock_display(u32 frequency) * been determined through trial and error (must lead to div 13 at 24MHz). */ void clock_early_uart(void) { - write32(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | - CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), &clk_rst->clk_src_uarta); + write32(&clk_rst->clk_src_uarta, + CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); udelay(2); clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); @@ -484,28 +473,24 @@ void clock_cpu0_config_and_reset(void *entry) { void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; - write32(CONFIG_STACK_TOP, &maincpu_stack_pointer); - write32((uintptr_t)entry, &maincpu_entry_point); - write32((uintptr_t)&maincpu_setup, evp_cpu_reset); + write32(&maincpu_stack_pointer, CONFIG_STACK_TOP); + write32(&maincpu_entry_point, (uintptr_t)entry); + write32(evp_cpu_reset, (uintptr_t)&maincpu_setup); /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); // Set up cclk_brst and divider. - write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | - (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | - (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | - (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | - (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28), - &clk_rst->cclk_brst_pol); - write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, - &clk_rst->super_cclk_div); + write32(&clk_rst->cclk_brst_pol, + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28)); + write32(&clk_rst->super_cclk_div, + CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB); // Enable the clocks for CPUs 0-3. uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; - write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); + write32(&clk_rst->clk_cpu_cmplx_clr, cpu_cmplx_clr); // Enable other CPU related clocks. setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); @@ -513,36 +498,23 @@ void clock_cpu0_config_and_reset(void *entry) setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); // Disable the reset on the non-CPU parts of the fast cluster. - write32(CRC_RST_CPUG_CLR_NONCPU, - &clk_rst->rst_cpug_cmplx_clr); + write32(&clk_rst->rst_cpug_cmplx_clr, CRC_RST_CPUG_CLR_NONCPU); // Disable the various resets on the CPUs. - write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | - CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | - CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | - CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | - CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | - CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | - CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | - CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | - CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, - &clk_rst->rst_cpug_cmplx_clr); + write32(&clk_rst->rst_cpug_cmplx_clr, + CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG); // Disable the reset on the non-CPU parts of the slow cluster. - write32(CRC_RST_CPULP_CLR_NONCPU, - &clk_rst->rst_cpulp_cmplx_clr); + write32(&clk_rst->rst_cpulp_cmplx_clr, CRC_RST_CPULP_CLR_NONCPU); // Disable the various resets on the LP CPU. - write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | - CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | - CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG, - &clk_rst->rst_cpulp_cmplx_clr); + write32(&clk_rst->rst_cpulp_cmplx_clr, + CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG); } void clock_halt_avp(void) { for (;;) { - write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | - FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT, - &flow->halt_cop_events); + write32(&flow->halt_cop_events, + FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); } } @@ -559,13 +531,12 @@ void clock_init(void) /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA * features section in the TRM). */ - write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT, - &clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */ - write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_CLKEN | PLL_OUT_RSTN, &clk_rst->pllc_out); - write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | - SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, - &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */ + write32(&clk_rst->clk_sys_rate, + 1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT); /* pclk = hclk = sclk/2 */ + write32(&clk_rst->pllc_out, + CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN); + write32(&clk_rst->sclk_brst_pol, + SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* sclk = 300 MHz */ /* Change the oscillator drive strength (from U-Boot -- why?) */ clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, @@ -583,16 +554,10 @@ void clock_init(void) clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ - write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT, - &clk_rst->pllp_outa); - write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT, - &clk_rst->pllp_outb); + write32(&clk_rst->pllp_outa, + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); + write32(&clk_rst->pllp_outb, + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); /* init pllx */ init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 0b519d6..6b22b80 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -274,17 +274,17 @@ inline static void write32(uint32_t val, void *addr) inline static void setbits32(uint32_t bits, void *addr) { - write32(read32(addr) | bits, addr); + write32(addr, read32(addr) | bits); } inline static void clrbits32(uint32_t bits, void *addr) { - write32(read32(addr) & ~bits, addr); + write32(addr, read32(addr) & ~bits); } static void __attribute__((noreturn)) reset(void) { - write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr); + write32(clk_rst_rst_devices_l_ptr, SWR_TRIG_SYS_RST); halt(); } @@ -329,7 +329,7 @@ static void config_oscillator(void) osc_ctrl &= ~OSC_XOFS_MASK; osc_ctrl |= (xofs << OSC_XOFS_SHIFT); osc_ctrl |= OSC_XOE; - write32(osc_ctrl, clk_rst_osc_ctrl_ptr); + write32(clk_rst_osc_ctrl_ptr, osc_ctrl); } static void config_pllu(void) @@ -374,17 +374,17 @@ static void config_pllu(void) // Configure PLLU. uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE | (divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT); - write32(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) | (lfcon << PLLU_LFCON_SHIFT); - write32(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); // Enable PLLU. base &= ~PLLU_BYPASS; base |= PLLU_ENABLE; - write32(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); misc |= PLLU_LOCK_ENABLE; - write32(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); } static void config_tsc(void) @@ -392,26 +392,26 @@ static void config_tsc(void) // Tell the TSC the oscillator frequency. switch (get_osc_freq()) { case OSC_FREQ_12: - write32(12000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 12000000); break; case OSC_FREQ_48: - write32(48000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 48000000); break; case OSC_FREQ_16P8: - write32(16800000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 16800000); break; case OSC_FREQ_19P2: - write32(19200000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 19200000); break; case OSC_FREQ_38P4: - write32(38400000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 38400000); break; case OSC_FREQ_26: - write32(26000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 26000000); break; default: // Default to 13MHz. - write32(13000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 13000000); break; } @@ -426,7 +426,7 @@ static void config_tsc(void) static void config_core_sight(void) { // Enable the CoreSight clock. - write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr); + write32(clk_rst_clk_out_enb_u_set_ptr, CLK_ENB_CSITE); /* * De-assert CoreSight reset. @@ -434,22 +434,22 @@ static void config_core_sight(void) * now. It will be restored to its original clock source * when the CPU-side restoration code runs. */ - write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr); + write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); } static void config_mselect(void) { // Set MSELECT clock source to PLLP with 1:4 divider. - write32((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0, - clk_rst_clk_src_mselect_ptr); + write32(clk_rst_clk_src_mselect_ptr, + (6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0); // Enable clock to MSELECT. - write32(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr); + write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_MSELECT); udelay(2); // Bring MSELECT out of reset. - write32(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr); + write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST); } @@ -459,19 +459,16 @@ static void config_mselect(void) static void clear_cpu_resets(void) { // Take the non-cpu of the G and LP clusters out of reset. - write32(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr); - write32(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpulp_cmplx_clr_ptr, CLR_NONCPURESET); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, CLR_NONCPURESET); // Clear software controlled reset of the slow cluster. - write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0, - clk_rst_rst_cpulp_cmplx_clr_ptr); + write32(clk_rst_rst_cpulp_cmplx_clr_ptr, + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0); // Clear software controlled reset of the fast cluster. - write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | - CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | - CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | - CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3, - clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); } @@ -483,7 +480,8 @@ static void power_on_partition(unsigned id) uint32_t bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { // Partition is not on. Turn it on. - write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr); + write32(pmc_ctlr_pwrgate_toggle_ptr, + id | PWRGATE_TOGGLE_START); // Wait until the partition is powerd on. while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) @@ -513,8 +511,8 @@ static void power_on_main_cpu(void) */ uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); - write32(orig_timer * (408000000 / 32768), - pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, + orig_timer * (408000000 / 32768)); if (wakeup_on_lp()) { power_on_partition(PARTID_C1NC); @@ -526,11 +524,11 @@ static void power_on_main_cpu(void) } // Give I/O signals time to stablize. - write32(20 | EVENT_MSEC | FLOW_MODE_STOP, - flow_ctlr_halt_cop_events_ptr); + write32(flow_ctlr_halt_cop_events_ptr, + 20 | EVENT_MSEC | FLOW_MODE_STOP); // Restore the original PMC_CPUPWRGOOD_TIMER. - write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); } @@ -552,17 +550,17 @@ void lp0_resume(void) flow_ctlr_cluster_control_ptr); // Program SUPER_CCLK_DIVIDER. - write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr); + write32(clk_rst_super_cclk_div_ptr, SUPER_CDIV_ENB); config_core_sight(); config_pllu(); // Set the CPU reset vector. - write32(get_wakeup_vector(), evp_cpu_reset_ptr); + write32(evp_cpu_reset_ptr, get_wakeup_vector()); // Select CPU complex clock source. - write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr); + write32(clk_rst_cclk_burst_policy_ptr, CCLK_PLLP_BURST_POLICY); config_mselect(); @@ -573,27 +571,27 @@ void lp0_resume(void) uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; - write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); + write32(clk_rst_cpu_softrst_ctrl2_ptr, ack_width); // Enable the CPU complex clock. - write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); - write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); + write32(clk_rst_clk_enb_l_set_ptr, CLK_ENB_CPU); + write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); clear_cpu_resets(); config_tsc(); // Disable VPR. - write32(0, mc_video_protect_size_mb_ptr); - write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, - mc_video_protect_reg_ctrl_ptr); + write32(mc_video_protect_size_mb_ptr, 0); + write32(mc_video_protect_reg_ctrl_ptr, + VIDEO_PROTECT_WRITE_ACCESS_DISABLE); power_on_main_cpu(); // Halt the AVP. while (1) - write32(FLOW_MODE_STOP | EVENT_JTAG, - flow_ctlr_halt_cop_events_ptr); + write32(flow_ctlr_halt_cop_events_ptr, + FLOW_MODE_STOP | EVENT_JTAG); } diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index 760d058..0054036 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -41,7 +41,7 @@ static void power_ungate_partition(uint32_t id) pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; - write32(pwrgate_toggle, &pmc->pwrgate_toggle); + write32(&pmc->pwrgate_toggle, pwrgate_toggle); // Wait for the request to be accepted. while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) @@ -67,14 +67,14 @@ void power_enable_cpu_rail(void) * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), * set it for 5ms as per SysEng (102MHz/5mS = 510000). */ - write32(510000, &pmc->cpupwrgood_timer); + write32(&pmc->cpupwrgood_timer, 510000); power_ungate_partition(POWER_PARTID_CRAIL); uint32_t cntrl = read32(&pmc->cntrl); cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY; cntrl |= PMC_CNTRL_CPUPWRREQ_OE; - write32(cntrl, &pmc->cntrl); + write32(&pmc->cntrl, cntrl); } void power_ungate_cpu(void) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 8e090aa..4eca16f 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -231,7 +231,7 @@ int spi_claim_bus(struct spi_slave *slave) else val |= SPI_CMD1_CS_SW_VAL; - write32(val, &regs->command1); + write32(&regs->command1, val); return 0; } @@ -247,7 +247,7 @@ void spi_release_bus(struct spi_slave *slave) else val &= ~SPI_CMD1_CS_SW_VAL; - write32(val, &regs->command1); + write32(&regs->command1, val); } static void dump_fifo_status(struct tegra_spi_channel *spi) @@ -384,12 +384,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and * PIO transfers */ - write32(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); if (dir == SPI_SEND) { unsigned int to_fifo = bytes; while (to_fifo) { - write32(*p, &spi->regs->tx_fifo); + write32(&spi->regs->tx_fifo, *p); p++; to_fifo--; } @@ -496,11 +496,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* ensure bytes to send will be visible to DMA controller */ dcache_clean_by_mva(spi->out_buf, bytes); - write32((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr); - write32((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr); + write32(&spi->dma_out->regs->apb_ptr, + (u32)&spi->regs->tx_fifo); + write32(&spi->dma_out->regs->ahb_ptr, (u32)spi->out_buf); setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); - write32(wcount, &spi->dma_out->regs->wcount); + write32(&spi->dma_out->regs->wcount, wcount); } else { spi->dma_in = dma_claim(); if (!spi->dma_in) @@ -509,15 +510,15 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* avoid data collisions */ dcache_clean_invalidate_by_mva(spi->in_buf, bytes); - write32((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr); - write32((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr); + write32(&spi->dma_in->regs->apb_ptr, (u32)&spi->regs->rx_fifo); + write32(&spi->dma_in->regs->ahb_ptr, (u32)spi->in_buf); clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); - write32(wcount, &spi->dma_in->regs->wcount); + write32(&spi->dma_in->regs->wcount, wcount); } /* BLOCK_SIZE starts at n-1 */ - write32(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); return todo; } diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index fd8074d..726278e 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -56,20 +56,19 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr) tegra124_uart_tx_flush(uart_ptr); // Disable interrupts. - write8(0, &uart_ptr->ier); + write8(&uart_ptr->ier, 0); // Force DTR and RTS to high. - write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr); + write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); // Set line configuration, access divisor latches. - write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); // Set the divisor. - write8(divisor & 0xff, &uart_ptr->dll); - write8((divisor >> 8) & 0xff, &uart_ptr->dlm); + write8(&uart_ptr->dll, divisor & 0xff); + write8(&uart_ptr->dlm, (divisor >> 8) & 0xff); // Hide the divisor latches. - write8(line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, line_config); // Enable FIFOs, and clear receive and transmit. - write8(UART8250_FCR_FIFO_EN | - UART8250_FCR_CLEAR_RCVR | - UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr); + write8(&uart_ptr->fcr, + UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); } static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr) @@ -82,7 +81,7 @@ static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr) static void tegra124_uart_tx_byte(struct tegra124_uart *uart_ptr, unsigned char data) { while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)); - write8(data, &uart_ptr->thr); + write8(&uart_ptr->thr, data); } static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr) diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 88056d4..9020fa4 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -125,22 +125,17 @@ void nand_clock_config(void) void usb_clock_config(void) { /* Magic clock initialization numbers, nobody knows how they work... */ - write32(0x10, USB30_MASTER_CLK_CTL_REG); - write32(0x10, USB30_1_MASTER_CLK_CTL_REG); - write32(0x500DF, USB30_MASTER_CLK_MD); - write32(0xE40942, USB30_MASTER_CLK_NS); - write32(0x100D7, USB30_MOC_UTMI_CLK_MD); - write32(0xD80942, USB30_MOC_UTMI_CLK_NS); - write32(0x10, USB30_MOC_UTMI_CLK_CTL); - write32(0x10, USB30_1_MOC_UTMI_CLK_CTL); - - write32(1 << 5 | /* assert port2 HS PHY async reset */ - 1 << 4 | /* assert master async reset */ - 1 << 3 | /* assert sleep async reset */ - 1 << 2 | /* assert MOC UTMI async reset */ - 1 << 1 | /* assert power-on async reset */ - 1 << 0 | /* assert PHY async reset */ - 0, USB30_RESET); + write32(USB30_MASTER_CLK_CTL_REG, 0x10); + write32(USB30_1_MASTER_CLK_CTL_REG, 0x10); + write32(USB30_MASTER_CLK_MD, 0x500DF); + write32(USB30_MASTER_CLK_NS, 0xE40942); + write32(USB30_MOC_UTMI_CLK_MD, 0x100D7); + write32(USB30_MOC_UTMI_CLK_NS, 0xD80942); + write32(USB30_MOC_UTMI_CLK_CTL, 0x10); + write32(USB30_1_MOC_UTMI_CLK_CTL, 0x10); + + write32(USB30_RESET, + 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0 | 0); udelay(5); - write32(0, USB30_RESET); /* deassert all USB resets again */ + write32(USB30_RESET, 0); /* deassert all USB resets again */ } diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h index 69744bc..8fe775e 100644 --- a/src/soc/qualcomm/ipq806x/include/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/iomap.h @@ -45,7 +45,7 @@ included to do this in one place for all occurrences in vendor code */ #define readl_i(a) read32((const void *)(a)) -#define writel_i(v,a) write32(v,(void *)a) +#define writel_i(v,a) write32((void *)a,v) #define clrsetbits_le32_i(addr, clear, set) \ clrsetbits_le32(((void *)(addr)), (clear), (set)) diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index a9214be..9ae29b3 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -102,33 +102,16 @@ static struct usb_dwc3 * const usb_host2_dwc3 = (void *)USB_HOST2_DWC3_BASE; static void setup_dwc3(struct usb_dwc3 *dwc3) { - write32(0x1 << 31 | /* assert PHY soft reset */ - 0x1 << 25 | /* (default) U1/U2 exit fail -> recovery? */ - 0x1 << 24 | /* (default) activate PHY low power states */ - 0x1 << 19 | /* (default) PHY low power delay value */ - 0x1 << 18 | /* (default) activate PHY low power delay */ - 0x1 << 1 | /* (default) Tx deemphasis value */ - 0x1 << 0 | /* (default) elastic buffer mode */ - 0, &dwc3->usb3pipectl); - - write32(0x1 << 31 | /* assert PHY soft reset */ - 0x9 << 10 | /* (default) PHY clock turnaround 8-bit UTMI+ */ - 0x1 << 8 | /* (default) enable PHY sleep in L1 */ - 0x1 << 6 | /* (default) enable PHY suspend */ - 0, &dwc3->usb2phycfg); - - write32(0x2 << 19 | /* (default) suspend clock scaling */ - 0x1 << 16 | /* retry SS three times before HS downgrade */ - 0x1 << 12 | /* port capability HOST */ - 0x1 << 11 | /* assert core soft reset */ - 0x1 << 10 | /* (default) sync ITP to refclk */ - 0x1 << 2 | /* U2 exit after 8us LFPS (instead of 248ns) */ - 0, &dwc3->ctl); - - write32(0x32 << 22 | /* (default) reference clock period in ns */ - 0x1 << 15 | /* (default) XHCI compliant device addressing */ - 0x10 << 0 | /* (default) devices time out after 32us */ - 0, &dwc3->uctl); + write32(&dwc3->usb3pipectl, + 0x1 << 31 | 0x1 << 25 | 0x1 << 24 | 0x1 << 19 | 0x1 << 18 | 0x1 << 1 | 0x1 << 0 | 0); + + write32(&dwc3->usb2phycfg, + 0x1 << 31 | 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0); + + write32(&dwc3->ctl, + 0x2 << 19 | 0x1 << 16 | 0x1 << 12 | 0x1 << 11 | 0x1 << 10 | 0x1 << 2 | 0); + + write32(&dwc3->uctl, 0x32 << 22 | 0x1 << 15 | 0x10 << 0 | 0); udelay(5); @@ -139,34 +122,16 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) static void setup_phy(struct usb_qc_phy *phy) { - write32(0x1 << 24 | /* Indicate VBUS power present */ - 0x1 << 8 | /* Enable USB3 ref clock to prescaler */ - 0x1 << 7 | /* assert SS PHY reset */ - 0x19 << 0 | /* (default) reference clock multiplier */ - 0, &phy->ss_phy_ctrl); - - write32(0x1 << 26 | /* (default) unclamp DPSE/DMSE VLS */ - 0x1 << 25 | /* (default) select freeclk for utmi_clk */ - 0x1 << 24 | /* (default) unclamp DMSE VLS */ - 0x1 << 21 | /* (default) enable UTMI clock */ - 0x1 << 20 | /* set OTG VBUS as valid */ - 0x1 << 18 | /* use ref clock from core */ - 0x1 << 17 | /* (default) unclamp DPSE VLS */ - 0x1 << 11 | /* force xo/bias/pll to stay on in suspend */ - 0x1 << 9 | /* (default) unclamp IDHV */ - 0x1 << 8 | /* (default) unclamp VLS (again???) */ - 0x1 << 7 | /* (default) unclamp HV VLS */ - 0x7 << 4 | /* select frequency (no idea which one) */ - 0x1 << 1 | /* (default) "retention enable" */ - 0, &phy->hs_phy_ctrl); - - write32(0x6e << 20 | /* full TX swing amplitude */ - 0x20 << 14 | /* (default) 6dB TX deemphasis */ - 0x17 << 8 | /* 3.5dB TX deemphasis */ - 0x9 << 3 | /* (default) LoS detector level */ - 0, &phy->ss_phy_param1); - - write32(0x1 << 2, &phy->general_cfg); /* set XHCI 1.00 compliance */ + write32(&phy->ss_phy_ctrl, + 0x1 << 24 | 0x1 << 8 | 0x1 << 7 | 0x19 << 0 | 0); + + write32(&phy->hs_phy_ctrl, + 0x1 << 26 | 0x1 << 25 | 0x1 << 24 | 0x1 << 21 | 0x1 << 20 | 0x1 << 18 | 0x1 << 17 | 0x1 << 11 | 0x1 << 9 | 0x1 << 8 | 0x1 << 7 | 0x7 << 4 | 0x1 << 1 | 0); + + write32(&phy->ss_phy_param1, + 0x6e << 20 | 0x20 << 14 | 0x17 << 8 | 0x9 << 3 | 0); + + write32(&phy->general_cfg, 0x1 << 2); /* set XHCI 1.00 compliance */ udelay(5); clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */ @@ -177,9 +142,9 @@ static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data) int usec = 100; if (capture_reg) - write32(data, capture_reg); + write32(capture_reg, data); - write32(0x1 << 0, acknowledge_bit); + write32(acknowledge_bit, 0x1 << 0); while (read32(acknowledge_bit) && --usec) udelay(1); diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 28603ae..ae0553a 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -189,8 +189,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) * release pad retention and retain the memory content until the * initialization is complete. */ - write32(PAD_RETENTION_DRAM_COREBLK_VAL, - &exynos_power->padret_dram_cblk_opt); + write32(&exynos_power->padret_dram_cblk_opt, + PAD_RETENTION_DRAM_COREBLK_VAL); do { ret = read32(&exynos_power->padret_dram_status); } while (ret != 0x1); diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index e8892cd..73daebf 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -56,7 +56,7 @@ static inline unsigned long fradl(void *v) { #define lread32(a) fradl((void *)(a)) #else -#define lwrite32(a,b) write32((unsigned long)(a), (void *)(b)) +#define lwrite32(a,b) write32((void *)(b), (unsigned long)(a)) #define lread32(a) read32((void *)(a)) #endif diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 49875d7..0dc1834 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -433,7 +433,7 @@ static int hsi2c_senddata(struct hsi2c_regs *regs, const uint8_t *data, int len) { while (!hsi2c_check_transfer(regs) && len) { if (!(read32(&regs->usi_fifo_stat) & Hsi2cTxFifoFull)) { - write32(*data++, &regs->usi_txdata); + write32(&regs->usi_txdata, *data++); len--; } } @@ -455,7 +455,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) { const uint32_t usi_ctl = Hsi2cFuncModeI2c | Hsi2cMaster; - write32(HSI2C_SLV_ADDR_MAS(seg->chip), &regs->i2c_addr); + write32(&regs->i2c_addr, HSI2C_SLV_ADDR_MAS(seg->chip)); /* * We really only want to stop after this transaction (I think) if the @@ -468,14 +468,14 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) seg->len | Hsi2cMasterRun | Hsi2cStopAfterTrans; if (seg->read) { - write32(usi_ctl | Hsi2cRxchon, &regs->usi_ctl); - write32(autoconf | Hsi2cReadWrite, &regs->i2c_auto_conf); + write32(&regs->usi_ctl, usi_ctl | Hsi2cRxchon); + write32(&regs->i2c_auto_conf, autoconf | Hsi2cReadWrite); if (hsi2c_recvdata(regs, seg->buf, seg->len)) return -1; } else { - write32(usi_ctl | Hsi2cTxchon, &regs->usi_ctl); - write32(autoconf, &regs->i2c_auto_conf); + write32(&regs->usi_ctl, usi_ctl | Hsi2cTxchon); + write32(&regs->i2c_auto_conf, autoconf); if (hsi2c_senddata(regs, seg->buf, seg->len)) return -1;

1 0

Patch set updated for coreboot: 05d7d40 arm: Change MMIO function parameter order to match x86
by Kevin Paul Herbert 07 Jan '15

07 Jan '15

Kevin Paul Herbert (kph(a)meraki.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7924 -gerrit commit 05d7d40e09000ea6692d85caa92ff502f9842cf2 Author: Kevin Paul Herbert <kph(a)meraki.net> Date: Wed Dec 24 20:49:42 2014 -0800 arm: Change MMIO function parameter order to match x86 x86 defines the I/O accessors write8/write16/write32 as writeN(addr, val) while ARM defined them as writeN(val, addr). Change ARM to be the same as x86. Change-Id: I26606e7487405fe1d6bb495573a3a7c0967acf64 Signed-off-by: Kevin Paul Herbert <kph(a)meraki.net> --- src/arch/arm/include/arch/io.h | 4 +- src/arch/arm/include/armv4/arch/arch_io.h | 6 +- src/arch/arm/include/armv7/arch/arch_io.h | 6 +- src/cpu/allwinner/a10/clock.c | 12 +-- src/cpu/allwinner/a10/gpio.c | 2 +- src/cpu/allwinner/a10/pinmux.c | 4 +- src/cpu/allwinner/a10/raminit.c | 28 +++---- src/cpu/allwinner/a10/timer.c | 6 +- src/cpu/allwinner/a10/twi.c | 14 ++-- src/cpu/allwinner/a10/uart.c | 12 +-- src/cpu/ti/am335x/uart.c | 52 ++++++------ src/mainboard/cubietech/cubieboard/bootblock.c | 14 ++-- src/soc/nvidia/tegra/apbmisc.c | 4 +- src/soc/nvidia/tegra/gpio.c | 4 +- src/soc/nvidia/tegra/i2c.c | 6 +- src/soc/nvidia/tegra/pingroup.c | 2 +- src/soc/nvidia/tegra/pinmux.c | 2 +- src/soc/nvidia/tegra/usb.c | 64 ++++----------- src/soc/nvidia/tegra124/clock.c | 105 +++++++++---------------- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 92 +++++++++++----------- src/soc/nvidia/tegra124/power.c | 6 +- src/soc/nvidia/tegra124/spi.c | 23 +++--- src/soc/nvidia/tegra124/uart.c | 19 +++-- src/soc/samsung/exynos5420/dmc_init_ddr3.c | 4 +- src/soc/samsung/exynos5420/dp_lowlevel.c | 2 +- src/soc/samsung/exynos5420/i2c.c | 12 +-- 26 files changed, 217 insertions(+), 288 deletions(-) diff --git a/src/arch/arm/include/arch/io.h b/src/arch/arm/include/arch/io.h index e537297..0320264 100644 --- a/src/arch/arm/include/arch/io.h +++ b/src/arch/arm/include/arch/io.h @@ -32,9 +32,9 @@ * re-factor all code to specify the data length intended. */ #define readb(a) read8(a) -#define writeb(v,a) write8(v,a) +#define writeb(v,a) write8(a,v) #define readl(a) read32(a) -#define writel(v,a) write32(v,a) +#define writel(v,a) write32(a,v) /* * Clear and set bits in one shot. These macros can be used to clear and diff --git a/src/arch/arm/include/armv4/arch/arch_io.h b/src/arch/arm/include/armv4/arch/arch_io.h index 72653da..cf5a9e1 100644 --- a/src/arch/arm/include/armv4/arch/arch_io.h +++ b/src/arch/arm/include/armv4/arch/arch_io.h @@ -40,17 +40,17 @@ static inline uint32_t read32(const void *addr) return *(volatile uint32_t *)addr; } -static inline void write8(uint8_t val, void *addr) +static inline void write8(void *addr, uint8_t val) { *(volatile uint8_t *)addr = val; } -static inline void write16(uint16_t val, void *addr) +static inline void write16(void *addr, uint16_t val) { *(volatile uint16_t *)addr = val; } -static inline void write32(uint32_t val, void *addr) +static inline void write32(void *addr, uint32_t val) { *(volatile uint32_t *)addr = val; } diff --git a/src/arch/arm/include/armv7/arch/arch_io.h b/src/arch/arm/include/armv7/arch/arch_io.h index 360fa64..53eafc6 100644 --- a/src/arch/arm/include/armv7/arch/arch_io.h +++ b/src/arch/arm/include/armv7/arch/arch_io.h @@ -44,21 +44,21 @@ static inline uint32_t read32(const void *addr) return *(volatile uint32_t *)addr; } -static inline void write8(uint8_t val, void *addr) +static inline void write8(void *addr, uint8_t val) { dmb(); *(volatile uint8_t *)addr = val; dmb(); } -static inline void write16(uint16_t val, void *addr) +static inline void write16(void *addr, uint16_t val) { dmb(); *(volatile uint16_t *)addr = val; dmb(); } -static inline void write32(uint32_t val, void *addr) +static inline void write32(void *addr, uint32_t val) { dmb(); *(volatile uint32_t *)addr = val; diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c index f189aea..c73566a 100644 --- a/src/cpu/allwinner/a10/clock.c +++ b/src/cpu/allwinner/a10/clock.c @@ -28,7 +28,7 @@ void a1x_periph_clock_enable(enum a1x_clken periph) addr = (void *)A1X_CCM_BASE + (periph >> 5); reg32 = read32(addr); reg32 |= 1 << (periph & 0x1f); - write32(reg32, addr); + write32(addr, reg32); } /** @@ -44,7 +44,7 @@ void a1x_periph_clock_disable(enum a1x_clken periph) addr = (void *)A1X_CCM_BASE + (periph >> 5); reg32 = read32(addr); reg32 &= ~(1 << (periph & 0x1f)); - write32(reg32, addr); + write32(addr, reg32); } /** @@ -88,7 +88,7 @@ void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p) reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) | PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p)); reg32 |= PLL5_PLL_ENABLE; - write32(reg32, &ccm->pll5_cfg); + write32(&ccm->pll5_cfg, reg32); } /** @@ -166,7 +166,7 @@ static void cpu_clk_src_switch(u32 clksel_bits) reg32 = read32(&ccm->cpu_ahb_apb0_cfg); reg32 &= ~CPU_CLK_SRC_MASK; reg32 |= clksel_bits & CPU_CLK_SRC_MASK; - write32(reg32, &ccm->cpu_ahb_apb0_cfg); + write32(&ccm->cpu_ahb_apb0_cfg, reg32); } static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp) @@ -179,7 +179,7 @@ static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp) reg32 |= ((axi - 1) << 0) & AXI_DIV_MASK; reg32 |= (ahb_exp << 4) & AHB_DIV_MASK; reg32 |= (apb0_exp << 8) & APB0_DIV_MASK; - write32(reg32, &ccm->cpu_ahb_apb0_cfg); + write32(&ccm->cpu_ahb_apb0_cfg, reg32); } static void spin_delay(u32 loops) @@ -262,7 +262,7 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz) change_sys_divisors(axi, ahb_exp, apb0_exp); /* Configure PLL1 at the desired frequency */ - write32(pll1_table[i].pll1_cfg, &ccm->pll1_cfg); + write32(&ccm->pll1_cfg, pll1_table[i].pll1_cfg); spin_delay(8); cpu_clk_src_switch(CPU_CLK_SRC_PLL1); diff --git a/src/cpu/allwinner/a10/gpio.c b/src/cpu/allwinner/a10/gpio.c index 5fca2d7..95854e5 100644 --- a/src/cpu/allwinner/a10/gpio.c +++ b/src/cpu/allwinner/a10/gpio.c @@ -76,7 +76,7 @@ void gpio_write(u8 port, u32 val) if ((port > GPS)) return; - write32(val, &gpio->port[port].dat); + write32(&gpio->port[port].dat, val); } /** diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c index de87440..f5ed19a 100644 --- a/src/cpu/allwinner/a10/pinmux.c +++ b/src/cpu/allwinner/a10/pinmux.c @@ -33,7 +33,7 @@ void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func) reg32 = read32(&gpio->port[port].cfg[reg]); reg32 &= ~(0xf << bit); reg32 |= (pad_func & 0xf) << bit; - write32(reg32, &gpio->port[port].cfg[reg]); + write32(&gpio->port[port].cfg[reg], reg32); } /** @@ -74,6 +74,6 @@ void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func) reg32 &= ~(0xf << bit); reg32 |= (pad_func & 0xf) << bit; } - write32(reg32, &gpio->port[port].cfg[reg]); + write32(&gpio->port[port].cfg[reg], reg32); } } diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c index de24e03..28fd408 100644 --- a/src/cpu/allwinner/a10/raminit.c +++ b/src/cpu/allwinner/a10/raminit.c @@ -118,7 +118,7 @@ static void mctl_configure_hostport(void) u32 i; for (i = 0; i < 32; i++) - write32(hpcr_value[i], &dram->hpcr[i]); + write32(&dram->hpcr[i], hpcr_value[i]); } static void mctl_setup_dram_clock(u32 clk) @@ -333,9 +333,9 @@ static void dramc_set_autorefresh_cycle(u32 clk) tmp_val = tmp_val * 9 - 200; reg32 |= tmp_val << 8; reg32 |= 0x8 << 24; - write32(reg32, &dram->drr); + write32(&dram->drr, reg32); } else { - write32(0x0, &dram->drr); + write32(&dram->drr, 0x0); } } @@ -360,7 +360,7 @@ unsigned long dramc_init(struct dram_para *para) a1x_gate_dram_clock_output(); /* select dram controller 1 */ - write32(DRAM_CSEL_MAGIC, &dram->csel); + write32(&dram->csel, DRAM_CSEL_MAGIC); mctl_itm_disable(); mctl_enable_dll0(para->tpr3); @@ -390,7 +390,7 @@ unsigned long dramc_init(struct dram_para *para) reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1); reg32 |= DRAM_DCR_CMD_RANK_ALL; reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE); - write32(reg32, &dram->dcr); + write32(&dram->dcr, reg32); /* dram clock on */ a1x_ungate_dram_clock_output(); @@ -405,21 +405,21 @@ unsigned long dramc_init(struct dram_para *para) reg32 = ((para->zq) >> 8) & 0xfffff; reg32 |= ((para->zq) & 0xff) << 20; reg32 |= (para->zq) & 0xf0000000; - write32(reg32, &dram->zqcr0); + write32(&dram->zqcr0, reg32); /* set I/O configure register */ reg32 = 0x00cc0000; reg32 |= (para->odt_en) & 0x3; reg32 |= ((para->odt_en) & 0x3) << 30; - write32(reg32, &dram->iocr); + write32(&dram->iocr, reg32); /* set refresh period */ dramc_set_autorefresh_cycle(para->clock); /* set timing parameters */ - write32(para->tpr0, &dram->tpr0); - write32(para->tpr1, &dram->tpr1); - write32(para->tpr2, &dram->tpr2); + write32(&dram->tpr0, para->tpr0); + write32(&dram->tpr1, para->tpr1); + write32(&dram->tpr2, para->tpr2); if (para->type == DRAM_MEMORY_TYPE_DDR3) { reg32 = DRAM_MR_BURST_LENGTH(0x0); @@ -430,11 +430,11 @@ unsigned long dramc_init(struct dram_para *para) reg32 |= DRAM_MR_CAS_LAT(para->cas); reg32 |= DRAM_MR_WRITE_RECOVERY(0x5); } - write32(reg32, &dram->mr); + write32(&dram->mr, reg32); - write32(para->emr1, &dram->emr); - write32(para->emr2, &dram->emr2); - write32(para->emr3, &dram->emr3); + write32(&dram->emr, para->emr1); + write32(&dram->emr2, para->emr2); + write32(&dram->emr3, para->emr3); /* set DQS window mode */ clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE); diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c index 7d5d141..5082114 100644 --- a/src/cpu/allwinner/a10/timer.c +++ b/src/cpu/allwinner/a10/timer.c @@ -24,13 +24,13 @@ void init_timer(void) { u32 reg32; /* Load the timer rollover value */ - write32(0xffffffff, &tmr0->interval); + write32(&tmr0->interval, 0xffffffff); /* Configure the timer to run from 24MHz oscillator, no prescaler */ reg32 = TIMER_CTRL_PRESC_DIV_EXP(0); reg32 |= TIMER_CTRL_CLK_SRC_OSC24M; reg32 |= TIMER_CTRL_RELOAD; reg32 |= TIMER_CTRL_TMR_EN; - write32(reg32, &tmr0->ctrl); + write32(&tmr0->ctrl, reg32); } void udelay(unsigned usec) @@ -61,6 +61,6 @@ void udelay(unsigned usec) */ u8 a1x_get_cpu_chip_revision(void) { - write32(0, &timer_module->cpu_cfg); + write32(&timer_module->cpu_cfg, 0); return (read32(&timer_module->cpu_cfg) >> 6) & 0x3; } diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c index d6a0127..2e516c6 100644 --- a/src/cpu/allwinner/a10/twi.c +++ b/src/cpu/allwinner/a10/twi.c @@ -42,7 +42,7 @@ static void configure_clock(struct a1x_twi *twi, u32 speed_hz) /* Pre-divide the clock by 8 */ n = 3; m = (apb_clk >> n) / speed_hz; - write32(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk); + write32(&twi->clk, TWI_CLK_M(m) | TWI_CLK_N(n)); } void a1x_twi_init(u8 bus, u32 speed_hz) @@ -53,9 +53,9 @@ void a1x_twi_init(u8 bus, u32 speed_hz) configure_clock(twi, speed_hz); /* Enable the I²C bus */ - write32(TWI_CTL_BUS_EN, &twi->ctl); + write32(&twi->ctl, TWI_CTL_BUS_EN); /* Issue soft reset */ - write32(1, &twi->reset); + write32(&twi->reset, 1); while (i-- && read32(&twi->reset)) udelay(1); @@ -63,12 +63,12 @@ void a1x_twi_init(u8 bus, u32 speed_hz) static void clear_interrupt_flag(struct a1x_twi *twi) { - write32(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl); + write32(&twi->ctl, read32(&twi->ctl) & ~TWI_CTL_INT_FLAG); } static void i2c_send_data(struct a1x_twi *twi, u8 data) { - write32(data, &twi->data); + write32(&twi->data, data); clear_interrupt_flag(twi); } @@ -90,7 +90,7 @@ static void i2c_send_start(struct a1x_twi *twi) reg32 = read32(&twi->ctl); reg32 &= ~TWI_CTL_INT_FLAG; reg32 |= TWI_CTL_M_START; - write32(reg32, &twi->ctl); + write32(&twi->ctl, reg32); /* M_START is automatically cleared after condition is transmitted */ i = TWI_TIMEOUT; @@ -106,7 +106,7 @@ static void i2c_send_stop(struct a1x_twi *twi) reg32 = read32(&twi->ctl); reg32 &= ~TWI_CTL_INT_FLAG; reg32 |= TWI_CTL_M_STOP; - write32(reg32, &twi->ctl); + write32(&twi->ctl, reg32); } static int i2c_read(unsigned bus, unsigned chip, unsigned addr, diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index 407bd86..3c02867 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -22,10 +22,10 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit div = (u16) uart_baudrate_divisor(baud_rate, uart_platform_refclk(), 16); /* Enable access to Divisor Latch register */ - write32(UART8250_LCR_DLAB, &uart->lcr); + write32(&uart->lcr, UART8250_LCR_DLAB); /* Set baudrate */ - write32((div >> 8) & 0xff, &uart->dlh); - write32(div & 0xff, &uart->dll); + write32(&uart->dlh, (div >> 8) & 0xff); + write32(&uart->dll, div & 0xff); /* Set line control */ reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK; switch (parity) { @@ -40,12 +40,12 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit default: break; } - write32(reg32, &uart->lcr); + write32(&uart->lcr, reg32); } static void a10_uart_enable_fifos(struct a10_uart *uart) { - write32(UART8250_FCR_FIFO_EN, &uart->fcr); + write32(&uart->fcr, UART8250_FCR_FIFO_EN); } static int tx_fifo_full(struct a10_uart *uart) @@ -83,7 +83,7 @@ static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data) { while (tx_fifo_full(uart)) ; - return write32(data, &uart->thr); + return write32(&uart->thr, data); } diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 5756834..4518ff8 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -42,88 +42,88 @@ static void am335x_uart_init(struct am335x_uart *uart, uint16_t div) uint16_t lcr_orig, efr_orig, mcr_orig; /* reset the UART */ - write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc); + write16(&uart->sysc, uart->sysc | SYSC_SOFTRESET); while (!(read16(&uart->syss) & SYSS_RESETDONE)) ; /* 1. switch to register config mode B */ lcr_orig = read16(&uart->lcr); - write16(0xbf, &uart->lcr); + write16(&uart->lcr, 0xbf); /* * 2. Set EFR ENHANCED_EN bit. To access this bit, registers must * be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1. */ efr_orig = read16(&uart->efr); - write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + write16(&uart->efr, efr_orig | EFR_ENHANCED_EN); /* 3. Switch to register config mode A */ - write16(0x80, &uart->lcr); + write16(&uart->lcr, 0x80); /* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */ mcr_orig = read16(&uart->mcr); - write16(mcr_orig | MCR_TCR_TLR, &uart->mcr); + write16(&uart->mcr, mcr_orig | MCR_TCR_TLR); /* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */ - write16(FCR_FIFO_EN, &uart->fcr); + write16(&uart->fcr, FCR_FIFO_EN); /* 6. Switch to configuration mode B */ - write16(0xbf, &uart->lcr); + write16(&uart->lcr, 0xbf); /* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */ /* 9. Restore original EFR value */ - write16(efr_orig, &uart->efr); + write16(&uart->efr, efr_orig); /* 10. Switch to config mode A */ - write16(0x80, &uart->lcr); + write16(&uart->lcr, 0x80); /* 11. Restore original MCR value */ - write16(mcr_orig, &uart->mcr); + write16(&uart->mcr, mcr_orig); /* 12. Restore original LCR value */ - write16(lcr_orig, &uart->lcr); + write16(&uart->lcr, lcr_orig); /* Protocol, baud rate and interrupt settings */ /* 1. Disable UART access to DLL and DLH registers */ - write16(read16(&uart->mdr1) | 0x7, &uart->mdr1); + write16(&uart->mdr1, read16(&uart->mdr1) | 0x7); /* 2. Switch to config mode B */ - write16(0xbf, &uart->lcr); + write16(&uart->lcr, 0xbf); /* 3. Enable access to IER[7:4] */ - write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + write16(&uart->efr, efr_orig | EFR_ENHANCED_EN); /* 4. Switch to operational mode */ - write16(0x0, &uart->lcr); + write16(&uart->lcr, 0x0); /* 5. Clear IER */ - write16(0x0, &uart->ier); + write16(&uart->ier, 0x0); /* 6. Switch to config mode B */ - write16(0xbf, &uart->lcr); + write16(&uart->lcr, 0xbf); /* 7. Set dll and dlh to the desired values (table 19-25) */ - write16((div >> 8), &uart->dlh); - write16((div & 0xff), &uart->dll); + write16(&uart->dlh, (div >> 8)); + write16(&uart->dll, (div & 0xff)); /* 8. Switch to operational mode to access ier */ - write16(0x0, &uart->lcr); + write16(&uart->lcr, 0x0); /* 9. Clear ier to disable all interrupts */ - write16(0x0, &uart->ier); + write16(&uart->ier, 0x0); /* 10. Switch to config mode B */ - write16(0xbf, &uart->lcr); + write16(&uart->lcr, 0xbf); /* 11. Restore efr */ - write16(efr_orig, &uart->efr); + write16(&uart->efr, efr_orig); /* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */ - write16(0x3, &uart->lcr); + write16(&uart->lcr, 0x3); /* 13. Load the new UART mode */ - write16(0x0, &uart->mdr1); + write16(&uart->mdr1, 0x0); } /* @@ -145,7 +145,7 @@ static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data) { while (!(read16(&uart->lsr) & LSR_TXFIFOE)); - return write8(data, &uart->thr); + return write8(&uart->thr, data); } unsigned int uart_platform_refclk(void) diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 360f914..e4a0313 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -38,12 +38,12 @@ static void cubieboard_set_sys_clock(void) struct a10_ccm *ccm = (void *)A1X_CCM_BASE; /* Switch CPU clock to main oscillator */ - write32(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg); + write32(&ccm->cpu_ahb_apb0_cfg, CPU_AHB_APB0_DEFAULT); /* Configure the PLL1. The value is the same one used by u-boot * P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz */ - write32(0xa1005000, &ccm->pll1_cfg); + write32(&ccm->pll1_cfg, 0xa1005000); /* FIXME: Delay to wait for PLL to lock */ u32 wait = 1000; @@ -53,7 +53,7 @@ static void cubieboard_set_sys_clock(void) reg32 = read32(&ccm->cpu_ahb_apb0_cfg); reg32 &= ~CPU_CLK_SRC_MASK; reg32 |= CPU_CLK_SRC_PLL1; - write32(reg32, &ccm->cpu_ahb_apb0_cfg); + write32(&ccm->cpu_ahb_apb0_cfg, reg32); } static void cubieboard_setup_clocks(void) @@ -62,12 +62,12 @@ static void cubieboard_setup_clocks(void) cubieboard_set_sys_clock(); /* Configure the clock source for APB1. This drives our UART */ - write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0), - &ccm->apb1_clk_div_cfg); + write32(&ccm->apb1_clk_div_cfg, + APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0)); /* Configure the clock for SD0 */ - write32(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) - | SDx_RAT_M(1), &ccm->sd0_clk_cfg); + write32(&ccm->sd0_clk_cfg, + SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1)); /* Enable clock to SD0 */ a1x_periph_clock_enable(A1X_CLKEN_MMC0); diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c index 5983d54..9034c97 100644 --- a/src/soc/nvidia/tegra/apbmisc.c +++ b/src/soc/nvidia/tegra/apbmisc.c @@ -26,10 +26,10 @@ static struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE; void enable_jtag(void) { - write32(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl); + write32(&misc->pp_config_ctl, PP_CONFIG_CTL_JTAG); } void clamp_tristate_inputs(void) { - write32(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global); + write32(&misc->pp_pinmux_global, PP_PINMUX_CLAMP_INPUTS); } diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index b10cded..833020d 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -98,8 +98,8 @@ static void gpio_write_port(int index, size_t offset, u32 mask, u32 value) u32 new_reg = (reg & ~mask) | (value & mask); if (new_reg != reg) { - write32(new_reg, (u8 *)&gpio_banks[bank] + offset + - port * sizeof(u32)); + write32((u8 *)&gpio_banks[bank] + offset + port * sizeof(u32), + new_reg); } } diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 26c2559..a68129a 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -74,7 +74,7 @@ static int tegra_i2c_send_recv(int bus, int read, rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT; while (header_words && tx_empty) { - write32(*headers++, &regs->tx_packet_fifo); + write32(&regs->tx_packet_fifo, *headers++); header_words--; tx_empty--; } @@ -96,7 +96,7 @@ static int tegra_i2c_send_recv(int bus, int read, int todo = MIN(data_len, sizeof(word)); memcpy(&word, data, todo); - write32(word, &regs->tx_packet_fifo); + write32(&regs->tx_packet_fifo, word); data_len -= todo; data += sizeof(word); tx_empty--; @@ -203,5 +203,5 @@ void i2c_init(unsigned bus) { struct tegra_i2c_regs * const regs = tegra_i2c_info[bus].base; - write32(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg); + write32(&regs->cnfg, I2C_CNFG_PACKET_MODE_EN); } diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c index 858cb44..332e05a 100644 --- a/src/soc/nvidia/tegra/pingroup.c +++ b/src/soc/nvidia/tegra/pingroup.c @@ -26,7 +26,7 @@ static uint32_t *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE; void pingroup_set_config(int group_index, uint32_t config) { - write32(config, &pingroup_regs[group_index]); + write32(&pingroup_regs[group_index], config); } uint32_t pingroup_get_config(int group_index) diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c index 6e4b3ff..f28b026 100644 --- a/src/soc/nvidia/tegra/pinmux.c +++ b/src/soc/nvidia/tegra/pinmux.c @@ -26,7 +26,7 @@ static uint32_t *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE; void pinmux_set_config(int pin_index, uint32_t config) { - write32(config, &pinmux_regs[pin_index]); + write32(&pinmux_regs[pin_index], config); } uint32_t pinmux_get_config(int pin_index) diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index e0455ed..9bd639e 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -35,61 +35,27 @@ void usb_setup_utmip(struct usb_ctlr *usb) udelay(1); /* Take stuff out of pwrdn and add some magic numbers from U-Boot */ - write32(0x8 << 25 | /* HS slew rate [10:4] */ - 0x3 << 22 | /* HS driver output 'SETUP' [6:4] */ - 0 << 21 | /* LS bias selection */ - 0 << 18 | /* PDZI pwrdn */ - 0 << 16 | /* PD2 pwrdn */ - 0 << 14 | /* PD pwrdn */ - 1 << 13 | /* (rst) HS receiver terminations */ - 0x1 << 10 | /* (rst) LS falling slew rate */ - 0x1 << 8 | /* (rst) LS rising slew rate */ - 0x4 << 0 | /* HS driver output 'SETUP' [3:0] */ - 0, &usb->utmip.xcvr0); - write32(0x7 << 18 | /* Termination range adjustment */ - 0 << 4 | /* PDDR pwrdn */ - 0 << 2 | /* PDCHRP pwrdn */ - 0 << 0 | /* PDDISC pwrdn */ - 0, &usb->utmip.xcvr1); - write32(1 << 19 | /* FS send initial J before sync(?) */ - 1 << 16 | /* (rst) Allow stuff error on SoP */ - 1 << 9 | /* (rst) Check disc only on EoP */ - 0, &usb->utmip.tx); - write32(0x2 << 30 | /* (rst) Keep pattern on active */ - 1 << 28 | /* (rst) Realign inertia on pkt */ - 0x1 << 24 | /* (rst) edges-1 to move sampling */ - 0x3 << 21 | /* (rst) squelch delay on EoP */ - 0x11 << 15 | /* cycles until IDLE */ - 0x10 << 10 | /* elastic input depth */ - 0, &usb->utmip.hsrx0); + write32(&usb->utmip.xcvr0, + 0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0); + write32(&usb->utmip.xcvr1, 0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0); + write32(&usb->utmip.tx, 1 << 19 | 1 << 16 | 1 << 9 | 0); + write32(&usb->utmip.hsrx0, + 0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0); /* U-Boot claims the USBD values for these are used across all UTMI+ * PHYs. That sounds so horribly wrong that I'm not going to implement * it, but keep it in mind if we're ever not using the USBD port. */ - write32(0x1 << 24 | /* HS disconnect detect level [2] */ - 1 << 23 | /* (rst) IDPD value */ - 1 << 22 | /* (rst) IDPD select */ - 1 << 11 | /* (rst) OTG pwrdn */ - 0 << 10 | /* bias pwrdn */ - 0x1 << 2 | /* HS disconnect detect level [1:0] */ - 0x2 << 0 | /* HS squelch detect level */ - 0, &usb->utmip.bias0); + write32(&usb->utmip.bias0, + 0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0); - write32(khz / 2200 << 3 | /* bias pwrdn cycles (20us?) */ - 1 << 2 | /* (rst) VBUS wakeup pwrdn */ - 0 << 0 | /* PDTRK pwrdn */ - 0, &usb->utmip.bias1); + write32(&usb->utmip.bias1, khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0); - write32(0xffff << 16 | /* (rst) */ - 25 * khz / 10 << 0 | /* TODO: what's this, really? */ - 0, &usb->utmip.debounce); + write32(&usb->utmip.debounce, 0xffff << 16 | 25 * khz / 10 << 0 | 0); udelay(1); setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ - write32(1 << 12 | /* UTMI+ enable */ - 0 << 11 | /* UTMI+ reset */ - 0, &usb->suspend_ctrl); + write32(&usb->suspend_ctrl, 1 << 12 | 0 << 11 | 0); } /* @@ -105,7 +71,7 @@ void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type) { int timeout = 1000; - write32(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */ + write32(&usb->ehci_usbcmd, 1 << 1); /* Host Controller Reset */ /* TODO: Resets are long, find way to parallelize... or just use XHCI */ while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1)) /* wait for HC to reset */; @@ -115,7 +81,7 @@ void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type) return; } - write32(3 << 0, &usb->usb_mode); /* Controller mode: HOST */ - write32(type << 29, &usb->lpm_ctrl); /* Parallel transceiver selct */ - write32(0x10 << 16, &usb->tx_fill_tuning); /* Tx FIFO Burst thresh */ + write32(&usb->usb_mode, 3 << 0); /* Controller mode: HOST */ + write32(&usb->lpm_ctrl, type << 29); /* Parallel transceiver selct */ + write32(&usb->tx_fill_tuning, 0x10 << 16); /* Tx FIFO Burst thresh */ } diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index af2f96a..48bf765 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -184,11 +184,11 @@ void clock_init_arm_generic_timer(void) __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); // Record the system timer frequency. - write32(freq, &sysctr->cntfid0); + write32(&sysctr->cntfid0, freq); // Enable the system counter. uint32_t cntcr = read32(&sysctr->cntcr); cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; - write32(cntcr, &sysctr->cntcr); + write32(&sysctr->cntcr, cntcr); } #define SOR0_CLK_SEL0 (1 << 14) @@ -241,25 +241,14 @@ static void init_utmip_pll(void) clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); - write32(80 << 16 | /* (rst) phy_divn */ - 1 << 8 | /* (rst) phy_divm */ - 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */ + write32(&clk_rst->utmip_pll_cfg0, 80 << 16 | 1 << 8 | 0); /* 960MHz * 1 / 80 == 12 MHz */ - write32(CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ - 0 << 16 | /* PLLU pwrdn */ - 0 << 14 | /* pll_enable pwrdn */ - 0 << 12 | /* pll_active pwrdn */ - CEIL_DIV(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */ - 0, &clk_rst->utmip_pll_cfg1); + write32(&clk_rst->utmip_pll_cfg1, + CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0); /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ - write32(0 << 24 | /* SAMP_D/XDEV pwrdn */ - CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ - CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ - 0 << 4 | /* SAMP_C/USB3 pwrdn */ - 0 << 2 | /* SAMP_B/XHOST pwrdn */ - 0 << 0 | /* SAMP_A/USBD pwrdn */ - 0, &clk_rst->utmip_pll_cfg2); + write32(&clk_rst->utmip_pll_cfg2, + 0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0); setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ } @@ -396,8 +385,8 @@ clock_display(u32 frequency) * been determined through trial and error (must lead to div 13 at 24MHz). */ void clock_early_uart(void) { - write32(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | - CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), &clk_rst->clk_src_uarta); + write32(&clk_rst->clk_src_uarta, + CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); udelay(2); clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); @@ -484,28 +473,24 @@ void clock_cpu0_config_and_reset(void *entry) { void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; - write32(CONFIG_STACK_TOP, &maincpu_stack_pointer); - write32((uintptr_t)entry, &maincpu_entry_point); - write32((uintptr_t)&maincpu_setup, evp_cpu_reset); + write32(&maincpu_stack_pointer, CONFIG_STACK_TOP); + write32(&maincpu_entry_point, (uintptr_t)entry); + write32(evp_cpu_reset, (uintptr_t)&maincpu_setup); /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); // Set up cclk_brst and divider. - write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | - (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | - (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | - (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | - (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28), - &clk_rst->cclk_brst_pol); - write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, - &clk_rst->super_cclk_div); + write32(&clk_rst->cclk_brst_pol, + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28)); + write32(&clk_rst->super_cclk_div, + CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB); // Enable the clocks for CPUs 0-3. uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; - write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); + write32(&clk_rst->clk_cpu_cmplx_clr, cpu_cmplx_clr); // Enable other CPU related clocks. setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); @@ -513,36 +498,23 @@ void clock_cpu0_config_and_reset(void *entry) setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); // Disable the reset on the non-CPU parts of the fast cluster. - write32(CRC_RST_CPUG_CLR_NONCPU, - &clk_rst->rst_cpug_cmplx_clr); + write32(&clk_rst->rst_cpug_cmplx_clr, CRC_RST_CPUG_CLR_NONCPU); // Disable the various resets on the CPUs. - write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | - CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | - CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | - CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | - CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | - CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | - CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | - CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | - CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, - &clk_rst->rst_cpug_cmplx_clr); + write32(&clk_rst->rst_cpug_cmplx_clr, + CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG); // Disable the reset on the non-CPU parts of the slow cluster. - write32(CRC_RST_CPULP_CLR_NONCPU, - &clk_rst->rst_cpulp_cmplx_clr); + write32(&clk_rst->rst_cpulp_cmplx_clr, CRC_RST_CPULP_CLR_NONCPU); // Disable the various resets on the LP CPU. - write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | - CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | - CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG, - &clk_rst->rst_cpulp_cmplx_clr); + write32(&clk_rst->rst_cpulp_cmplx_clr, + CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG); } void clock_halt_avp(void) { for (;;) { - write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | - FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT, - &flow->halt_cop_events); + write32(&flow->halt_cop_events, + FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); } } @@ -559,13 +531,12 @@ void clock_init(void) /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA * features section in the TRM). */ - write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT, - &clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */ - write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_CLKEN | PLL_OUT_RSTN, &clk_rst->pllc_out); - write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | - SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, - &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */ + write32(&clk_rst->clk_sys_rate, + 1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT); /* pclk = hclk = sclk/2 */ + write32(&clk_rst->pllc_out, + CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN); + write32(&clk_rst->sclk_brst_pol, + SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* sclk = 300 MHz */ /* Change the oscillator drive strength (from U-Boot -- why?) */ clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, @@ -583,16 +554,10 @@ void clock_init(void) clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ - write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT, - &clk_rst->pllp_outa); - write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | - (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | - PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT, - &clk_rst->pllp_outb); + write32(&clk_rst->pllp_outa, + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); + write32(&clk_rst->pllp_outb, + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); /* init pllx */ init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 0b519d6..6b22b80 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -274,17 +274,17 @@ inline static void write32(uint32_t val, void *addr) inline static void setbits32(uint32_t bits, void *addr) { - write32(read32(addr) | bits, addr); + write32(addr, read32(addr) | bits); } inline static void clrbits32(uint32_t bits, void *addr) { - write32(read32(addr) & ~bits, addr); + write32(addr, read32(addr) & ~bits); } static void __attribute__((noreturn)) reset(void) { - write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr); + write32(clk_rst_rst_devices_l_ptr, SWR_TRIG_SYS_RST); halt(); } @@ -329,7 +329,7 @@ static void config_oscillator(void) osc_ctrl &= ~OSC_XOFS_MASK; osc_ctrl |= (xofs << OSC_XOFS_SHIFT); osc_ctrl |= OSC_XOE; - write32(osc_ctrl, clk_rst_osc_ctrl_ptr); + write32(clk_rst_osc_ctrl_ptr, osc_ctrl); } static void config_pllu(void) @@ -374,17 +374,17 @@ static void config_pllu(void) // Configure PLLU. uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE | (divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT); - write32(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) | (lfcon << PLLU_LFCON_SHIFT); - write32(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); // Enable PLLU. base &= ~PLLU_BYPASS; base |= PLLU_ENABLE; - write32(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); misc |= PLLU_LOCK_ENABLE; - write32(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); } static void config_tsc(void) @@ -392,26 +392,26 @@ static void config_tsc(void) // Tell the TSC the oscillator frequency. switch (get_osc_freq()) { case OSC_FREQ_12: - write32(12000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 12000000); break; case OSC_FREQ_48: - write32(48000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 48000000); break; case OSC_FREQ_16P8: - write32(16800000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 16800000); break; case OSC_FREQ_19P2: - write32(19200000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 19200000); break; case OSC_FREQ_38P4: - write32(38400000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 38400000); break; case OSC_FREQ_26: - write32(26000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 26000000); break; default: // Default to 13MHz. - write32(13000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 13000000); break; } @@ -426,7 +426,7 @@ static void config_tsc(void) static void config_core_sight(void) { // Enable the CoreSight clock. - write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr); + write32(clk_rst_clk_out_enb_u_set_ptr, CLK_ENB_CSITE); /* * De-assert CoreSight reset. @@ -434,22 +434,22 @@ static void config_core_sight(void) * now. It will be restored to its original clock source * when the CPU-side restoration code runs. */ - write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr); + write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); } static void config_mselect(void) { // Set MSELECT clock source to PLLP with 1:4 divider. - write32((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0, - clk_rst_clk_src_mselect_ptr); + write32(clk_rst_clk_src_mselect_ptr, + (6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0); // Enable clock to MSELECT. - write32(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr); + write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_MSELECT); udelay(2); // Bring MSELECT out of reset. - write32(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr); + write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST); } @@ -459,19 +459,16 @@ static void config_mselect(void) static void clear_cpu_resets(void) { // Take the non-cpu of the G and LP clusters out of reset. - write32(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr); - write32(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpulp_cmplx_clr_ptr, CLR_NONCPURESET); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, CLR_NONCPURESET); // Clear software controlled reset of the slow cluster. - write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0, - clk_rst_rst_cpulp_cmplx_clr_ptr); + write32(clk_rst_rst_cpulp_cmplx_clr_ptr, + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0); // Clear software controlled reset of the fast cluster. - write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | - CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | - CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | - CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3, - clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); } @@ -483,7 +480,8 @@ static void power_on_partition(unsigned id) uint32_t bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { // Partition is not on. Turn it on. - write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr); + write32(pmc_ctlr_pwrgate_toggle_ptr, + id | PWRGATE_TOGGLE_START); // Wait until the partition is powerd on. while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) @@ -513,8 +511,8 @@ static void power_on_main_cpu(void) */ uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); - write32(orig_timer * (408000000 / 32768), - pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, + orig_timer * (408000000 / 32768)); if (wakeup_on_lp()) { power_on_partition(PARTID_C1NC); @@ -526,11 +524,11 @@ static void power_on_main_cpu(void) } // Give I/O signals time to stablize. - write32(20 | EVENT_MSEC | FLOW_MODE_STOP, - flow_ctlr_halt_cop_events_ptr); + write32(flow_ctlr_halt_cop_events_ptr, + 20 | EVENT_MSEC | FLOW_MODE_STOP); // Restore the original PMC_CPUPWRGOOD_TIMER. - write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); } @@ -552,17 +550,17 @@ void lp0_resume(void) flow_ctlr_cluster_control_ptr); // Program SUPER_CCLK_DIVIDER. - write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr); + write32(clk_rst_super_cclk_div_ptr, SUPER_CDIV_ENB); config_core_sight(); config_pllu(); // Set the CPU reset vector. - write32(get_wakeup_vector(), evp_cpu_reset_ptr); + write32(evp_cpu_reset_ptr, get_wakeup_vector()); // Select CPU complex clock source. - write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr); + write32(clk_rst_cclk_burst_policy_ptr, CCLK_PLLP_BURST_POLICY); config_mselect(); @@ -573,27 +571,27 @@ void lp0_resume(void) uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; - write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); + write32(clk_rst_cpu_softrst_ctrl2_ptr, ack_width); // Enable the CPU complex clock. - write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); - write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); + write32(clk_rst_clk_enb_l_set_ptr, CLK_ENB_CPU); + write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); clear_cpu_resets(); config_tsc(); // Disable VPR. - write32(0, mc_video_protect_size_mb_ptr); - write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, - mc_video_protect_reg_ctrl_ptr); + write32(mc_video_protect_size_mb_ptr, 0); + write32(mc_video_protect_reg_ctrl_ptr, + VIDEO_PROTECT_WRITE_ACCESS_DISABLE); power_on_main_cpu(); // Halt the AVP. while (1) - write32(FLOW_MODE_STOP | EVENT_JTAG, - flow_ctlr_halt_cop_events_ptr); + write32(flow_ctlr_halt_cop_events_ptr, + FLOW_MODE_STOP | EVENT_JTAG); } diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index 760d058..0054036 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -41,7 +41,7 @@ static void power_ungate_partition(uint32_t id) pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; - write32(pwrgate_toggle, &pmc->pwrgate_toggle); + write32(&pmc->pwrgate_toggle, pwrgate_toggle); // Wait for the request to be accepted. while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) @@ -67,14 +67,14 @@ void power_enable_cpu_rail(void) * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), * set it for 5ms as per SysEng (102MHz/5mS = 510000). */ - write32(510000, &pmc->cpupwrgood_timer); + write32(&pmc->cpupwrgood_timer, 510000); power_ungate_partition(POWER_PARTID_CRAIL); uint32_t cntrl = read32(&pmc->cntrl); cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY; cntrl |= PMC_CNTRL_CPUPWRREQ_OE; - write32(cntrl, &pmc->cntrl); + write32(&pmc->cntrl, cntrl); } void power_ungate_cpu(void) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 8e090aa..4eca16f 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -231,7 +231,7 @@ int spi_claim_bus(struct spi_slave *slave) else val |= SPI_CMD1_CS_SW_VAL; - write32(val, &regs->command1); + write32(&regs->command1, val); return 0; } @@ -247,7 +247,7 @@ void spi_release_bus(struct spi_slave *slave) else val &= ~SPI_CMD1_CS_SW_VAL; - write32(val, &regs->command1); + write32(&regs->command1, val); } static void dump_fifo_status(struct tegra_spi_channel *spi) @@ -384,12 +384,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and * PIO transfers */ - write32(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); if (dir == SPI_SEND) { unsigned int to_fifo = bytes; while (to_fifo) { - write32(*p, &spi->regs->tx_fifo); + write32(&spi->regs->tx_fifo, *p); p++; to_fifo--; } @@ -496,11 +496,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* ensure bytes to send will be visible to DMA controller */ dcache_clean_by_mva(spi->out_buf, bytes); - write32((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr); - write32((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr); + write32(&spi->dma_out->regs->apb_ptr, + (u32)&spi->regs->tx_fifo); + write32(&spi->dma_out->regs->ahb_ptr, (u32)spi->out_buf); setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); - write32(wcount, &spi->dma_out->regs->wcount); + write32(&spi->dma_out->regs->wcount, wcount); } else { spi->dma_in = dma_claim(); if (!spi->dma_in) @@ -509,15 +510,15 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* avoid data collisions */ dcache_clean_invalidate_by_mva(spi->in_buf, bytes); - write32((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr); - write32((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr); + write32(&spi->dma_in->regs->apb_ptr, (u32)&spi->regs->rx_fifo); + write32(&spi->dma_in->regs->ahb_ptr, (u32)spi->in_buf); clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); - write32(wcount, &spi->dma_in->regs->wcount); + write32(&spi->dma_in->regs->wcount, wcount); } /* BLOCK_SIZE starts at n-1 */ - write32(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); return todo; } diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index fd8074d..726278e 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -56,20 +56,19 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr) tegra124_uart_tx_flush(uart_ptr); // Disable interrupts. - write8(0, &uart_ptr->ier); + write8(&uart_ptr->ier, 0); // Force DTR and RTS to high. - write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr); + write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); // Set line configuration, access divisor latches. - write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); // Set the divisor. - write8(divisor & 0xff, &uart_ptr->dll); - write8((divisor >> 8) & 0xff, &uart_ptr->dlm); + write8(&uart_ptr->dll, divisor & 0xff); + write8(&uart_ptr->dlm, (divisor >> 8) & 0xff); // Hide the divisor latches. - write8(line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, line_config); // Enable FIFOs, and clear receive and transmit. - write8(UART8250_FCR_FIFO_EN | - UART8250_FCR_CLEAR_RCVR | - UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr); + write8(&uart_ptr->fcr, + UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); } static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr) @@ -82,7 +81,7 @@ static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr) static void tegra124_uart_tx_byte(struct tegra124_uart *uart_ptr, unsigned char data) { while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)); - write8(data, &uart_ptr->thr); + write8(&uart_ptr->thr, data); } static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr) diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 28603ae..ae0553a 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -189,8 +189,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) * release pad retention and retain the memory content until the * initialization is complete. */ - write32(PAD_RETENTION_DRAM_COREBLK_VAL, - &exynos_power->padret_dram_cblk_opt); + write32(&exynos_power->padret_dram_cblk_opt, + PAD_RETENTION_DRAM_COREBLK_VAL); do { ret = read32(&exynos_power->padret_dram_status); } while (ret != 0x1); diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index e8892cd..73daebf 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -56,7 +56,7 @@ static inline unsigned long fradl(void *v) { #define lread32(a) fradl((void *)(a)) #else -#define lwrite32(a,b) write32((unsigned long)(a), (void *)(b)) +#define lwrite32(a,b) write32((void *)(b), (unsigned long)(a)) #define lread32(a) read32((void *)(a)) #endif diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 49875d7..0dc1834 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -433,7 +433,7 @@ static int hsi2c_senddata(struct hsi2c_regs *regs, const uint8_t *data, int len) { while (!hsi2c_check_transfer(regs) && len) { if (!(read32(&regs->usi_fifo_stat) & Hsi2cTxFifoFull)) { - write32(*data++, &regs->usi_txdata); + write32(&regs->usi_txdata, *data++); len--; } } @@ -455,7 +455,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) { const uint32_t usi_ctl = Hsi2cFuncModeI2c | Hsi2cMaster; - write32(HSI2C_SLV_ADDR_MAS(seg->chip), &regs->i2c_addr); + write32(&regs->i2c_addr, HSI2C_SLV_ADDR_MAS(seg->chip)); /* * We really only want to stop after this transaction (I think) if the @@ -468,14 +468,14 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) seg->len | Hsi2cMasterRun | Hsi2cStopAfterTrans; if (seg->read) { - write32(usi_ctl | Hsi2cRxchon, &regs->usi_ctl); - write32(autoconf | Hsi2cReadWrite, &regs->i2c_auto_conf); + write32(&regs->usi_ctl, usi_ctl | Hsi2cRxchon); + write32(&regs->i2c_auto_conf, autoconf | Hsi2cReadWrite); if (hsi2c_recvdata(regs, seg->buf, seg->len)) return -1; } else { - write32(usi_ctl | Hsi2cTxchon, &regs->usi_ctl); - write32(autoconf, &regs->i2c_auto_conf); + write32(&regs->usi_ctl, usi_ctl | Hsi2cTxchon); + write32(&regs->i2c_auto_conf, autoconf); if (hsi2c_senddata(regs, seg->buf, seg->len)) return -1;

1 0

Patch set updated for coreboot: 9bbfd94 southbridge/intel/lynxpoint/me_9.x.c: Avoid unused func warn
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8157 -gerrit commit 9bbfd949fc07a387d993b5fda12c2a1fe5070ddf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 7 15:53:00 2015 +1100 southbridge/intel/lynxpoint/me_9.x.c: Avoid unused func warn Put a guard around this function to avoid compiler warnings pretaining to unused functions when a false branch is hit on a guard further down the file. Change-Id: Ie4955ee9df6904c38848f46226b53be37d9fa239 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/intel/lynxpoint/me_9.x.c | 50 +++++++++++++++++--------------- 1 file changed, 26 insertions(+), 24 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index dfed6de..9670bbb 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -374,6 +374,7 @@ static int mei_recv_msg(void *header, int header_bytes, return mei_wait_for_me_ready(); } +#if IS_ENABLED (CONFIG_DEBUG_INTEL_ME) || defined(__SMM__) static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, void *req_data, int req_bytes, void *rsp_data, int rsp_bytes) @@ -411,30 +412,7 @@ static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, return 0; } - -static inline int mei_sendrecv_icc(struct icc_header *icc, - void *req_data, int req_bytes, - void *rsp_data, int rsp_bytes) -{ - struct icc_header icc_rsp; - - /* Send header */ - if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, - icc, sizeof(*icc), req_bytes ? 0 : 1) < 0) - return -1; - - /* Send data if available */ - if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, - req_data, req_bytes) < 0) - return -1; - - /* Read header and data, if needed */ - if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp), - rsp_data, rsp_bytes) < 0) - return -1; - - return 0; -} +#endif /* CONFIG_DEBUG_INTEL_ME || __SMM__ */ /* * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read @@ -636,6 +614,30 @@ void intel_me_finalize_smm(void) #else /* !__SMM__ */ +static inline int mei_sendrecv_icc(struct icc_header *icc, + void *req_data, int req_bytes, + void *rsp_data, int rsp_bytes) +{ + struct icc_header icc_rsp; + + /* Send header */ + if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, + icc, sizeof(*icc), req_bytes ? 0 : 1) < 0) + return -1; + + /* Send data if available */ + if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, + req_data, req_bytes) < 0) + return -1; + + /* Read header and data, if needed */ + if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp), + rsp_data, rsp_bytes) < 0) + return -1; + + return 0; +} + static int me_icc_set_clock_enables(u32 mask) { struct icc_clock_enables_msg clk = {

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Patch set updated for coreboot: 217cf01 mainboard/lenovo/x201/romstage.c: Avoid unused func warning
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8158 -gerrit commit 217cf01282ba98dbda78b200012c07739adedb7e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 7 15:55:32 2015 +1100 mainboard/lenovo/x201/romstage.c: Avoid unused func warning Change-Id: I646dddd39e61b59358b29a49239c0a1de77c7e55 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/x201/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 64011b1..535c373 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -167,10 +167,14 @@ static inline u32 read_acpi32(u32 addr) return inl(DEFAULT_PMBASE | addr); } +// Used for reverse engining purposes +// avoid unused func compiler warn +#if 0 static inline u16 read_acpi16(u32 addr) { return inw(DEFAULT_PMBASE | addr); } +#endif static void set_fsb_frequency(void) {

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Patch set updated for coreboot: d0a1d81 Makefile: clang - ramp up some more warnings
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8136 -gerrit commit d0a1d81ab4ea0e8eaa99e8a2ef83452496598569 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 14:58:31 2015 +1100 Makefile: clang - ramp up some more warnings Change-Id: I5262cba22d262f5d74d1edd958b59c2695271293 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6ef9838..ce2b727 100644 --- a/Makefile +++ b/Makefile @@ -119,7 +119,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # this means the triple is i386-linux-elf instead of i386-none-elf CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 # Tone down some clang warnings -CFLAGS_x86_32 += -Wno-unused-variable -Wno-unused-function -Wno-tautological-compare -Wno-shift-overflow +CFLAGS_x86_32 += -Wno-unused-variable -Wno-tautological-compare -Wno-shift-overflow CC_x86_32:=clang HOSTCC := clang

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Patch set updated for coreboot: 3eb09ad soc/intel/broadwell/spi_loading.c: Remove dead code
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8168 -gerrit commit 3eb09ad6d1bad8c2e6b80b265d4d6d199a95fe08 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 8 02:05:21 2015 +1100 soc/intel/broadwell/spi_loading.c: Remove dead code I would appear from commit a6354a1 that this is now dead code. Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/spi_loading.c | 67 ----------------------------------- 2 files changed, 68 deletions(-) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 43be95e..feead00 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -52,7 +52,6 @@ smm-y += smihandler.c ramstage-y += smmrelocate.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += spi_loading.c ramstage-y += stage_cache.c romstage-y += stage_cache.c ramstage-y += systemagent.c diff --git a/src/soc/intel/broadwell/spi_loading.c b/src/soc/intel/broadwell/spi_loading.c deleted file mode 100644 index 9454d03..0000000 --- a/src/soc/intel/broadwell/spi_loading.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -}

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Patch set updated for coreboot: 2b46640 mainboard/packardbell/ms2290/romstage.c: Comment unused func
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8167 -gerrit commit 2b46640bbc6590d72fa15de8588c91579a7f72c2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 8 01:57:43 2015 +1100 mainboard/packardbell/ms2290/romstage.c: Comment unused func Take unused reverse eng function out of build by wrapping in #if 0. Change-Id: I816b3ea08a8858fc03e4455c1d7711265e63cba4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/packardbell/ms2290/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index a366d38..f702e9f 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -163,10 +163,13 @@ static inline u32 read_acpi32(u32 addr) return inl(DEFAULT_PMBASE | addr); } +// unused func - used for RE +#if 0 static inline u16 read_acpi16(u32 addr) { return inw(DEFAULT_PMBASE | addr); } +#endif #include <cpu/intel/romstage.h> void main(unsigned long bist)

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Patch set updated for coreboot: 6d711d5 Re-factor 'to_flash_offset()' into 'spi_flash.h'
by Edward O'Callaghan 07 Jan '15

07 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8165 -gerrit commit 6d711d561032976265f06ddf6b32bd1ea076dd99 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:09:50 2014 +1000 Re-factor 'to_flash_offset()' into 'spi_flash.h' Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by Clang complaining that the function 'to_flash_offset' is unused. Change-Id: Ie2a8ac3cddac1cd87f1197efcd1bc9eb3189136e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/intel/fsp/fastboot_cache.c | 13 ++----------- src/include/spi_flash.h | 8 ++++++++ src/northbridge/intel/haswell/mrccache.c | 7 +------ src/northbridge/intel/sandybridge/mrccache.c | 7 +------ src/soc/intel/common/nvm.c | 10 ++-------- src/soc/intel/fsp_baytrail/nvm.c | 13 ++----------- 6 files changed, 16 insertions(+), 42 deletions(-) diff --git a/src/drivers/intel/fsp/fastboot_cache.c b/src/drivers/intel/fsp/fastboot_cache.c index 64982d8..907e143 100644 --- a/src/drivers/intel/fsp/fastboot_cache.c +++ b/src/drivers/intel/fsp/fastboot_cache.c @@ -31,15 +31,6 @@ #include <lib.h> // hexdump #include "fsp_util.h" -#ifndef CONFIG_VIRTUAL_ROM_SIZE -#error "CONFIG_VIRTUAL_ROM_SIZE must be set." -#endif - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -205,7 +196,7 @@ void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -213,7 +204,7 @@ void update_mrc_cache(void *unused) /* 4. write mrc data with flash->write() */ printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); } diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 7e430d0..0d8331e 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -76,4 +76,12 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, return flash->erase(flash, offset, len); } +#if !defined(__PRE_RAM__) +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + u32 size = CONFIG_VIRTUAL_ROM_SIZE ? CONFIG_VIRTUAL_ROM_SIZE : flash->size; + return ((u32)p + size); +} +#endif /* !defined(__PRE_RAM__) */ + #endif /* _SPI_FLASH_H_ */ diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index a921e04..88af789 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -228,7 +223,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..664fb7f 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -227,7 +222,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 791422f..54b3baf 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -46,12 +46,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -70,7 +64,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - return flash->erase(flash, to_flash_offset(start), size); + return flash->erase(flash, to_flash_offset(flash, start), size); } /* Write data to NVM. Returns 0 on success < 0 on error. */ @@ -78,5 +72,5 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - return flash->write(flash, to_flash_offset(start), size, data); + return flash->write(flash, to_flash_offset(flash, start), size, data); } diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c index 0224463..d1e5223 100644 --- a/src/soc/intel/fsp_baytrail/nvm.c +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -47,15 +47,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ -#ifndef CONFIG_ROM_SIZE -#error CONFIG_ROM_SIZE must be set. -#endif - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -74,7 +65,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + flash->erase(flash, to_flash_offset(flash, start), size); return 0; } @@ -83,6 +74,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + flash->write(flash, to_flash_offset(flash, start), size, data); return 0; }

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coreboot-gerrit January 2015