coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: c1f6faf src/device: Doxygen fixes
by Martin Roth 08 Jan '15

08 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8173 -gerrit commit c1f6fafbe5641fa3d65b5ab0f7ec50219faeed6e Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jan 6 21:02:52 2015 -0700 src/device: Doxygen fixes - Add missing parameters - add missing @param commands Change-Id: I029b5dafde94bd250800b06c0e9bd2118f10ef48 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/device/dram/ddr3.c | 11 ++++++++++- src/device/pci_device.c | 4 ++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 86abea8..8170ae1 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -18,7 +18,7 @@ */ /** - * @file ddr3_util.h + * @file ddr3.c * * \brief Utilities for decoding DDR3 SPDs */ @@ -452,8 +452,13 @@ static u16 ddr3_cas_to_mr0_map(u8 cas) * write_recovery and cas are given in clock cycles. For example, a CAS of 7T * should be given as 7. * + * @param precharge_pd * @param write_recovery Write recovery latency, tWR in clock cycles. + * @param dll_reset + * @param mode * @param cas CAS latency in clock cycles. + * @param burst_type + * @param burst_length */ mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, u8 write_recovery, @@ -555,8 +560,12 @@ mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, * cas_cwl is given in clock cycles. For example, a cas_cwl of 7T should be * given as 7. * + * @param rtt_wr + * @param extended_temp + * @param self_refresh * @param cas_cwl CAS write latency in clock cycles. */ + mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, enum ddr3_mr2_srt_range extended_temp, enum ddr3_mr2_asr self_refresh, u8 cas_cwl) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 22454d6..862ed0e 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -818,8 +818,8 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) * The driver entry can either point at a zero terminated array of acceptable * device IDs, or include a single device ID. * - * @driver pointer to the PCI driver entry being checked - * @device_id PCI device ID of the device being matched + * @param driver pointer to the PCI driver entry being checked + * @param device_id PCI device ID of the device being matched */ static int device_id_match(struct pci_driver *driver, unsigned short device_id) {

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Patch merged into coreboot/master: 543888d northbridg/via/vx900: Doxygen fixes
by gerrit＠coreboot.org 08 Jan '15

08 Jan '15

the following patch was just integrated into master: commit 543888d5820ce28cbf1e03d53da9e7f75001c4c7 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jan 6 10:20:42 2015 -0700 northbridg/via/vx900: Doxygen fixes - @todo has to be lowercase for doxygen - Fix some parameters that had changed in the code. - The @file entries needed to be more specific. Change-Id: Icdce08735f581609cd25cce41e986c71435368a4 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/8154 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/8154 for details. -gerrit

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Patch merged into coreboot/master: d7689e4 Doxygen: add a "simple" output config and make target
by gerrit＠coreboot.org 08 Jan '15

08 Jan '15

the following patch was just integrated into master: commit d7689e4ad588ee1affee1d4edb3e5b0bd8098b0a Author: Martin Roth <gaumless(a)gmail.com> Date: Mon Dec 29 14:56:19 2014 -0700 Doxygen: add a "simple" output config and make target This is a doxygen target I'm using for cleaning up the coreboot doxygen output. It runs in about a minute instead of.... a lot longer, and only generates documentation for the coreboot/src directory, excluding vendorcode. It was requested that the comments be stripped to make it easier to read. This was done through the following command (split for gerrit): head -n 1 Doxyfile.coreboot_simple > Doxyfile.tmp ; cat Doxyfile.coreboot_simple | sed 's|^\s*#.*$||' | sed '/^$/d' | sed 's|[[:space:]]\+$||' >> Doxyfile.tmp ; mv Doxyfile.tmp Doxyfile.coreboot_simple I'm including the command here because any time the file is updated with the doxygen wizard, it will need to be run again. It might be desirable to turn this into a script in the documentation directory. Change-Id: Ic0cbbcd21aa647e80a037481546bdcd2aab8949e Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/8068 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8068 for details. -gerrit

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Patch merged into coreboot/master: f4cb412 northbridge/amd: Doxygen fixes
by gerrit＠coreboot.org 08 Jan '15

08 Jan '15

the following patch was just integrated into master: commit f4cb4128adea4b8ebdd92ae05d7d8e733e35eb1c Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jan 6 10:27:39 2015 -0700 northbridge/amd: Doxygen fixes - Add missing parameter names in several files - remove parameter types in several files - remove lines from doxygen documentation. These should be outside the doxygen comments. - Some of the comments shouldn't have been doxygen style. Turn these into regular non-doxygen comments. Change-Id: Ieccfe237385efee007b48308d58eb0a6a12f5bfa Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/8153 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/8153 for details. -gerrit

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Patch set updated for coreboot: 34fea52 intel: Use defined ACPI S3 magic values
by Kyösti Mälkki 08 Jan '15

08 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8170 -gerrit commit 34fea527d0a551efd42e01cd006c5bc6afccc9c2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 intel: Use defined ACPI S3 magic values Unify this, until converted to CBMEM romstage_handoff. Change-Id: I2fdf44b2f654242369a9d0983a2dfa9aad1669e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 4 ++-- src/mainboard/packardbell/ms2290/romstage.c | 4 ++-- src/northbridge/intel/fsp_sandybridge/northbridge.c | 4 ++-- src/northbridge/intel/nehalem/northbridge.c | 4 ++-- src/northbridge/intel/sandybridge/early_init.c | 4 ++-- src/northbridge/intel/sandybridge/northbridge.c | 4 ++-- src/northbridge/intel/sandybridge/sandybridge.h | 3 +++ src/northbridge/intel/sch/northbridge.c | 4 ++-- 8 files changed, 17 insertions(+), 14 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 64011b1..b102993 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -305,9 +305,9 @@ void main(unsigned long bist) HIGH_MEMORY_SAVE); /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); quick_ram_check(); } #endif diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index a366d38..7ba02b4 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -289,9 +289,9 @@ void main(unsigned long bist) HIGH_MEMORY_SAVE); /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); quick_ram_check(); } #endif diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index a95d736..b9ecdfa 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -333,11 +333,11 @@ static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: + case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); acpi_slp_type=0; break; - case 0xcafed00d: + case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); acpi_slp_type=3; break; diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 11d335a..2c4b1ff 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -287,11 +287,11 @@ static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: + case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); acpi_slp_type = 0; break; - case 0xcafed00d: + case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); acpi_slp_type = 3; break; diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 3156f86..597d886 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -196,9 +196,9 @@ void northbridge_romstage_finalize(int s3resume) *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); } #endif } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 55395ea..7159700 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -416,11 +416,11 @@ static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: + case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); acpi_slp_type=0; break; - case 0xcafed00d: + case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); acpi_slp_type=3; break; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 0790ae8..ea760a9 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -99,6 +99,9 @@ #define SKPAD 0xdc /* Scratchpad Data */ +#define SKPAD_ACPI_S3_MAGIC 0xcafed00d +#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe + /* Device 0:1.0 PCI configuration space (PCI Express) */ #define BCTRL1 0x3e /* 16bit */ diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index c552879..be4785e 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -254,11 +254,11 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void northbridge_init(struct device *dev) { switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: + case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); acpi_slp_type = 0; break; - case 0xcafed00d: + case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); acpi_slp_type = 3; break;

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New patch to review for coreboot: 953566e baytrail broadwell: Use acpi_is_wakeup_s3()
by Kyösti Mälkki 08 Jan '15

08 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8172 -gerrit commit 953566e6141a7dec5547b5718d5dcbd9798033db Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 07:33:50 2015 +0200 baytrail broadwell: Use acpi_is_wakeup_s3() Global acpi_slp_type will be declared static in a follow-up patch. This change also guarantees it is properly initialized before use. Change-Id: I0f074bb80f06f6f0ddf4212cd8872e94ae57f949 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/acpi.h | 1 - src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/baytrail/xhci.c | 4 ++-- src/soc/intel/broadwell/lpc.c | 4 ++-- src/soc/intel/broadwell/me.c | 4 +--- src/soc/intel/broadwell/refcode.c | 11 +---------- 6 files changed, 7 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 502c826..2dc8bb7 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -587,7 +587,6 @@ static inline int acpi_s3_resume_allowed(void) } #if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -#define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_early(void) { return 0; } diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 5274b03..f6462fa 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -215,7 +215,7 @@ static void sc_init(device_t dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) com1_configure_resume(dev); } diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..19339e4 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -184,7 +184,7 @@ static void xhci_route_all(device_t dev) /* Route ports to XHCI controller */ reg_script_run_on_dev(dev, xhci_route_all_script); - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) return; /* Reset enabled USB3 ports */ @@ -222,7 +222,7 @@ static void xhci_init(device_t dev) }; /* Initialize XHCI controller for boot or resume path */ - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 394a9d7..c670440 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -394,7 +394,7 @@ static void pch_cg_init(device_t dev) static void pch_set_acpi_mode(void) { #if CONFIG_HAVE_SMI_HANDLER - if (acpi_slp_type != 3) { + if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); @@ -551,7 +551,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (acpi_slp_type != 3 && gnvs) + if (!acpi_is_wakeup_s3() && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); } diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 2bdb1ed..9fc6a41 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -830,13 +830,11 @@ static void intel_me_init(device_t dev) static void intel_me_enable(device_t dev) { -#if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { dev->enabled = 0; pch_disable_devfn(dev); } -#endif } static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index a745101..d66d036 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -30,15 +30,6 @@ #include <broadwell/pei_wrapper.h> #include <broadwell/ramstage.h> -static inline int is_s3_resume(void) -{ -#if CONFIG_HAVE_ACPI_RESUME - return acpi_slp_type == 3; -#else - return 0; -#endif -} - static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) { return (struct ramstage_cache *)&c->program[c->size]; @@ -136,7 +127,7 @@ static pei_wrapper_entry_t load_reference_code(void) }; int ret; - if (is_s3_resume()) { + if (acpi_is_wakeup_s3()) { return load_refcode_from_cache(); }

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New patch to review for coreboot: 1978bba cpu/amd/pi: Use acpi_is_wakeup()
by Kyösti Mälkki 08 Jan '15

08 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8171 -gerrit commit 1978bbad1b6370a151ce92c7a27827728ec33441 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:44:30 2015 +0200 cpu/amd/pi: Use acpi_is_wakeup() Propagate commit 9107e53 from amd/agesa and fix some related #includes under cpu/amd/pi. Change test to return true on S2 wakeup too. In S2 CPU would have been powered down so MTRR recovery is required. Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00730F01/model_16_init.c | 8 ++------ src/cpu/amd/pi/heapmanager.c | 2 +- src/cpu/amd/pi/s3_resume.c | 2 +- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 8053fd1..336618a 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -33,9 +33,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam16.h> #include <arch/acpi.h> -#if CONFIG_HAVE_ACPI_RESUME -#include <cpu/amd/agesa/s3_resume.h> -#endif +#include <cpu/amd/pi/s3_resume.h> static void model_16_init(device_t dev) { @@ -72,10 +70,8 @@ static void model_16_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) + if (acpi_is_wakeup()) restore_mtrr(); -#endif x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index d2c3931..aa251e0 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -1,7 +1,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/pi/BiosCallOuts.h> #include "heapManager.h" #include <cbmem.h> diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index fc619f7..bc82964 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <string.h> #include "Porting.h" -#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/pi/BiosCallOuts.h> #include "s3_resume.h" /* The size needs to be 4k aligned, which is the sector size of most flashes. */

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New patch to review for coreboot: 86292af intel: Use defined ACPI S3 magic values
by Kyösti Mälkki 08 Jan '15

08 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8170 -gerrit commit 86292afad63b4a552262ed52ec607df51814648f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 intel: Use defined ACPI S3 magic values Unify this, until converted to CBMEM romstage_handoff. Change-Id: I2fdf44b2f654242369a9d0983a2dfa9aad1669e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 4 ++-- src/mainboard/packardbell/ms2290/romstage.c | 4 ++-- src/northbridge/intel/fsp_sandybridge/northbridge.c | 4 ++-- src/northbridge/intel/nehalem/northbridge.c | 4 ++-- src/northbridge/intel/sandybridge/early_init.c | 4 ++-- src/northbridge/intel/sandybridge/northbridge.c | 4 ++-- src/northbridge/intel/sch/northbridge.c | 4 ++-- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 64011b1..b102993 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -305,9 +305,9 @@ void main(unsigned long bist) HIGH_MEMORY_SAVE); /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); quick_ram_check(); } #endif diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index a366d38..7ba02b4 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -289,9 +289,9 @@ void main(unsigned long bist) HIGH_MEMORY_SAVE); /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); quick_ram_check(); } #endif diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index a95d736..b9ecdfa 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -333,11 +333,11 @@ static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: + case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); acpi_slp_type=0; break; - case 0xcafed00d: + case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); acpi_slp_type=3; break; diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 11d335a..2c4b1ff 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -287,11 +287,11 @@ static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: + case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); acpi_slp_type = 0; break; - case 0xcafed00d: + case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); acpi_slp_type = 3; break; diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 3156f86..597d886 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -196,9 +196,9 @@ void northbridge_romstage_finalize(int s3resume) *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); } #endif } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 55395ea..7159700 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -416,11 +416,11 @@ static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: + case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); acpi_slp_type=0; break; - case 0xcafed00d: + case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); acpi_slp_type=3; break; diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index c552879..be4785e 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -254,11 +254,11 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void northbridge_init(struct device *dev) { switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: + case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); acpi_slp_type = 0; break; - case 0xcafed00d: + case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); acpi_slp_type = 3; break;

1 0

Patch set updated for coreboot: 12c994b intel SMI handlers: Refactor GPI SMI/SCI routing
by Kyösti Mälkki 08 Jan '15

08 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7967 -gerrit commit 12c994b3d1a8ec1c59a04c8711c4d6b55a66115c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 29 11:32:27 2014 +0200 intel SMI handlers: Refactor GPI SMI/SCI routing For lenovo/x201, this also changes GPI_ROUT (0xb8-0xbb) programming to change GPI1 between SCI/SMI modes, while previous programming was for GPI12. Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/apple/macbook21/smihandler.c | 22 +++----------- src/mainboard/google/parrot/smihandler.c | 43 ++------------------------- src/mainboard/lenovo/t420s/smihandler.c | 37 +++++------------------ src/mainboard/lenovo/t520/smihandler.c | 37 +++++------------------ src/mainboard/lenovo/t530/smihandler.c | 37 +++++------------------ src/mainboard/lenovo/t60/smihandler.c | 24 ++++----------- src/mainboard/lenovo/x201/smihandler.c | 37 +++++------------------ src/mainboard/lenovo/x220/smihandler.c | 37 +++++------------------ src/mainboard/lenovo/x230/smihandler.c | 38 +++++------------------ src/mainboard/lenovo/x60/smihandler.c | 24 ++++----------- src/mainboard/packardbell/ms2290/smihandler.c | 24 +++++---------- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/bd82x6x/pch.h | 6 ++++ src/southbridge/intel/bd82x6x/smihandler.c | 36 ++++++++++++++++++++++ src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +- src/southbridge/intel/i82801gx/i82801gx.h | 7 +++++ src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 36 ++++++++++++++++++++++ src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/ibexpeak/pch.h | 6 ++++ src/southbridge/intel/ibexpeak/smihandler.c | 36 ++++++++++++++++++++++ src/southbridge/intel/lynxpoint/lpc.c | 2 +- 22 files changed, 198 insertions(+), 299 deletions(-) diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index 449e367..4e4a4b6 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -27,6 +27,8 @@ #include <pc80/mc146818rtc.h> #include <delay.h> +#define GPE_H8SCI 12 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -58,30 +60,14 @@ int mainboard_io_trap_handler(int smif) int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); - - if (!pmbase) - return 0; - switch(data) { case APM_CNT_ACPI_ENABLE: /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); break; default: break; diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 4a189f8..1d1b23c 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -29,44 +29,6 @@ #include <ec/compal/ene932/ec.h> #include "ec.h" -/* Power Management PCI Configuration Registers - * Bus 0, Device 31, Function 0, Offset 0xB8 - * 00 = No Effect - * 01 = SMI# - * 10 = SCI - * 11 = NMI - */ -#define GPI_ROUT 0x8000F8B8 -#define GPI_IS_SMI 0x01 -#define GPI_IS_SCI 0x02 - -static void set_lid_gpi_mode(u32 mode) -{ - u32 reg32 = 0; - u16 reg16 = 0; - - /* read the GPI register, clear the lid GPI's mode, write the new mode - * and write out the register. - */ - outl(GPI_ROUT, 0xcf8); - reg32 = inl(0xcfc); - reg32 &= ~(0x03 << (EC_LID_GPI * 2)); - reg32 |= (mode << (EC_LID_GPI * 2)); - outl(GPI_ROUT, 0xcf8); - outl(reg32, 0xcfc); - - /* Set or Disable Lid GPE as SMI source in the ALT_GPI_SMI_EN register. */ - reg16 = inw(smm_get_pmbase() + ALT_GP_SMI_EN); - if (mode == GPI_IS_SCI) { - reg16 &= ~(1 << EC_LID_GPI); - } else { - reg16 |= (1 << EC_LID_GPI); - } - outw(reg16, smm_get_pmbase() + ALT_GP_SMI_EN); - - return; -} - int mainboard_io_trap_handler(int smif) { printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif); @@ -200,8 +162,7 @@ int mainboard_smi_apmc(u8 apmc) ec_kbc_write_ib(0xE8); /* Set LID GPI to generate SCIs */ - set_lid_gpi_mode(GPI_IS_SCI); - + gpi_route_interrupt(EC_LID_GPI, GPI_IS_SCI); break; case APMC_ACPI_DIS: printk(BIOS_DEBUG, "APMC: ACPI_DIS\n"); @@ -211,7 +172,7 @@ int mainboard_smi_apmc(u8 apmc) ec_kbc_write_ib(0xE9); /* Set LID GPI to generate SMIs */ - set_lid_gpi_mode(GPI_IS_SMI); + gpi_route_interrupt(EC_LID_GPI, GPI_IS_SMI); break; } return 0; diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index 6c80573..80a4e80 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_H8SCI 12 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -116,25 +119,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -143,12 +133,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -179,16 +164,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index bb3ad78..18fac5d 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_H8SCI 12 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -103,7 +106,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -111,25 +114,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -138,12 +128,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -174,16 +159,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index 6f6cca1..fe7cd65 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_H8SCI 12 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -116,25 +119,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -143,12 +133,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -179,16 +164,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 36495dc..d3ada43 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -28,6 +28,8 @@ #include "dock.h" #include "smi.h" +#define GPE_H8SCI 12 + #define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */ /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler @@ -154,41 +156,25 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi) { - if (gpi & (1 << 12)) + if (gpi & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); - - if (!pmbase) - return 0; - switch(data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); break; default: break; diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 7af613b..de40cea 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -34,6 +34,9 @@ #include "dock.h" #include "smi.h" +#define GPE_H8SCI 1 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -137,7 +140,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 1)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -145,15 +148,6 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "APMC: FINALIZE\n"); @@ -173,11 +167,7 @@ int mainboard_smi_apmc(u8 data) /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -186,12 +176,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -207,16 +192,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 6f6cca1..fe7cd65 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_H8SCI 12 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -116,25 +119,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -143,12 +133,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -179,16 +164,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index 6f6cca1..f8b723b 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -33,6 +33,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> + +#define GPE_H8SCI 12 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -108,7 +112,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } @@ -116,25 +120,12 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -143,12 +134,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, - pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -179,16 +165,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - u32 gpe_rout; - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); - gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } } diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index ccc328e..054400e 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -31,6 +31,8 @@ #include "dock.h" #include "smi.h" +#define GPE_H8SCI 12 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -160,30 +162,18 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi) { - if (gpi & (1 << 12)) + if (gpi & (1 << GPE_H8SCI)) mainboard_smi_handle_ec_sci(); } int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); - - if (!pmbase) - return 0; - switch(data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -192,11 +182,7 @@ int mainboard_smi_apmc(u8 data) provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + gpi_route_interrupt(GPE_H8SCI, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index f04ff90..eda17f3 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -31,6 +31,9 @@ #include <pc80/mc146818rtc.h> #include <delay.h> +/* This GPI is not confirmed. */ +#define MS2290_ENABLE_GPI12 1 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -69,15 +72,6 @@ static int mainboard_finalized = 0; int mainboard_smi_apmc(u8 data) { - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - u8 tmp; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - switch (data) { case APM_CNT_FINALIZE: printk(BIOS_DEBUG, "APMC: FINALIZE\n"); @@ -94,16 +88,12 @@ int mainboard_smi_apmc(u8 data) mainboard_finalized = 1; break; case APM_CNT_ACPI_ENABLE: - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + if (MS2290_ENABLE_GPI12) + gpi_route_interrupt(12, GPI_IS_SCI); break; case APM_CNT_ACPI_DISABLE: - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); - tmp &= ~0x03; - tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + if (MS2290_ENABLE_GPI12) + gpi_route_interrupt(12, GPI_IS_SMI); break; default: break; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 11b765a..98f13be 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -167,7 +167,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7cde7bc..c0a6c56 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -66,6 +66,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void gpi_route_interrupt(u8 gpi, u8 mode); #if CONFIG_ELOG void pch_log_state(void); #endif @@ -142,7 +143,12 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ + #define GPIO_ROUT 0xb8 +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 45612d0..8f69af9 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -75,6 +75,42 @@ void tseg_relocate(void **ptr) } #endif +static void alt_gpi_mask(u16 clr, u16 set) +{ + u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); + alt_gp &= ~clr; + alt_gp |= set; + outw(alt_gp, pmbase + ALT_GP_SMI_EN); +} + +static void gpe0_mask(u32 clr, u32 set) +{ + u32 gpe0 = inl(pmbase + GPE0_EN); + gpe0 &= ~clr; + gpe0 |= set; + outl(gpe0, pmbase + GPE0_EN); +} + +void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + if (gpi >= 16) + return; + + alt_gpi_mask(1 << gpi, 0); + gpe0_mask(1 << (gpi+16), 0); + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); + + if (mode == GPI_IS_SCI) + gpe0_mask(0, 1 << (gpi+16)); + else if (mode == GPI_IS_SMI) + alt_gpi_mask(0, 1 << gpi); +} + /** * @brief read and clear PM1_STS * @return PM1_STS register diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index f9961f9..6b95d08 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -185,7 +185,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index ee13b7d..c436209 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -41,6 +41,7 @@ #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); +void gpi_route_interrupt(u8 gpi, u8 mode); #else void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); @@ -74,6 +75,12 @@ int southbridge_detect_s3_resume(void); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 +#define GPIO_ROUT 0xb8 +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 6b9d11e..aae0be6 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -158,7 +158,7 @@ static void i82801gx_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void i82801gx_power_options(device_t dev) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index e2505ce..fb439c6 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -50,6 +50,42 @@ u8 smm_initialized = 0; */ global_nvs_t *gnvs = (global_nvs_t *)0x0; +static void alt_gpi_mask(u16 clr, u16 set) +{ + u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); + alt_gp &= ~clr; + alt_gp |= set; + outw(alt_gp, pmbase + ALT_GP_SMI_EN); +} + +static void gpe0_mask(u32 clr, u32 set) +{ + u32 gpe0 = inl(pmbase + GPE0_EN); + gpe0 &= ~clr; + gpe0 |= set; + outl(gpe0, pmbase + GPE0_EN); +} + +void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + if (gpi >= 16) + return; + + alt_gpi_mask(1 << gpi, 0); + gpe0_mask(1 << (gpi+16), 0); + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); + + if (mode == GPI_IS_SCI) + gpe0_mask(0, 1 << (gpi+16)); + else if (mode == GPI_IS_SMI) + alt_gpi_mask(0, 1 << gpi); +} + /** * @brief read and clear PM1_STS * @return PM1_STS register diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2124711..7ccc00b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -166,7 +166,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index bd94689..4840a1a 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -67,6 +67,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void gpi_route_interrupt(u8 gpi, u8 mode); #if CONFIG_ELOG void pch_log_state(void); #endif @@ -129,7 +130,12 @@ void southbridge_configure_default_intmap(void); #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ + #define GPIO_ROUT 0xb8 +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e2032ad..95530c4 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -75,6 +75,42 @@ void tseg_relocate(void **ptr) } #endif +static void alt_gpi_mask(u16 clr, u16 set) +{ + u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN); + alt_gp &= ~clr; + alt_gp |= set; + outw(alt_gp, pmbase + ALT_GP_SMI_EN); +} + +static void gpe0_mask(u32 clr, u32 set) +{ + u32 gpe0 = inl(pmbase + GPE0_EN); + gpe0 &= ~clr; + gpe0 |= set; + outl(gpe0, pmbase + GPE0_EN); +} + +void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + if (gpi >= 16) + return; + + alt_gpi_mask(1 << gpi, 0); + gpe0_mask(1 << (gpi+16), 0); + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); + + if (mode == GPI_IS_SCI) + gpe0_mask(0, 1 << (gpi+16)); + else if (mode == GPI_IS_SMI) + alt_gpi_mask(0, 1 << gpi); +} + /** * @brief read and clear PM1_STS * @return PM1_STS register diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 563cb0a..c551c8b 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -175,7 +175,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev)

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Patch merged into coreboot/master: aa3dd5d inteltool: add `-s` to dump spi bar and bios_cntl registers
by gerrit＠coreboot.org 08 Jan '15

08 Jan '15

the following patch was just integrated into master: commit aa3dd5d5db2bb3a9825a3c5104f28699f7b43f87 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Jan 3 02:52:10 2015 +0100 inteltool: add `-s` to dump spi bar and bios_cntl registers Change-Id: I3bb5dc23885af8c992456ee5e4bd374cd4b813bf Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: http://review.coreboot.org/8049 Reviewed-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8049 for details. -gerrit

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coreboot-gerrit January 2015