coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: c253189 samus: Updates from P2 build
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit c25318938fd9b86969057f3b4e741b949624ec41 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jun 18 14:03:08 2014 +0800 samus: Updates from P2 build - SPD GPIO table was changed from earlier builds and GPIO67 needs to be swapped with GPIO69 - Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD - Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround - In order to support both P2A and P2B with one firmware image we need to read the EC board version and use the right SPD GPIO for bit3 - Touchpad I2C address changed to 0x4a/0x26 BUG=chrome-os-partner:29502 BRANCH=None TEST=boot on P2A and P2B boards Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204818 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d Reviewed-on: http://review.coreboot.org/8135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8135 for details. -gerrit

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Patch merged into coreboot/master: bb0d5ef x86: Initialize drivers in SMM context if needed
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit bb0d5ef97a10bada5310ec7fc4faf53a15e98e71 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jun 19 15:39:29 2014 -0700 x86: Initialize drivers in SMM context if needed This adds a block in the SMI handler to call init functions for drivers which may be used in SMM. A static variable is used to ensure the init functions are only called once. BUG=chrome-os-partner:29580 BRANCH=mccloud TEST=Built and booted on mccloud, system no longer hangs when pressing power button at the dev mode screen. Also tested on parrot. Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I225f572f7b3072bec2bc06aac3fb50d90a2e30ee Original-Reviewed-on: https://chromium-review.googlesource.com/204764 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 9315c485deb5f24df753e2d69f4819b2cb6accc2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8d2b21765c35c7ac7746986d5334dca17dcd6861 Reviewed-on: http://review.coreboot.org/8134 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8134 for details. -gerrit

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Patch merged into coreboot/master: 990a592 samus: Enable EC ALS device
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit 990a592c1d2a58753decc72a75820177d92b555f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jun 13 10:36:34 2014 -0700 samus: Enable EC ALS device Enable the ACPI Device for the EC ALS. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: I9e957464f835d5bd96d4806f896ac60db9dea5dc Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203744 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit a4f78b0b78c53bc0397d9a21dd8f3fa040f41616) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib83d6211d323770c9498180a7721d45e4aefca9d Reviewed-on: http://review.coreboot.org/8133 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8133 for details. -gerrit

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Patch merged into coreboot/master: 612163eb chrome ec: Add ACPI Device for ALS if enabled
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit 612163ebaae60b0bc724324abb882f995072b104 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jun 13 10:35:22 2014 -0700 chrome ec: Add ACPI Device for ALS if enabled The EC can export ALS information if the sensor is attached to it directly rather than to the host. This adds a basic ACPI ALS device and implements the required information. The kernel does not use the _ALR tuple set but it is required by the ACPI spec so this just adds the sample two point response curve defined in ACPI 5.0 section 9.2.5. The EC does not currently send events for lux value changes so a polling interval of 1 second is defined. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: Id29b72a68aa21c1a7c71d5f87223ac010cef0377 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203743 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 81f44b33b87a6ee3079b8ef6efffacd0eeb0283f) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5a0ccd30e8b453675beaf7d0363dbfa162bd5b3f Reviewed-on: http://review.coreboot.org/8132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8132 for details. -gerrit

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Patch merged into coreboot/master: a416f21 samus: Updates for P2 board
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit a416f212dcf57e33d633516bf39ca1a9e97848e6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 10 10:06:46 2014 -0700 samus: Updates for P2 board - RAM ID3 moved to GPIO65 to avoid Top Block Swap strap on GPIO66 - LTE_POWER_ON connection removed BUG=chrome-os-partner:29502 BRANCH=None TEST=none yet, preparing for new board Original-Change-Id: I521fe963cbed57ef5f56cfb0e89aec50bfc48b21 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203186 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 1eb65e058307a172f0af9c27d2d2d87d1b78c514) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ibf16dcfd83242c487232f34a310c9f6b2cb69314 Reviewed-on: http://review.coreboot.org/8131 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8131 for details. -gerrit

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Patch set updated for coreboot: ece588c libpayload: Add Rock Chip drivers
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8127 -gerrit commit ece588c53a684287e3e0126438c46265111a8c4b Author: huang lin <hl(a)rock-chips.com> Date: Fri Jun 20 11:34:46 2014 +0800 libpayload: Add Rock Chip drivers Add support: 1)Support driver rktimer 2)Support driver rkserial BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Original-Change-Id: I2cccedf3b62883dd372842a7972e93f2ebbfb282 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206184 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 387450d7c36b201bd177d46eb9f1d280fc043aab) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia6b7a8ee2439a6f2bf7577df822d3f4f3a1e441c --- payloads/libpayload/Config.in | 12 +++ payloads/libpayload/configs/config.arm64-generic | 1 + payloads/libpayload/configs/defconfig | 5 +- payloads/libpayload/configs/defconfig-arm | 4 +- payloads/libpayload/drivers/Makefile.inc | 3 +- payloads/libpayload/drivers/serial/rk_serial.c | 115 +++++++++++++++++++++++ payloads/libpayload/drivers/timer/rktimer.c | 46 +++++++++ 7 files changed, 182 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index a0889c8..6c95bfa 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -199,6 +199,11 @@ config TEGRA_SERIAL_CONSOLE depends on SERIAL_CONSOLE default n +config RK_SERIAL_CONSOLE + bool "Rockchip SOC serial port driver" + depends on SERIAL_CONSOLE + default n + config IPQ806X_SERIAL_CONSOLE bool "IPQ806x SOC compatible serial port driver" depends on SERIAL_CONSOLE @@ -383,6 +388,8 @@ config TIMER_TEGRA_1US config TIMER_IPQ806X bool "Timer for ipq806x platforms" +config TIMER_RK + bool "Timer for Rockchip" endchoice config TIMER_MCT_HZ @@ -395,6 +402,11 @@ config TIMER_MCT_ADDRESS depends on TIMER_MCT default 0x101c0000 +config TIMER_RK_ADDRESS + hex "Rockchip timer base address" + depends on TIMER_RK + default 0xff810020 + config TIMER_TEGRA_1US_ADDRESS hex "Tegra u1s timer base address" depends on TIMER_TEGRA_1US diff --git a/payloads/libpayload/configs/config.arm64-generic b/payloads/libpayload/configs/config.arm64-generic index 97d865b..c2285fe 100644 --- a/payloads/libpayload/configs/config.arm64-generic +++ b/payloads/libpayload/configs/config.arm64-generic @@ -48,6 +48,7 @@ CONFIG_LP_TIMER_NONE=y # CONFIG_LP_TIMER_MCT is not set # CONFIG_LP_TIMER_TEGRA_1US is not set # CONFIG_LP_TIMER_IPQ806X is not set +# CONFIG_LP_TIMER_RK is not set CONFIG_LP_USB=y # CONFIG_LP_USB_OHCI is not set CONFIG_LP_USB_EHCI=y diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 1fbd961..a09a78c 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.2.0 -# Wed Dec 31 11:36:31 2014 +# Mon Jan 5 15:27:43 2015 # # @@ -17,8 +17,8 @@ # Architecture Options # # CONFIG_LP_ARCH_ARM is not set -# CONFIG_LP_ARCH_ARM64 is not set CONFIG_LP_ARCH_X86=y +# CONFIG_LP_ARCH_ARM64 is not set # CONFIG_LP_MEMMAP_RAM_ONLY is not set # CONFIG_LP_MULTIBOOT is not set @@ -41,6 +41,7 @@ CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_8250_SERIAL_CONSOLE=y # CONFIG_LP_S5P_SERIAL_CONSOLE is not set # CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set +# CONFIG_LP_RK_SERIAL_CONSOLE is not set # CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set # CONFIG_LP_PL011_SERIAL_CONSOLE is not set CONFIG_LP_SERIAL_IOBASE=0x3f8 diff --git a/payloads/libpayload/configs/defconfig-arm b/payloads/libpayload/configs/defconfig-arm index 862443d..b765422 100644 --- a/payloads/libpayload/configs/defconfig-arm +++ b/payloads/libpayload/configs/defconfig-arm @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.2.0 -# Mon Jan 5 15:06:15 2015 +# Mon Jan 5 15:28:18 2015 # # @@ -40,6 +40,7 @@ CONFIG_LP_SERIAL_CONSOLE=y # CONFIG_LP_8250_SERIAL_CONSOLE is not set # CONFIG_LP_S5P_SERIAL_CONSOLE is not set # CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set +# CONFIG_LP_RK_SERIAL_CONSOLE is not set # CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set # CONFIG_LP_SERIAL_SET_SPEED is not set # CONFIG_LP_SERIAL_ACS_FALLBACK is not set @@ -59,6 +60,7 @@ CONFIG_LP_TIMER_NONE=y # CONFIG_LP_TIMER_MCT is not set # CONFIG_LP_TIMER_TEGRA_1US is not set # CONFIG_LP_TIMER_IPQ806X is not set +# CONFIG_LP_TIMER_RK is not set CONFIG_LP_USB=y CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 538a8a6..0fc2faa 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -37,7 +37,7 @@ libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial/8250.c libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c libc-$(CONFIG_LP_TEGRA_SERIAL_CONSOLE) += serial/tegra.c libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c - +libc-$(CONFIG_LP_RK_SERIAL_CONSOLE) += serial/rk_serial.c libc-$(CONFIG_LP_PC_KEYBOARD) += keyboard.c libc-$(CONFIG_LP_CBMEM_CONSOLE) += cbmem_console.c @@ -50,6 +50,7 @@ libc-$(CONFIG_LP_TIMER_MCT) += timer/mct.c libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c libc-$(CONFIG_LP_TIMER_TEGRA_1US) += timer/tegra_1us.c libc-$(CONFIG_LP_TIMER_IPQ806X) += timer/ipq806x.c +libc-$(CONFIG_LP_TIMER_RK) += timer/rktimer.c # Video console drivers libc-$(CONFIG_LP_VIDEO_CONSOLE) += video/video.c diff --git a/payloads/libpayload/drivers/serial/rk_serial.c b/payloads/libpayload/drivers/serial/rk_serial.c new file mode 100644 index 0000000..91a6e1b --- /dev/null +++ b/payloads/libpayload/drivers/serial/rk_serial.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Rockchip Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <libpayload-config.h> +#include <libpayload.h> +struct rk_uart { + union { + u32 uart_thr; /* Transmit holding register. */ + u32 uart_rbr; /* Receive buffer register. */ + u32 uart_dll; /* Divisor latch lsb. */ + }; + union { + u32 uart_ier; /* Interrupt enable register. */ + u32 uart_dlh; /* Divisor latch msb. */ + }; + union { + uint32_t uart_iir; /* Interrupt identification register. */ + uint32_t uart_fcr; /* FIFO control register. */ + }; + u32 uart_lcr; + u32 uart_mcr; + u32 uart_lsr; + u32 uart_msr; + u32 uart_scr; + u32 reserved1[(0x30 - 0x20) / 4]; + u32 uart_srbr[(0x70 - 0x30) / 4]; + u32 uart_far; + u32 uart_tfr; + u32 uart_rfw; + u32 uart_usr; + u32 uart_tfl; + u32 uart_rfl; + u32 uart_srr; + u32 uart_srts; + u32 uart_sbcr; + u32 uart_sdmam; + u32 uart_sfe; + u32 uart_srt; + u32 uart_stet; + u32 uart_htx; + u32 uart_dmasa; + u32 reserver2[(0xf4 - 0xac) / 4]; + u32 uart_cpr; + u32 uart_ucv; + u32 uart_ctr; +}; +enum { + UART_LSR_DR = 0x1 << 0, /* Data ready. */ + UART_LSR_OE = 0x1 << 1, /* Overrun. */ + UART_LSR_PE = 0x1 << 2, /* Parity error. */ + UART_LSR_FE = 0x1 << 3, /* Framing error. */ + UART_LSR_BI = 0x1 << 4, /* Break. */ + UART_LSR_THRE = 0x1 << 5, /* Xmit holding register empty. */ + UART_LSR_TEMT = 0x1 << 6, /* Xmitter empty. */ + UART_LSR_ERR = 0x1 << 7 /* Error. */ +}; + +static struct rk_uart *uart_regs; +void serial_putchar(unsigned int c) +{ + while (!(readl(&uart_regs->uart_lsr) & UART_LSR_THRE)); + writel((c & 0xff), &uart_regs->uart_thr); + if (c == '\n') + serial_putchar('\r'); +} + +int serial_havechar(void) +{ + uint8_t lsr = readl(&uart_regs->uart_lsr); + return (lsr & UART_LSR_DR) == UART_LSR_DR; +} + +int serial_getchar(void) +{ + while (!serial_havechar()); + return readl(&uart_regs->uart_rbr)&0xff; +} + +static struct console_input_driver consin = { + .havekey = &serial_havechar, + .getchar = &serial_getchar +}; + +static struct console_output_driver consout = {.putchar = &serial_putchar +}; + +void serial_init(void) +{ + if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) + return; + + uart_regs = (struct rk_uart *)lib_sysinfo.serial->baseaddr; +} + +void serial_console_init(void) +{ + serial_init(); + console_add_input_driver(&consin); + console_add_output_driver(&consout); +} diff --git a/payloads/libpayload/drivers/timer/rktimer.c b/payloads/libpayload/drivers/timer/rktimer.c new file mode 100644 index 0000000..040ac32 --- /dev/null +++ b/payloads/libpayload/drivers/timer/rktimer.c @@ -0,0 +1,46 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Rockchip Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <arch/io.h> +#include <libpayload.h> +#include <stdint.h> +struct rk_timer { + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_curr_value0; + u32 timer_curr_value1; + u32 timer_ctrl_reg; + u32 timer_int_status; +}; + +uint64_t timer_hz(void) +{ + return 24000000; +} + +uint64_t timer_raw_value(void) +{ + uint64_t upper; + uint64_t lower; + struct rk_timer *rk_timer; + rk_timer = (struct rk_timer *) CONFIG_LP_TIMER_RK_ADDRESS; + lower = (uint64_t) rk_timer->timer_curr_value0; + upper = (uint64_t) rk_timer->timer_curr_value1; + return (upper << 32) | lower; +}

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Patch set updated for coreboot: b631d12 libpayload: Expand setbits_le32() and fix readl() const-ness
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8129 -gerrit commit b631d12cea33726caffbce2906df2e388bcccf09 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jul 17 10:43:15 2014 -0700 libpayload: Expand setbits_le32() and fix readl() const-ness setbits_le32() is not really arch-specific... the arch-specific part of accessing memory is wrapped by readl() and writel(), and the endianness can be accounted for with the right macros. Generalize the definitions, add a be32 version and move them to endian.h so that all platforms can use them. Also include endian.h from libpayload.h so we won't update any payload's old use of the macros (endianness is something useful enough to always have avalable anyway, and shouldn't clash with other things). This also fixes a bug where these macros would only be available if libpayload-config.h had been independently included before. Also fix a bug with readl() macros on all archs where they refused to work on const pointers (which they should). CQ-DEPEND=CL:208712 BUG=None TEST=Stuff still compiles. Built and booted on Storm. Original-Change-Id: I01a7fbadbb5d740675657d95c1e969027562ba8c Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208713 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 951f8a6d77bc21bd793bf4f228a0965ade586f00) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I51c25f01b200b91abbe32c879905349bb05dc9c8 --- payloads/libpayload/include/arm/arch/io.h | 24 ++++++------------------ payloads/libpayload/include/arm64/arch/io.h | 12 ++++++------ payloads/libpayload/include/endian.h | 17 +++++++++++++++++ payloads/libpayload/include/libpayload.h | 1 + payloads/libpayload/include/x86/arch/io.h | 6 +++--- 5 files changed, 33 insertions(+), 27 deletions(-) diff --git a/payloads/libpayload/include/arm/arch/io.h b/payloads/libpayload/include/arm/arch/io.h index 5cb66dc..4b0a687 100644 --- a/payloads/libpayload/include/arm/arch/io.h +++ b/payloads/libpayload/include/arm/arch/io.h @@ -34,22 +34,22 @@ #include <stdint.h> #include <arch/cache.h> -static inline uint8_t readb(volatile void *_a) +static inline uint8_t readb(volatile const void *_a) { dmb(); - return *(volatile uint8_t *)_a; + return *(volatile const uint8_t *)_a; } -static inline uint16_t readw(volatile void *_a) +static inline uint16_t readw(volatile const void *_a) { dmb(); - return *(volatile uint16_t *)_a; + return *(volatile const uint16_t *)_a; } -static inline uint32_t readl(volatile void *_a) +static inline uint32_t readl(volatile const void *_a) { dmb(); - return *(volatile uint32_t *)_a; + return *(volatile const uint32_t *)_a; } static inline void writeb(uint8_t _v, volatile void *_a) @@ -73,17 +73,5 @@ static inline void writel(uint32_t _v, volatile void *_a) dmb(); } -/* - * Handy bit manipulation macros, BE version will have to be added when/if - * needed. - */ - -#ifdef CONFIG_LP_LITTLE_ENDIAN -#define clrsetbits_le32(addr, clear, set) writel((readl(addr) & ~(clear)) |\ - (set), (addr)) -#define setbits_le32(addr, set) writel(readl(addr) | (set), (addr)) -#define clrbits_le32(addr, clear) writel(readl(addr) & ~(clear), (addr)) -#endif - #endif diff --git a/payloads/libpayload/include/arm64/arch/io.h b/payloads/libpayload/include/arm64/arch/io.h index 8948e13..df3a0d5 100644 --- a/payloads/libpayload/include/arm64/arch/io.h +++ b/payloads/libpayload/include/arm64/arch/io.h @@ -34,22 +34,22 @@ #include <stdint.h> #include <arch/cache.h> -static inline uint8_t readb(volatile void *_a) +static inline uint8_t readb(volatile const void *_a) { dmb(); - return *(volatile uint8_t *)_a; + return *(volatile const uint8_t *)_a; } -static inline uint16_t readw(volatile void *_a) +static inline uint16_t readw(volatile const void *_a) { dmb(); - return *(volatile uint16_t *)_a; + return *(volatile const uint16_t *)_a; } -static inline uint32_t readl(volatile void *_a) +static inline uint32_t readl(volatile const void *_a) { dmb(); - return *(volatile uint32_t *)_a; + return *(volatile const uint32_t *)_a; } static inline void writeb(uint8_t _v, volatile void *_a) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index dd4d9fa..3b79393 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -30,6 +30,7 @@ #ifndef _ENDIAN_H_ #define _ENDIAN_H_ +#include <arch/io.h> #include <arch/types.h> #include <libpayload-config.h> @@ -178,4 +179,20 @@ static inline void le32enc(void *pp, uint32_t u) #define letohl(in) le32toh(in) #define letohll(in) le64toh(in) +/* Handy bit manipulation macros */ + +#define clrsetbits_le32(addr, clear, set) writel(htole32((le32toh(readl(addr)) \ + & ~(clear)) | (set)), (addr)) +#define setbits_le32(addr, set) writel(htole32(le32toh(readl(addr)) \ + | (set)), (addr)) +#define clrbits_le32(addr, clear) writel(htole32(le32toh(readl(addr)) \ + & ~(clear)), (addr)) + +#define clrsetbits_be32(addr, clear, set) writel(htobe32((be32toh(readl(addr)) \ + & ~(clear)) | (set)), (addr)) +#define setbits_be32(addr, set) writel(htobe32(be32toh(readl(addr)) \ + | (set)), (addr)) +#define clrbits_be32(addr, clear) writel(htobe32(be32toh(readl(addr)) \ + & ~(clear)), (addr)) + #endif /* _ENDIAN_H_ */ diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 21b9da7..5bdd55d 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -46,6 +46,7 @@ #include <libpayload-config.h> #include <ctype.h> #include <die.h> +#include <endian.h> #include <ipchksum.h> #include <stddef.h> #include <stdio.h> diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h index bcfd307..0cb610f 100644 --- a/payloads/libpayload/include/x86/arch/io.h +++ b/payloads/libpayload/include/x86/arch/io.h @@ -31,9 +31,9 @@ #ifndef _ARCH_IO_H #define _ARCH_IO_H -#define readb(_a) (*(volatile unsigned char *) (_a)) -#define readw(_a) (*(volatile unsigned short *) (_a)) -#define readl(_a) (*(volatile unsigned long *) (_a)) +#define readb(_a) (*(volatile const unsigned char *) (_a)) +#define readw(_a) (*(volatile const unsigned short *) (_a)) +#define readl(_a) (*(volatile const unsigned long *) (_a)) #define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) #define writew(_v, _a) (*(volatile unsigned short *) (_a) = (_v))

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Patch set updated for coreboot: b43e84b libpayload: improve us timer accuracy
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8128 -gerrit commit b43e84b84dbe57fd2d608e174e9e2a06cf81eb29 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Jul 10 12:49:46 2014 -0700 libpayload: improve us timer accuracy In cases where timer clock frequency is not an integer number of megahertz, the calculations in timer_us() lack accuracy. This patch modifies calculations to reduce the error. The maximum interval this calculation would support decreases, but it still is in excess of 1844674 seconds for a timer clocked by 10 MHz, which is more than enough. BUG=none TEST=manual . verified timer accuracy using a depthcharge CLI command Original-Change-Id: Iffb323db10e74b0ce3b4d59a56983bfee12e6805 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207358 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit e1abf87d438de1a04714482d5b610671e8cc0663) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia892726187ab040dd235f493c92856c15951cc06 --- payloads/libpayload/libc/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index 0d81634..8d07c4f 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -204,5 +204,5 @@ u64 timer_us(u64 base) } } - return timer_raw_value() / (hz / 1000000) - base; + return (1000000 * timer_raw_value()) / hz - base; }

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Patch set updated for coreboot: f11b9b7 libpayload: Let GDB stub read/write memory with aligned MMIO words
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8130 -gerrit commit f11b9b75df337ba8479bdb1707f77d33b38ed11a Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Jul 16 18:39:58 2014 -0700 libpayload: Let GDB stub read/write memory with aligned MMIO words Looks like we got our first SoC that actually insists on using word-sized accesses for its MMIO registers with the Rk3288. This patch changes the GDB command handler for reading and writing memory to always perform word-sized accesses. This isn't really perfect since the remote GDB interface is just not really meant to interact with MMIO (e.g. you shouldn't use this on something with read side effects), but for most of our purposes it should be good enough. BUG=chrome-os-partner:18390 TEST=Remote GDB works on Veyron even when writing MMIO registers. Original-Change-Id: I2ae52636593499f70701582811f1b692c1ea8fcc Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208554 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 028940934e6b45a02122b61bb859588bf8671938) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4185a6efe9a5211525781acd0a167b821e854211 --- payloads/libpayload/gdb/transport.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/payloads/libpayload/gdb/transport.c b/payloads/libpayload/gdb/transport.c index 596ceb5..22983e1 100644 --- a/payloads/libpayload/gdb/transport.c +++ b/payloads/libpayload/gdb/transport.c @@ -16,9 +16,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <endian.h> #include <gdb.h> #include <libpayload.h> +/* MMIO word size is not standardized, but *usually* 32 (even on ARM64) */ +typedef u32 mmio_word_t; + static const int timeout_us = 100 * 1000; static const char output_overrun[] = "GDB output buffer overrun (try " "increasing reply.size)!\n"; @@ -55,7 +59,7 @@ void gdb_transport_teardown(void) /* Hex digit character <-> number conversion (illegal chars undefined!). */ -static s8 from_hex(unsigned char c) +static u8 from_hex(unsigned char c) { static const s8 values[] = { -1, 10, 11, 12, 13, 14, 15, -1, @@ -74,30 +78,43 @@ static char to_hex(u8 v) return digits[v & 0xf]; } -/* Message encode/decode functions */ +/* Message encode/decode functions (must access whole aligned words for MMIO) */ void gdb_message_encode_bytes(struct gdb_message *message, const void *data, int length) { - const u8 *bytes = data; die_if(message->used + length * 2 > message->size, output_overrun); + const mmio_word_t *aligned = + (mmio_word_t *)ALIGN_DOWN((uintptr_t)data, sizeof(*aligned)); + mmio_word_t word = be32toh(readl(aligned++)); while (length--) { - message->buf[message->used++] = to_hex(*bytes >> 4); - message->buf[message->used++] = to_hex(*bytes & 0xf); - bytes++; + u8 byte = (word >> ((((void *)aligned - data) - 1) * 8)); + message->buf[message->used++] = to_hex(byte >> 4); + message->buf[message->used++] = to_hex(byte & 0xf); + if (length && ++data == (void *)aligned) + word = be32toh(readl(aligned++)); } } void gdb_message_decode_bytes(const struct gdb_message *message, int offset, void *data, int length) { - u8 *bytes = data; die_if(offset + 2 * length > message->used, "Decode overrun in GDB " "message: %.*s", message->used, message->buf); + mmio_word_t *aligned = + (mmio_word_t *)ALIGN_DOWN((uintptr_t)data, sizeof(*aligned)); + int shift = ((void *)(aligned + 1) - data) * 8; + mmio_word_t word = be32toh(readl(aligned)) >> shift; while (length--) { - *bytes = from_hex(message->buf[offset++]) << 4; - *bytes += from_hex(message->buf[offset++]); - bytes++; + word <<= 8; + word |= from_hex(message->buf[offset++]) << 4; + word |= from_hex(message->buf[offset++]); + if (++data - (void *)aligned == sizeof(*aligned)) + writel(htobe32(word), aligned++); + } + if (data != (void *)aligned) { + shift = ((void *)(aligned + 1) - data) * 8; + clrsetbits_be32(aligned, ~((1 << shift) - 1), word << shift); } }

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Patch merged into coreboot/master: dbadb1d libpayload: Reorder default memcpy, speed up memset and memcmp
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit dbadb1dd634c8c9419215ade0666a7fb69a4447b Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jun 12 10:28:57 2014 -0700 libpayload: Reorder default memcpy, speed up memset and memcmp The current default memcpy first copies single bytes to align the amount, then copies the rest as full words. In practice, the start of a buffer is much more likely to be word-aligned then the end, and aligned word access are usually more efficient. This patch reorders those accesses to first copy as many full words as possible and then finish the rest with byte accesses to optimize this common case. This fixes a data abort when using USB on ARM without CONFIG_GPL. Due to some limitations of how DMA memory is set up in coreboot on ARM, it currently does not support unaligned accesses. (This could be fixed with a more complicated patch, but it's usually not an issue... unless, of course, your memcpy happens to be braindead). Also add word-aligned accesses to memset and memcmp while I'm at it, and make memcmp's return value standard's compliant. BUG=chrome-os-partner:24957 TEST=Manual Original-Change-Id: I2a7bcb35626a05a9a43fcfd99eb958b485d7622a Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203547 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 05a64d2e107e1675cc3442e6dabe14a341e55673) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0030ca8a203c97587b0da31a0a5e9e11b0be050f Reviewed-on: http://review.coreboot.org/8126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8126 for details. -gerrit

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coreboot-gerrit January 2015