coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 0b5b541 AMD binaryPI 00730F01: Switch to per-device ACPI
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit 0b5b541373bd5853d2fd6093c32d46d8f6003dd0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 26 08:11:07 2014 +0200 AMD binaryPI 00730F01: Switch to per-device ACPI Change-Id: Iad31ae3e511c8ebacc973b2d8a8e3bfca719ee7c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7583 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7583 for details. -gerrit

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Patch merged into coreboot/master: dc35756 cpu/amd/pi: Use acpi_is_wakeup()
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit dc357566ea715cd5dedd277046ff58c36b622dfd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:44:30 2015 +0200 cpu/amd/pi: Use acpi_is_wakeup() Propagate commit 9107e53 from amd/agesa and fix some related #includes under cpu/amd/pi. Change test to return true on S2 wakeup too. In S2 CPU would have been powered down so MTRR recovery is required. Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8171 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/8171 for details. -gerrit

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Patch merged into coreboot/master: 6d28b91 amd/agesa/family12/northbridge.c: Indent (tab) fix
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit 6d28b91d3817c3bf411db07de7e34356bdebdb19 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 1 03:49:47 2015 +1100 amd/agesa/family12/northbridge.c: Indent (tab) fix Trivial; Use tab over space for indent. Change-Id: Iba0e006197a020157b11746dd4999d87a8ca8d97 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/8015 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8015 for details. -gerrit

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New patch to review for coreboot: c5811e6 intel: Drop romstage handoff via scratchpad
by Kyösti Mälkki 09 Jan '15

09 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8182 -gerrit commit c5811e6c8c139b4b9ab874e2792c442f7cfe5830 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 9 09:57:26 2015 +0200 intel: Drop romstage handoff via scratchpad If HAVE_ACPI_RESUME ever gets implemented, use CBMEM handoff instead. Change-Id: I77463988fa5324c729579902f4796be4da15d551 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- .../intel/fsp_sandybridge/northbridge.c | 21 -------------------- src/northbridge/intel/sch/northbridge.c | 23 ---------------------- 2 files changed, 44 deletions(-) diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index a95d736..adc69bc 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -329,26 +329,6 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case 0xcafed00d: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -358,7 +338,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index c552879..92c5467 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -250,26 +250,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -#if CONFIG_HAVE_ACPI_RESUME -static void northbridge_init(struct device *dev) -{ - switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; - case 0xcafed00d: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; - } -} -#endif - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -278,9 +258,6 @@ static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, -#if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, -#endif .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops,

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Patch set updated for coreboot: 9bdf9f1 ACPI: Fix S3 handoff state to ramstage
by Kyösti Mälkki 09 Jan '15

09 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8172 -gerrit commit 9bdf9f1fa5cad89f0c64d2575c96c1f93e7a7f88 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 07:33:50 2015 +0200 ACPI: Fix S3 handoff state to ramstage Global acpi_slp_type is now declared static. The change also guarantees it will always be initialized before use. Change-Id: I0f074bb80f06f6f0ddf4212cd8872e94ae57f949 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 17 +++------- src/arch/x86/include/arch/acpi.h | 22 ++++++------- src/mainboard/lenovo/t60/mainboard.c | 7 ++--- src/mainboard/lenovo/x201/mainboard.c | 5 ++- src/mainboard/lenovo/x60/mainboard.c | 7 ++--- src/northbridge/intel/gm45/northbridge.c | 31 +++++++++--------- src/northbridge/intel/haswell/northbridge.c | 11 +++---- src/northbridge/intel/i945/northbridge.c | 17 +++------- src/northbridge/intel/nehalem/northbridge.c | 15 +++------ src/northbridge/intel/sandybridge/northbridge.c | 15 +++------ src/soc/intel/baytrail/ramstage.c | 42 ++++++++++++++----------- src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/baytrail/xhci.c | 4 +-- src/soc/intel/broadwell/lpc.c | 4 +-- src/soc/intel/broadwell/me.c | 4 +-- src/soc/intel/broadwell/ramstage.c | 41 +++++++++++++----------- src/soc/intel/broadwell/refcode.c | 11 +------ src/soc/intel/broadwell/systemagent.c | 22 ------------- src/soc/intel/fsp_baytrail/ramstage.c | 33 ++++++++++--------- src/southbridge/amd/sb700/lpc.c | 17 ++++------ src/southbridge/intel/i82371eb/smbus.c | 11 ------- src/southbridge/intel/i82371eb/wakeup.c | 3 +- src/southbridge/via/vt8237r/lpc.c | 10 +++--- 23 files changed, 139 insertions(+), 212 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 61f0954..b5c22a4 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -854,22 +854,13 @@ void acpi_resume(void *wake_vec) acpi_jump_to_wakeup(wake_vec); } -/* This is to be filled by SB code - startup value what was found. */ -u8 acpi_slp_type = 0; - -int __attribute__((weak)) acpi_get_sleep_type(void) -{ - return 0; -} +/* This is filled with acpi_is_wakeup() call early in ramstage. */ +static int acpi_slp_type = -1; static void acpi_handoff_wakeup(void) { - static int once = 0; - if (once) - return; - - acpi_slp_type = acpi_get_sleep_type(); - once = 1; + if (acpi_slp_type < 0) + acpi_slp_type = acpi_get_sleep_type(); } int acpi_is_wakeup(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 502c826..e748e95 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -559,14 +559,10 @@ unsigned long acpi_fill_hest(acpi_hest_t *hest); void acpi_save_gnvs(u32 gnvs_address); -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -/* 0 = S0, 1 = S1 ...*/ -extern u8 acpi_slp_type; - -int acpi_is_wakeup(void); -int acpi_is_wakeup_s3(void); -int acpi_is_wakeup_early(void); +/* cpu/intel/speedstep/acpi.c */ +void generate_cpu_entries(void); +/* For ACPI S3 resume support. */ void acpi_fail_wakeup(void); void acpi_resume(void *wake_vec); void acpi_prepare_resume_backup(void); @@ -575,19 +571,19 @@ void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr); +/* Returns 0 = S0, 1 = S1 ... */ int acpi_get_sleep_type(void); -#endif /* IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) */ - -/* cpu/intel/speedstep/acpi.c */ -void generate_cpu_entries(void); static inline int acpi_s3_resume_allowed(void) { return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); } -#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -#define acpi_slp_type 0 +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +int acpi_is_wakeup(void); +int acpi_is_wakeup_s3(void); +int acpi_is_wakeup_early(void); +#else static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_early(void) { return 0; } diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index abda9ea..6647970 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -22,12 +22,12 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <arch/io.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> @@ -69,13 +69,12 @@ const char *smbios_mainboard_bios_version(void) static void mainboard_init(device_t dev) { struct southbridge_intel_i82801gx_config *config; - device_t dev0, idedev; + device_t idedev; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 3cda4fa..40d52a4 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> @@ -116,7 +117,6 @@ static void fill_ssdt(void) static void mainboard_enable(device_t dev) { - device_t dev0; u16 pmbase; dev->ops->init = mainboard_init; @@ -136,8 +136,7 @@ static void mainboard_enable(device_t dev) 0x10); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 334c27d..778690b 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -22,13 +22,13 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <arch/interrupt.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> @@ -58,7 +58,7 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_init(device_t dev) { - device_t dev0, idedev, sdhci_dev; + device_t idedev, sdhci_dev; ec_clr_bit(0x03, 2); @@ -70,8 +70,7 @@ static void mainboard_init(device_t dev) install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index fc54a8c..5b7a563 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -220,28 +220,27 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; +int acpi_get_sleep_type(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + switch (pci_read_config32(dev, D0F0_SKPD)) { + case SKPAD_NORMAL_BOOT_MAGIC: + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + case SKPAD_ACPI_S3_MAGIC: + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + default: + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } +} static void enable_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..498cd0b 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -433,24 +433,22 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); if (handoff == NULL) { printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; + return 0; } else if (handoff->s3_resume) { printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; + return 3; } else { printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; + return 0; } -#endif } static struct pci_operations intel_pci_ops = { @@ -462,7 +460,6 @@ static struct device_operations mc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 1aaeb3b..d4e5ef2 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -232,25 +232,21 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -#if CONFIG_HAVE_ACPI_RESUME -static void northbridge_init(struct device *dev) +int acpi_get_sleep_type(void) { + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; + return 0; } } -#endif static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, @@ -261,9 +257,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, -#if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, -#endif .scan_bus = 0, .ops_pci = &intel_pci_ops, }; diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 2c4b1ff..21900e5 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -283,24 +283,20 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; + return 0; } -#endif } static struct pci_operations intel_pci_ops = { @@ -312,7 +308,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7159700..b96ce8b 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -412,24 +412,20 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; + return 0; } -#endif } static struct pci_operations intel_pci_ops = { @@ -441,7 +437,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..ab54049 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -130,13 +130,6 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) { @@ -163,25 +156,36 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) gnvs->pm1i); } +int acpi_get_sleep_type(void) +{ + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } +} + static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 5274b03..f6462fa 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -215,7 +215,7 @@ static void sc_init(device_t dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) com1_configure_resume(dev); } diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..19339e4 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -184,7 +184,7 @@ static void xhci_route_all(device_t dev) /* Route ports to XHCI controller */ reg_script_run_on_dev(dev, xhci_route_all_script); - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) return; /* Reset enabled USB3 ports */ @@ -222,7 +222,7 @@ static void xhci_init(device_t dev) }; /* Initialize XHCI controller for boot or resume path */ - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 394a9d7..c670440 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -394,7 +394,7 @@ static void pch_cg_init(device_t dev) static void pch_set_acpi_mode(void) { #if CONFIG_HAVE_SMI_HANDLER - if (acpi_slp_type != 3) { + if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); @@ -551,7 +551,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (acpi_slp_type != 3 && gnvs) + if (!acpi_is_wakeup_s3() && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); } diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 2bdb1ed..9fc6a41 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -830,13 +830,11 @@ static void intel_me_init(device_t dev) static void intel_me_enable(device_t dev) { -#if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { dev->enabled = 0; pch_disable_devfn(dev); } -#endif } static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 0563064..38f7b5d 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -54,31 +54,36 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) gnvs->pm1i); } -static inline void set_acpi_sleep_type(int val) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } } static void s3_resume_prepare(void) { - global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; + global_nvs_t *gnvs; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); - return; - } + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + if (gnvs == NULL) + return; - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void broadwell_init_pre_device(void *chip_info) diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index a745101..d66d036 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -30,15 +30,6 @@ #include <broadwell/pei_wrapper.h> #include <broadwell/ramstage.h> -static inline int is_s3_resume(void) -{ -#if CONFIG_HAVE_ACPI_RESUME - return acpi_slp_type == 3; -#else - return 0; -#endif -} - static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) { return (struct ramstage_cache *)&c->program[c->size]; @@ -136,7 +127,7 @@ static pei_wrapper_entry_t load_reference_code(void) }; int ret; - if (is_s3_resume()) { + if (acpi_is_wakeup_s3()) { return load_refcode_from_cache(); } diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 74c43f2..2e0a492 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -412,27 +412,6 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -451,7 +430,6 @@ static struct device_operations systemagent_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &systemagent_init, - .enable = &systemagent_enable, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..0b3db41 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -125,31 +125,34 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } - -static inline void set_acpi_sleep_type(int val) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } } static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - set_acpi_sleep_type(3); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); } void baytrail_init_pre_device(void) diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 8ebc765..658e954 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -29,7 +29,6 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> -#include <arch/acpi.h> #include <cbmem.h> #include <cpu/amd/powernow.h> #include "sb700.h" @@ -80,19 +79,15 @@ static void lpc_init(device_t dev) #endif pci_write_config8(dev, 0x78, byte); - /* hack, but the whole sb700 startup lacks any device which - is doing the acpi init */ -#if CONFIG_HAVE_ACPI_RESUME - { - u16 tmp = inw(ACPI_PM1_CNT_BLK); - acpi_slp_type = ((tmp & (7 << 10)) >> 10); - printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); - } -#endif - cmos_check_update_date(); } +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + return ((tmp & (7 << 10)) >> 10); +} + void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index d236cfa..6341751 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -31,11 +31,6 @@ #include "i82371eb.h" #include "smbus.h" -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -int acpi_get_sleep_type(void); -#endif - static void pwrmgt_enable(struct device *dev) { struct southbridge_intel_i82371eb_config *sb = dev->chip_info; @@ -92,12 +87,6 @@ static void pwrmgt_enable(struct device *dev) outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); -#if CONFIG_HAVE_ACPI_RESUME - /* this reads PMCNTRL, so we have to call it before writing the - * default value */ - acpi_slp_type = acpi_get_sleep_type(); -#endif - /* set PMCNTRL default */ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); } diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index dd4a28f..f9ca385 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -19,12 +19,11 @@ */ #include <stdint.h> +#include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> #include "i82371eb.h" -int acpi_get_sleep_type(void); - /* * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 * diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 92eaa39..d3e3d32 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -244,10 +244,6 @@ static void setup_pm(device_t dev) /* SCI is generated for RTC/pwrBtn/slpBtn. */ tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; - printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); -#endif /* All SMI on, both IDE buses ON, PSON rising edge. */ outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c); @@ -258,6 +254,12 @@ static void setup_pm(device_t dev) outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); } +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; +} + static void vt8237r_init(struct device *dev) { u8 enables;

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Patch set updated for coreboot: b04b233 cpu/amd/pi: Use acpi_is_wakeup()
by Kyösti Mälkki 09 Jan '15

09 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8171 -gerrit commit b04b233fd6f03fff06106ccbc7ddc4f9d54e9ccf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:44:30 2015 +0200 cpu/amd/pi: Use acpi_is_wakeup() Propagate commit 9107e53 from amd/agesa and fix some related #includes under cpu/amd/pi. Change test to return true on S2 wakeup too. In S2 CPU would have been powered down so MTRR recovery is required. Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00730F01/model_16_init.c | 8 ++------ src/cpu/amd/pi/heapmanager.c | 2 +- src/cpu/amd/pi/s3_resume.c | 2 +- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 8053fd1..336618a 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -33,9 +33,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam16.h> #include <arch/acpi.h> -#if CONFIG_HAVE_ACPI_RESUME -#include <cpu/amd/agesa/s3_resume.h> -#endif +#include <cpu/amd/pi/s3_resume.h> static void model_16_init(device_t dev) { @@ -72,10 +70,8 @@ static void model_16_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_slp_type == 3) + if (acpi_is_wakeup()) restore_mtrr(); -#endif x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index d2c3931..aa251e0 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -1,7 +1,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/pi/BiosCallOuts.h> #include "heapManager.h" #include <cbmem.h> diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index fc619f7..bc82964 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -31,7 +31,7 @@ #include <arch/acpi.h> #include <string.h> #include "Porting.h" -#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/pi/BiosCallOuts.h> #include "s3_resume.h" /* The size needs to be 4k aligned, which is the sector size of most flashes. */

1 0

Patch set updated for coreboot: c79b69b intel: Use defined ACPI S3 magic values
by Kyösti Mälkki 09 Jan '15

09 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8170 -gerrit commit c79b69ba7933bf86c8eecd9eff78f4d1209e63e5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 intel: Use defined ACPI S3 magic values Unify this, until converted to CBMEM romstage_handoff. Change-Id: I2fdf44b2f654242369a9d0983a2dfa9aad1669e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 4 ++-- src/mainboard/packardbell/ms2290/romstage.c | 4 ++-- src/northbridge/intel/nehalem/northbridge.c | 4 ++-- src/northbridge/intel/sandybridge/early_init.c | 4 ++-- src/northbridge/intel/sandybridge/northbridge.c | 4 ++-- src/northbridge/intel/sandybridge/sandybridge.h | 3 +++ 6 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 64011b1..b102993 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -305,9 +305,9 @@ void main(unsigned long bist) HIGH_MEMORY_SAVE); /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); quick_ram_check(); } #endif diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index a366d38..7ba02b4 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -289,9 +289,9 @@ void main(unsigned long bist) HIGH_MEMORY_SAVE); /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); quick_ram_check(); } #endif diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 11d335a..2c4b1ff 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -287,11 +287,11 @@ static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: + case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); acpi_slp_type = 0; break; - case 0xcafed00d: + case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); acpi_slp_type = 3; break; diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 3156f86..597d886 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -196,9 +196,9 @@ void northbridge_romstage_finalize(int s3resume) *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); } #endif } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 55395ea..7159700 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -416,11 +416,11 @@ static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: + case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); acpi_slp_type=0; break; - case 0xcafed00d: + case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); acpi_slp_type=3; break; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 0790ae8..ea760a9 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -99,6 +99,9 @@ #define SKPAD 0xdc /* Scratchpad Data */ +#define SKPAD_ACPI_S3_MAGIC 0xcafed00d +#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe + /* Device 0:1.0 PCI configuration space (PCI Express) */ #define BCTRL1 0x3e /* 16bit */

1 0

Patch merged into coreboot/master: f4ef77e tegra: i2c: re-init i2c controller after reset
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit f4ef77e8449338931a990cb35580dad584cc6053 Author: Jimmy Zhang <jimmzhang(a)nvidia.com> Date: Thu Jun 5 15:20:56 2014 -0700 tegra: i2c: re-init i2c controller after reset This serves as supplemental patch to CL:197732. After clearing bus, we should also redo controller init (because controller has been reset before bus clear). On the upper layer, upon receiving error return status, it should just retry instead of simply call cpu_reset(). BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Built and tested on nyan and nyan_big. Original-Change-Id: Ib526bc730cb73ffef8696fc2a6a2769d6e71eb9e Original-Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/202784 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 06f8917c70ddca88c847d0f15ebe7f286a3f6338) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1d8bc43d730b53fe7f2dad8713831311e96e3984 Reviewed-on: http://review.coreboot.org/8145 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8145 for details. -gerrit

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Patch set updated for coreboot: abd8199 cbmem: Add support for new 'coreboot' compatible device tree binding
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8141 -gerrit commit abd8199cfbb114549c75a81ac6e5100bb5a39a0b Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Jun 16 23:02:03 2014 -0700 cbmem: Add support for new 'coreboot' compatible device tree binding This patch brings the cbmem utility in line with the recent change to coreboot's device tree binding. Since trying to find the right node to place this binding has been so hard (and still isn't quite agreed upon), and because it's really the more correct thing to do, this code searches through the device tree for the 'coreboot' compatible property instead of looking up a hardcoded path. It also provides bullet-proof '#address-cells' handling that should work for any endianness and size. BUG=chrome-os-partner:29311 TEST=Ran cbmem -c and cbmem -t on Nyan_Big. Also straced the to make sure everything looks as expected. 'time cbmem -t' = ~35ms shows that there is no serious performance problem from the more thorough lookup code. Original-Change-Id: I806a21270ba6cec6e81232075749016eaf18508b Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204274 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit 3e64e28f684e60e8b300906c1abffee75ec6a5c2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0a0a4f69330d3d8c5c3ea92b55f5dde4d43fca65 --- util/cbmem/cbmem.c | 175 +++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 158 insertions(+), 17 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 1117c66..aa9fa13 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -24,6 +24,7 @@ #include <unistd.h> #include <inttypes.h> #include <getopt.h> +#include <dirent.h> #include <errno.h> #include <fcntl.h> #include <ctype.h> @@ -40,6 +41,7 @@ #include "boot/coreboot_tables.h" +typedef uint8_t u8; typedef uint16_t u16; typedef uint32_t u32; typedef uint64_t u64; @@ -54,7 +56,7 @@ static int verbose = 0; #define debug(x...) if(verbose) printf(x) /* File handle used to access /dev/mem */ -static int fd; +static int mem_fd; /* * calculate ip checksum (16 bit quantities) on a passed in buffer. In case @@ -118,7 +120,7 @@ static void *map_memory_size(u64 physical, size_t size) debug("Mapping %zuMB of physical memory at 0x%jx.\n", size_to_mib(size), (intmax_t)p); - v = mmap(NULL, size, PROT_READ, MAP_SHARED, fd, p); + v = mmap(NULL, size, PROT_READ, MAP_SHARED, mem_fd, p); if (v == MAP_FAILED) { fprintf(stderr, "Failed to mmap /dev/mem: %s\n", @@ -823,6 +825,121 @@ static void print_usage(const char *name) exit(1); } +#ifdef __arm__ +static void dt_update_cells(const char *name, int *addr_cells_ptr, + int *size_cells_ptr) +{ + if (*addr_cells_ptr >= 0 && *size_cells_ptr >= 0) + return; + + int buffer; + size_t nlen = strlen(name); + char *prop = alloca(nlen + sizeof("/#address-cells")); + strcpy(prop, name); + + if (*addr_cells_ptr < 0) { + strcpy(prop + nlen, "/#address-cells"); + int fd = open(prop, O_RDONLY); + if (fd < 0 && errno != ENOENT) { + perror(prop); + } else if (fd >= 0) { + if (read(fd, &buffer, sizeof(int)) < 0) + perror(prop); + else + *addr_cells_ptr = ntohl(buffer); + close(fd); + } + } + + if (*size_cells_ptr < 0) { + strcpy(prop + nlen, "/#size-cells"); + int fd = open(prop, O_RDONLY); + if (fd < 0 && errno != ENOENT) { + perror(prop); + } else if (fd >= 0) { + if (read(fd, &buffer, sizeof(int)) < 0) + perror(prop); + else + *size_cells_ptr = ntohl(buffer); + close(fd); + } + } +} + +static char *dt_find_compat(const char *parent, const char *compat, + int *addr_cells_ptr, int *size_cells_ptr) +{ + char *ret = NULL; + struct dirent *entry; + DIR *dir; + + if (!(dir = opendir(parent))) { + perror(parent); + return NULL; + } + + /* Loop through all files in the directory (DT node). */ + while ((entry = readdir(dir))) { + /* We only care about compatible props or subnodes. */ + if (entry->d_name[0] == '.' || !((entry->d_type & DT_DIR) || + !strcmp(entry->d_name, "compatible"))) + continue; + + /* Assemble the file name (on the stack, for speed). */ + size_t plen = strlen(parent); + char *name = alloca(plen + strlen(entry->d_name) + 2); + + strcpy(name, parent); + name[plen] = '/'; + strcpy(name + plen + 1, entry->d_name); + + /* If it's a subnode, recurse. */ + if (entry->d_type & DT_DIR) { + ret = dt_find_compat(name, compat, addr_cells_ptr, + size_cells_ptr); + + /* There is only one matching node to find, abort. */ + if (ret) { + /* Gather cells values on the way up. */ + dt_update_cells(parent, addr_cells_ptr, + size_cells_ptr); + break; + } + continue; + } + + /* If it's a compatible string, see if it's the right one. */ + int fd = open(name, O_RDONLY); + int clen = strlen(compat); + char *buffer = alloca(clen + 1); + + if (fd < 0) { + perror(name); + continue; + } + + if (read(fd, buffer, clen + 1) < 0) { + perror(name); + close(fd); + continue; + } + close(fd); + + if (!strcmp(compat, buffer)) { + /* Initialize these to "unset" for the way up. */ + *addr_cells_ptr = *size_cells_ptr = -1; + + /* Can't leave string on the stack or we'll lose it! */ + ret = strdup(parent); + break; + } + } + + closedir(dir); + return ret; +} +#endif /* __arm__ */ + int main(int argc, char** argv) { int print_defaults = 1; @@ -883,33 +1000,57 @@ int main(int argc, char** argv) } } - fd = open("/dev/mem", O_RDONLY, 0); - if (fd < 0) { + mem_fd = open("/dev/mem", O_RDONLY, 0); + if (mem_fd < 0) { fprintf(stderr, "Failed to gain memory access: %s\n", strerror(errno)); return 1; } #ifdef __arm__ - int dt_fd; - uint32_t cbtable_base; + int addr_cells, size_cells; + char *coreboot_node = dt_find_compat("/proc/device-tree", "coreboot", + &addr_cells, &size_cells); - dt_fd = open("/proc/device-tree/firmware/coreboot/coreboot-table", - O_RDONLY, 0); - if (dt_fd < 0) { - fprintf(stderr, "Failed to open device tree node: %s\n", - strerror(errno)); + if (!coreboot_node) { + fprintf(stderr, "Could not find 'coreboot' compatible node!\n"); return 1; } - if (read(dt_fd, &cbtable_base, 4) != 4) { - fprintf(stderr, "Failed to read device tree node: %s\n", - strerror(errno)); + if (addr_cells < 0) { + fprintf(stderr, "Warning: no #address-cells node in tree!\n"); + addr_cells = 1; + } + + int nlen = strlen(coreboot_node); + char *reg = alloca(nlen + sizeof("/reg")); + + strcpy(reg, coreboot_node); + strcpy(reg + nlen, "/reg"); + free(coreboot_node); + + int fd = open(reg, O_RDONLY); + if (fd < 0) { + perror(reg); + return 1; + } + + int i; + u8 *baseaddr_buffer = alloca(addr_cells * 4); + if (read(fd, baseaddr_buffer, addr_cells * 4) < 0) { + perror(reg); return 1; } - close(dt_fd); + close(fd); - parse_cbtable(ntohl(cbtable_base)); + /* No variable-length byte swap function anywhere in C... how sad. */ + u64 baseaddr = 0; + for (i = 0; i < addr_cells * 4; i++) { + baseaddr <<= 8; + baseaddr |= baseaddr_buffer[i]; + } + + parse_cbtable(baseaddr); #else int j; static const int possible_base_addresses[] = { 0, 0xf0000 }; @@ -936,6 +1077,6 @@ int main(int argc, char** argv) if (print_defaults || print_timestamps) dump_timestamps(); - close(fd); + close(mem_fd); return 0; }

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New patch to review for coreboot: 0053795 cbfs: add cbfs_read()
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8181 -gerrit commit 0053795fb7cb35e0d97f2b9b6c6cebdb54aba1e7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 27 15:28:39 2014 -0500 cbfs: add cbfs_read() Allow for reading from cbfs media without having a handle to a non-CBFS_DEFAULT_MEDIA cbfs_media. In conjunction with cbfs_locate_file() one can locate and cbfs_read() a file without bringing the entire file through a potentially temporary buffer (non-memory-mappable cbfs media platforms). BUG=chrome-os-partner:29922 BRANCH=None TEST=Built. Original-Change-Id: Ib5d965334bce1267650fc23c9e9f496675cf8450 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205991 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 85200f28863e5ea8888322f5787dc6de9a2999f0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I25e3221beefd0155305ad63da6be9f47e756f7d0 --- src/include/cbfs_core.h | 4 ++++ src/lib/cbfs_core.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index 3cef903..b01a307 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -224,6 +224,10 @@ struct cbfs_media { ssize_t cbfs_locate_file(struct cbfs_media *media, struct cbfs_file *file, const char *name); +/* Read count bytes at offset into dest. Return number of bytes read. */ +size_t cbfs_read(struct cbfs_media *media, void *dest, size_t offset, + size_t count); + /* returns pointer to a file entry inside CBFS or NULL */ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 24e5998..6455a07 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -194,6 +194,22 @@ ssize_t cbfs_locate_file(struct cbfs_media *media, struct cbfs_file *file, return -1; } +size_t cbfs_read(struct cbfs_media *media, void *dest, size_t offset, + size_t count) +{ + struct cbfs_media default_media; + size_t nread; + + if (init_media(&media, &default_media)) + return 0; + + media->open(media); + nread = media->read(media, dest, offset, count); + media->close(media); + + return nread; +} + struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) { struct cbfs_media default_media;

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coreboot-gerrit January 2015