coreboot-gerrit January 2015

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Patch set updated for coreboot: 4bfabf9 Re-factor 'to_flash_offset()' into 'spi_flash.h'
by Edward O'Callaghan 10 Jan '15

10 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8165 -gerrit commit 4bfabf94d72de62d63f73dbef9cebd523deb724e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:09:50 2014 +1000 Re-factor 'to_flash_offset()' into 'spi_flash.h' Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by Clang complaining that the function 'to_flash_offset' is unused. Change-Id: Ie2a8ac3cddac1cd87f1197efcd1bc9eb3189136e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/intel/fsp/fastboot_cache.c | 13 ++----------- src/include/spi_flash.h | 8 ++++++++ src/northbridge/intel/haswell/mrccache.c | 7 +------ src/northbridge/intel/sandybridge/mrccache.c | 7 +------ src/soc/intel/common/nvm.c | 10 ++-------- src/soc/intel/fsp_baytrail/nvm.c | 13 ++----------- 6 files changed, 16 insertions(+), 42 deletions(-) diff --git a/src/drivers/intel/fsp/fastboot_cache.c b/src/drivers/intel/fsp/fastboot_cache.c index 64982d8..907e143 100644 --- a/src/drivers/intel/fsp/fastboot_cache.c +++ b/src/drivers/intel/fsp/fastboot_cache.c @@ -31,15 +31,6 @@ #include <lib.h> // hexdump #include "fsp_util.h" -#ifndef CONFIG_VIRTUAL_ROM_SIZE -#error "CONFIG_VIRTUAL_ROM_SIZE must be set." -#endif - -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -205,7 +196,7 @@ void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -213,7 +204,7 @@ void update_mrc_cache(void *unused) /* 4. write mrc data with flash->write() */ printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); } diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index d697d8f..e0b1f0d 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -58,4 +58,12 @@ struct spi_flash { struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs); +#if !defined(__PRE_RAM__) +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + u32 size = CONFIG_VIRTUAL_ROM_SIZE ? CONFIG_VIRTUAL_ROM_SIZE : flash->size; + return ((u32)p + size); +} +#endif /* !defined(__PRE_RAM__) */ + #endif /* _SPI_FLASH_H_ */ diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 540bbf6..53da68e 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -226,7 +221,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..664fb7f 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -33,11 +33,6 @@ #include <vendorcode/google/chromeos/fmap.h> #endif -/* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { - return ((u32)p + flash->size); -} - static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) { @@ -227,7 +222,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) { diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 791422f..54b3baf 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -46,12 +46,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -70,7 +64,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - return flash->erase(flash, to_flash_offset(start), size); + return flash->erase(flash, to_flash_offset(flash, start), size); } /* Write data to NVM. Returns 0 on success < 0 on error. */ @@ -78,5 +72,5 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - return flash->write(flash, to_flash_offset(start), size, data); + return flash->write(flash, to_flash_offset(flash, start), size, data); } diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c index 0224463..d1e5223 100644 --- a/src/soc/intel/fsp_baytrail/nvm.c +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -47,15 +47,6 @@ static int nvm_init(void) return 0; } -/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) -{ -#ifndef CONFIG_ROM_SIZE -#error CONFIG_ROM_SIZE must be set. -#endif - return CONFIG_ROM_SIZE + (uintptr_t)p; -} - int nvm_is_erased(const void *start, size_t size) { const uint8_t *cur = start; @@ -74,7 +65,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + flash->erase(flash, to_flash_offset(flash, start), size); return 0; } @@ -83,6 +74,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + flash->write(flash, to_flash_offset(flash, start), size, data); return 0; }

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Patch set updated for coreboot: 6256bcc mainboard/lenovo/x201/romstage.c: Remove unused function
by Edward O'Callaghan 10 Jan '15

10 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8158 -gerrit commit 6256bccd4612f3aa8b41ce73cbeacad500633da7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 7 15:55:32 2015 +1100 mainboard/lenovo/x201/romstage.c: Remove unused function Function was orginally used for reverse engineering. Change-Id: I646dddd39e61b59358b29a49239c0a1de77c7e55 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/x201/romstage.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 64011b1..624440a 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -167,11 +167,6 @@ static inline u32 read_acpi32(u32 addr) return inl(DEFAULT_PMBASE | addr); } -static inline u16 read_acpi16(u32 addr) -{ - return inw(DEFAULT_PMBASE | addr); -} - static void set_fsb_frequency(void) { u8 block[5];

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New patch to review for coreboot: 1355af9 drivers/ati/ragexl: Kill off dead driver
by Edward O'Callaghan 10 Jan '15

10 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8190 -gerrit commit 1355af9a59aa45bde097fb56e480d2fd01191bd0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 11 01:13:06 2015 +1100 drivers/ati/ragexl: Kill off dead driver Change-Id: I20b2f3e1ae30de42e8eef2810960369ce4903df5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/Kconfig | 1 - src/drivers/Makefile.inc | 1 - src/drivers/ati/Kconfig | 1 - src/drivers/ati/Makefile.inc | 1 - src/drivers/ati/ragexl/Kconfig | 2 - src/drivers/ati/ragexl/Makefile.inc | 1 - src/drivers/ati/ragexl/atyfb.h | 407 ---------- src/drivers/ati/ragexl/fb.h | 344 -------- src/drivers/ati/ragexl/fbcon.h | 139 ---- src/drivers/ati/ragexl/mach64.h | 1169 --------------------------- src/drivers/ati/ragexl/mach64_ct.c | 370 --------- src/drivers/ati/ragexl/xlinit.c | 1518 ----------------------------------- 12 files changed, 3954 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 08de415..2975464 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -18,7 +18,6 @@ ## source src/drivers/ams/Kconfig -source src/drivers/ati/Kconfig source src/drivers/dec/Kconfig source src/drivers/elog/Kconfig source src/drivers/emulation/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 151e3f7..c9f3eb9 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -18,7 +18,6 @@ ## subdirs-y += ams -subdirs-y += ati subdirs-y += dec subdirs-y += emulation subdirs-y += generic diff --git a/src/drivers/ati/Kconfig b/src/drivers/ati/Kconfig deleted file mode 100644 index f1ea32c..0000000 --- a/src/drivers/ati/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/ati/ragexl/Kconfig diff --git a/src/drivers/ati/Makefile.inc b/src/drivers/ati/Makefile.inc deleted file mode 100644 index 15b5dfc..0000000 --- a/src/drivers/ati/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += ragexl diff --git a/src/drivers/ati/ragexl/Kconfig b/src/drivers/ati/ragexl/Kconfig deleted file mode 100644 index 86109b1..0000000 --- a/src/drivers/ati/ragexl/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config DRIVERS_ATI_RAGEXL - bool diff --git a/src/drivers/ati/ragexl/Makefile.inc b/src/drivers/ati/ragexl/Makefile.inc deleted file mode 100644 index fbec414..0000000 --- a/src/drivers/ati/ragexl/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_ATI_RAGEXL) += xlinit.c diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h deleted file mode 100644 index 94f31fe..0000000 --- a/src/drivers/ati/ragexl/atyfb.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * ATI Frame Buffer Device Driver Core Definitions - */ - -#define PLL_CRTC_DECODE 0 - -#define EINVAL -1 - -#if CONFIG_CONSOLE_BTEXT - /* - * Elements of the hardware specific atyfb_par structure - */ -struct crtc { - u32 vxres; - u32 vyres; - u32 xoffset; - u32 yoffset; - u32 bpp; - u32 h_tot_disp; - u32 h_sync_strt_wid; - u32 v_tot_disp; - u32 v_sync_strt_wid; - u32 off_pitch; - u32 gen_cntl; - u32 dp_pix_width; /* acceleration */ - u32 dp_chain_mask; /* acceleration */ -}; -#endif /* CONFIG_CONSOLE_BTEXT */ -#if 0 -struct pll_514 { - u8 m; - u8 n; -}; - -struct pll_18818 -{ - u32 program_bits; - u32 locationAddr; - u32 period_in_ps; - u32 post_divider; -}; -#endif -struct pll_ct { - u8 pll_ref_div; - u8 pll_gen_cntl; - u8 mclk_fb_div; - u8 mclk_fb_mult; /* 2 or 4 */ - u8 sclk_fb_div; - u8 pll_vclk_cntl; - u8 vclk_post_div; - u8 vclk_fb_div; - u8 pll_ext_cntl; - u8 spll_cntl2; - u32 dsp_config; /* Mach64 GTB DSP */ - u32 dsp_on_off; /* Mach64 GTB DSP */ - u8 mclk_post_div_real; - u8 xclk_post_div_real; - u8 vclk_post_div_real; -}; - -union aty_pll { - struct pll_ct ct; -#if 0 - struct pll_514 ibm514; - struct pll_18818 ics2595; -#endif -}; - - - /* - * The hardware parameters for each card - */ -struct atyfb_par { -#if CONFIG_CONSOLE_BTEXT - struct crtc crtc; -#endif - union aty_pll pll; - u32 accel_flags; -}; -#if 0 -struct aty_cursor { - int enable; - int on; - int vbl_cnt; - int blink_rate; - u32 offset; - struct { - u16 x, y; - } pos, hot, size; - u32 color[2]; - u8 bits[8][64]; - u8 mask[8][64]; - u8 *ram; - struct timer_list *timer; -}; -#endif -struct fb_info_aty { -#if CONFIG_CONSOLE_BTEXT -#if PLL_CRTC_DECODE==1 - struct fb_info fb_info; -#endif -#endif -#if 0 - struct fb_info_aty *next; - unsigned long ati_regbase_phys; -#endif - unsigned long ati_regbase; -#if 0 - unsigned long frame_buffer_phys; -#endif - unsigned long frame_buffer; - unsigned long clk_wr_offset; -#if 0 - struct pci_mmap_map *mmap_map; - struct aty_cursor *cursor; -#endif - struct aty_cmap_regs *aty_cmap_regs; -#if 0 - struct { u8 red, green, blue, pad; } palette[256]; -#endif - struct atyfb_par default_par; -#if PLL_CRTC_DECODE==1 - struct atyfb_par current_par; -#endif - - u32 features; - u32 total_vram; - u32 ref_clk_per; - u32 pll_per; - u32 mclk_per; - u32 xclk_per; - u8 bus_type; - u8 ram_type; - u8 mem_refresh_rate; -#if 0 - struct aty_dac_ops *dac_ops; - struct aty_pll_ops *pll_ops; - struct display disp; - struct display_switch dispsw; -#endif - -#if 0 - union { -#ifdef FBCON_HAS_CFB16 - u16 cfb16[16]; -#endif -#ifdef FBCON_HAS_CFB24 - u32 cfb24[16]; -#endif -#ifdef FBCON_HAS_CFB32 - u32 cfb32[16]; -#endif - } fbcon_cmap; -#endif - u8 blitter_may_be_busy; -#if 0 -#ifdef __sparc__ - u8 mmaped; - int open; - int vtconsole; - int consolecnt; -#endif -#ifdef CONFIG_PMAC_PBOOK - unsigned char *save_framebuffer; - unsigned long save_pll[64]; -#endif -#endif -}; - - - /* - * ATI Mach64 features - */ - -#define M64_HAS(feature) ((info)->features & (M64F_##feature)) - -#define M64F_RESET_3D 0x00000001 -#define M64F_MAGIC_FIFO 0x00000002 -#define M64F_GTB_DSP 0x00000004 -#define M64F_FIFO_24 0x00000008 -#define M64F_SDRAM_MAGIC_PLL 0x00000010 -#define M64F_MAGIC_POSTDIV 0x00000020 -#define M64F_INTEGRATED 0x00000040 -#define M64F_CT_BUS 0x00000080 -#define M64F_VT_BUS 0x00000100 -#define M64F_MOBIL_BUS 0x00000200 -#define M64F_GX 0x00000400 -#define M64F_CT 0x00000800 -#define M64F_VT 0x00001000 -#define M64F_GT 0x00002000 -#define M64F_MAGIC_VRAM_SIZE 0x00004000 -#define M64F_G3_PB_1_1 0x00008000 -#define M64F_G3_PB_1024x768 0x00010000 -#define M64F_EXTRA_BRIGHT 0x00020000 -#define M64F_LT_SLEEP 0x00040000 -#define M64F_XL_DLL 0x00080000 -#define M64F_MFB_TIMES_4 0x00100000 - - - /* - * Register access - */ - -static inline u32 aty_ld_le32(int regindex, - const struct fb_info_aty *info) -{ - /* Hack for bloc 1, should be cleanly optimized by compiler */ - if (regindex >= 0x400) - regindex -= 0x800; - -#ifdef ATARI - return in_le32((volatile u32 *)(info->ati_regbase+regindex)); -#else - return read32 (info->ati_regbase + regindex); -#endif -} - -static inline void aty_st_le32(int regindex, u32 val, - const struct fb_info_aty *info) -{ - /* Hack for bloc 1, should be cleanly optimized by compiler */ - if (regindex >= 0x400) - regindex -= 0x800; - -#ifdef ATARI - out_le32 (info->ati_regbase+regindex, val); -#else - write32 (info->ati_regbase + regindex, val); -#endif -} - -static inline u16 aty_ld_le16(int regindex, - const struct fb_info_aty *info) -{ - /* Hack for bloc 1, should be cleanly optimized by compiler */ - if (regindex >= 0x400) - regindex -= 0x800; - -#if defined(__mc68000__) - return le16_to_cpu(*((volatile u16 *)(info->ati_regbase+regindex))); -#else - return read16 (info->ati_regbase + regindex); -#endif -} - -static inline void aty_st_le16(int regindex, u16 val, - const struct fb_info_aty *info) -{ - /* Hack for bloc 1, should be cleanly optimized by compiler */ - if (regindex >= 0x400) - regindex -= 0x800; - -#if defined(__mc68000__) - *((volatile u16 *)(info->ati_regbase+regindex)) = cpu_to_le16(val); -#else - write16 (info->ati_regbase + regindex, val); -#endif -} - -static inline u8 aty_ld_8(int regindex, - const struct fb_info_aty *info) -{ - /* Hack for bloc 1, should be cleanly optimized by compiler */ - if (regindex >= 0x400) - regindex -= 0x800; - -#ifdef ATARI - return in_8 (info->ati_regbase + regindex); -#else - return read8 (info->ati_regbase + regindex); -#endif -} - -static inline void aty_st_8(int regindex, u8 val, - const struct fb_info_aty *info) -{ - /* Hack for bloc 1, should be cleanly optimized by compiler */ - if (regindex >= 0x400) - regindex -= 0x800; - -#ifdef ATARI - out_8 (info->ati_regbase + regindex, val); -#else - write8 (info->ati_regbase + regindex, val); -#endif -} - -static inline u8 aty_ld_pll(int offset, const struct fb_info_aty *info) -{ - u8 res; - - /* write addr byte */ - aty_st_8(CLOCK_CNTL + 1, (offset << 2), info); - /* read the register value */ - res = aty_ld_8(CLOCK_CNTL + 2, info); - return res; -} - -/* - * CT family only. - */ -static inline void aty_st_pll(int offset, u8 val, - const struct fb_info_aty *info) -{ - /* write addr byte */ - aty_st_8(CLOCK_CNTL + 1, (offset << 2) | PLL_WR_EN, info); - /* write the register value */ - aty_st_8(CLOCK_CNTL + 2, val, info); - aty_st_8(CLOCK_CNTL + 1, (offset << 2) & ~PLL_WR_EN, info); -} - - - /* - * DAC operations - */ - -#if 0 - -struct aty_dac_ops { - int (*set_dac)(const struct fb_info_aty *info, const union aty_pll *pll, - u32 bpp, u32 accel); -}; -extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */ -extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */ -extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */ -extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */ -static struct aty_dac_ops aty_dac_ct; /* Integrated */ - -#endif - - /* - * Clock operations - */ - -#if 0 -struct aty_pll_ops { - int (*var_to_pll)(const struct fb_info_aty *info, u32 vclk_per, u8 bpp, - union aty_pll *pll); -#if 0 - u32 (*pll_to_var)(const struct fb_info_aty *info, - const union aty_pll *pll); - void (*set_pll)(const struct fb_info_aty *info, const union aty_pll *pll); -#endif -}; - -#endif - -#if 0 -extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */ -extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */ -extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */ -extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */ -extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */ -extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */ -#endif -#if 0 -static struct aty_pll_ops aty_pll_ct; /* Integrated */ - -static void aty_set_pll_ct(const struct fb_info_aty *info, - const union aty_pll *pll); - -static void aty_calc_pll_ct(const struct fb_info_aty *info, - struct pll_ct *pll); -#endif -#if 0 - /* - * Hardware cursor support - */ -extern struct aty_cursor *aty_init_cursor(struct fb_info_aty *fb); -extern void atyfb_cursor(struct display *p, int mode, int x, int y); -extern void aty_set_cursor_color(struct fb_info_aty *fb); -extern void aty_set_cursor_shape(struct fb_info_aty *fb); -extern int atyfb_set_font(struct display *d, int width, int height); -#endif - /* - * Hardware acceleration - */ - -static inline void wait_for_fifo(u16 entries, const struct fb_info_aty *info) -{ - while ((aty_ld_le32(FIFO_STAT, info) & 0xffff) > - ((u32)(0x8000 >> entries))); -} - -static inline void wait_for_idle(struct fb_info_aty *info) -{ - wait_for_fifo(16, info); - while ((aty_ld_le32(GUI_STAT, info) & 1)!= 0); - info->blitter_may_be_busy = 0; -} -#if 0 -extern void aty_reset_engine(const struct fb_info_aty *info); -extern void aty_init_engine(const struct atyfb_par *par, - struct fb_info_aty *info); -extern void aty_rectfill(int dstx, int dsty, u32 width, u32 height, - u32 color, struct fb_info_aty *info); - - - /* - * Text console acceleration - */ - -extern const struct display_switch fbcon_aty8; -extern const struct display_switch fbcon_aty16; -extern const struct display_switch fbcon_aty24; -extern const struct display_switch fbcon_aty32; -#endif diff --git a/src/drivers/ati/ragexl/fb.h b/src/drivers/ati/ragexl/fb.h deleted file mode 100644 index 48d0f01..0000000 --- a/src/drivers/ati/ragexl/fb.h +++ /dev/null @@ -1,344 +0,0 @@ -#ifndef _LINUX_FB_H -#define _LINUX_FB_H - -#define u32 uint32_t -#define u16 uint16_t -#define u8 uint8_t -#define s16 short - -/* Definitions of frame buffers */ - -#define FB_MAJOR 29 -#define FB_MAX 32 /* sufficient for now */ - -/* ioctls - 0x46 is 'F' */ -#define FBIOGET_VSCREENINFO 0x4600 -#define FBIOPUT_VSCREENINFO 0x4601 -#define FBIOGET_FSCREENINFO 0x4602 -#define FBIOGETCMAP 0x4604 -#define FBIOPUTCMAP 0x4605 -#define FBIOPAN_DISPLAY 0x4606 -/* 0x4607-0x460B are defined below */ -/* #define FBIOGET_MONITORSPEC 0x460C */ -/* #define FBIOPUT_MONITORSPEC 0x460D */ -/* #define FBIOSWITCH_MONIBIT 0x460E */ -#define FBIOGET_CON2FBMAP 0x460F -#define FBIOPUT_CON2FBMAP 0x4610 -#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ -#define FBIOGET_VBLANK _IOR('F', 0x12, struct fb_vblank) -#define FBIO_ALLOC 0x4613 -#define FBIO_FREE 0x4614 -#define FBIOGET_GLYPH 0x4615 -#define FBIOGET_HWCINFO 0x4616 -#define FBIOPUT_MODEINFO 0x4617 -#define FBIOGET_DISPINFO 0x4618 - - -#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ -#define FB_TYPE_PLANES 1 /* Non interleaved planes */ -#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */ -#define FB_TYPE_TEXT 3 /* Text/attributes */ -#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */ - -#define FB_AUX_TEXT_MDA 0 /* Monochrome text */ -#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */ -#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */ -#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */ -#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */ - -#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */ -#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */ -#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */ - -#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */ -#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */ -#define FB_VISUAL_TRUECOLOR 2 /* True color */ -#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */ -#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */ -#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */ - -#define FB_ACCEL_NONE 0 /* no hardware accelerator */ -#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */ -#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */ -#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */ -#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */ -#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */ -#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */ -#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */ -#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */ -#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */ -#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */ -#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */ -#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */ -#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */ -#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */ -#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */ -#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */ -#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */ -#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */ -#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */ -#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */ -#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */ -#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */ -#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */ -#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */ -#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */ -#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */ -#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */ -#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */ -#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */ -#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */ -#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */ -#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */ -#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */ -#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */ -#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */ -#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */ -#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */ -#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */ -#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */ -#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */ - -#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */ -#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */ -#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */ -#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */ -#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */ -#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */ -#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */ -#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */ -#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */ - -#if 0 - -struct fb_fix_screeninfo { - char id[16]; /* identification string eg "TT Builtin" */ - unsigned long smem_start; /* Start of frame buffer mem */ - /* (physical address) */ - u32 smem_len; /* Length of frame buffer mem */ - u32 type; /* see FB_TYPE_* */ - u32 type_aux; /* Interleave for interleaved Planes */ - u32 visual; /* see FB_VISUAL_* */ - u16 xpanstep; /* zero if no hardware panning */ - u16 ypanstep; /* zero if no hardware panning */ - u16 ywrapstep; /* zero if no hardware ywrap */ - u32 line_length; /* length of a line in bytes */ - unsigned long mmio_start; /* Start of Memory Mapped I/O */ - /* (physical address) */ - u32 mmio_len; /* Length of Memory Mapped I/O */ - u32 accel; /* Type of acceleration available */ - u16 reserved[3]; /* Reserved for future compatibility */ -}; - -#endif - -/* Interpretation of offset for color fields: All offsets are from the right, - * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you - * can use the offset as right argument to <<). A pixel afterwards is a bit - * stream and is written to video memory as that unmodified. This implies - * big-endian byte order if bits_per_pixel is greater than 8. - */ -struct fb_bitfield { - u32 offset; /* beginning of bitfield */ - u32 length; /* length of bitfield */ - u32 msb_right; /* != 0 : Most significant bit is */ - /* right */ -}; - -#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ - -#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/ -#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */ -#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */ -#define FB_ACTIVATE_MASK 15 - /* values */ -#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */ -#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */ -#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */ - -#define FB_ACCELF_TEXT 1 /* text mode acceleration */ - -#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ -#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ -#define FB_SYNC_EXT 4 /* external sync */ -#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ -#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ - /* vtotal = 144d/288n/576i => PAL */ - /* vtotal = 121d/242n/484i => NTSC */ -#define FB_SYNC_ON_GREEN 32 /* sync on green */ - -#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ -#define FB_VMODE_INTERLACED 1 /* interlaced */ -#define FB_VMODE_DOUBLE 2 /* double scan */ -#define FB_VMODE_MASK 255 - -#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ -#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ -#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ - -struct fb_var_screeninfo { - u32 xres; /* visible resolution */ - u32 yres; - u32 xres_virtual; /* virtual resolution */ - u32 yres_virtual; - u32 xoffset; /* offset from virtual to visible */ - u32 yoffset; /* resolution */ - - u32 bits_per_pixel; /* guess what */ - u32 grayscale; /* != 0 Graylevels instead of colors */ - - struct fb_bitfield red; /* bitfield in fb mem if true color, */ - struct fb_bitfield green; /* else only length is significant */ - struct fb_bitfield blue; - struct fb_bitfield transp; /* transparency */ - - u32 nonstd; /* != 0 Non standard pixel format */ - - u32 activate; /* see FB_ACTIVATE_* */ - - u32 height; /* height of picture in mm */ - u32 width; /* width of picture in mm */ - - u32 accel_flags; /* acceleration flags (hints) */ - - /* Timing: All values in pixclocks, except pixclock (of course) */ - u32 pixclock; /* pixel clock in ps (pico seconds) */ - u32 left_margin; /* time from sync to picture */ - u32 right_margin; /* time from picture to sync */ - u32 upper_margin; /* time from sync to picture */ - u32 lower_margin; - u32 hsync_len; /* length of horizontal sync */ - u32 vsync_len; /* length of vertical sync */ - u32 sync; /* see FB_SYNC_* */ - u32 vmode; /* see FB_VMODE_* */ - u32 reserved[6]; /* Reserved for future compatibility */ -}; - -struct fb_cmap { - u32 start; /* First entry */ - u32 len; /* Number of entries */ - u16 *red; /* Red values */ - u16 *green; - u16 *blue; - u16 *transp; /* transparency, can be NULL */ -}; - -struct fb_con2fbmap { - u32 console; - u32 framebuffer; -}; - -/* VESA Blanking Levels */ -#define VESA_NO_BLANKING 0 -#define VESA_VSYNC_SUSPEND 1 -#define VESA_HSYNC_SUSPEND 2 -#define VESA_POWERDOWN 3 - -struct fb_monspecs { - u32 hfmin; /* hfreq lower limit (Hz) */ - u32 hfmax; /* hfreq upper limit (Hz) */ - u16 vfmin; /* vfreq lower limit (Hz) */ - u16 vfmax; /* vfreq upper limit (Hz) */ - unsigned dpms : 1; /* supports DPMS */ -}; - -#define FB_VBLANK_VBLANKING 0x001 /* currently in a vertical blank */ -#define FB_VBLANK_HBLANKING 0x002 /* currently in a horizontal blank */ -#define FB_VBLANK_HAVE_VBLANK 0x004 /* vertical blanks can be detected */ -#define FB_VBLANK_HAVE_HBLANK 0x008 /* horizontal blanks can be detected */ -#define FB_VBLANK_HAVE_COUNT 0x010 /* global retrace counter is available */ -#define FB_VBLANK_HAVE_VCOUNT 0x020 /* the vcount field is valid */ -#define FB_VBLANK_HAVE_HCOUNT 0x040 /* the hcount field is valid */ -#define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */ -#define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */ - -struct fb_vblank { - u32 flags; /* FB_VBLANK flags */ - u32 count; /* counter of retraces since boot */ - u32 vcount; /* current scanline position */ - u32 hcount; /* current scandot position */ - u32 reserved[4]; /* reserved for future compatibility */ -}; - - -#if 1 - -#define FBCMD_GET_CURRENTPAR 0xDEAD0005 -#define FBCMD_SET_CURRENTPAR 0xDEAD8005 - -#endif - - - - /* - * Hardware Cursor - */ - -#define FBIOGET_FCURSORINFO 0x4607 -#define FBIOGET_VCURSORINFO 0x4608 -#define FBIOPUT_VCURSORINFO 0x4609 -#define FBIOGET_CURSORSTATE 0x460A -#define FBIOPUT_CURSORSTATE 0x460B - - -struct fb_fix_cursorinfo { - u16 crsr_width; /* width and height of the cursor in */ - u16 crsr_height; /* pixels (zero if no cursor) */ - u16 crsr_xsize; /* cursor size in display pixels */ - u16 crsr_ysize; - u16 crsr_color1; /* colormap entry for cursor color1 */ - u16 crsr_color2; /* colormap entry for cursor color2 */ -}; - -struct fb_var_cursorinfo { - u16 width; - u16 height; - u16 xspot; - u16 yspot; - u8 data[1]; /* field with [height][width] */ -}; - -struct fb_cursorstate { - s16 xoffset; - s16 yoffset; - u16 mode; -}; - - -struct fb_info { - char modename[40]; /* default video mode */ -// kdev_t node; - int flags; - int open; /* Has this been open already ? */ - struct fb_var_screeninfo var; /* Current var */ -#if 0 - struct fb_fix_screeninfo fix; /* Current fix */ -#endif - struct fb_monspecs monspecs; /* Current Monitor specs */ - struct fb_cmap cmap; /* Current cmap */ -// struct fb_ops *fbops; - char *screen_base; /* Virtual address */ - struct display *disp; /* initial display variable */ -// struct vc_data *display_fg; /* Console visible on this display */ - char fontname[40]; /* default font name */ -#if 0 - devfs_handle_t devfs_handle; /* Devfs handle for new name */ - devfs_handle_t devfs_lhandle; /* Devfs handle for compat. symlink */ - int (*changevar)(int); /* tell console var has changed */ - int (*switch_con)(int, struct fb_info*); - /* tell fb to switch consoles */ - int (*updatevar)(int, struct fb_info*); - /* tell fb to update the vars */ - void (*blank)(int, struct fb_info*); /* tell fb to (un)blank the screen */ - /* arg = 0: unblank */ - /* arg > 0: VESA level (arg-1) */ -#endif - void *pseudo_palette; /* Fake palette of 16 colors and - the cursor's color for non - palette mode */ - /* From here on everything is device dependent */ - void *par; -}; - -#endif /* _LINUX_FB_H */ diff --git a/src/drivers/ati/ragexl/fbcon.h b/src/drivers/ati/ragexl/fbcon.h deleted file mode 100644 index d6f122c..0000000 --- a/src/drivers/ati/ragexl/fbcon.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * linux/drivers/video/fbcon.h -- Low level frame buffer based console driver - * - * Copyright (C) 1997 Geert Uytterhoeven - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _VIDEO_FBCON_H -#define _VIDEO_FBCON_H - -struct display { - /* Filled in by the frame buffer device */ - struct fb_var_screeninfo var; /* variable infos. yoffset and vmode */ - /* are updated by fbcon.c */ - struct fb_cmap cmap; /* colormap */ - char *screen_base; /* pointer to top of virtual screen */ - /* (virtual address) */ - int visual; - int type; /* see FB_TYPE_* */ - int type_aux; /* Interleave for interleaved Planes */ - u16 ypanstep; /* zero if no hardware ypan */ - u16 ywrapstep; /* zero if no hardware ywrap */ - u32 line_length; /* length of a line in bytes */ - u16 can_soft_blank; /* zero if no hardware blanking */ - u16 inverse; /* != 0 text black on white as default */ - - /* Filled in by the low-level console driver */ - - struct vc_data *conp; /* pointer to console data */ - int vrows; /* number of virtual rows */ - unsigned short cursor_x; /* current cursor position */ - unsigned short cursor_y; - int fgcol; /* text colors */ - int bgcol; - u32 next_line; /* offset to one line below */ - u32 next_plane; /* offset to next plane */ - u8 *fontdata; /* Font associated to this display */ - unsigned short _fontheightlog; - unsigned short _fontwidthlog; - unsigned short _fontheight; - unsigned short _fontwidth; - int userfont; /* != 0 if fontdata kmalloc()ed */ - u16 scrollmode; /* Scroll Method */ - short yscroll; /* Hardware scrolling */ - unsigned char fgshift, bgshift; - unsigned short charmask; /* 0xff or 0x1ff */ -}; - - -#define fontheight(p) ((p)->_fontheight) -#define fontheightlog(p) ((p)->_fontheightlog) - -#ifdef FBCON_FONTWIDTH8_ONLY - -/* fontwidth w is supported by dispsw */ -#define FONTWIDTH(w) (1 << ((8) - 1)) -/* fontwidths w1-w2 inclusive are supported by dispsw */ -#define FONTWIDTHRANGE(w1,w2) FONTWIDTH(8) - -#define fontwidth(p) (8) -#define fontwidthlog(p) (0) - -#else - -/* fontwidth w is supported by dispsw */ -#define FONTWIDTH(w) (1 << ((w) - 1)) -/* fontwidths w1-w2 inclusive are supported by dispsw */ -#define FONTWIDTHRANGE(w1,w2) (FONTWIDTH(w2+1) - FONTWIDTH(w1)) - -#define fontwidth(p) ((p)->_fontwidth) -#define fontwidthlog(p) ((p)->_fontwidthlog) - -#endif - - /* - * Attribute Decoding - */ - -/* Color */ -#define attr_fgcol(p,s) \ - (((s) >> ((p)->fgshift)) & 0x0f) -#define attr_bgcol(p,s) \ - (((s) >> ((p)->bgshift)) & 0x0f) -#define attr_bgcol_ec(p,conp) \ - ((conp) ? (((conp)->vc_video_erase_char >> ((p)->bgshift)) & 0x0f) : 0) - -/* Monochrome */ -#define attr_bold(p,s) \ - ((s) & 0x200) -#define attr_reverse(p,s) \ - (((s) & 0x800) ^ ((p)->inverse ? 0x800 : 0)) -#define attr_underline(p,s) \ - ((s) & 0x400) -#define attr_blink(p,s) \ - ((s) & 0x8000) - - /* - * Scroll Method - */ - -/* Internal flags */ -#define __SCROLL_YPAN 0x001 -#define __SCROLL_YWRAP 0x002 -#define __SCROLL_YMOVE 0x003 -#define __SCROLL_YREDRAW 0x004 -#define __SCROLL_YMASK 0x00f -#define __SCROLL_YFIXED 0x010 -#define __SCROLL_YNOMOVE 0x020 -#define __SCROLL_YPANREDRAW 0x040 -#define __SCROLL_YNOPARTIAL 0x080 - -/* Only these should be used by the drivers */ -/* Which one should you use? If you have a fast card and slow bus, - then probably just 0 to indicate fbcon should choose between - YWRAP/YPAN+MOVE/YMOVE. On the other side, if you have a fast bus - and even better if your card can do fonting (1->8/32bit painting), - you should consider either SCROLL_YREDRAW (if your card is - able to do neither YPAN/YWRAP), or SCROLL_YNOMOVE. - The best is to test it with some real life scrolling (usually, not - all lines on the screen are filled completely with non-space characters, - and REDRAW performs much better on such lines, so don't cat a file - with every line covering all screen columns, it would not be the right - benchmark). - */ -#define SCROLL_YREDRAW (__SCROLL_YFIXED|__SCROLL_YREDRAW) -#define SCROLL_YNOMOVE (__SCROLL_YNOMOVE|__SCROLL_YPANREDRAW) - -/* SCROLL_YNOPARTIAL, used in combination with the above, is for video - cards which can not handle using panning to scroll a portion of the - screen without excessive flicker. Panning will only be used for - whole screens. - */ -/* Namespace consistency */ -#define SCROLL_YNOPARTIAL __SCROLL_YNOPARTIAL - -#endif /* _VIDEO_FBCON_H */ diff --git a/src/drivers/ati/ragexl/mach64.h b/src/drivers/ati/ragexl/mach64.h deleted file mode 100644 index 3acbef4..0000000 --- a/src/drivers/ati/ragexl/mach64.h +++ /dev/null @@ -1,1169 +0,0 @@ -/* - * ATI Mach64 Register Definitions - * - * Copyright (C) 1997 Michael AK Tesch - * written with much help from Jon Howell - * - * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/* - * most of the rest of this file comes from ATI sample code - */ -#ifndef REGMACH64_H -#define REGMACH64_H - -/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */ - -/* Accelerator CRTC */ -#define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */ -#define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */ -#define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */ -#define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */ -#define CRTC_H_SYNC_STRT 0x0004 -#define CRTC2_H_SYNC_STRT 0x0004 -#define CRTC_H_SYNC_DLY 0x0005 -#define CRTC2_H_SYNC_DLY 0x0005 -#define CRTC_H_SYNC_WID 0x0006 -#define CRTC2_H_SYNC_WID 0x0006 -#define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */ -#define CRTC2_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */ -#define CRTC_V_TOTAL 0x0008 -#define CRTC2_V_TOTAL 0x0008 -#define CRTC_V_DISP 0x000A -#define CRTC2_V_DISP 0x000A -#define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */ -#define CRTC2_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */ -#define CRTC_V_SYNC_STRT 0x000C -#define CRTC2_V_SYNC_STRT 0x000C -#define CRTC_V_SYNC_WID 0x000E -#define CRTC2_V_SYNC_WID 0x000E -#define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */ -#define CRTC2_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */ -#define CRTC_OFF_PITCH 0x0014 /* Dword offset 0_05 */ -#define CRTC_OFFSET 0x0014 -#define CRTC_PITCH 0x0016 -#define CRTC_INT_CNTL 0x0018 /* Dword offset 0_06 */ -#define CRTC_GEN_CNTL 0x001C /* Dword offset 0_07 */ -#define CRTC_PIX_WIDTH 0x001D -#define CRTC_FIFO 0x001E -#define CRTC_EXT_DISP 0x001F - -/* Memory Buffer Control */ -#define DSP_CONFIG 0x0020 /* Dword offset 0_08 */ -#define PM_DSP_CONFIG 0x0020 /* Dword offset 0_08 (Mobility Only) */ -#define DSP_ON_OFF 0x0024 /* Dword offset 0_09 */ -#define PM_DSP_ON_OFF 0x0024 /* Dword offset 0_09 (Mobility Only) */ -#define TIMER_CONFIG 0x0028 /* Dword offset 0_0A */ -#define MEM_BUF_CNTL 0x002C /* Dword offset 0_0B */ -#define MEM_ADDR_CONFIG 0x0034 /* Dword offset 0_0D */ - -/* Accelerator CRTC */ -#define CRT_TRAP 0x0038 /* Dword offset 0_0E */ - -#define I2C_CNTL_0 0x003C /* Dword offset 0_0F */ - -/* Overscan */ -#define OVR_CLR 0x0040 /* Dword offset 0_10 */ -#define OVR2_CLR 0x0040 /* Dword offset 0_10 */ -#define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */ -#define OVR2_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */ -#define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */ -#define OVR2_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */ - -/* Memory Buffer Control */ -#define VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 */ -#define PM_VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 (Mobility Only) */ -#define VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 */ -#define PM_VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 (Mobility Only) */ -#define DSP2_CONFIG 0x0054 /* Dword offset 0_15 */ -#define PM_DSP2_CONFIG 0x0054 /* Dword offset 0_15 (Mobility Only) */ -#define DSP2_ON_OFF 0x0058 /* Dword offset 0_16 */ -#define PM_DSP2_ON_OFF 0x0058 /* Dword offset 0_16 (Mobility Only) */ - -/* Accelerator CRTC */ -#define CRTC2_OFF_PITCH 0x005C /* Dword offset 0_17 */ - -/* Hardware Cursor */ -#define CUR_CLR0 0x0060 /* Dword offset 0_18 */ -#define CUR2_CLR0 0x0060 /* Dword offset 0_18 */ -#define CUR_CLR1 0x0064 /* Dword offset 0_19 */ -#define CUR2_CLR1 0x0064 /* Dword offset 0_19 */ -#define CUR_OFFSET 0x0068 /* Dword offset 0_1A */ -#define CUR2_OFFSET 0x0068 /* Dword offset 0_1A */ -#define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */ -#define CUR2_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */ -#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ -#define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ - -#define CONFIG_PANEL_LG 0x0074 /* Dword offset 0_1D */ - -/* General I/O Control */ -#define GP_IO 0x0078 /* Dword offset 0_1E */ - -/* Test and Debug */ -#define HW_DEBUG 0x007C /* Dword offset 0_1F */ - -/* Scratch Pad and Test */ -#define SCRATCH_REG0 0x0080 /* Dword offset 0_20 */ -#define SCRATCH_REG1 0x0084 /* Dword offset 0_21 */ -#define SCRATCH_REG2 0x0088 /* Dword offset 0_22 */ -#define SCRATCH_REG3 0x008C /* Dword offset 0_23 */ - -/* Clock Control */ -#define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */ -#define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */ - -/* Configuration */ -#define CONFIG_STAT1 0x0094 /* Dword offset 0_25 */ -#define CONFIG_STAT2 0x0098 /* Dword offset 0_26 */ - -/* Bus Control */ -#define BUS_CNTL 0x00A0 /* Dword offset 0_28 */ - -#define LCD_INDEX 0x00A4 /* Dword offset 0_29 */ -#define LCD_DATA 0x00A8 /* Dword offset 0_2A */ - -/* Memory Control */ -#define EXT_MEM_CNTL 0x00AC /* Dword offset 0_2B */ -#define MEM_CNTL 0x00B0 /* Dword offset 0_2C */ -#define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 0_2D */ -#define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 0_2E */ - -#define I2C_CNTL_1 0x00BC /* Dword offset 0_2F */ - -/* DAC Control */ -#define DAC_REGS 0x00C0 /* Dword offset 0_30 */ -#define DAC_W_INDEX 0x00C0 /* Dword offset 0_30 */ -#define DAC_DATA 0x00C1 /* Dword offset 0_30 */ -#define DAC_MASK 0x00C2 /* Dword offset 0_30 */ -#define DAC_R_INDEX 0x00C3 /* Dword offset 0_30 */ -#define DAC_CNTL 0x00C4 /* Dword offset 0_31 */ - -#define EXT_DAC_REGS 0x00C8 /* Dword offset 0_32 */ - -/* Test and Debug */ -#define GEN_TEST_CNTL 0x00D0 /* Dword offset 0_34 */ - -/* Custom Macros */ -#define CUSTOM_MACRO_CNTL 0x00D4 /* Dword offset 0_35 */ - -#define LCD_GEN_CNTL_LG 0x00D4 /* Dword offset 0_35 */ - -#define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */ - -/* Configuration */ -#define CONFIG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */ -#define CONFIG_CHIP_ID 0x00E0 /* Dword offset 0_38 */ -#define CONFIG_STAT0 0x00E4 /* Dword offset 0_39 */ - -/* Test and Debug */ -#define CRC_SIG 0x00E8 /* Dword offset 0_3A */ -#define CRC2_SIG 0x00E8 /* Dword offset 0_3A */ - - -/* GUI MEMORY MAPPED Registers */ - -/* Draw Engine Destination Trajectory */ -#define DST_OFF_PITCH 0x0100 /* Dword offset 0_40 */ -#define DST_X 0x0104 /* Dword offset 0_41 */ -#define DST_Y 0x0108 /* Dword offset 0_42 */ -#define DST_Y_X 0x010C /* Dword offset 0_43 */ -#define DST_WIDTH 0x0110 /* Dword offset 0_44 */ -#define DST_HEIGHT 0x0114 /* Dword offset 0_45 */ -#define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 0_46 */ -#define DST_X_WIDTH 0x011C /* Dword offset 0_47 */ -#define DST_BRES_LNTH 0x0120 /* Dword offset 0_48 */ -#define DST_BRES_ERR 0x0124 /* Dword offset 0_49 */ -#define DST_BRES_INC 0x0128 /* Dword offset 0_4A */ -#define DST_BRES_DEC 0x012C /* Dword offset 0_4B */ -#define DST_CNTL 0x0130 /* Dword offset 0_4C */ -#define DST_Y_X__ALIAS__ 0x0134 /* Dword offset 0_4D */ -#define TRAIL_BRES_ERR 0x0138 /* Dword offset 0_4E */ -#define TRAIL_BRES_INC 0x013C /* Dword offset 0_4F */ -#define TRAIL_BRES_DEC 0x0140 /* Dword offset 0_50 */ -#define LEAD_BRES_LNTH 0x0144 /* Dword offset 0_51 */ -#define Z_OFF_PITCH 0x0148 /* Dword offset 0_52 */ -#define Z_CNTL 0x014C /* Dword offset 0_53 */ -#define ALPHA_TST_CNTL 0x0150 /* Dword offset 0_54 */ -#define SECONDARY_STW_EXP 0x0158 /* Dword offset 0_56 */ -#define SECONDARY_S_X_INC 0x015C /* Dword offset 0_57 */ -#define SECONDARY_S_Y_INC 0x0160 /* Dword offset 0_58 */ -#define SECONDARY_S_START 0x0164 /* Dword offset 0_59 */ -#define SECONDARY_W_X_INC 0x0168 /* Dword offset 0_5A */ -#define SECONDARY_W_Y_INC 0x016C /* Dword offset 0_5B */ -#define SECONDARY_W_START 0x0170 /* Dword offset 0_5C */ -#define SECONDARY_T_X_INC 0x0174 /* Dword offset 0_5D */ -#define SECONDARY_T_Y_INC 0x0178 /* Dword offset 0_5E */ -#define SECONDARY_T_START 0x017C /* Dword offset 0_5F */ - -/* Draw Engine Source Trajectory */ -#define SRC_OFF_PITCH 0x0180 /* Dword offset 0_60 */ -#define SRC_X 0x0184 /* Dword offset 0_61 */ -#define SRC_Y 0x0188 /* Dword offset 0_62 */ -#define SRC_Y_X 0x018C /* Dword offset 0_63 */ -#define SRC_WIDTH1 0x0190 /* Dword offset 0_64 */ -#define SRC_HEIGHT1 0x0194 /* Dword offset 0_65 */ -#define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 0_66 */ -#define SRC_X_START 0x019C /* Dword offset 0_67 */ -#define SRC_Y_START 0x01A0 /* Dword offset 0_68 */ -#define SRC_Y_X_START 0x01A4 /* Dword offset 0_69 */ -#define SRC_WIDTH2 0x01A8 /* Dword offset 0_6A */ -#define SRC_HEIGHT2 0x01AC /* Dword offset 0_6B */ -#define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 0_6C */ -#define SRC_CNTL 0x01B4 /* Dword offset 0_6D */ - -#define SCALE_OFF 0x01C0 /* Dword offset 0_70 */ -#define SECONDARY_SCALE_OFF 0x01C4 /* Dword offset 0_71 */ - -#define TEX_0_OFF 0x01C0 /* Dword offset 0_70 */ -#define TEX_1_OFF 0x01C4 /* Dword offset 0_71 */ -#define TEX_2_OFF 0x01C8 /* Dword offset 0_72 */ -#define TEX_3_OFF 0x01CC /* Dword offset 0_73 */ -#define TEX_4_OFF 0x01D0 /* Dword offset 0_74 */ -#define TEX_5_OFF 0x01D4 /* Dword offset 0_75 */ -#define TEX_6_OFF 0x01D8 /* Dword offset 0_76 */ -#define TEX_7_OFF 0x01DC /* Dword offset 0_77 */ - -#define SCALE_WIDTH 0x01DC /* Dword offset 0_77 */ -#define SCALE_HEIGHT 0x01E0 /* Dword offset 0_78 */ - -#define TEX_8_OFF 0x01E0 /* Dword offset 0_78 */ -#define TEX_9_OFF 0x01E4 /* Dword offset 0_79 */ -#define TEX_10_OFF 0x01E8 /* Dword offset 0_7A */ -#define S_Y_INC 0x01EC /* Dword offset 0_7B */ - -#define SCALE_PITCH 0x01EC /* Dword offset 0_7B */ -#define SCALE_X_INC 0x01F0 /* Dword offset 0_7C */ - -#define RED_X_INC 0x01F0 /* Dword offset 0_7C */ -#define GREEN_X_INC 0x01F4 /* Dword offset 0_7D */ - -#define SCALE_Y_INC 0x01F4 /* Dword offset 0_7D */ -#define SCALE_VACC 0x01F8 /* Dword offset 0_7E */ -#define SCALE_3D_CNTL 0x01FC /* Dword offset 0_7F */ - -/* Host Data */ -#define HOST_DATA0 0x0200 /* Dword offset 0_80 */ -#define HOST_DATA1 0x0204 /* Dword offset 0_81 */ -#define HOST_DATA2 0x0208 /* Dword offset 0_82 */ -#define HOST_DATA3 0x020C /* Dword offset 0_83 */ -#define HOST_DATA4 0x0210 /* Dword offset 0_84 */ -#define HOST_DATA5 0x0214 /* Dword offset 0_85 */ -#define HOST_DATA6 0x0218 /* Dword offset 0_86 */ -#define HOST_DATA7 0x021C /* Dword offset 0_87 */ -#define HOST_DATA8 0x0220 /* Dword offset 0_88 */ -#define HOST_DATA9 0x0224 /* Dword offset 0_89 */ -#define HOST_DATAA 0x0228 /* Dword offset 0_8A */ -#define HOST_DATAB 0x022C /* Dword offset 0_8B */ -#define HOST_DATAC 0x0230 /* Dword offset 0_8C */ -#define HOST_DATAD 0x0234 /* Dword offset 0_8D */ -#define HOST_DATAE 0x0238 /* Dword offset 0_8E */ -#define HOST_DATAF 0x023C /* Dword offset 0_8F */ -#define HOST_CNTL 0x0240 /* Dword offset 0_90 */ - -/* GUI Bus Mastering */ -#define BM_HOSTDATA 0x0244 /* Dword offset 0_91 */ -#define BM_ADDR 0x0248 /* Dword offset 0_92 */ -#define BM_DATA 0x0248 /* Dword offset 0_92 */ -#define BM_GUI_TABLE_CMD 0x024C /* Dword offset 0_93 */ - -/* Pattern */ -#define PAT_REG0 0x0280 /* Dword offset 0_A0 */ -#define PAT_REG1 0x0284 /* Dword offset 0_A1 */ -#define PAT_CNTL 0x0288 /* Dword offset 0_A2 */ - -/* Scissors */ -#define SC_LEFT 0x02A0 /* Dword offset 0_A8 */ -#define SC_RIGHT 0x02A4 /* Dword offset 0_A9 */ -#define SC_LEFT_RIGHT 0x02A8 /* Dword offset 0_AA */ -#define SC_TOP 0x02AC /* Dword offset 0_AB */ -#define SC_BOTTOM 0x02B0 /* Dword offset 0_AC */ -#define SC_TOP_BOTTOM 0x02B4 /* Dword offset 0_AD */ - -/* Data Path */ -#define USR1_DST_OFF_PITCH 0x02B8 /* Dword offset 0_AE */ -#define USR2_DST_OFF_PITCH 0x02BC /* Dword offset 0_AF */ -#define DP_BKGD_CLR 0x02C0 /* Dword offset 0_B0 */ -#define DP_FOG_CLR 0x02C4 /* Dword offset 0_B1 */ -#define DP_FRGD_CLR 0x02C4 /* Dword offset 0_B1 */ -#define DP_WRITE_MASK 0x02C8 /* Dword offset 0_B2 */ -#define DP_CHAIN_MASK 0x02CC /* Dword offset 0_B3 */ -#define DP_PIX_WIDTH 0x02D0 /* Dword offset 0_B4 */ -#define DP_MIX 0x02D4 /* Dword offset 0_B5 */ -#define DP_SRC 0x02D8 /* Dword offset 0_B6 */ -#define DP_FRGD_CLR_MIX 0x02DC /* Dword offset 0_B7 */ -#define DP_FRGD_BKGD_CLR 0x02E0 /* Dword offset 0_B8 */ - -/* Draw Engine Destination Trajectory */ -#define DST_X_Y 0x02E8 /* Dword offset 0_BA */ -#define DST_WIDTH_HEIGHT 0x02EC /* Dword offset 0_BB */ - -/* Data Path */ -#define USR_DST_PICTH 0x02F0 /* Dword offset 0_BC */ -#define DP_SET_GUI_ENGINE2 0x02F8 /* Dword offset 0_BE */ -#define DP_SET_GUI_ENGINE 0x02FC /* Dword offset 0_BF */ - -/* Color Compare */ -#define CLR_CMP_CLR 0x0300 /* Dword offset 0_C0 */ -#define CLR_CMP_MASK 0x0304 /* Dword offset 0_C1 */ -#define CLR_CMP_CNTL 0x0308 /* Dword offset 0_C2 */ - -/* Command FIFO */ -#define FIFO_STAT 0x0310 /* Dword offset 0_C4 */ - -#define CONTEXT_MASK 0x0320 /* Dword offset 0_C8 */ -#define CONTEXT_LOAD_CNTL 0x032C /* Dword offset 0_CB */ - -/* Engine Control */ -#define GUI_TRAJ_CNTL 0x0330 /* Dword offset 0_CC */ - -/* Engine Status/FIFO */ -#define GUI_STAT 0x0338 /* Dword offset 0_CE */ - -#define TEX_PALETTE_INDEX 0x0340 /* Dword offset 0_D0 */ -#define STW_EXP 0x0344 /* Dword offset 0_D1 */ -#define LOG_MAX_INC 0x0348 /* Dword offset 0_D2 */ -#define S_X_INC 0x034C /* Dword offset 0_D3 */ -#define S_Y_INC__ALIAS__ 0x0350 /* Dword offset 0_D4 */ - -#define SCALE_PITCH__ALIAS__ 0x0350 /* Dword offset 0_D4 */ - -#define S_START 0x0354 /* Dword offset 0_D5 */ -#define W_X_INC 0x0358 /* Dword offset 0_D6 */ -#define W_Y_INC 0x035C /* Dword offset 0_D7 */ -#define W_START 0x0360 /* Dword offset 0_D8 */ -#define T_X_INC 0x0364 /* Dword offset 0_D9 */ -#define T_Y_INC 0x0368 /* Dword offset 0_DA */ - -#define SECONDARY_SCALE_PITCH 0x0368 /* Dword offset 0_DA */ - -#define T_START 0x036C /* Dword offset 0_DB */ -#define TEX_SIZE_PITCH 0x0370 /* Dword offset 0_DC */ -#define TEX_CNTL 0x0374 /* Dword offset 0_DD */ -#define SECONDARY_TEX_OFFSET 0x0378 /* Dword offset 0_DE */ -#define TEX_PALETTE 0x037C /* Dword offset 0_DF */ - -#define SCALE_PITCH_BOTH 0x0380 /* Dword offset 0_E0 */ -#define SECONDARY_SCALE_OFF_ACC 0x0384 /* Dword offset 0_E1 */ -#define SCALE_OFF_ACC 0x0388 /* Dword offset 0_E2 */ -#define SCALE_DST_Y_X 0x038C /* Dword offset 0_E3 */ - -/* Draw Engine Destination Trajectory */ -#define COMPOSITE_SHADOW_ID 0x0398 /* Dword offset 0_E6 */ - -#define SECONDARY_SCALE_X_INC 0x039C /* Dword offset 0_E7 */ - -#define SPECULAR_RED_X_INC 0x039C /* Dword offset 0_E7 */ -#define SPECULAR_RED_Y_INC 0x03A0 /* Dword offset 0_E8 */ -#define SPECULAR_RED_START 0x03A4 /* Dword offset 0_E9 */ - -#define SECONDARY_SCALE_HACC 0x03A4 /* Dword offset 0_E9 */ - -#define SPECULAR_GREEN_X_INC 0x03A8 /* Dword offset 0_EA */ -#define SPECULAR_GREEN_Y_INC 0x03AC /* Dword offset 0_EB */ -#define SPECULAR_GREEN_START 0x03B0 /* Dword offset 0_EC */ -#define SPECULAR_BLUE_X_INC 0x03B4 /* Dword offset 0_ED */ -#define SPECULAR_BLUE_Y_INC 0x03B8 /* Dword offset 0_EE */ -#define SPECULAR_BLUE_START 0x03BC /* Dword offset 0_EF */ - -#define SCALE_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */ - -#define RED_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */ -#define RED_Y_INC 0x03C4 /* Dword offset 0_F1 */ -#define RED_START 0x03C8 /* Dword offset 0_F2 */ - -#define SCALE_HACC 0x03C8 /* Dword offset 0_F2 */ -#define SCALE_Y_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */ - -#define GREEN_X_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */ -#define GREEN_Y_INC 0x03D0 /* Dword offset 0_F4 */ - -#define SECONDARY_SCALE_Y_INC 0x03D0 /* Dword offset 0_F4 */ -#define SECONDARY_SCALE_VACC 0x03D4 /* Dword offset 0_F5 */ - -#define GREEN_START 0x03D4 /* Dword offset 0_F5 */ -#define BLUE_X_INC 0x03D8 /* Dword offset 0_F6 */ -#define BLUE_Y_INC 0x03DC /* Dword offset 0_F7 */ -#define BLUE_START 0x03E0 /* Dword offset 0_F8 */ -#define Z_X_INC 0x03E4 /* Dword offset 0_F9 */ -#define Z_Y_INC 0x03E8 /* Dword offset 0_FA */ -#define Z_START 0x03EC /* Dword offset 0_FB */ -#define ALPHA_X_INC 0x03F0 /* Dword offset 0_FC */ -#define FOG_X_INC 0x03F0 /* Dword offset 0_FC */ -#define ALPHA_Y_INC 0x03F4 /* Dword offset 0_FD */ -#define FOG_Y_INC 0x03F4 /* Dword offset 0_FD */ -#define ALPHA_START 0x03F8 /* Dword offset 0_FE */ -#define FOG_START 0x03F8 /* Dword offset 0_FE */ - -#define OVERLAY_Y_X_START 0x0400 /* Dword offset 1_00 */ -#define OVERLAY_Y_X_END 0x0404 /* Dword offset 1_01 */ -#define OVERLAY_VIDEO_KEY_CLR 0x0408 /* Dword offset 1_02 */ -#define OVERLAY_VIDEO_KEY_MSK 0x040C /* Dword offset 1_03 */ -#define OVERLAY_GRAPHICS_KEY_CLR 0x0410 /* Dword offset 1_04 */ -#define OVERLAY_GRAPHICS_KEY_MSK 0x0414 /* Dword offset 1_05 */ -#define OVERLAY_KEY_CNTL 0x0418 /* Dword offset 1_06 */ - -#define OVERLAY_SCALE_INC 0x0420 /* Dword offset 1_08 */ -#define OVERLAY_SCALE_CNTL 0x0424 /* Dword offset 1_09 */ -#define SCALER_HEIGHT_WIDTH 0x0428 /* Dword offset 1_0A */ -#define SCALER_TEST 0x042C /* Dword offset 1_0B */ -#define SCALER_BUF0_OFFSET 0x0434 /* Dword offset 1_0D */ -#define SCALER_BUF1_OFFSET 0x0438 /* Dword offset 1_0E */ -#define SCALE_BUF_PITCH 0x043C /* Dword offset 1_0F */ - -#define CAPTURE_START_END 0x0440 /* Dword offset 1_10 */ -#define CAPTURE_X_WIDTH 0x0444 /* Dword offset 1_11 */ -#define VIDEO_FORMAT 0x0448 /* Dword offset 1_12 */ -#define VBI_START_END 0x044C /* Dword offset 1_13 */ -#define CAPTURE_CONFIG 0x0450 /* Dword offset 1_14 */ -#define TRIG_CNTL 0x0454 /* Dword offset 1_15 */ - -#define OVERLAY_EXCLUSIVE_HORZ 0x0458 /* Dword offset 1_16 */ -#define OVERLAY_EXCLUSIVE_VERT 0x045C /* Dword offset 1_17 */ - -#define VAL_WIDTH 0x0460 /* Dword offset 1_18 */ -#define CAPTURE_DEBUG 0x0464 /* Dword offset 1_19 */ -#define VIDEO_SYNC_TEST 0x0468 /* Dword offset 1_1A */ - -/* GenLocking */ -#define SNAPSHOT_VH_COUNTS 0x0470 /* Dword offset 1_1C */ -#define SNAPSHOT_F_COUNT 0x0474 /* Dword offset 1_1D */ -#define N_VIF_COUNT 0x0478 /* Dword offset 1_1E */ -#define SNAPSHOT_VIF_COUNT 0x047C /* Dword offset 1_1F */ - -#define CAPTURE_BUF0_OFFSET 0x0480 /* Dword offset 1_20 */ -#define CAPTURE_BUF1_OFFSET 0x0484 /* Dword offset 1_21 */ -#define CAPTURE_BUF_PITCH 0x0488 /* Dword offset 1_22 */ - -/* GenLocking */ -#define SNAPSHOT2_VH_COUNTS 0x04B0 /* Dword offset 1_2C */ -#define SNAPSHOT2_F_COUNT 0x04B4 /* Dword offset 1_2D */ -#define N_VIF2_COUNT 0x04B8 /* Dword offset 1_2E */ -#define SNAPSHOT2_VIF_COUNT 0x04BC /* Dword offset 1_2F */ - -#define MPP_CONFIG 0x04C0 /* Dword offset 1_30 */ -#define MPP_STROBE_SEQ 0x04C4 /* Dword offset 1_31 */ -#define MPP_ADDR 0x04C8 /* Dword offset 1_32 */ -#define MPP_DATA 0x04CC /* Dword offset 1_33 */ -#define TVO_CNTL 0x0500 /* Dword offset 1_40 */ - -/* Test and Debug */ -#define CRT_HORZ_VERT_LOAD 0x0544 /* Dword offset 1_51 */ - -/* AGP */ -#define AGP_BASE 0x0548 /* Dword offset 1_52 */ -#define AGP_CNTL 0x054C /* Dword offset 1_53 */ - -#define SCALER_COLOUR_CNTL 0x0550 /* Dword offset 1_54 */ -#define SCALER_H_COEFF0 0x0554 /* Dword offset 1_55 */ -#define SCALER_H_COEFF1 0x0558 /* Dword offset 1_56 */ -#define SCALER_H_COEFF2 0x055C /* Dword offset 1_57 */ -#define SCALER_H_COEFF3 0x0560 /* Dword offset 1_58 */ -#define SCALER_H_COEFF4 0x0564 /* Dword offset 1_59 */ - -/* Command FIFO */ -#define GUI_CMDFIFO_DEBUG 0x0570 /* Dword offset 1_5C */ -#define GUI_CMDFIFO_DATA 0x0574 /* Dword offset 1_5D */ -#define GUI_CNTL 0x0578 /* Dword offset 1_5E */ - -/* Bus Mastering */ -#define BM_FRAME_BUF_OFFSET 0x0580 /* Dword offset 1_60 */ -#define BM_SYSTEM_MEM_ADDR 0x0584 /* Dword offset 1_61 */ -#define BM_COMMAND 0x0588 /* Dword offset 1_62 */ -#define BM_STATUS 0x058C /* Dword offset 1_63 */ -#define BM_GUI_TABLE 0x05B8 /* Dword offset 1_6E */ -#define BM_SYSTEM_TABLE 0x05BC /* Dword offset 1_6F */ - -#define SCALER_BUF0_OFFSET_U 0x05D4 /* Dword offset 1_75 */ -#define SCALER_BUF0_OFFSET_V 0x05D8 /* Dword offset 1_76 */ -#define SCALER_BUF1_OFFSET_U 0x05DC /* Dword offset 1_77 */ -#define SCALER_BUF1_OFFSET_V 0x05E0 /* Dword offset 1_78 */ - -/* Setup Engine */ -#define VERTEX_1_S 0x0640 /* Dword offset 1_90 */ -#define VERTEX_1_T 0x0644 /* Dword offset 1_91 */ -#define VERTEX_1_W 0x0648 /* Dword offset 1_92 */ -#define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_93 */ -#define VERTEX_1_Z 0x0650 /* Dword offset 1_94 */ -#define VERTEX_1_ARGB 0x0654 /* Dword offset 1_95 */ -#define VERTEX_1_X_Y 0x0658 /* Dword offset 1_96 */ -#define ONE_OVER_AREA 0x065C /* Dword offset 1_97 */ -#define VERTEX_2_S 0x0660 /* Dword offset 1_98 */ -#define VERTEX_2_T 0x0664 /* Dword offset 1_99 */ -#define VERTEX_2_W 0x0668 /* Dword offset 1_9A */ -#define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_9B */ -#define VERTEX_2_Z 0x0670 /* Dword offset 1_9C */ -#define VERTEX_2_ARGB 0x0674 /* Dword offset 1_9D */ -#define VERTEX_2_X_Y 0x0678 /* Dword offset 1_9E */ -#define ONE_OVER_AREA 0x065C /* Dword offset 1_9F */ -#define VERTEX_3_S 0x0680 /* Dword offset 1_A0 */ -#define VERTEX_3_T 0x0684 /* Dword offset 1_A1 */ -#define VERTEX_3_W 0x0688 /* Dword offset 1_A2 */ -#define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_A3 */ -#define VERTEX_3_Z 0x0690 /* Dword offset 1_A4 */ -#define VERTEX_3_ARGB 0x0694 /* Dword offset 1_A5 */ -#define VERTEX_3_X_Y 0x0698 /* Dword offset 1_A6 */ -#define ONE_OVER_AREA 0x065C /* Dword offset 1_A7 */ -#define VERTEX_1_S 0x0640 /* Dword offset 1_AB */ -#define VERTEX_1_T 0x0644 /* Dword offset 1_AC */ -#define VERTEX_1_W 0x0648 /* Dword offset 1_AD */ -#define VERTEX_2_S 0x0660 /* Dword offset 1_AE */ -#define VERTEX_2_T 0x0664 /* Dword offset 1_AF */ -#define VERTEX_2_W 0x0668 /* Dword offset 1_B0 */ -#define VERTEX_3_SECONDARY_S 0x06C0 /* Dword offset 1_B0 */ -#define VERTEX_3_S 0x0680 /* Dword offset 1_B1 */ -#define VERTEX_3_SECONDARY_T 0x06C4 /* Dword offset 1_B1 */ -#define VERTEX_3_T 0x0684 /* Dword offset 1_B2 */ -#define VERTEX_3_SECONDARY_W 0x06C8 /* Dword offset 1_B2 */ -#define VERTEX_3_W 0x0688 /* Dword offset 1_B3 */ -#define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_B4 */ -#define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_B5 */ -#define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_B6 */ -#define VERTEX_1_Z 0x0650 /* Dword offset 1_B7 */ -#define VERTEX_2_Z 0x0670 /* Dword offset 1_B8 */ -#define VERTEX_3_Z 0x0690 /* Dword offset 1_B9 */ -#define VERTEX_1_ARGB 0x0654 /* Dword offset 1_BA */ -#define VERTEX_2_ARGB 0x0674 /* Dword offset 1_BB */ -#define VERTEX_3_ARGB 0x0694 /* Dword offset 1_BC */ -#define VERTEX_1_X_Y 0x0658 /* Dword offset 1_BD */ -#define VERTEX_2_X_Y 0x0678 /* Dword offset 1_BE */ -#define VERTEX_3_X_Y 0x0698 /* Dword offset 1_BF */ -#define ONE_OVER_AREA_UC 0x0700 /* Dword offset 1_C0 */ -#define SETUP_CNTL 0x0704 /* Dword offset 1_C1 */ -#define VERTEX_1_SECONDARY_S 0x0728 /* Dword offset 1_CA */ -#define VERTEX_1_SECONDARY_T 0x072C /* Dword offset 1_CB */ -#define VERTEX_1_SECONDARY_W 0x0730 /* Dword offset 1_CC */ -#define VERTEX_2_SECONDARY_S 0x0734 /* Dword offset 1_CD */ -#define VERTEX_2_SECONDARY_T 0x0738 /* Dword offset 1_CE */ -#define VERTEX_2_SECONDARY_W 0x073C /* Dword offset 1_CF */ - - -#define GTC_3D_RESET_DELAY 3 /* 3D engine reset delay in ms */ - -/* CRTC control values (mostly CRTC_GEN_CNTL) */ - -#define CRTC_H_SYNC_NEG 0x00200000 -#define CRTC_V_SYNC_NEG 0x00200000 - -#define CRTC_DBL_SCAN_EN 0x00000001 -#define CRTC_INTERLACE_EN 0x00000002 -#define CRTC_HSYNC_DIS 0x00000004 -#define CRTC_VSYNC_DIS 0x00000008 -#define CRTC_CSYNC_EN 0x00000010 -#define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */ -#define CRTC_DISPLAY_DIS 0x00000040 -#define CRTC_VGA_XOVERSCAN 0x00000040 - -#define CRTC_PIX_WIDTH_MASK 0x00000700 -#define CRTC_PIX_WIDTH_4BPP 0x00000100 -#define CRTC_PIX_WIDTH_8BPP 0x00000200 -#define CRTC_PIX_WIDTH_15BPP 0x00000300 -#define CRTC_PIX_WIDTH_16BPP 0x00000400 -#define CRTC_PIX_WIDTH_24BPP 0x00000500 -#define CRTC_PIX_WIDTH_32BPP 0x00000600 - -#define CRTC_BYTE_PIX_ORDER 0x00000800 -#define CRTC_PIX_ORDER_MSN_LSN 0x00000000 -#define CRTC_PIX_ORDER_LSN_MSN 0x00000800 - -#define CRTC_FIFO_LWM 0x000f0000 - -#define VGA_128KAP_PAGING 0x00100000 -#define VFC_SYNC_TRISTATE 0x00200000 -#define CRTC_LOCK_REGS 0x00400000 -#define CRTC_SYNC_TRISTATE 0x00800000 - -#define CRTC_EXT_DISP_EN 0x01000000 -#define CRTC_ENABLE 0x02000000 -#define CRTC_DISP_REQ_ENB 0x04000000 -#define VGA_ATI_LINEAR 0x08000000 -#define CRTC_VSYNC_FALL_EDGE 0x10000000 -#define VGA_TEXT_132 0x20000000 -#define VGA_XCRT_CNT_EN 0x40000000 -#define VGA_CUR_B_TEST 0x80000000 - -#define CRTC_CRNT_VLINE 0x07f00000 -#define CRTC_VBLANK 0x00000001 - - -/* DAC control values */ - -#define DAC_EXT_SEL_RS2 0x01 -#define DAC_EXT_SEL_RS3 0x02 -#define DAC_8BIT_EN 0x00000100 -#define DAC_PIX_DLY_MASK 0x00000600 -#define DAC_PIX_DLY_0NS 0x00000000 -#define DAC_PIX_DLY_2NS 0x00000200 -#define DAC_PIX_DLY_4NS 0x00000400 -#define DAC_BLANK_ADJ_MASK 0x00001800 -#define DAC_BLANK_ADJ_0 0x00000000 -#define DAC_BLANK_ADJ_1 0x00000800 -#define DAC_BLANK_ADJ_2 0x00001000 - - -/* Mix control values */ - -#define MIX_NOT_DST 0x0000 -#define MIX_0 0x0001 -#define MIX_1 0x0002 -#define MIX_DST 0x0003 -#define MIX_NOT_SRC 0x0004 -#define MIX_XOR 0x0005 -#define MIX_XNOR 0x0006 -#define MIX_SRC 0x0007 -#define MIX_NAND 0x0008 -#define MIX_NOT_SRC_OR_DST 0x0009 -#define MIX_SRC_OR_NOT_DST 0x000a -#define MIX_OR 0x000b -#define MIX_AND 0x000c -#define MIX_SRC_AND_NOT_DST 0x000d -#define MIX_NOT_SRC_AND_DST 0x000e -#define MIX_NOR 0x000f - -/* Maximum engine dimensions */ -#define ENGINE_MIN_X 0 -#define ENGINE_MIN_Y 0 -#define ENGINE_MAX_X 4095 -#define ENGINE_MAX_Y 16383 - -/* Mach64 engine bit constants - these are typically ORed together */ - -/* BUS_CNTL register constants */ -#define BUS_FIFO_ERR_ACK 0x00200000 -#define BUS_HOST_ERR_ACK 0x00800000 - -/* GEN_TEST_CNTL register constants */ -#define GEN_OVR_OUTPUT_EN 0x20 -#define HWCURSOR_ENABLE 0x80 -#define GUI_ENGINE_ENABLE 0x100 -#define BLOCK_WRITE_ENABLE 0x200 - -/* DSP_CONFIG register constants */ -#define DSP_XCLKS_PER_QW 0x00003fff -#define DSP_LOOP_LATENCY 0x000f0000 -#define DSP_PRECISION 0x00700000 - -/* DSP_ON_OFF register constants */ -#define DSP_OFF 0x000007ff -#define DSP_ON 0x07ff0000 - -/* CLOCK_CNTL register constants */ -#define CLOCK_SEL 0x0f -#define CLOCK_DIV 0x30 -#define CLOCK_DIV1 0x00 -#define CLOCK_DIV2 0x10 -#define CLOCK_DIV4 0x20 -#define CLOCK_STROBE 0x40 -#define PLL_WR_EN 0x02 - -/* PLL register indices */ -#define MPLL_CNTL 0x00 -#define VPLL_CNTL 0x01 -#define PLL_REF_DIV 0x02 -#define PLL_GEN_CNTL 0x03 -#define MCLK_FB_DIV 0x04 -#define PLL_VCLK_CNTL 0x05 -#define VCLK_POST_DIV 0x06 -#define VCLK0_FB_DIV 0x07 -#define VCLK1_FB_DIV 0x08 -#define VCLK2_FB_DIV 0x09 -#define VCLK3_FB_DIV 0x0A -#define PLL_EXT_CNTL 0x0B -#define DLL_CNTL 0x0C -#define DLL1_CNTL 0x0C -#define VFC_CNTL 0x0D -#define PLL_TEST_CNTL 0x0E -#define PLL_TEST_COUNT 0x0F -#define LVDS_CNTL0 0x10 -#define LVDS_CNTL1 0x11 -#define AGP1_CNTL 0x12 -#define AGP2_CNTL 0x13 -#define DLL2_CNTL 0x14 -#define SCLK_FB_DIV 0x15 -#define SPLL_CNTL1 0x16 -#define SPLL_CNTL2 0x17 -#define APLL_STRAPS 0x18 -#define EXT_VPLL_CNTL 0x19 -#define EXT_VPLL_REF_DIV 0x1A -#define EXT_VPLL_FB_DIV 0x1B -#define EXT_VPLL_MSB 0x1C -#define HTOTAL_CNTL 0x1D -#define BYTE_CLK_CNTL 0x1E -#define TV_PLL_CNTL1 0x1F -#define TV_PLL_CNTL2 0x20 -#define TV_PLL_CNTL 0x21 -#define EXT_TV_PLL 0x22 -#define V2PLL_CNTL 0x23 -#define PLL_V2CLK_CNTL 0x24 -#define EXT_V2PLL_REF_DIV 0x25 -#define EXT_V2PLL_FB_DIV 0x26 -#define EXT_V2PLL_MSB 0x27 -#define HTOTAL2_CNTL 0x28 -#define PLL_YCLK_CNTL 0x29 -#define PM_DYN_CLK_CNTL 0x2A - -/* Fields in PLL registers */ -#define PLL_PC_GAIN 0x07 -#define PLL_VC_GAIN 0x18 -#define PLL_DUTY_CYC 0xE0 -#define PLL_OVERRIDE 0x01 -#define PLL_MCLK_RST 0x02 -#define OSC_EN 0x04 -#define EXT_CLK_EN 0x08 -#define MCLK_SRC_SEL 0x70 -#define EXT_CLK_CNTL 0x80 -#define VCLK_SRC_SEL 0x03 -#define PLL_VCLK_RST 0x04 -#define VCLK_INVERT 0x08 -#define VCLK0_POST 0x03 -#define VCLK1_POST 0x0C -#define VCLK2_POST 0x30 -#define VCLK3_POST 0xC0 - -/* CONFIG_CNTL register constants */ -#define APERTURE_4M_ENABLE 1 -#define APERTURE_8M_ENABLE 2 -#define VGA_APERTURE_ENABLE 4 - -/* CONFIG_STAT0 register constants (GX, CX) */ -#define CFG_BUS_TYPE 0x00000007 -#define CFG_MEM_TYPE 0x00000038 -#define CFG_INIT_DAC_TYPE 0x00000e00 - -/* CONFIG_STAT0 register constants (CT, ET, VT) */ -#define CFG_MEM_TYPE_xT 0x00000007 - -#define ISA 0 -#define EISA 1 -#define LOCAL_BUS 6 -#define PCI 7 - -/* Memory types for GX, CX */ -#define DRAMx4 0 -#define VRAMx16 1 -#define VRAMx16ssr 2 -#define DRAMx16 3 -#define GraphicsDRAMx16 4 -#define EnhancedVRAMx16 5 -#define EnhancedVRAMx16ssr 6 - -/* Memory types for CT, ET, VT, GT */ -#define DRAM 1 -#define EDO 2 -#define PSEUDO_EDO 3 -#define SDRAM 4 -#define SGRAM 5 -#define WRAM 6 - -#define DAC_INTERNAL 0x00 -#define DAC_IBMRGB514 0x01 -#define DAC_ATI68875 0x02 -#define DAC_TVP3026_A 0x72 -#define DAC_BT476 0x03 -#define DAC_BT481 0x04 -#define DAC_ATT20C491 0x14 -#define DAC_SC15026 0x24 -#define DAC_MU9C1880 0x34 -#define DAC_IMSG174 0x44 -#define DAC_ATI68860_B 0x05 -#define DAC_ATI68860_C 0x15 -#define DAC_TVP3026_B 0x75 -#define DAC_STG1700 0x06 -#define DAC_ATT498 0x16 -#define DAC_STG1702 0x07 -#define DAC_SC15021 0x17 -#define DAC_ATT21C498 0x27 -#define DAC_STG1703 0x37 -#define DAC_CH8398 0x47 -#define DAC_ATT20C408 0x57 - -#define CLK_ATI18818_0 0 -#define CLK_ATI18818_1 1 -#define CLK_STG1703 2 -#define CLK_CH8398 3 -#define CLK_INTERNAL 4 -#define CLK_ATT20C408 5 -#define CLK_IBMRGB514 6 - -/* MEM_CNTL register constants */ -#define MEM_SIZE_ALIAS 0x00000007 -#define MEM_SIZE_512K 0x00000000 -#define MEM_SIZE_1M 0x00000001 -#define MEM_SIZE_2M 0x00000002 -#define MEM_SIZE_4M 0x00000003 -#define MEM_SIZE_6M 0x00000004 -#define MEM_SIZE_8M 0x00000005 -#define MEM_SIZE_ALIAS_GTB 0x0000000F -#define MEM_SIZE_2M_GTB 0x00000003 -#define MEM_SIZE_4M_GTB 0x00000007 -#define MEM_SIZE_6M_GTB 0x00000009 -#define MEM_SIZE_8M_GTB 0x0000000B -#define MEM_BNDRY 0x00030000 -#define MEM_BNDRY_0K 0x00000000 -#define MEM_BNDRY_256K 0x00010000 -#define MEM_BNDRY_512K 0x00020000 -#define MEM_BNDRY_1M 0x00030000 -#define MEM_BNDRY_EN 0x00040000 - -/* ATI PCI constants */ -#define PCI_ATI_VENDOR_ID 0x1002 - - -/* CONFIG_CHIP_ID register constants */ -#define CFG_CHIP_TYPE 0x0000FFFF -#define CFG_CHIP_CLASS 0x00FF0000 -#define CFG_CHIP_REV 0xFF000000 -#define CFG_CHIP_MAJOR 0x07000000 -#define CFG_CHIP_FND_ID 0x38000000 -#define CFG_CHIP_MINOR 0xC0000000 - - -/* Chip IDs read from CONFIG_CHIP_ID */ - -/* mach64GX family */ -#define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */ -#define CX_CHIP_ID 0x57 /* mach64CX (ATI888CX00) */ - -#define GX_PCI_ID 0x4758 /* mach64GX (ATI888GX00) */ -#define CX_PCI_ID 0x4358 /* mach64CX (ATI888CX00) */ - -/* mach64CT family */ -#define CT_CHIP_ID 0x4354 /* mach64CT (ATI264CT) */ -#define ET_CHIP_ID 0x4554 /* mach64ET (ATI264ET) */ - -/* mach64CT family / mach64VT class */ -#define VT_CHIP_ID 0x5654 /* mach64VT (ATI264VT) */ -#define VU_CHIP_ID 0x5655 /* mach64VTB (ATI264VTB) */ -#define VV_CHIP_ID 0x5656 /* mach64VT4 (ATI264VT4) */ - -/* mach64CT family / mach64GT (3D RAGE) class */ -#define LB_CHIP_ID 0x4c42 /* RAGE LT PRO, AGP */ -#define LD_CHIP_ID 0x4c44 /* RAGE LT PRO */ -#define LG_CHIP_ID 0x4c47 /* RAGE LT */ -#define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */ -#define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */ -#define LT_CHIP_ID 0x4c54 /* RAGE LT */ - -#define GR_CHIP_ID 0x4752 /* RAGE XL, BGA, PCI33 */ -#define GS_CHIP_ID 0x4753 /* RAGE XL, PQFP, PCI33 */ -#define GM_CHIP_ID 0x474d /* RAGE XL, BGA, AGP 1x,2x */ -#define GN_CHIP_ID 0x474e /* RAGE XL, PQFP,AGP 1x,2x */ -#define GO_CHIP_ID 0x474f /* RAGE XL, BGA, PCI66 */ -#define GL_CHIP_ID 0x474c /* RAGE XL, PQFP, PCI66 */ - -#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \ - (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \ - (id)==GO_CHIP_ID || (id)==GL_CHIP_ID) - -#define GT_CHIP_ID 0x4754 /* RAGE (GT) */ -#define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */ -#define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */ -#define GW_CHIP_ID 0x4757 /* RAGE IIC, AGP */ -#define GZ_CHIP_ID 0x475a /* RAGE IIC, AGP */ -#define GB_CHIP_ID 0x4742 /* RAGE PRO, BGA, AGP 1x and 2x */ -#define GD_CHIP_ID 0x4744 /* RAGE PRO, BGA, AGP 1x only */ -#define GI_CHIP_ID 0x4749 /* RAGE PRO, BGA, PCI33 only */ -#define GP_CHIP_ID 0x4750 /* RAGE PRO, PQFP, PCI33, full 3D */ -#define GQ_CHIP_ID 0x4751 /* RAGE PRO, PQFP, PCI33, limited 3D */ -#define LM_CHIP_ID 0x4c4d /* RAGE Mobility PCI */ -#define LN_CHIP_ID 0x4c4e /* RAGE Mobility AGP */ - - -/* Mach64 major ASIC revisions */ -#define MACH64_ASIC_NEC_VT_A3 0x08 -#define MACH64_ASIC_NEC_VT_A4 0x48 -#define MACH64_ASIC_SGS_VT_A4 0x40 -#define MACH64_ASIC_SGS_VT_B1S1 0x01 -#define MACH64_ASIC_SGS_GT_B1S1 0x01 -#define MACH64_ASIC_SGS_GT_B1S2 0x41 -#define MACH64_ASIC_UMC_GT_B2U1 0x1a -#define MACH64_ASIC_UMC_GT_B2U2 0x5a -#define MACH64_ASIC_UMC_VT_B2U3 0x9a -#define MACH64_ASIC_UMC_GT_B2U3 0x9a -#define MACH64_ASIC_UMC_R3B_D_P_A1 0x1b -#define MACH64_ASIC_UMC_R3B_D_P_A2 0x5b -#define MACH64_ASIC_UMC_R3B_D_P_A3 0x1c -#define MACH64_ASIC_UMC_R3B_D_P_A4 0x5c - -/* Mach64 foundries */ -#define MACH64_FND_SGS 0 -#define MACH64_FND_NEC 1 -#define MACH64_FND_UMC 3 - -/* Mach64 chip types */ -#define MACH64_UNKNOWN 0 -#define MACH64_GX 1 -#define MACH64_CX 2 -#define MACH64_CT 3 -#define MACH64_ET 4 -#define MACH64_VT 5 -#define MACH64_GT 6 - -/* DST_CNTL register constants */ -#define DST_X_RIGHT_TO_LEFT 0 -#define DST_X_LEFT_TO_RIGHT 1 -#define DST_Y_BOTTOM_TO_TOP 0 -#define DST_Y_TOP_TO_BOTTOM 2 -#define DST_X_MAJOR 0 -#define DST_Y_MAJOR 4 -#define DST_X_TILE 8 -#define DST_Y_TILE 0x10 -#define DST_LAST_PEL 0x20 -#define DST_POLYGON_ENABLE 0x40 -#define DST_24_ROTATION_ENABLE 0x80 - -/* SRC_CNTL register constants */ -#define SRC_PATTERN_ENABLE 1 -#define SRC_ROTATION_ENABLE 2 -#define SRC_LINEAR_ENABLE 4 -#define SRC_BYTE_ALIGN 8 -#define SRC_LINE_X_RIGHT_TO_LEFT 0 -#define SRC_LINE_X_LEFT_TO_RIGHT 0x10 - -/* HOST_CNTL register constants */ -#define HOST_BYTE_ALIGN 1 - -/* GUI_TRAJ_CNTL register constants */ -#define PAT_MONO_8x8_ENABLE 0x01000000 -#define PAT_CLR_4x2_ENABLE 0x02000000 -#define PAT_CLR_8x1_ENABLE 0x04000000 - -/* DP_CHAIN_MASK register constants */ -#define DP_CHAIN_4BPP 0x8888 -#define DP_CHAIN_7BPP 0xD2D2 -#define DP_CHAIN_8BPP 0x8080 -#define DP_CHAIN_8BPP_RGB 0x9292 -#define DP_CHAIN_15BPP 0x4210 -#define DP_CHAIN_16BPP 0x8410 -#define DP_CHAIN_24BPP 0x8080 -#define DP_CHAIN_32BPP 0x8080 - -/* DP_PIX_WIDTH register constants */ -#define DST_1BPP 0 -#define DST_4BPP 1 -#define DST_8BPP 2 -#define DST_15BPP 3 -#define DST_16BPP 4 -#define DST_32BPP 6 -#define SRC_1BPP 0 -#define SRC_4BPP 0x100 -#define SRC_8BPP 0x200 -#define SRC_15BPP 0x300 -#define SRC_16BPP 0x400 -#define SRC_32BPP 0x600 -#define HOST_1BPP 0 -#define HOST_4BPP 0x10000 -#define HOST_8BPP 0x20000 -#define HOST_15BPP 0x30000 -#define HOST_16BPP 0x40000 -#define HOST_32BPP 0x60000 -#define BYTE_ORDER_MSB_TO_LSB 0 -#define BYTE_ORDER_LSB_TO_MSB 0x1000000 - -/* DP_MIX register constants */ -#define BKGD_MIX_NOT_D 0 -#define BKGD_MIX_ZERO 1 -#define BKGD_MIX_ONE 2 -#define BKGD_MIX_D 3 -#define BKGD_MIX_NOT_S 4 -#define BKGD_MIX_D_XOR_S 5 -#define BKGD_MIX_NOT_D_XOR_S 6 -#define BKGD_MIX_S 7 -#define BKGD_MIX_NOT_D_OR_NOT_S 8 -#define BKGD_MIX_D_OR_NOT_S 9 -#define BKGD_MIX_NOT_D_OR_S 10 -#define BKGD_MIX_D_OR_S 11 -#define BKGD_MIX_D_AND_S 12 -#define BKGD_MIX_NOT_D_AND_S 13 -#define BKGD_MIX_D_AND_NOT_S 14 -#define BKGD_MIX_NOT_D_AND_NOT_S 15 -#define BKGD_MIX_D_PLUS_S_DIV2 0x17 -#define FRGD_MIX_NOT_D 0 -#define FRGD_MIX_ZERO 0x10000 -#define FRGD_MIX_ONE 0x20000 -#define FRGD_MIX_D 0x30000 -#define FRGD_MIX_NOT_S 0x40000 -#define FRGD_MIX_D_XOR_S 0x50000 -#define FRGD_MIX_NOT_D_XOR_S 0x60000 -#define FRGD_MIX_S 0x70000 -#define FRGD_MIX_NOT_D_OR_NOT_S 0x80000 -#define FRGD_MIX_D_OR_NOT_S 0x90000 -#define FRGD_MIX_NOT_D_OR_S 0xa0000 -#define FRGD_MIX_D_OR_S 0xb0000 -#define FRGD_MIX_D_AND_S 0xc0000 -#define FRGD_MIX_NOT_D_AND_S 0xd0000 -#define FRGD_MIX_D_AND_NOT_S 0xe0000 -#define FRGD_MIX_NOT_D_AND_NOT_S 0xf0000 -#define FRGD_MIX_D_PLUS_S_DIV2 0x170000 - -/* DP_SRC register constants */ -#define BKGD_SRC_BKGD_CLR 0 -#define BKGD_SRC_FRGD_CLR 1 -#define BKGD_SRC_HOST 2 -#define BKGD_SRC_BLIT 3 -#define BKGD_SRC_PATTERN 4 -#define FRGD_SRC_BKGD_CLR 0 -#define FRGD_SRC_FRGD_CLR 0x100 -#define FRGD_SRC_HOST 0x200 -#define FRGD_SRC_BLIT 0x300 -#define FRGD_SRC_PATTERN 0x400 -#define MONO_SRC_ONE 0 -#define MONO_SRC_PATTERN 0x10000 -#define MONO_SRC_HOST 0x20000 -#define MONO_SRC_BLIT 0x30000 - -/* CLR_CMP_CNTL register constants */ -#define COMPARE_FALSE 0 -#define COMPARE_TRUE 1 -#define COMPARE_NOT_EQUAL 4 -#define COMPARE_EQUAL 5 -#define COMPARE_DESTINATION 0 -#define COMPARE_SOURCE 0x1000000 - -/* FIFO_STAT register constants */ -#define FIFO_ERR 0x80000000 - -/* CONTEXT_LOAD_CNTL constants */ -#define CONTEXT_NO_LOAD 0 -#define CONTEXT_LOAD 0x10000 -#define CONTEXT_LOAD_AND_DO_FILL 0x20000 -#define CONTEXT_LOAD_AND_DO_LINE 0x30000 -#define CONTEXT_EXECUTE 0 -#define CONTEXT_CMD_DISABLE 0x80000000 - -/* GUI_STAT register constants */ -#define ENGINE_IDLE 0 -#define ENGINE_BUSY 1 -#define SCISSOR_LEFT_FLAG 0x10 -#define SCISSOR_RIGHT_FLAG 0x20 -#define SCISSOR_TOP_FLAG 0x40 -#define SCISSOR_BOTTOM_FLAG 0x80 - -/* ATI VGA Extended Registers */ -#define sioATIEXT 0x1ce -#define bioATIEXT 0x3ce - -#define ATI2E 0xae -#define ATI32 0xb2 -#define ATI36 0xb6 - -/* VGA Graphics Controller Registers */ -#define VGAGRA 0x3ce -#define GRA06 0x06 - -/* VGA Sequencer Registers */ -#define VGASEQ 0x3c4 -#define SEQ02 0x02 -#define SEQ04 0x04 - -#define MACH64_MAX_X ENGINE_MAX_X -#define MACH64_MAX_Y ENGINE_MAX_Y - -#define INC_X 0x0020 -#define INC_Y 0x0080 - -#define RGB16_555 0x0000 -#define RGB16_565 0x0040 -#define RGB16_655 0x0080 -#define RGB16_664 0x00c0 - -#define POLY_TEXT_TYPE 0x0001 -#define IMAGE_TEXT_TYPE 0x0002 -#define TEXT_TYPE_8_BIT 0x0004 -#define TEXT_TYPE_16_BIT 0x0008 -#define POLY_TEXT_TYPE_8 (POLY_TEXT_TYPE | TEXT_TYPE_8_BIT) -#define IMAGE_TEXT_TYPE_8 (IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT) -#define POLY_TEXT_TYPE_16 (POLY_TEXT_TYPE | TEXT_TYPE_16_BIT) -#define IMAGE_TEXT_TYPE_16 (IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT) - -#define MACH64_NUM_CLOCKS 16 -#define MACH64_NUM_FREQS 50 - -/* Power Management register constants (LT & LT Pro) */ -#define PWR_MGT_ON 0x00000001 -#define PWR_MGT_MODE_MASK 0x00000006 -#define AUTO_PWR_UP 0x00000008 -#define USE_F32KHZ 0x00000400 -#define TRISTATE_MEM_EN 0x00000800 -#define SELF_REFRESH 0x00000080 -#define PWR_BLON 0x02000000 -#define STANDBY_NOW 0x10000000 -#define SUSPEND_NOW 0x20000000 -#define PWR_MGT_STATUS_MASK 0xC0000000 -#define PWR_MGT_STATUS_SUSPEND 0x80000000 - -/* PM Mode constants */ -#define PWR_MGT_MODE_PIN 0x00000000 -#define PWR_MGT_MODE_REG 0x00000002 -#define PWR_MGT_MODE_TIMER 0x00000004 -#define PWR_MGT_MODE_PCI 0x00000006 - -/* LCD registers (LT Pro) */ - -/* LCD Index register */ -#define LCD_INDEX_MASK 0x0000003F -#define LCD_DISPLAY_DIS 0x00000100 -#define LCD_SRC_SEL 0x00000200 -#define CRTC2_DISPLAY_DIS 0x00000400 - -/* LCD register indices */ -#define CONFIG_PANEL 0x00 -#define LCD_GEN_CTRL 0x01 -#define DSTN_CONTROL 0x02 -#define HFB_PITCH_ADDR 0x03 -#define HORZ_STRETCHING 0x04 -#define VERT_STRETCHING 0x05 -#define EXT_VERT_STRETCH 0x06 -#define LT_GIO 0x07 -#define POWER_MANAGEMENT 0x08 -#define ZVGPIO 0x09 -#define ICON_CLR0 0x0A -#define ICON_CLR1 0x0B -#define ICON_OFFSET 0x0C -#define ICON_HORZ_VERT_POSN 0x0D -#define ICON_HORZ_VERT_OFF 0x0E -#define ICON2_CLR0 0x0F -#define ICON2_CLR1 0x10 -#define ICON2_OFFSET 0x11 -#define ICON2_HORZ_VERT_POSN 0x12 -#define ICON2_HORZ_VERT_OFF 0x13 -#define LCD_MISC_CNTL 0x14 -#define APC_CNTL 0x1C -#define POWER_MANAGEMENT_2 0x1D -#define ALPHA_BLENDING 0x25 -#define PORTRAIT_GEN_CNTL 0x26 -#define APC_CTRL_IO 0x27 -#define TEST_IO 0x28 -#define TEST_OUTPUTS 0x29 -#define DP1_MEM_ACCESS 0x2A -#define DP0_MEM_ACCESS 0x2B -#define DP0_DEBUG_A 0x2C -#define DP0_DEBUG_B 0x2D -#define DP1_DEBUG_A 0x2E -#define DP1_DEBUG_B 0x2F -#define DPCTRL_DEBUG_A 0x30 -#define DPCTRL_DEBUG_B 0x31 -#define MEMBLK_DEBUG 0x32 -#define APC_LUT_AB 0x33 -#define APC_LUT_CD 0x34 -#define APC_LUT_EF 0x35 -#define APC_LUT_GH 0x36 -#define APC_LUT_IJ 0x37 -#define APC_LUT_KL 0x38 -#define APC_LUT_MN 0x39 -#define APC_LUT_OP 0x3A - - -/* Values in LCD_MISC_CNTL */ -#define BIAS_MOD_LEVEL_MASK 0x0000ff00 -#define BIAS_MOD_LEVEL_SHIFT 8 -#define BLMOD_EN 0x00010000 -#define BIASMOD_EN 0x00020000 - -#endif /* REGMACH64_H */ diff --git a/src/drivers/ati/ragexl/mach64_ct.c b/src/drivers/ati/ragexl/mach64_ct.c deleted file mode 100644 index 9b45f2a..0000000 --- a/src/drivers/ati/ragexl/mach64_ct.c +++ /dev/null @@ -1,370 +0,0 @@ -#define DEBUG_PLL 0 -#define PLL_CRTC_DECODE 0 - -/* FIXME: remove the FAIL definition */ -#if 0 -#define FAIL(x) do { printk(BIOS_DEBUG, x); return -EINVAL; } while (0) -#else -#define FAIL(x) -#endif - -static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, - struct pll_ct *pll); -static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp, - struct pll_ct *pll); -static int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per, - u8 bpp, union aty_pll *pll); -#if PLL_CRTC_DECODE==1 -static u32 aty_pll_ct_to_var(const struct fb_info_aty *info, - const union aty_pll *pll); -#endif - -/* ------------------------------------------------------------------------- */ - - /* - * PLL programming (Mach64 CT family) - */ -static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp, - struct pll_ct *pll) -{ - u32 dsp_xclks_per_row, dsp_loop_latency, dsp_precision, dsp_off, dsp_on; - u32 xclks_per_row, fifo_off, fifo_on, y, fifo_size; - u32 memcntl, n, t_pfc, t_rp, t_ras, t_rcd, t_crd, t_rcc, t_lat; - -#if DEBUG_PLL==1 - printk(BIOS_DEBUG, "aty_dsp_gt : mclk_fb_mult=%d\n", pll->mclk_fb_mult); -#endif - - /* (64*xclk/vclk/bpp)<<11 = xclocks_per_row<<11 */ - xclks_per_row = ((u32)pll->mclk_fb_mult * (u32)pll->mclk_fb_div * - (u32)pll->vclk_post_div_real * 64) << 11; - xclks_per_row /= - (2 * (u32)pll->vclk_fb_div * (u32)pll->xclk_post_div_real * bpp); - - if (xclks_per_row < (1<<11)) - FAIL("Dotclock too high"); - if (M64_HAS(FIFO_24)) { - fifo_size = 24; - dsp_loop_latency = 0; - } else { - fifo_size = 32; - dsp_loop_latency = 2; - } - dsp_precision = 0; - y = (xclks_per_row*fifo_size)>>11; - while (y) { - y >>= 1; - dsp_precision++; - } - dsp_precision -= 5; - - /* fifo_off<<6 */ - fifo_off = ((xclks_per_row*(fifo_size-1))>>5); // + (3<<6); - - if (info->total_vram > 1*1024*1024) { - switch (info->ram_type) { - case WRAM: - /* >1 MB WRAM */ - dsp_loop_latency += 9; - n = 4; - break; - case SDRAM: - case SGRAM: - /* >1 MB SDRAM */ - dsp_loop_latency += 8; - n = 2; - break; - default: - /* >1 MB DRAM */ - dsp_loop_latency += 6; - n = 3; - break; - } - } else { - if (info->ram_type >= SDRAM) { - /* <2 MB SDRAM */ - dsp_loop_latency += 9; - n = 2; - } else { - /* <2 MB DRAM */ - dsp_loop_latency += 8; - n = 3; - } - } - - memcntl = aty_ld_le32(MEM_CNTL, info); - t_rcd = ((memcntl >> 10) & 0x03) + 1; - t_crd = ((memcntl >> 12) & 0x01); - t_rp = ((memcntl >> 8) & 0x03) + 1; - t_ras = ((memcntl >> 16) & 0x07) + 1; - t_lat = (memcntl >> 4) & 0x03; - - t_pfc = t_rp + t_rcd + t_crd; - - t_rcc = max(t_rp + t_ras, t_pfc + n); - - /* fifo_on<<6 */ - fifo_on = (2 * t_rcc + t_pfc + n - 1) << 6; - - dsp_xclks_per_row = xclks_per_row>>dsp_precision; - dsp_on = fifo_on>>dsp_precision; - dsp_off = fifo_off>>dsp_precision; - - pll->dsp_config = (dsp_xclks_per_row & 0x3fff) | - ((dsp_loop_latency & 0xf)<<16) | - ((dsp_precision & 7)<<20); - pll->dsp_on_off = (dsp_off & 0x7ff) | ((dsp_on & 0x7ff)<<16); - return 0; -} - - -static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, - struct pll_ct *pll) -{ -#if DEBUG_PLL==1 - int pllmclk, pllsclk; -#endif - u32 q; - - pll->pll_ref_div = info->pll_per*2*255/info->ref_clk_per; - - /* FIXME: use the VTB/GTB /3 post divider if it's better suited */ - - /* actually 8*q */ - q = info->ref_clk_per*pll->pll_ref_div*4/info->mclk_per; - - if (q < 16*8 || q > 255*8) - FAIL("mclk out of range\n"); - else if (q < 32*8) - pll->mclk_post_div_real = 8; - else if (q < 64*8) - pll->mclk_post_div_real = 4; - else if (q < 128*8) - pll->mclk_post_div_real = 2; - else - pll->mclk_post_div_real = 1; - pll->sclk_fb_div = q*pll->mclk_post_div_real/8; - -#if DEBUG_PLL==1 - pllsclk = (1000000 * 2 * pll->sclk_fb_div) / - (info->ref_clk_per * pll->pll_ref_div); - - printk(BIOS_DEBUG, "aty_valid_pll_ct: pllsclk=%d MHz, mclk=%d MHz\n", - pllsclk, pllsclk / pll->mclk_post_div_real); -#endif - - pll->mclk_fb_mult = M64_HAS(MFB_TIMES_4) ? 4 : 2; - - /* actually 8*q */ - q = info->ref_clk_per * pll->pll_ref_div * 8 / - (pll->mclk_fb_mult * info->xclk_per); - - if (q < 16*8 || q > 255*8) - FAIL("mclk out of range\n"); - else if (q < 32*8) - pll->xclk_post_div_real = 8; - else if (q < 64*8) - pll->xclk_post_div_real = 4; - else if (q < 128*8) - pll->xclk_post_div_real = 2; - else - pll->xclk_post_div_real = 1; - pll->mclk_fb_div = q*pll->xclk_post_div_real/8; - -#if DEBUG_PLL==1 - pllmclk = (1000000 * pll->mclk_fb_mult * pll->mclk_fb_div) / - (info->ref_clk_per * pll->pll_ref_div); - printk(BIOS_DEBUG, "aty_valid_pll_ct: pllmclk=%d MHz, xclk=%d MHz\n", - pllmclk, pllmclk / pll->xclk_post_div_real); -#endif - - /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */ - q = info->ref_clk_per*pll->pll_ref_div*4/vclk_per; /* actually 8*q */ - if (q < 16*8 || q > 255*8) - FAIL("vclk out of range\n"); - else if (q < 32*8) - pll->vclk_post_div_real = 8; - else if (q < 64*8) - pll->vclk_post_div_real = 4; - else if (q < 128*8) - pll->vclk_post_div_real = 2; - else - pll->vclk_post_div_real = 1; - pll->vclk_fb_div = q*pll->vclk_post_div_real/8; - return 0; -} - -static void aty_calc_pll_ct(const struct fb_info_aty *info, struct pll_ct *pll) -{ - u8 xpostdiv = 0; - u8 mpostdiv = 0; - u8 vpostdiv = 0; - - if (M64_HAS(SDRAM_MAGIC_PLL) && (info->ram_type >= SDRAM)) - pll->pll_gen_cntl = 0x64; /* mclk = sclk */ - else - pll->pll_gen_cntl = 0xe4; /* mclk = sclk */ - - switch (pll->mclk_post_div_real) { - case 1: - mpostdiv = 0; - break; - case 2: - mpostdiv = 1; - break; - case 4: - mpostdiv = 2; - break; - case 8: - mpostdiv = 3; - break; - } - - pll->spll_cntl2 = mpostdiv << 4; /* sclk == pllsclk / mpostdiv */ - - switch (pll->xclk_post_div_real) { - case 1: - xpostdiv = 0; - break; - case 2: - xpostdiv = 1; - break; - case 3: - xpostdiv = 4; - break; - case 4: - xpostdiv = 2; - break; - case 8: - xpostdiv = 3; - break; - } - - if (M64_HAS(MAGIC_POSTDIV)) - pll->pll_ext_cntl = 0; - else - pll->pll_ext_cntl = xpostdiv; /* xclk == pllmclk / xpostdiv */ - - if (pll->mclk_fb_mult == 4) - pll->pll_ext_cntl |= 0x08; - - switch (pll->vclk_post_div_real) { - case 2: - vpostdiv = 1; - break; - case 3: - pll->pll_ext_cntl |= 0x10; - case 1: - vpostdiv = 0; - break; - case 6: - pll->pll_ext_cntl |= 0x10; - case 4: - vpostdiv = 2; - break; - case 12: - pll->pll_ext_cntl |= 0x10; - case 8: - vpostdiv = 3; - break; - } - - pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ - pll->vclk_post_div = vpostdiv; -} - -int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per, - u8 bpp, union aty_pll *pll) -{ - int err; - if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct))) - return err; - if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct))) - return err; - aty_calc_pll_ct(info, &pll->ct); - return 0; -} -#if CONFIG_CONSOLE_BTEXT -#if PLL_CRTC_DECODE==1 -u32 aty_pll_ct_to_var(const struct fb_info_aty *info, - const union aty_pll *pll) -{ - u32 ref_clk_per = info->ref_clk_per; - u8 pll_ref_div = pll->ct.pll_ref_div; - u8 vclk_fb_div = pll->ct.vclk_fb_div; - u8 vclk_post_div = pll->ct.vclk_post_div_real; - - return ref_clk_per*pll_ref_div*vclk_post_div/vclk_fb_div/2; -} -#endif -void aty_set_pll_ct(const struct fb_info_aty *info, const union aty_pll *pll) -{ -#if DEBUG_PLL==1 - printk(BIOS_DEBUG, "aty_set_pll_ct: about to program:\n" - "refdiv=%d, extcntl=0x%02x, mfbdiv=%d\n" - "spllcntl2=0x%02x, sfbdiv=%d, gencntl=0x%02x\n" - "vclkcntl=0x%02x, vpostdiv=0x%02x, vfbdiv=%d\n" - "clocksel=%d\n", - pll->ct.pll_ref_div, pll->ct.pll_ext_cntl, - pll->ct.mclk_fb_div, pll->ct.spll_cntl2, - pll->ct.sclk_fb_div, pll->ct.pll_gen_cntl, - pll->ct.pll_vclk_cntl, pll->ct.vclk_post_div, - pll->ct.vclk_fb_div, aty_ld_le32(CLOCK_CNTL, info) & 0x03); -#endif - - aty_st_pll(PLL_REF_DIV, pll->ct.pll_ref_div, info); - - aty_st_pll(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, info); - aty_st_pll(MCLK_FB_DIV, pll->ct.mclk_fb_div, info); // for XCLK - - aty_st_pll(SPLL_CNTL2, pll->ct.spll_cntl2, info); - aty_st_pll(SCLK_FB_DIV, pll->ct.sclk_fb_div, info); // for MCLK - - aty_st_pll(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, info); - - aty_st_pll(EXT_VPLL_CNTL, 0, info); - aty_st_pll(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, info); - aty_st_pll(VCLK_POST_DIV, pll->ct.vclk_post_div, info); - aty_st_pll(VCLK0_FB_DIV, pll->ct.vclk_fb_div, info); - - if (M64_HAS(GTB_DSP)) { - u8 dll_cntl; - - if (M64_HAS(XL_DLL)) - dll_cntl = 0x80; - else if (info->ram_type >= SDRAM) - dll_cntl = 0xa6; - else - dll_cntl = 0xa0; - aty_st_pll(DLL_CNTL, dll_cntl, info); - aty_st_pll(VFC_CNTL, 0x1b, info); - aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, info); - aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, info); - - mdelay(10); - aty_st_pll(DLL_CNTL, dll_cntl, info); - mdelay(10); - aty_st_pll(DLL_CNTL, dll_cntl | 0x40, info); - mdelay(10); - aty_st_pll(DLL_CNTL, dll_cntl & ~0x40, info); - } -} -#if 0 -static int dummy(void) -{ - return 0; -} -static struct aty_dac_ops aty_dac_ct = { - set_dac: (void *)dummy, -}; - -static struct aty_pll_ops aty_pll_ct = { - var_to_pll: aty_var_to_pll_ct, -#if 0 - pll_to_var: aty_pll_ct_to_var, - set_pll: aty_set_pll_ct, -#endif -}; -#endif - -#endif /* CONFIG_CONSOLE_BTEXT */ diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c deleted file mode 100644 index 41cea72..0000000 --- a/src/drivers/ati/ragexl/xlinit.c +++ /dev/null @@ -1,1518 +0,0 @@ -/* - * ATI Rage XL Initialization. Support for Xpert98 and Victoria - * PCI cards. - * - * Copyright (C) 2002 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * stevel(a)mvista.com or source(a)mvista.com - * Copyright (C) 2004 Tyan Computer. - * Auther: Yinghai Lu yhlu(a)tyan.com - * move to coreboot - * This code is distributed without warranty under the GPL v2 (see COPYING) * - */ -#include <delay.h> -#include <stdlib.h> -#include <string.h> -#include <arch/io.h> - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - -// FIXME BTEXT console within coreboot has been obsoleted -// and will go away. The BTEXT code in this file should be -// fixed to export a framebuffer console through the coreboot -// table (and possibly make it available for bootsplash use) -// Hence do only remove this if you fix the code. -#define CONFIG_CONSOLE_BTEXT 0 - -#if CONFIG_CONSOLE_BTEXT - -#define PLL_CRTC_DECODE 0 -#define SUPPORT_8_BPP_ABOVE 0 - -#include "fb.h" -#include "fbcon.h" - -struct aty_cmap_regs { - u8 windex; - u8 lut; - u8 mask; - u8 rindex; - u8 cntl; -}; - -#include <console/btext.h> - -#endif /*CONFIG_CONSOLE_BTEXT*/ - -#include "mach64.h" - -#include "atyfb.h" - -#include "mach64_ct.c" - -#define MPLL_GAIN 0xad -#define VPLL_GAIN 0xd5 - -#define HAS_VICTORIA 0 - -enum { -#if HAS_VICTORIA==1 - VICTORIA = 0, - XPERT98, -#else - XPERT98=0, -#endif - NUM_XL_CARDS -}; - -//static struct aty_pll_ops aty_pll_ct; - -#define DEFAULT_CARD XPERT98 -static int xl_card = DEFAULT_CARD; - -static const struct xl_card_cfg_t { - int ref_crystal; // 10^4 Hz - int mem_type; - int mem_size; - u32 mem_cntl; - u32 ext_mem_cntl; - u32 mem_addr_config; - u32 bus_cntl; - u32 dac_cntl; - u32 hw_debug; - u32 custom_macro_cntl; - u8 dll2_cntl; - u8 pll_yclk_cntl; -} card_cfg[NUM_XL_CARDS] = { -#if HAS_VICTORIA==1 - // VICTORIA - { 2700, SDRAM, 0x800000, - 0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040, - 0x82010102, 0x48803800, 0x005E0179, - 0x50, 0x25 - }, -#endif - // XPERT98 - { 1432, WRAM, 0x800000, - 0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001, - 0x8000000A, 0x48833800, 0x007F0779, - 0x10, 0x19 - } -}; - -typedef struct { - u8 lcd_reg; - u32 val; -} lcd_tbl_t; - -static const lcd_tbl_t lcd_tbl[] = { - { 0x01, 0x000520C0 }, - { 0x08, 0x02000408 }, - { 0x03, 0x00000F00 }, - { 0x00, 0x00000000 }, - { 0x02, 0x00000000 }, - { 0x04, 0x00000000 }, - { 0x05, 0x00000000 }, - { 0x06, 0x00000000 }, - { 0x33, 0x00000000 }, - { 0x34, 0x00000000 }, - { 0x35, 0x00000000 }, - { 0x36, 0x00000000 }, - { 0x37, 0x00000000 } -}; - -static inline u32 aty_ld_lcd(u8 lcd_reg, struct fb_info_aty *info) -{ - aty_st_8(LCD_INDEX, lcd_reg, info); - return aty_ld_le32(LCD_DATA, info); -} - -static inline void aty_st_lcd(u8 lcd_reg, u32 val, - struct fb_info_aty *info) -{ - aty_st_8(LCD_INDEX, lcd_reg, info); - aty_st_le32(LCD_DATA, val, info); -} - -static void reset_gui(struct fb_info_aty *info) -{ - aty_st_8(GEN_TEST_CNTL+1, 0x01, info); - aty_st_8(GEN_TEST_CNTL+1, 0x00, info); - aty_st_8(GEN_TEST_CNTL+1, 0x02, info); - mdelay(5); -} - - -static void reset_sdram(struct fb_info_aty *info) -{ - u8 temp; - - temp = aty_ld_8(EXT_MEM_CNTL, info); - temp |= 0x02; - aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_RESET = 1b - temp |= 0x08; - aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 10b - temp |= 0x0c; - aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 11b - mdelay(5); - temp &= 0xf3; - aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 00b - temp &= 0xfd; - aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_REST = 0b - mdelay(5); -} - -static void init_dll(struct fb_info_aty *info) -{ - // enable DLL - aty_st_pll(PLL_GEN_CNTL, - aty_ld_pll(PLL_GEN_CNTL, info) & 0x7f, - info); - - // reset DLL - aty_st_pll(DLL_CNTL, 0x82, info); - aty_st_pll(DLL_CNTL, 0xE2, info); - mdelay(5); - aty_st_pll(DLL_CNTL, 0x82, info); - mdelay(6); -} - -static void reset_clocks(struct fb_info_aty *info, struct pll_ct *pll, - int hsync_enb) -{ - reset_gui(info); - aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, info); - aty_st_pll(SCLK_FB_DIV, pll->sclk_fb_div, info); - - mdelay(15); - init_dll(info); - aty_st_8(GEN_TEST_CNTL+1, 0x00, info); - mdelay(5); - aty_st_8(CRTC_GEN_CNTL+3, 0x04, info); - mdelay(6); - reset_sdram(info); - aty_st_8(CRTC_GEN_CNTL+3, - hsync_enb ? 0x00 : 0x04, info); - - aty_st_pll(SPLL_CNTL2, pll->spll_cntl2, info); - aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, info); - aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, info); -} - -static int atyfb_xl_init(struct fb_info_aty *info) -{ - int i, err; - u32 temp; - union aty_pll pll; - const struct xl_card_cfg_t * card = &card_cfg[xl_card]; - - aty_st_8(CONFIG_STAT0, 0x85, info); - mdelay(10); - - /* - * The following needs to be set before the call - * to var_to_pll() below. They'll be re-set again - * to the same values in aty_init(). - */ - info->ref_clk_per = 100000000UL/card->ref_crystal; - info->ram_type = card->mem_type; - info->total_vram = card->mem_size; -#if HAS_VICTORIA == 1 - if (xl_card == VICTORIA) { - // the MCLK, XCLK are 120MHz on victoria card - info->mclk_per = 1000000/120; - info->xclk_per = 1000000/120; - info->features &= ~M64F_MFB_TIMES_4; - } -#endif - - /* - * Calculate mclk and xclk dividers, etc. The passed - * pixclock and bpp values don't matter yet, the vclk - * isn't programmed until later. - */ - if ((err = aty_var_to_pll_ct(info, 39726, 8, &pll))) return err; -// if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err; - - - aty_st_pll(LVDS_CNTL0, 0x00, info); - aty_st_pll(DLL2_CNTL, card->dll2_cntl, info); - aty_st_pll(V2PLL_CNTL, 0x10, info); - aty_st_pll(MPLL_CNTL, MPLL_GAIN, info); - aty_st_pll(VPLL_CNTL, VPLL_GAIN, info); - aty_st_pll(PLL_VCLK_CNTL, 0x00, info); - aty_st_pll(VFC_CNTL, 0x1B, info); - aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, info); - aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info); - aty_st_pll(SPLL_CNTL2, 0x03, info); - aty_st_pll(PLL_GEN_CNTL, 0x44, info); - - reset_clocks(info, &pll.ct, 0); - mdelay(10); - - aty_st_pll(VCLK_POST_DIV, 0x03, info); - aty_st_pll(VCLK0_FB_DIV, 0xDA, info); - aty_st_pll(VCLK_POST_DIV, 0x0F, info); - aty_st_pll(VCLK1_FB_DIV, 0xF5, info); - aty_st_pll(VCLK_POST_DIV, 0x3F, info); - aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, info); - aty_st_pll(VCLK2_FB_DIV, 0x00, info); - aty_st_pll(VCLK_POST_DIV, 0xFF, info); - aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, info); - aty_st_pll(VCLK3_FB_DIV, 0x00, info); - - aty_st_8(BUS_CNTL, 0x01, info); - aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info); - - aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info); - aty_st_le16(CONFIG_STAT0, 0x0020, info); - aty_st_le32(MEM_CNTL, 0x10151A33, info); - aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info); - aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info); - aty_st_le32(DAC_CNTL, card->dac_cntl, info); - aty_st_le16(GEN_TEST_CNTL, 0x0100, info); - aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, info); - aty_st_le32(MEM_BUF_CNTL, 0x00382848, info); - - aty_st_le32(HW_DEBUG, card->hw_debug, info); - aty_st_le16(MEM_ADDR_CONFIG, 0x0000, info); - aty_st_le16(GP_IO+2, 0x0000, info); - aty_st_le16(GEN_TEST_CNTL, 0x0000, info); - aty_st_le16(EXT_DAC_REGS+2, 0x0000, info); - aty_st_le32(CRTC_INT_CNTL, 0x00000000, info); - aty_st_le32(TIMER_CONFIG, 0x00000000, info); - aty_st_le32(0xEC, 0x00000000, info); - aty_st_le32(0xFC, 0x00000000, info); - - for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) { - aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info); - } - - aty_st_le16(CONFIG_STAT0, 0x00A4, info); - mdelay(10); - - aty_st_8(BUS_CNTL+1, 0xA0, info); - mdelay(10); - - reset_clocks(info, &pll.ct, 1); - mdelay(10); - - // something about power management - aty_st_8(LCD_INDEX, 0x08, info); - aty_st_8(LCD_DATA, 0x0A, info); - aty_st_8(LCD_INDEX, 0x08, info); - aty_st_8(LCD_DATA+3, 0x02, info); - aty_st_8(LCD_INDEX, 0x08, info); - aty_st_8(LCD_DATA, 0x0B, info); - mdelay(2); - - // enable display requests, enable CRTC - aty_st_8(CRTC_GEN_CNTL+3, 0x02, info); - // disable display - aty_st_8(CRTC_GEN_CNTL, 0x40, info); - // disable display requests, disable CRTC - aty_st_8(CRTC_GEN_CNTL+3, 0x04, info); - mdelay(10); - - aty_st_pll(PLL_YCLK_CNTL, 0x25, info); - - aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, info); - aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, info); - aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, info); - aty_st_8(CUSTOM_MACRO_CNTL+1, - (card->custom_macro_cntl>>8) & 0xff, info); - - aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, info); - aty_st_le32(MEM_CNTL, card->mem_cntl, info); - aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info); - - aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, info); - - aty_st_pll(PLL_YCLK_CNTL, 0x01, info); - mdelay(15); - aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, info); - mdelay(1); - - reset_clocks(info, &pll.ct, 0); - mdelay(50); - reset_clocks(info, &pll.ct, 0); - mdelay(50); - - // enable extended register block - aty_st_8(BUS_CNTL+3, 0x7B, info); - mdelay(1); - // disable extended register block - aty_st_8(BUS_CNTL+3, 0x73, info); - - aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, info); - - // disable display requests, disable CRTC - aty_st_8(CRTC_GEN_CNTL+3, 0x04, info); - // disable mapping registers in VGA aperture - aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, info) & ~0x04, info); - mdelay(50); - // enable display requests, enable CRTC - aty_st_8(CRTC_GEN_CNTL+3, 0x02, info); - - // make GPIO's 14,15,16 all inputs - aty_st_8(LCD_INDEX, 0x07, info); - aty_st_8(LCD_DATA+3, 0x00, info); - - // enable the display - aty_st_8(CRTC_GEN_CNTL, 0x00, info); - mdelay(17); - // reset the memory controller - aty_st_8(GEN_TEST_CNTL+1, 0x02, info); - mdelay(15); - aty_st_8(GEN_TEST_CNTL+1, 0x00, info); - mdelay(30); - - // enable extended register block - aty_st_8(BUS_CNTL+3, - (u8)(aty_ld_8(BUS_CNTL+3, info) | 0x08), - info); - // set FIFO size to 512 (PIO) - aty_st_le32(GUI_CNTL, - aty_ld_le32(GUI_CNTL, info) & ~0x3, - info); - - // enable CRT and disable lcd - aty_st_8(LCD_INDEX, 0x01, info); - temp = aty_ld_le32(LCD_DATA, info); - temp = (temp | 0x01) & ~0x02; - aty_st_le32(LCD_DATA, temp, info); - - return 0; -} - -static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)"; -static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)"; - - -#if CONFIG_CONSOLE_BTEXT -static void aty_set_crtc(const struct fb_info_aty *info, - const struct crtc *crtc); -static int aty_var_to_crtc(const struct fb_info_aty *info, - const struct fb_var_screeninfo *var, - struct crtc *crtc); -#if PLL_CRTC_DECODE==1 -static int aty_crtc_to_var(const struct crtc *crtc, - struct fb_var_screeninfo *var); -#endif - -static void atyfb_set_par(const struct atyfb_par *par, - struct fb_info_aty *info); -static int atyfb_decode_var(const struct fb_var_screeninfo *var, - struct atyfb_par *par, - const struct fb_info_aty *info); -#if PLL_CRTC_DECODE==1 -static int atyfb_encode_var(struct fb_var_screeninfo *var, - const struct atyfb_par *par, - const struct fb_info_aty *info); -#endif - -static void do_install_cmap(int con, struct fb_info_aty *info); - -#if 0 -static u32 default_vram = 0; -#endif - -unsigned char color_table[] = { 0, 4, 2, 6, 1, 5, 3, 7, - 8,12,10,14, 9,13,11,15 }; -#if 0 -/* the default colour table, for VGA+ colour systems */ -int default_red[] = {0x00,0xaa,0x00,0xaa,0x00,0xaa,0x00,0xaa, - 0x55,0xff,0x55,0xff,0x55,0xff,0x55,0xff}; -int default_grn[] = {0x00,0x00,0xaa,0x55,0x00,0x00,0xaa,0xaa, - 0x55,0x55,0xff,0xff,0x55,0x55,0xff,0xff}; -int default_blu[] = {0x00,0x00,0x00,0x00,0xaa,0xaa,0xaa,0xaa, - 0x55,0x55,0x55,0x55,0xff,0xff,0xff,0xff}; -#endif - -struct fb_var_screeninfo default_var = { - /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ - 640, 480, 640, 480, 0, 0, 8, 0, - {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, - 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, - 0, FB_VMODE_NONINTERLACED -}; - -#endif /*CONFIG_CONSOLE_BTEXT*/ - -static struct { - u16 pci_id, chip_type; - u8 rev_mask, rev_val; - const char *name; - int pll, mclk, xclk; - u32 features; -} aty_chips[] = { - /* 3D RAGE XL PCI-66/BGA */ - { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 }, - /* 3D RAGE XL PCI-33/BGA */ - { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 }, -}; -#if CONFIG_CONSOLE_BTEXT -static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) -{ - int i, size; -#if 0 - const int ragepro_tbl[] = { - 44, 50, 55, 66, 75, 80, 100 - }; -#endif - const int ragexl_tbl[] = { - 50, 66, 75, 83, 90, 95, 100, 105, - 110, 115, 120, 125, 133, 143, 166 - }; - const int *refresh_tbl; -#if 0 - if (IS_XL(id)) { -#endif - refresh_tbl = ragexl_tbl; - size = sizeof(ragexl_tbl)/sizeof(int); -#if 0 - } else { - refresh_tbl = ragepro_tbl; - size = sizeof(ragepro_tbl)/sizeof(int); - } -#endif - - for (i=0; i < size; i++) { - if (xclk < refresh_tbl[i]) - break; - } - - info->mem_refresh_rate = i; -} -#endif /*CONFIG_CONSOLE_BTEXT */ -static void ati_ragexl_init(struct device *dev) -{ - u32 chip_id; - int j; - u16 type; - u8 rev; - const char *chipname = NULL; -#if CONFIG_CONSOLE_BTEXT - u32 i; - const char *xtal; -#endif - int pll, mclk, xclk; - -#if CONFIG_CONSOLE_BTEXT - -#if 0 - int gtb_memsize, k; -#endif - - struct fb_var_screeninfo var; -#if 0 - struct display *disp; -#endif - -#if 0 - u8 pll_ref_div; -#endif - -#endif /*CONFIG_CONSOLE_BTEXT==1 */ - - struct fb_info_aty *info; - struct fb_info_aty info_t; - struct resource *res; - info = &info_t; - -#define USE_AUX_REG 1 - - - res = dev->resource_list; - if(res->flags & IORESOURCE_IO) { - res = res->next; - } - -#if CONFIG_CONSOLE_BTEXT - info->frame_buffer = res->base; -#endif /* CONFIG_CONSOLE_BTEXT */ - -#if USE_AUX_REG==0 - info->ati_regbase = res->base+0x7ff000+0xc00; -#else - /* Fix this to look for the correct index. */ - //if (dev->resource_list && dev->resource_list->next) - res = dev->resource_list->next->next; - if(res->flags & IORESOURCE_MEM) { - info->ati_regbase = res->base+0x400; //using auxiliary register - } - -#endif - -#if CONFIG_CONSOLE_BTEXT - info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0); -#endif - -#if 0 - printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer); -#endif - - chip_id = aty_ld_le32(CONFIG_CHIP_ID, info); - type = chip_id & CFG_CHIP_TYPE; - rev = (chip_id & CFG_CHIP_REV)>>24; - for (j = 0; j < ARRAY_SIZE(aty_chips); j++) - if (type == aty_chips[j].chip_type && - (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) { - chipname = aty_chips[j].name; - pll = aty_chips[j].pll; - mclk = aty_chips[j].mclk; - xclk = aty_chips[j].xclk; - info->features = aty_chips[j].features; - goto found; - } - printk(BIOS_SPEW, "ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev); - return ; - -found: - printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev); -#if 0 - if (M64_HAS(INTEGRATED)) { - /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ - if (mclk == 67 && info->ram_type < SDRAM) - mclk = 63; - } -#endif -#if CONFIG_CONSOLE_BTEXT - aty_calc_mem_refresh(info, type, xclk); -#endif /* CONFIG_CONSOLE_BTEXT */ - - info->pll_per = 1000000/pll; - info->mclk_per = 1000000/mclk; - info->xclk_per = 1000000/xclk; - -// info->dac_ops = &aty_dac_ct; -// info->pll_ops = &aty_pll_ct; - info->bus_type = PCI; - - - atyfb_xl_init(info); - -#if CONFIG_CONSOLE_BTEXT - - info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07); - - info->ref_clk_per = 1000000000000ULL/14318180; - xtal = "14.31818"; -#if 0 - if (M64_HAS(GTB_DSP) && (pll_ref_div = aty_ld_pll(PLL_REF_DIV, info))) { - int diff1, diff2; - diff1 = 510*14/pll_ref_div-pll; - diff2 = 510*29/pll_ref_div-pll; - if (diff1 < 0) - diff1 = -diff1; - if (diff2 < 0) - diff2 = -diff2; - if (diff2 < diff1) { - info->ref_clk_per = 1000000000000ULL/29498928; - xtal = "29.498928"; - } - } -#endif - - i = aty_ld_le32(MEM_CNTL, info); -#if 0 - gtb_memsize = M64_HAS(GTB_DSP); - if (gtb_memsize) // We have -#endif - switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */ - case MEM_SIZE_512K: - info->total_vram = 0x80000; - break; - case MEM_SIZE_1M: - info->total_vram = 0x100000; - break; - case MEM_SIZE_2M_GTB: - info->total_vram = 0x200000; - break; - case MEM_SIZE_4M_GTB: - info->total_vram = 0x400000; - break; - case MEM_SIZE_6M_GTB: - info->total_vram = 0x600000; - break; - case MEM_SIZE_8M_GTB: - info->total_vram = 0x800000; - break; - default: - info->total_vram = 0x80000; - } -#if 0 - else - switch (i & MEM_SIZE_ALIAS) { - case MEM_SIZE_512K: - info->total_vram = 0x80000; - break; - case MEM_SIZE_1M: - info->total_vram = 0x100000; - break; - case MEM_SIZE_2M: - info->total_vram = 0x200000; - break; - case MEM_SIZE_4M: - info->total_vram = 0x400000; - break; - case MEM_SIZE_6M: - info->total_vram = 0x600000; - break; - case MEM_SIZE_8M: - info->total_vram = 0x800000; - break; - default: - info->total_vram = 0x80000; - } -#endif - - if (M64_HAS(MAGIC_VRAM_SIZE)) { - if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000) - info->total_vram += 0x400000; - } -#if 0 - if (default_vram) { - info->total_vram = default_vram*1024; - i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS); - if (info->total_vram <= 0x80000) - i |= MEM_SIZE_512K; - else if (info->total_vram <= 0x100000) - i |= MEM_SIZE_1M; - else if (info->total_vram <= 0x200000) - i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M; - else if (info->total_vram <= 0x400000) - i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M; - else if (info->total_vram <= 0x600000) - i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M; - else - i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M; - aty_st_le32(MEM_CNTL, i, info); - } -#endif - - /* Clear the video memory */ -// fb_memset((void *)info->frame_buffer, 0, info->total_vram); -#if 0 - disp = &info->disp; - -// strcpy(info->fb_info.modename, atyfb_name); - info->fb_info.node = -1; -// info->fb_info.fbops = &atyfb_ops; - info->fb_info.disp = disp; -// strcpy(info->fb_info.fontname, fontname); - info->fb_info.changevar = NULL; -// info->fb_info.switch_con = &atyfbcon_switch; -// info->fb_info.updatevar = &atyfbcon_updatevar; -// info->fb_info.blank = &atyfbcon_blank; - info->fb_info.flags = FBINFO_FLAG_DEFAULT; -#endif - var = default_var; - -#if 0 - if (noaccel) // We has noaccel in default - var.accel_flags &= ~FB_ACCELF_TEXT; - else - var.accel_flags |= FB_ACCELF_TEXT; -#endif - - if (var.yres == var.yres_virtual) { - u32 vram = info->total_vram ; - var.yres_virtual = ((vram * 8) / var.bits_per_pixel) / var.xres_virtual; - if (var.yres_virtual < var.yres) - var.yres_virtual = var.yres; - } - - if (atyfb_decode_var(&var, &info->default_par, info)) { -#if 0 - printk(BIOS_DEBUG, "atyfb: can't set default video mode\n"); -#endif - return ; - } -#if 0 - for (j = 0; j < 16; j++) { - k = color_table[j]; - info->palette[j].red = default_red[k]; - info->palette[j].green = default_grn[k]; - info->palette[j].blue = default_blu[k]; - } -#endif - -#if 0 - if (curblink && M64_HAS(INTEGRATED)) { - info->cursor = aty_init_cursor(info); - if (info->cursor) { - info->dispsw.cursor = atyfb_cursor; - info->dispsw.set_font = atyfb_set_font; - } - } -#endif - -#if PLL_CRTC_DECODE==1 - atyfb_set_var(&var, -1, &info->fb_info); -#else - atyfb_set_par(&info->default_par, info); -// do_install_cmap(-1, &info->fb_info); - do_install_cmap(-1, info); -#endif - -#if PLL_CRTC_DECODE==1 - - printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer, - (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, - ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1, - info->current_par.crtc.bpp, - info->current_par.crtc.vxres*info->default_par.crtc.bpp/8 - ); - btext_setup_display( - (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, - ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1, - info->current_par.crtc.bpp, - info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer); -#else - printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer, - (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, - ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1, - info->default_par.crtc.bpp, - info->default_par.crtc.vxres*info->default_par.crtc.bpp/8 - ); - btext_setup_display( - (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, - ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1, - info->default_par.crtc.bpp, - info->default_par.crtc.vxres*info->default_par.crtc.bpp/8,info->frame_buffer); -#endif - - btext_clearscreen(); - - map_boot_text(); - -#if 0 - - btext_drawstring("test framebuffer\n"); - - mdelay(10000); -// test end -#endif - -#endif /* CONFIG_CONSOLE_BTEXT */ - -} - -#if CONFIG_CONSOLE_BTEXT - -static int atyfb_decode_var(const struct fb_var_screeninfo *var, - struct atyfb_par *par, - const struct fb_info_aty *info) -{ - int err; - - if ((err = aty_var_to_crtc(info, var, &par->crtc)) || - (err = aty_var_to_pll_ct(info, var->pixclock, par->crtc.bpp, - &par->pll))) - return err; - -#if 0 - if (var->accel_flags & FB_ACCELF_TEXT) - par->accel_flags = FB_ACCELF_TEXT; - else -#endif - par->accel_flags = 0; - -#if 0 /* fbmon is not done. uncomment for 2.5.x -brad */ - if (!fbmon_valid_timings(var->pixclock, htotal, vtotal, info)) - return -EINVAL; -#endif - - return 0; -} -#if PLL_CRTC_DECODE==1 -static int atyfb_encode_var(struct fb_var_screeninfo *var, - const struct atyfb_par *par, - const struct fb_info_aty *info) -{ - int err; - - memset(var, 0, sizeof(struct fb_var_screeninfo)); - - if ((err = aty_crtc_to_var(&par->crtc, var))) - return err; - var->pixclock = aty_pll_ct_to_var(info, &par->pll); - - var->height = -1; - var->width = -1; - var->accel_flags = par->accel_flags; - - return 0; -} -#endif -static void aty_set_crtc(const struct fb_info_aty *info, - const struct crtc *crtc) -{ - aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, info); - aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, info); - aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, info); - aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, info); - aty_st_le32(CRTC_VLINE_CRNT_VLINE, 0, info); - aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, info); - aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, info); -} - -static int aty_var_to_crtc(const struct fb_info_aty *info, - const struct fb_var_screeninfo *var, - struct crtc *crtc) -{ - u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp; - u32 left, right, upper, lower, hslen, vslen, sync, vmode; - u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; - u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; - u32 pix_width, dp_pix_width, dp_chain_mask; - - /* input */ - xres = var->xres; - yres = var->yres; - vxres = var->xres_virtual; - vyres = var->yres_virtual; - xoffset = var->xoffset; - yoffset = var->yoffset; - bpp = var->bits_per_pixel; - left = var->left_margin; - right = var->right_margin; - upper = var->upper_margin; - lower = var->lower_margin; - hslen = var->hsync_len; - vslen = var->vsync_len; - sync = var->sync; - vmode = var->vmode; - - /* convert (and round up) and validate */ - xres = (xres+7) & ~7; - xoffset = (xoffset+7) & ~7; - vxres = (vxres+7) & ~7; - if (vxres < xres+xoffset) - vxres = xres+xoffset; - h_disp = xres/8-1; - if (h_disp > 0xff) - FAIL("h_disp too large"); - h_sync_strt = h_disp+(right/8); - if (h_sync_strt > 0x1ff) - FAIL("h_sync_start too large"); - h_sync_dly = right & 7; - h_sync_wid = (hslen+7)/8; - if (h_sync_wid > 0x1f) - FAIL("h_sync_wid too large"); - h_total = h_sync_strt+h_sync_wid+(h_sync_dly+left+7)/8; - if (h_total > 0x1ff) - FAIL("h_total too large"); - h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; - - if (vyres < yres+yoffset) - vyres = yres+yoffset; - v_disp = yres-1; - if (v_disp > 0x7ff) - FAIL("v_disp too large"); - v_sync_strt = v_disp+lower; - if (v_sync_strt > 0x7ff) - FAIL("v_sync_strt too large"); - v_sync_wid = vslen; - if (v_sync_wid > 0x1f) - FAIL("v_sync_wid too large"); - v_total = v_sync_strt+v_sync_wid+upper; - if (v_total > 0x7ff) - FAIL("v_total too large"); - v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; - - c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0; - - if (bpp <= 8) { - bpp = 8; - pix_width = CRTC_PIX_WIDTH_8BPP; - dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB; - dp_chain_mask = 0x8080; - } -#if SUPPORT_8_BPP_ABOVE==1 - else if (bpp <= 16) { - bpp = 16; - pix_width = CRTC_PIX_WIDTH_15BPP; - dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP | - BYTE_ORDER_LSB_TO_MSB; - dp_chain_mask = 0x4210; - } else if (bpp <= 24 && M64_HAS(INTEGRATED)) { - bpp = 24; - pix_width = CRTC_PIX_WIDTH_24BPP; - dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB; - dp_chain_mask = 0x8080; - } else if (bpp <= 32) { - bpp = 32; - pix_width = CRTC_PIX_WIDTH_32BPP; - dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP | - BYTE_ORDER_LSB_TO_MSB; - dp_chain_mask = 0x8080; - } -#endif -else - FAIL("invalid bpp"); - - if (vxres*vyres*bpp/8 > info->total_vram) - FAIL("not enough video RAM"); - if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) - FAIL("invalid vmode"); - - /* output */ - crtc->vxres = vxres; - crtc->vyres = vyres; - crtc->xoffset = xoffset; - crtc->yoffset = yoffset; - crtc->bpp = bpp; - crtc->h_tot_disp = h_total | (h_disp<<16); - crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) | - ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | - (h_sync_pol<<21); - crtc->v_tot_disp = v_total | (v_disp<<16); - crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21); - crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19); - crtc->gen_cntl = pix_width | c_sync | CRTC_EXT_DISP_EN | CRTC_ENABLE; - if (M64_HAS(MAGIC_FIFO)) { - /* Not VTB/GTB */ - /* FIXME: magic FIFO values */ - crtc->gen_cntl |= aty_ld_le32(CRTC_GEN_CNTL, info) & 0x000e0000; - } - crtc->dp_pix_width = dp_pix_width; - crtc->dp_chain_mask = dp_chain_mask; - - return 0; -} -#if PLL_CRTC_DECODE==1 -static int aty_crtc_to_var(const struct crtc *crtc, - struct fb_var_screeninfo *var) -{ - u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync; - u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; - u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; - u32 pix_width; - - /* input */ - h_total = crtc->h_tot_disp & 0x1ff; - h_disp = (crtc->h_tot_disp>>16) & 0xff; - h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | - ((crtc->h_sync_strt_wid>>4) & 0x100); - h_sync_dly = (crtc->h_sync_strt_wid>>8) & 0x7; - h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x1f; - h_sync_pol = (crtc->h_sync_strt_wid>>21) & 0x1; - v_total = crtc->v_tot_disp & 0x7ff; - v_disp = (crtc->v_tot_disp>>16) & 0x7ff; - v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; - v_sync_wid = (crtc->v_sync_strt_wid>>16) & 0x1f; - v_sync_pol = (crtc->v_sync_strt_wid>>21) & 0x1; - c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; - pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; - - /* convert */ - xres = (h_disp+1)*8; - yres = v_disp+1; - left = (h_total-h_sync_strt-h_sync_wid)*8-h_sync_dly; - right = (h_sync_strt-h_disp)*8+h_sync_dly; - hslen = h_sync_wid*8; - upper = v_total-v_sync_strt-v_sync_wid; - lower = v_sync_strt-v_disp; - vslen = v_sync_wid; - sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | - (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | - (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); - - switch (pix_width) { -#if 0 - case CRTC_PIX_WIDTH_4BPP: - bpp = 4; - var->red.offset = 0; - var->red.length = 8; - var->green.offset = 0; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.offset = 0; - var->transp.length = 0; - break; -#endif - case CRTC_PIX_WIDTH_8BPP: - bpp = 8; - var->red.offset = 0; - var->red.length = 8; - var->green.offset = 0; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.offset = 0; - var->transp.length = 0; - break; -#if SUPPORT_8_BPP_ABOVE==1 - case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */ - bpp = 16; - var->red.offset = 10; - var->red.length = 5; - var->green.offset = 5; - var->green.length = 5; - var->blue.offset = 0; - var->blue.length = 5; - var->transp.offset = 0; - var->transp.length = 0; - break; - case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */ - bpp = 16; - var->red.offset = 11; - var->red.length = 5; - var->green.offset = 5; - var->green.length = 6; - var->blue.offset = 0; - var->blue.length = 5; - var->transp.offset = 0; - var->transp.length = 0; - break; - case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */ - bpp = 24; - var->red.offset = 16; - var->red.length = 8; - var->green.offset = 8; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.offset = 0; - var->transp.length = 0; - break; - case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */ - bpp = 32; - var->red.offset = 16; - var->red.length = 8; - var->green.offset = 8; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.offset = 24; - var->transp.length = 8; - break; -#endif - default: - FAIL("Invalid pixel width"); - } - - /* output */ - var->xres = xres; - var->yres = yres; - var->xres_virtual = crtc->vxres; - var->yres_virtual = crtc->vyres; - var->bits_per_pixel = bpp; - var->xoffset = crtc->xoffset; - var->yoffset = crtc->yoffset; - var->left_margin = left; - var->right_margin = right; - var->upper_margin = upper; - var->lower_margin = lower; - var->hsync_len = hslen; - var->vsync_len = vslen; - var->sync = sync; - var->vmode = FB_VMODE_NONINTERLACED; - - return 0; -} -#endif - -#if 0 -static int encode_fix(struct fb_fix_screeninfo *fix, - const struct atyfb_par *par, - const struct fb_info_aty *info) -{ - memset(fix, 0, sizeof(struct fb_fix_screeninfo)); - - // strcpy(fix->id, atyfb_name); - memcpy(fix->id, "atyfb", 5); - fix->smem_start = info->frame_buffer; - fix->smem_len = (u32)info->total_vram; - - /* - * Reg Block 0 (CT-compatible block) is at ati_regbase_phys - * Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400 - */ - if (M64_HAS(GX)) { - fix->mmio_start = info->ati_regbase; - fix->mmio_len = 0x400; - fix->accel = FB_ACCEL_ATI_MACH64GX; - } else if (M64_HAS(CT)) { - fix->mmio_start = info->ati_regbase; - fix->mmio_len = 0x400; - fix->accel = FB_ACCEL_ATI_MACH64CT; - } else if (M64_HAS(VT)) { - fix->mmio_start = info->ati_regbase-0x400; - fix->mmio_len = 0x800; - fix->accel = FB_ACCEL_ATI_MACH64VT; - } else /* if (M64_HAS(GT)) */ { - fix->mmio_start = info->ati_regbase-0x400; - fix->mmio_len = 0x800; - fix->accel = FB_ACCEL_ATI_MACH64GT; - } - fix->type = FB_TYPE_PACKED_PIXELS; - fix->type_aux = 0; - fix->line_length = par->crtc.vxres*par->crtc.bpp/8; - fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR - : FB_VISUAL_DIRECTCOLOR; - fix->ywrapstep = 0; - fix->xpanstep = 8; - fix->ypanstep = 1; - - return 0; -} -#endif - /* - * Set the User Defined Part of the Display - */ -#if PLL_CRTC_DECODE==1 -static int atyfb_set_var(struct fb_var_screeninfo *var, int con, - struct fb_info *fb) -{ - struct fb_info_aty *info = (struct fb_info_aty *)fb; - struct atyfb_par par; -#if 0 - struct display *display; - int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel; -#endif - int err; - int activate = var->activate; - -#if 0 - if (con >= 0) - display = &fb_display[con]; - else -#endif -#if 0 - display = fb->disp; /* used during initialization */ -#endif - - if ((err = atyfb_decode_var(var, &par, info))) - return err; - - atyfb_encode_var(var, &par, (struct fb_info_aty *)info); - -#if 0 - printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK); -#endif - - if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) { -#if 0 - oldxres = display->var.xres; - oldyres = display->var.yres; - oldvxres = display->var.xres_virtual; - oldvyres = display->var.yres_virtual; - oldbpp = display->var.bits_per_pixel; - oldaccel = display->var.accel_flags; - display->var = *var; - accel = var->accel_flags & FB_ACCELF_TEXT; - if (oldxres != var->xres || oldyres != var->yres || - oldvxres != var->xres_virtual || oldvyres != var->yres_virtual || - oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) { - struct fb_fix_screeninfo fix; - - encode_fix(&fix, &par, info); - display->screen_base = (char *)info->frame_buffer; - display->visual = fix.visual; - display->type = fix.type; - display->type_aux = fix.type_aux; - display->ypanstep = fix.ypanstep; - display->ywrapstep = fix.ywrapstep; - display->line_length = fix.line_length; - display->can_soft_blank = 1; - display->inverse = 0; -#if 0 - if (accel) - display->scrollmode = (info->bus_type == PCI) ? SCROLL_YNOMOVE : 0; - else -#endif - display->scrollmode = SCROLL_YREDRAW; -#if 0 - if (info->fb_info.changevar) - (*info->fb_info.changevar)(con); -#endif - } -#endif -// if (!info->fb_info.display_fg || -// info->fb_info.display_fg->vc_num == con) { - atyfb_set_par(&par, info); -#if 0 - atyfb_set_dispsw(display, info, par.crtc.bpp, accel); -#endif -// } -#if 0 - if (oldbpp != var->bits_per_pixel) { - if ((err = fb_alloc_cmap(&display->cmap, 0, 0))) - return err; -#endif - do_install_cmap(con, info); -#if 0 - } -#endif - } - - return 0; -} - -#endif -/* ------------------------------------------------------------------------- */ - -static void atyfb_set_par(const struct atyfb_par *par, - struct fb_info_aty *info) -{ - u32 i; - int accelmode; - u8 tmp; - - accelmode = par->accel_flags; /* hack */ - -#if PLL_CRTC_DECODE==1 - info->current_par = *par; -#endif - - if (info->blitter_may_be_busy) - wait_for_idle(info); - tmp = aty_ld_8(CRTC_GEN_CNTL + 3, info); - aty_set_crtc(info, &par->crtc); - aty_st_8(CLOCK_CNTL + info->clk_wr_offset, 0, info); - /* better call aty_StrobeClock ?? */ - aty_st_8(CLOCK_CNTL + info->clk_wr_offset, CLOCK_STROBE, info); - - //info->dac_ops->set_dac(info, &par->pll, par->crtc.bpp, accelmode); - //info->pll_ops->set_pll(info, &par->pll); - aty_set_pll_ct(info, &par->pll); - - - if (!M64_HAS(INTEGRATED)) { - /* Don't forget MEM_CNTL */ - i = aty_ld_le32(MEM_CNTL, info) & 0xf0ffffff; - switch (par->crtc.bpp) { - case 8: - i |= 0x02000000; - break; -#if SUPPORT_8_BPP_ABOVE==1 - case 16: - i |= 0x03000000; - break; - case 32: - i |= 0x06000000; - break; -#endif - } - aty_st_le32(MEM_CNTL, i, info); - } else { - i = aty_ld_le32(MEM_CNTL, info) & 0xf00fffff; - if (!M64_HAS(MAGIC_POSTDIV)) - i |= info->mem_refresh_rate << 20; - switch (par->crtc.bpp) { - case 8: -#if SUPPORT_8_BPP_ABOVE==1 - case 24: -#endif - i |= 0x00000000; - break; -#if SUPPORT_8_BPP_ABOVE==1 - case 16: - i |= 0x04000000; - break; - case 32: - i |= 0x08000000; - break; -#endif - } - if (M64_HAS(CT_BUS)) { - aty_st_le32(DAC_CNTL, 0x87010184, info); - aty_st_le32(BUS_CNTL, 0x680000f9, info); - } else if (M64_HAS(VT_BUS)) { - aty_st_le32(DAC_CNTL, 0x87010184, info); - aty_st_le32(BUS_CNTL, 0x680000f9, info); - } else if (M64_HAS(MOBIL_BUS)) { - aty_st_le32(DAC_CNTL, 0x80010102, info); - aty_st_le32(BUS_CNTL, 0x7b33a040, info); - } else { - /* GT */ - aty_st_le32(DAC_CNTL, 0x86010102, info); - aty_st_le32(BUS_CNTL, 0x7b23a040, info); - aty_st_le32(EXT_MEM_CNTL, - aty_ld_le32(EXT_MEM_CNTL, info) | 0x5000001, info); - } - - aty_st_le32(MEM_CNTL, i, info); - } - aty_st_8(DAC_MASK, 0xff, info); - - /* Initialize the graphics engine */ -#if 0 - if (par->accel_flags & FB_ACCELF_TEXT) - aty_init_engine(par, info); -#endif - - -} -#if 0 -static u16 red2[] = { - 0x0000, 0xaaaa -}; -static u16 green2[] = { - 0x0000, 0xaaaa -}; -static u16 blue2[] = { - 0x0000, 0xaaaa -}; - -static u16 red4[] = { - 0x0000, 0xaaaa, 0x5555, 0xffff -}; -static u16 green4[] = { - 0x0000, 0xaaaa, 0x5555, 0xffff -}; -static u16 blue4[] = { - 0x0000, 0xaaaa, 0x5555, 0xffff -}; - -static u16 red8[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa -}; -static u16 green8[] = { - 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa -}; -static u16 blue8[] = { - 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa -}; -#endif -static u16 red16[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, - 0x5555, 0x5555, 0x5555, 0x5555, 0xffff, 0xffff, 0xffff, 0xffff -}; -static u16 green16[] = { - 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa, - 0x5555, 0x5555, 0xffff, 0xffff, 0x5555, 0x5555, 0xffff, 0xffff -}; -static u16 blue16[] = { - 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, - 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff -}; -#if 0 -static struct fb_cmap default_2_colors = { - 0, 2, red2, green2, blue2, NULL -}; -static struct fb_cmap default_8_colors = { - 0, 8, red8, green8, blue8, NULL -}; -static struct fb_cmap default_4_colors = { - 0, 4, red4, green4, blue4, NULL -}; -#endif -static struct fb_cmap default_16_colors = { - 0, 16, red16, green16, blue16, NULL -}; - - - -static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, - u_int transp, struct fb_info_aty *info) -{ - int i, scale; - - if (regno > 255) - return 1; - red >>= 8; - green >>= 8; - blue >>= 8; -#if 0 -//We don't need to store it - info->palette[regno].red = red; - info->palette[regno].green = green; - info->palette[regno].blue = blue; -#endif - i = aty_ld_8(DAC_CNTL, info) & 0xfc; - if (M64_HAS(EXTRA_BRIGHT)) - i |= 0x2; /*DAC_CNTL|0x2 turns off the extra brightness for gt*/ - aty_st_8(DAC_CNTL, i, info); - aty_st_8(DAC_MASK, 0xff, info); -#if PLL_CRTC_DECODE==1 - scale = (M64_HAS(INTEGRATED) && info->current_par.crtc.bpp == 16) ? 3 : 0; -#else - scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0; -#endif - write8(&info->aty_cmap_regs->windex, regno << scale) - write8(&info->aty_cmap_regs->lut, red); - write8(&info->aty_cmap_regs->lut, green); - write8(&info->aty_cmap_regs->lut, blue); - return 0; -} - -int fb_set_cmap(struct fb_cmap *cmap, int kspc, - int (*setcolreg)(u_int, u_int, u_int, u_int, u_int, - struct fb_info_aty *), - struct fb_info_aty *info) -{ - int i, start; - u16 *red, *green, *blue, *transp; - u_int hred, hgreen, hblue, htransp; - - red = cmap->red; - green = cmap->green; - blue = cmap->blue; - transp = cmap->transp; - start = cmap->start; - - if (start < 0) - return -EINVAL; - for (i = 0; i < cmap->len; i++) { - hred = *red; - hgreen = *green; - hblue = *blue; - htransp = transp ? *transp : 0; - red++; - green++; - blue++; - if (transp) - transp++; - if (setcolreg(start++, hred, hgreen, hblue, htransp, info)) - return 0; - } - return 0; -} - -struct fb_cmap *fb_default_cmap(int len) -{ -#if 0 - if (len <= 2) - return &default_2_colors; - if (len <= 4) - return &default_4_colors; - if (len <= 8) - return &default_8_colors; -#endif - return &default_16_colors; -} - -static void do_install_cmap(int con, struct fb_info_aty *info) -{ -#if PLL_CRTC_DECODE==1 - int size = info->current_par.crtc.bpp == 16 ? 32 : 256; -#else - int size = 256; -#endif - fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info); -} - -#endif /*CONFIG_CONSOLE_BTEXT */ - -static struct device_operations ati_ragexl_graph_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ati_ragexl_init, - .scan_bus = 0, -}; - -static const struct pci_driver ati_ragexl_graph_driver __pci_driver = { - .ops = &ati_ragexl_graph_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_215XL, -};

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New patch to review for coreboot: 4fdc3fa mainboard: Kill off dead usage of ATi/RageXL driver
by Edward O'Callaghan 10 Jan '15

10 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8189 -gerrit commit 4fdc3fac9b6d7fd776a8e7cbceee68c0c5b03409 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 11 01:15:41 2015 +1100 mainboard: Kill off dead usage of ATi/RageXL driver Change-Id: Ib51287326af1af15155ee37336d3795137001686 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/iwill/dk8s2/Kconfig | 1 - src/mainboard/tyan/s2850/devicetree.cb | 1 - src/mainboard/tyan/s2882/devicetree.cb | 2 -- src/mainboard/tyan/s2891/devicetree.cb | 1 - src/mainboard/tyan/s2892/devicetree.cb | 2 -- src/mainboard/tyan/s4882/devicetree.cb | 2 -- 6 files changed, 9 deletions(-) diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index c4de3a1..6bb4c76 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select DRIVERS_ATI_RAGEXL select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb index 85c6384..5e80a87 100644 --- a/src/mainboard/tyan/s2850/devicetree.cb +++ b/src/mainboard/tyan/s2850/devicetree.cb @@ -17,7 +17,6 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/ati/ragexl device pci b.0 on end end device pci 1.0 on diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb index 4074695..3391567 100644 --- a/src/mainboard/tyan/s2882/devicetree.cb +++ b/src/mainboard/tyan/s2882/devicetree.cb @@ -31,9 +31,7 @@ chip northbridge/amd/amdk8/root_complex device pci 0.2 off end device pci 1.0 off end device pci 5.0 on end - # chip drivers/ati/ragexl device pci 6.0 on end - # end device pci 8.0 on end #intel 10/100 end device pci 1.0 on diff --git a/src/mainboard/tyan/s2891/devicetree.cb b/src/mainboard/tyan/s2891/devicetree.cb index 8442ec8..f9185ef 100644 --- a/src/mainboard/tyan/s2891/devicetree.cb +++ b/src/mainboard/tyan/s2891/devicetree.cb @@ -103,7 +103,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 7.0 on end # SATA 1 device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI - # chip drivers/ati/ragexl device pci 7.0 on end end device pci a.0 off end # NIC diff --git a/src/mainboard/tyan/s2892/devicetree.cb b/src/mainboard/tyan/s2892/devicetree.cb index 3edc156..5100dcc 100644 --- a/src/mainboard/tyan/s2892/devicetree.cb +++ b/src/mainboard/tyan/s2892/devicetree.cb @@ -104,9 +104,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 7.0 on end # SATA 1 device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI - # chip drivers/ati/ragexl device pci 6.0 on end - # end device pci 8.0 on end end device pci a.0 off end # NIC diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb index 44da2c2..e65a975 100644 --- a/src/mainboard/tyan/s4882/devicetree.cb +++ b/src/mainboard/tyan/s4882/devicetree.cb @@ -33,9 +33,7 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/ati/ragexl device pci 6.0 on end - #end device pci 5.0 on end #SiI end device pci 1.0 on

1 0

Patch merged into coreboot/master: 78c5d58 ACPI: Add acpi_is_wakeup_s3() for romstage
by gerrit＠coreboot.org 10 Jan '15

10 Jan '15

the following patch was just integrated into master: commit 78c5d584a087265e44b076647db19efd4db4a7bb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 9 23:48:47 2015 +0200 ACPI: Add acpi_is_wakeup_s3() for romstage This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8187 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/8187 for details. -gerrit

1 0

Patch merged into coreboot/master: 2320cbe AMD binaryPI: Drop ramtop via nvram
by gerrit＠coreboot.org 10 Jan '15

10 Jan '15

the following patch was just integrated into master: commit 2320cbebc667ac6871d4d6c8b59fee27ba6e75e5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 10 07:25:15 2015 +0200 AMD binaryPI: Drop ramtop via nvram If HAVE_ACPI_RESUME gets implemented, EARLY_CBMEM_INIT is required too. Change-Id: I8c7932297e0938eff629d1e46081ccf3e7690aea Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8185 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/8185 for details. -gerrit

1 0

Patch merged into coreboot/master: 7a846e7 ACPI: Prepare for HAVE_ACPI_RESUME changes
by gerrit＠coreboot.org 10 Jan '15

10 Jan '15

the following patch was just integrated into master: commit 7a846e7acc64c191a217710234c90ae3634d09ea Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 9 23:55:09 2015 +0200 ACPI: Prepare for HAVE_ACPI_RESUME changes Change-Id: I71d522b135dff8b3c287699cc649caece9e4342c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8186 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/8186 for details. -gerrit

1 0

Patch set updated for coreboot: 578d018 ACPI: Get S3 resume state from romstage_handoff
by Kyösti Mälkki 10 Jan '15

10 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8188 -gerrit commit 578d018179ef096dfad4a0fd4db638911caf3dcf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 ACPI: Get S3 resume state from romstage_handoff There is nothing platform specific in retrieving S3 resume state from romstage_handoff structure. Boards without EARLY_CBMEM_INIT update acpi_slp_type from ACPI power-management block or scratchpad registers. Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 20 +++++++++++++++++-- src/northbridge/intel/haswell/northbridge.c | 22 -------------------- src/soc/intel/baytrail/ramstage.c | 26 ++++++------------------ src/soc/intel/baytrail/southcluster.c | 3 +-- src/soc/intel/baytrail/xhci.c | 4 ++-- src/soc/intel/broadwell/lpc.c | 4 ++-- src/soc/intel/broadwell/me.c | 4 +--- src/soc/intel/broadwell/ramstage.c | 31 +++++++++-------------------- src/soc/intel/broadwell/refcode.c | 11 +--------- src/soc/intel/broadwell/systemagent.c | 23 --------------------- src/soc/intel/fsp_baytrail/ramstage.c | 24 +++++----------------- src/soc/intel/fsp_baytrail/southcluster.c | 1 - 12 files changed, 45 insertions(+), 128 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 621df2f..777053e 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -36,6 +36,7 @@ #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif +#include <romstage_handoff.h> /* FIXME: Kconfig doesn't support overridable defaults :-( */ #ifndef CONFIG_HPET_MIN_TICKS @@ -857,10 +858,25 @@ void acpi_resume(void *wake_vec) /* This is filled with acpi_is_wakeup() call early in ramstage. */ int acpi_slp_type = -1; -int __attribute__((weak)) acpi_get_sleep_type(void) +#if CONFIG_EARLY_CBMEM_INIT +int acpi_get_sleep_type(void) { - return 0; + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } } +#endif static void acpi_handoff_wakeup(void) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..7eb9f08 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -35,7 +35,6 @@ #include <cpu/x86/smm.h> #include <boot/tables.h> #include <cbmem.h> -#include <romstage_handoff.h> #include "chip.h" #include "haswell.h" @@ -433,26 +432,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -462,7 +441,6 @@ static struct device_operations mc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..9e429ab 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -27,8 +27,8 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <romstage_handoff.h> #include <stdlib.h> +#include <string.h> #include <baytrail/gpio.h> #include <baytrail/lpc.h> @@ -130,13 +130,6 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) { @@ -166,22 +159,15 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 5274b03..20cbbcf 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -29,7 +29,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> -#include <romstage_handoff.h> #include <drivers/uart/uart8250reg.h> #include <baytrail/iomap.h> @@ -215,7 +214,7 @@ static void sc_init(device_t dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) com1_configure_resume(dev); } diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..19339e4 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -184,7 +184,7 @@ static void xhci_route_all(device_t dev) /* Route ports to XHCI controller */ reg_script_run_on_dev(dev, xhci_route_all_script); - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) return; /* Reset enabled USB3 ports */ @@ -222,7 +222,7 @@ static void xhci_init(device_t dev) }; /* Initialize XHCI controller for boot or resume path */ - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 394a9d7..c670440 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -394,7 +394,7 @@ static void pch_cg_init(device_t dev) static void pch_set_acpi_mode(void) { #if CONFIG_HAVE_SMI_HANDLER - if (acpi_slp_type != 3) { + if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); @@ -551,7 +551,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (acpi_slp_type != 3 && gnvs) + if (!acpi_is_wakeup_s3() && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); } diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 2bdb1ed..9fc6a41 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -830,13 +830,11 @@ static void intel_me_init(device_t dev) static void intel_me_enable(device_t dev) { -#if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { dev->enabled = 0; pch_disable_devfn(dev); } -#endif } static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 0563064..2097f2f 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -21,8 +21,8 @@ #include <cbmem.h> #include <console/console.h> #include <device/device.h> -#include <romstage_handoff.h> #include <stdlib.h> +#include <string.h> #include <broadwell/nvs.h> #include <broadwell/pm.h> #include <broadwell/ramstage.h> @@ -54,31 +54,18 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) gnvs->pm1i); } -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - static void s3_resume_prepare(void) { - global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; + global_nvs_t *gnvs; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); - return; - } + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + if (gnvs == NULL) + return; - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void broadwell_init_pre_device(void *chip_info) diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index a745101..d66d036 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -30,15 +30,6 @@ #include <broadwell/pei_wrapper.h> #include <broadwell/ramstage.h> -static inline int is_s3_resume(void) -{ -#if CONFIG_HAVE_ACPI_RESUME - return acpi_slp_type == 3; -#else - return 0; -#endif -} - static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) { return (struct ramstage_cache *)&c->program[c->size]; @@ -136,7 +127,7 @@ static pei_wrapper_entry_t load_reference_code(void) }; int ret; - if (is_s3_resume()) { + if (acpi_is_wakeup_s3()) { return load_refcode_from_cache(); } diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 74c43f2..ac021fb 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -29,7 +29,6 @@ #include <stdlib.h> #include <string.h> #include <cbmem.h> -#include <romstage_handoff.h> #include <vendorcode/google/chromeos/chromeos.h> #include <broadwell/cpu.h> #include <broadwell/iomap.h> @@ -412,27 +411,6 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -451,7 +429,6 @@ static struct device_operations systemagent_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &systemagent_init, - .enable = &systemagent_enable, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..ad1db33 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -19,6 +19,7 @@ #include <arch/cpu.h> #include <arch/acpi.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> @@ -26,8 +27,8 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <romstage_handoff.h> #include <stdlib.h> +#include <string.h> #include <baytrail/gpio.h> #include <baytrail/lpc.h> @@ -125,31 +126,16 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } - -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - set_acpi_sleep_type(3); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); } void baytrail_init_pre_device(void) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index d87935b..9b1e42e 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -33,7 +33,6 @@ #include <pc80/i8254.h> #include <pc80/i8259.h> #include <pc80/isa-dma.h> -#include <romstage_handoff.h> #include <baytrail/baytrail.h> #include <baytrail/iomap.h>

1 0

Patch set updated for coreboot: 1f57b29 intel: Fix S3 handoff state to ramstage
by Kyösti Mälkki 10 Jan '15

10 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8172 -gerrit commit 1f57b2969fa2275681ff35e23e41f029075941e1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 intel: Fix S3 handoff state to ramstage TODO: missing romstage find_or_add_romstage_handoff() Global acpi_slp_type is now declared static. The change also guarantees it will always be initialized before use. Change-Id: I0f074bb80f06f6f0ddf4212cd8872e94ae57f949 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 2 +- src/arch/x86/include/arch/acpi.h | 2 -- src/mainboard/lenovo/t60/mainboard.c | 7 +++---- src/mainboard/lenovo/x200/romstage.c | 6 ------ src/mainboard/lenovo/x201/mainboard.c | 5 ++--- src/mainboard/lenovo/x201/romstage.c | 3 --- src/mainboard/lenovo/x60/mainboard.c | 7 +++---- src/mainboard/packardbell/ms2290/romstage.c | 3 --- src/mainboard/roda/rk9/romstage.c | 6 ------ src/northbridge/intel/gm45/northbridge.c | 17 ----------------- src/northbridge/intel/i945/early_init.c | 5 ----- src/northbridge/intel/i945/northbridge.c | 23 ----------------------- src/northbridge/intel/nehalem/nehalem.h | 4 ---- src/northbridge/intel/nehalem/northbridge.c | 21 --------------------- src/northbridge/intel/sandybridge/early_init.c | 4 ---- src/northbridge/intel/sandybridge/northbridge.c | 21 --------------------- src/southbridge/intel/i82801gx/i82801gx.h | 2 -- src/southbridge/intel/i82801gx/smi.c | 13 ++----------- src/southbridge/intel/i82801ix/i82801ix.h | 4 ---- src/southbridge/intel/i82801ix/smi.c | 13 ++----------- 20 files changed, 13 insertions(+), 155 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 777053e..50832e9 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -856,7 +856,7 @@ void acpi_resume(void *wake_vec) } /* This is filled with acpi_is_wakeup() call early in ramstage. */ -int acpi_slp_type = -1; +static int acpi_slp_type = -1; #if CONFIG_EARLY_CBMEM_INIT int acpi_get_sleep_type(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 771b51c..c2181d7 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -580,7 +580,6 @@ static inline int acpi_s3_resume_allowed(void) } #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -extern int acpi_slp_type; #ifdef __PRE_RAM__ static inline int acpi_is_wakeup_s3(void) @@ -593,7 +592,6 @@ int acpi_is_wakeup_s3(void); #endif #else -#define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } #endif diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index abda9ea..6647970 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -22,12 +22,12 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <arch/io.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> @@ -69,13 +69,12 @@ const char *smbios_mainboard_bios_version(void) static void mainboard_init(device_t dev) { struct southbridge_intel_i82801gx_config *config; - device_t dev0, idedev; + device_t idedev; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index f232642..76aa23a 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -192,12 +192,6 @@ void main(unsigned long bist) */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); } #endif printk(BIOS_SPEW, "exit main()\n"); diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 3cda4fa..40d52a4 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> @@ -116,7 +117,6 @@ static void fill_ssdt(void) static void mainboard_enable(device_t dev) { - device_t dev0; u16 pmbase; dev->ops->init = mainboard_init; @@ -136,8 +136,7 @@ static void mainboard_enable(device_t dev) 0x10); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 64011b1..bfe5f7f 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -304,10 +304,7 @@ void main(unsigned long bist) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); quick_ram_check(); } #endif diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 334c27d..778690b 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -22,13 +22,13 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <arch/interrupt.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> @@ -58,7 +58,7 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_init(device_t dev) { - device_t dev0, idedev, sdhci_dev; + device_t idedev, sdhci_dev; ec_clr_bit(0x03, 2); @@ -70,8 +70,7 @@ static void mainboard_init(device_t dev) install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index f702e9f..686a68e 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -291,10 +291,7 @@ void main(unsigned long bist) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); quick_ram_check(); } #endif diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index c8b75e0..a8937d4 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -206,12 +206,6 @@ void main(unsigned long bist) */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); } #endif printk(BIOS_SPEW, "exit main()\n"); diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index fc54a8c..6f9d4f9 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -220,28 +220,11 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; - static void enable_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 0b2acd7..6fb2385 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -195,7 +195,6 @@ static void i945_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); printk(BIOS_DEBUG, " done.\n"); /* Wait for MCH BAR to come up */ @@ -913,10 +912,6 @@ static void i945_prepare_resume(int s3resume) if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, - SKPAD_ACPI_S3_MAGIC); } } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 1aaeb3b..102b784 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -232,26 +232,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -#if CONFIG_HAVE_ACPI_RESUME -static void northbridge_init(struct device *dev) -{ - switch (pci_read_config32(dev, SKPAD)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -} -#endif - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -261,9 +241,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, -#if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, -#endif .scan_bus = 0, .ops_pci = &intel_pci_ops, }; diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 73137b2..c900904 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -226,10 +226,6 @@ enum { #define D0F0_TOLUD 0xb0 #define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe - - #define D0F0_CAPID0 0xe0 #define TSEG 0xac /* TSEG base */ diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 11d335a..b303882 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -283,26 +283,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; - case 0xcafed00d: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -312,7 +292,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 3156f86..e082a04 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -195,10 +195,6 @@ void northbridge_romstage_finalize(int s3resume) *(u32 *)CBMEM_BOOT_MODE = 2; *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } #endif } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 55395ea..8138b94 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -412,26 +412,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case 0xcafed00d: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -441,7 +421,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index ee13b7d..f96a491 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -365,7 +365,5 @@ int southbridge_detect_s3_resume(void); #define SS_CNT 0x50 #define C3_RES 0x54 -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 134c232..67fb5bf 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> @@ -320,16 +321,6 @@ static void smm_relocate(void) static int smm_handler_copied = 0; -static int is_wakeup(void) -{ - device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - - if (!dev0) - return 0; - - return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; -} - static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -343,7 +334,7 @@ static void smm_install(void) /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ - if (!is_wakeup()) { + if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index d8dc077..2ae6636 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -207,10 +207,6 @@ #define FD_SAD1 (1 << 2) /* SATA #1 */ -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe - - #ifndef __ACPI__ #ifndef __ASSEMBLER__ diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index de9931c..32d3ed0 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> @@ -319,16 +320,6 @@ static void smm_relocate(void) static int smm_handler_copied = 0; -static int is_wakeup(void) -{ - device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - - if (!dev0) - return 0; - - return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; -} - static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -342,7 +333,7 @@ static void smm_install(void) /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ - if (!is_wakeup()) { + if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);

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Patch merged into coreboot/master: 054c83a Fix mainboard names for daisy and peach_pit
by gerrit＠coreboot.org 10 Jan '15

10 Jan '15

the following patch was just integrated into master: commit 054c83ac72f162b7686a4bfa0013658aef11e0f6 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jan 9 11:46:43 2015 -0800 Fix mainboard names for daisy and peach_pit This just fixes name members of mainboard_ops for daisy and peach_pit, which were never officially supported but used for development and proof-of-concept. Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: Ia1f9b62bc9d91ed634ec1eaa7f907e8aed977f96 Reviewed-on: http://review.coreboot.org/8184 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8184 for details. -gerrit

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coreboot-gerrit January 2015