coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 1c5cdad libpayload: improve us timer accuracy
by gerrit＠coreboot.org 12 Jan '15

12 Jan '15

the following patch was just integrated into master: commit 1c5cdad09efa7d6bd196ad852dbeb5f740ac66e3 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Jul 10 12:49:46 2014 -0700 libpayload: improve us timer accuracy In cases where timer clock frequency is not an integer number of megahertz, the calculations in timer_us() lack accuracy. This patch modifies calculations to reduce the error. The maximum interval this calculation would support decreases, but it still is in excess of 1844674 seconds for a timer clocked by 10 MHz, which is more than enough. BUG=none TEST=manual . verified timer accuracy using a depthcharge CLI command Original-Change-Id: Iffb323db10e74b0ce3b4d59a56983bfee12e6805 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207358 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit e1abf87d438de1a04714482d5b610671e8cc0663) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia892726187ab040dd235f493c92856c15951cc06 Reviewed-on: http://review.coreboot.org/8128 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8128 for details. -gerrit

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Patch merged into coreboot/master: ab69984 libpayload: Add Rock Chip drivers
by gerrit＠coreboot.org 12 Jan '15

12 Jan '15

the following patch was just integrated into master: commit ab699846018d5a697d9d2c3f88031d932cc5fe58 Author: huang lin <hl(a)rock-chips.com> Date: Fri Jun 20 11:34:46 2014 +0800 libpayload: Add Rock Chip drivers Add support: 1)Support driver rktimer 2)Support driver rkserial BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Original-Change-Id: I2cccedf3b62883dd372842a7972e93f2ebbfb282 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206184 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 387450d7c36b201bd177d46eb9f1d280fc043aab) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia6b7a8ee2439a6f2bf7577df822d3f4f3a1e441c Reviewed-on: http://review.coreboot.org/8127 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/8127 for details. -gerrit

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Patch set updated for coreboot: 0f9dc64 NOTFORMERGE: abuild: Print how much disk space we've used
by Alexandru Gagniuc 12 Jan '15

12 Jan '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4842 -gerrit commit 0f9dc649b0e86c6ab2eeb7ea1c7488b694a0f9cf Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Jan 27 17:41:47 2014 -0600 NOTFORMERGE: abuild: Print how much disk space we've used YOU SHALL NOT MERGE !!! [image of Gandalf on stone walkway] Sorry. Gandalf is temporarily unavailable. Change-Id: I0faa7f3952621f8591e2ebf357f866515e15a2d2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/abuild/abuild | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/abuild/abuild b/util/abuild/abuild index 2f87767..44a1cef 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -627,4 +627,6 @@ else fi junit '</testsuite>' +du -sch coreboot-builds + exit $failed

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Patch set updated for coreboot: 2791e2a FSP & CBMEM: Fix broken cbmem CAR transition.
by Martin Roth 12 Jan '15

12 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8196 -gerrit commit 2791e2a1074ecd3d0bdf73229a46bd3f85089f11 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:29:29 2015 -0700 FSP & CBMEM: Fix broken cbmem CAR transition. 1) Save the pointer to the FSP HOB list to low memory at address 0x614. This is the same location as CBMEM_RESUME_BACKUP - the two aren't used in the same platform, so overlapping should be OK. I didn't see any documentation that actually said that this location was free to use, and didn't need to be restored after use in S3 resume, but it looks like the DOS boot vector gets loaded juat above this location, so it SHOULD be ok. The alternative is to copy the memory out and store it in cbmem until we're ready to restore it. 2) When a request for the pointer to a CAR variable comes in, pass back the location *INSIDE* the FSP hob structure. 3) Skip the memcopy of the CAR Data. The CAR variables do not get transitioned back into cbmem, but used out of the HOB structure. 4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform. Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 1 - src/cpu/x86/car.c | 36 +++++++++++++++++++--- src/include/cbmem.h | 1 + .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 2 ++ .../intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 1 + src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 ++ 8 files changed, 38 insertions(+), 7 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index e9cbe43..c05b12b 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -40,7 +40,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 5cd4c65..c090b84 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -35,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index cca9afd..da351c5 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -41,13 +41,16 @@ extern char _car_data_end[]; */ static int car_migrated CAR_GLOBAL; - +/** @brief returns pointer to a CAR variable, before or after migration. + * + * @param var pointer to the CAR variable + */ void *car_get_var_ptr(void *var) { char *migrated_base; - int offset; void * _car_start = &_car_data_start; void * _car_end = &_car_data_end; + int offset = (char *)var - (char *)_car_start; /* If the cache-as-ram has not been migrated return the pointer * passed in. */ @@ -61,6 +64,31 @@ void *car_get_var_ptr(void *var) return var; } +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) + /* Avoid including fsp_util.h and everything that goes with it */ + void * find_saved_temp_mem(void *hob_list_ptr); + + /* Before memory is initialized: + * CBMEM_FSP_HOB_PTR == 0xffffffff + * Use CAR - handled above. + * + * After memory is initialized, but before the migration: + * CBMEM_FSP_HOB_PTR is a pointer to the start of the FSP HOB list. + * Use saved CAR area in HOB - handled here. + */ + + if (*(uint32_t *)CBMEM_FSP_HOB_PTR != 0xffffffff) { + /* find the saved temp memory so we can recover cbmem */ + char *saved_tmp_mem_location=(char *)find_saved_temp_mem( + *(void **)CBMEM_FSP_HOB_PTR); + + if (saved_tmp_mem_location == NULL) + die("Error: Could not locate Saved CAR memory."); + + return (void *)(saved_tmp_mem_location + offset); + } +#endif + migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); if (migrated_base == NULL) { @@ -68,8 +96,6 @@ void *car_get_var_ptr(void *var) return var; } - offset = (char *)var - (char *)_car_start; - return &migrated_base[offset]; } @@ -121,7 +147,9 @@ static void do_car_migrate_variables(void) return; } +#if !IS_ENABLED(PLATFORM_USES_FSP) memcpy(migrated_base, &_car_data_start[0], car_data_size); +#endif /* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca7a5f4..2f86b85 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -40,6 +40,7 @@ */ #define CBMEM_BOOT_MODE 0x610 #define CBMEM_RESUME_BACKUP 0x614 +#define CBMEM_FSP_HOB_PTR 0x614 #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087..18c947f 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -167,6 +167,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { soft_reset(); } diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index a666d70..716873c 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -107,6 +107,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; if (Status == 0xFFFFFFFF) { hard_reset(); } diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 081ea09..3b6d093 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -49,7 +49,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c6b5f9c..b8c1bf6 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -329,6 +329,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { warm_reset(); }

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Patch set updated for coreboot: 9c96f90 Intel FSP platforms: Fix timestamps
by Martin Roth 12 Jan '15

12 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8024 -gerrit commit 9c96f90e7408a56145c9cf96cbb845e18cbe07f1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 21:48:48 2014 +0200 Intel FSP platforms: Fix timestamps Only after BROKEN_CAR_MIGRATE is fixed. Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/cougar_canyon2/romstage.c | 23 ++++------------------- src/soc/intel/fsp_baytrail/romstage/romstage.c | 11 ++++++----- src/southbridge/intel/fsp_rangeley/romstage.c | 11 ++++++----- 3 files changed, 16 insertions(+), 29 deletions(-) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 20d884c..0685c5c 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -185,11 +185,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x40); -#if CONFIG_COLLECT_TIMESTAMPS - uint32_t start_romstage_time = (uint32_t) (timestamp_get() >> 4); - /* since this mainboard doesn't use audio, we can stuff the TSC values in there */ - pci_write_config32(PCI_DEV(0, 27, 0), 0x2c, start_romstage_time); -#endif + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); pch_enable_lpc(); @@ -237,11 +234,7 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); -#if CONFIG_COLLECT_TIMESTAMPS - uint32_t before_initram_time = (uint32_t) (timestamp_get() >> 4); - /* since this mainboard doesn't use audio, we can stuff the TSC values in there */ - pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time); -#endif + timestamp_add_now(TS_BEFORE_INITRAM); /* * Call early init to initialize memory and chipset. This function returns @@ -262,11 +255,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { u32 reg32; void *cbmem_hob_ptr; -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t after_initram_time = timestamp_get(); - uint64_t start_romstage_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x2c) << 4; - uint64_t before_initram_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x14) << 4; -#endif + timestamp_add_now(TS_AFTER_INITRAM); /* * HD AUDIO is not used on this system, so we're using some registers @@ -320,10 +309,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { *(u32*)cbmem_hob_ptr = (u32)HobListPtr; post_code(0x4f); - timestamp_init(get_initial_timestamp()); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); - timestamp_add(TS_BEFORE_INITRAM, before_initram_time ); - timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); /* Load the ramstage. */ diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 17b62ef..865489a 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -162,6 +162,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) memset((void *)CONFIG_DCACHE_RAM_BASE,0,0x3000); post_code(0x40); + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + program_base_addresses(); post_code(0x41); @@ -200,6 +203,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x47); + timestamp_add_now(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -221,9 +226,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { uint32_t prev_sleep_state; struct romstage_handoff *handoff; -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - uint64_t after_initram_time = timestamp_get(); -#endif + timestamp_add_now(TS_AFTER_INITRAM); post_code(0x4a); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", @@ -266,8 +269,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - timestamp_init(get_initial_timestamp()); - timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); post_code(0x4f); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 778c653..a2cc443 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -56,6 +56,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) */ outb(0x40, 0x80); + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Rangeley UART POR state is enabled */ console_init(); post_code(0x41); @@ -78,6 +81,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) read32(func_dis); } + timestamp_add_now(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -97,9 +102,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { int cbmem_was_initted; void *cbmem_hob_ptr; -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - uint64_t after_initram_time = timestamp_get(); -#endif + timestamp_add_now(TS_AFTER_INITRAM); post_code(0x48); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", @@ -130,8 +133,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); - timestamp_init(get_initial_timestamp()); - timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); post_code(0x4f);

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Patch set updated for coreboot: bff6344 asus/m4a785/Kconfig: Add vgabios PCI id
by Paul Menzel 11 Jan '15

11 Jan '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8177 -gerrit commit bff6344ead64d4b81fbc8ff8adc2f45b1d68f60f Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Jan 4 16:26:08 2015 +0100 asus/m4a785/Kconfig: Add vgabios PCI id The PCI id defaults to 1106,3230 -> via chrome 9 ... Tested on the board. Change-Id: I5ad91faec9c97f34c8ca48eee9198237e9ea8336 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/asus/m4a785-m/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index 5162e16..3abeb0b 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -61,4 +61,8 @@ config AMD_UCODE_PATCH_FILE string default "mc_patch_010000b6.h" +config VGA_BIOS_ID + string + default "1002,9710" + endif

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Patch set updated for coreboot: 8952389 FSP & CBMEM: Fix broken cbmem CAR transition.
by Martin Roth 11 Jan '15

11 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8196 -gerrit commit 8952389e28603efa6b39b60c36a01bec96a5dfd8 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:29:29 2015 -0700 FSP & CBMEM: Fix broken cbmem CAR transition. 1) Save the pointer to the FSP HOB list to low memory at address 0x614. This is the same location as CBMEM_RESUME_BACKUP - the two aren't used in the same platform, so overlapping should be OK. I didn't see any documentation that actually said that this location was free to use, and didn't need to be restored after use in S3 resume, but it looks like the DOS boot vector gets loaded juat above this location, so it SHOULD be ok. The alternative is to copy the memory out and store it in cbmem until we're ready to restore it. 2) When a request for the pointer to a CAR variable comes in, pass back the location *INSIDE* the FSP hob structure. 3) Skip the memcopy of the CAR Data. The CAR variables do not get transitioned back into cbmem, but used out of the HOB structure. 4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform. Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 1 - src/cpu/x86/car.c | 34 +++++++++++++++++++--- src/include/cbmem.h | 1 + .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 2 ++ .../intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 1 + src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 ++ 8 files changed, 36 insertions(+), 7 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index e9cbe43..c05b12b 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -40,7 +40,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 5cd4c65..c090b84 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -35,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index cca9afd..1a95ea1 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -41,13 +41,16 @@ extern char _car_data_end[]; */ static int car_migrated CAR_GLOBAL; - +/** @brief returns pointer to a CAR variable, before or after migration. + * + * @param var pointer to the CAR variable + */ void *car_get_var_ptr(void *var) { char *migrated_base; - int offset; void * _car_start = &_car_data_start; void * _car_end = &_car_data_end; + int offset = (char *)var - (char *)_car_start; /* If the cache-as-ram has not been migrated return the pointer * passed in. */ @@ -61,6 +64,29 @@ void *car_get_var_ptr(void *var) return var; } +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) +#include <drivers/intel/fsp/fsp_util.h> + /* Before memory is initialized: + * CBMEM_FSP_HOB_PTR == 0xffffffff + * Use CAR - handled above. + * + * After memory is initialized, but before the migration: + * CBMEM_FSP_HOB_PTR is a pointer to the start of the FSP HOB list. + * Use saved CAR area in HOB - handled here. + */ + + if (*(uint32_t *)CBMEM_FSP_HOB_PTR != 0xffffffff) { + /* find the saved temp memory so we can recover cbmem */ + char *saved_tmp_mem_location=(char *)find_saved_temp_mem( + *(void **)CBMEM_FSP_HOB_PTR); + + if (saved_tmp_mem_location == NULL) + die("Error: Could not locate Saved CAR memory."); + + return (void *)(saved_tmp_mem_location + offset); + } +#endif + migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); if (migrated_base == NULL) { @@ -68,8 +94,6 @@ void *car_get_var_ptr(void *var) return var; } - offset = (char *)var - (char *)_car_start; - return &migrated_base[offset]; } @@ -121,7 +145,9 @@ static void do_car_migrate_variables(void) return; } +#if !IS_ENABLED(PLATFORM_USES_FSP) memcpy(migrated_base, &_car_data_start[0], car_data_size); +#endif /* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca7a5f4..2f86b85 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -40,6 +40,7 @@ */ #define CBMEM_BOOT_MODE 0x610 #define CBMEM_RESUME_BACKUP 0x614 +#define CBMEM_FSP_HOB_PTR 0x614 #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087..18c947f 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -167,6 +167,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { soft_reset(); } diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index a666d70..716873c 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -107,6 +107,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; if (Status == 0xFFFFFFFF) { hard_reset(); } diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 081ea09..3b6d093 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -49,7 +49,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c6b5f9c..b8c1bf6 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -329,6 +329,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { warm_reset(); }

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New patch to review for coreboot: 7723120 FSP & CBMEM: Fix broken cbmem CAR transition.
by Martin Roth 11 Jan '15

11 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8196 -gerrit commit 7723120bcfc940ffd85355a8dca1efa54d10668c Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:29:29 2015 -0700 FSP & CBMEM: Fix broken cbmem CAR transition. 1) Save the pointer to the FSP HOB list to low memory at address 0x614. This is the same location as CBMEM_RESUME_BACKUP - the two aren't used in the same platform, so overlapping should be OK. I didn't see any documentation that actually said that this location was free to use, and didn't need to be restored after use in S3 resume, but it looks like the DOS boot vector gets loaded juat above this location, so it SHOULD be ok. The alternative is to copy the memory out and store it in cbmem until we're ready to restore it. 2) When a request for the pointer to a CAR variable comes in, pass back the location *INSIDE* the FSP hob structure. 3) Skip the memcopy of the CAR Data. The CAR variables do not get transitioned back into cbmem, but used out of the HOB structure. 4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform. Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 2 +- src/cpu/intel/fsp_model_406dx/Kconfig | 2 +- src/cpu/x86/car.c | 34 +++++++++++++++++++--- src/include/cbmem.h | 1 + .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 2 ++ .../intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 1 + src/soc/intel/fsp_baytrail/Kconfig | 2 +- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 ++ 8 files changed, 39 insertions(+), 7 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index e9cbe43..8692ecb 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -40,7 +40,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE + select DYNAMIC_CBMEM config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 5cd4c65..633bd54 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -35,7 +35,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER - select BROKEN_CAR_MIGRATE + select DYNAMIC_CBMEM choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index cca9afd..1a95ea1 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -41,13 +41,16 @@ extern char _car_data_end[]; */ static int car_migrated CAR_GLOBAL; - +/** @brief returns pointer to a CAR variable, before or after migration. + * + * @param var pointer to the CAR variable + */ void *car_get_var_ptr(void *var) { char *migrated_base; - int offset; void * _car_start = &_car_data_start; void * _car_end = &_car_data_end; + int offset = (char *)var - (char *)_car_start; /* If the cache-as-ram has not been migrated return the pointer * passed in. */ @@ -61,6 +64,29 @@ void *car_get_var_ptr(void *var) return var; } +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP) +#include <drivers/intel/fsp/fsp_util.h> + /* Before memory is initialized: + * CBMEM_FSP_HOB_PTR == 0xffffffff + * Use CAR - handled above. + * + * After memory is initialized, but before the migration: + * CBMEM_FSP_HOB_PTR is a pointer to the start of the FSP HOB list. + * Use saved CAR area in HOB - handled here. + */ + + if (*(uint32_t *)CBMEM_FSP_HOB_PTR != 0xffffffff) { + /* find the saved temp memory so we can recover cbmem */ + char *saved_tmp_mem_location=(char *)find_saved_temp_mem( + *(void **)CBMEM_FSP_HOB_PTR); + + if (saved_tmp_mem_location == NULL) + die("Error: Could not locate Saved CAR memory."); + + return (void *)(saved_tmp_mem_location + offset); + } +#endif + migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); if (migrated_base == NULL) { @@ -68,8 +94,6 @@ void *car_get_var_ptr(void *var) return var; } - offset = (char *)var - (char *)_car_start; - return &migrated_base[offset]; } @@ -121,7 +145,9 @@ static void do_car_migrate_variables(void) return; } +#if !IS_ENABLED(PLATFORM_USES_FSP) memcpy(migrated_base, &_car_data_start[0], car_data_size); +#endif /* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca7a5f4..2f86b85 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -40,6 +40,7 @@ */ #define CBMEM_BOOT_MODE 0x610 #define CBMEM_RESUME_BACKUP 0x614 +#define CBMEM_FSP_HOB_PTR 0x614 #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index ae95087..18c947f 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -167,6 +167,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { soft_reset(); } diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index a666d70..716873c 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -107,6 +107,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; if (Status == 0xFFFFFFFF) { hard_reset(); } diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 081ea09..85b3d32 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_BOOTBLOCK_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select DYNAMIC_CBMEM select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT @@ -49,7 +50,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS if INCLUDE_MICROCODE_IN_BUILD select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT - select BROKEN_CAR_MIGRATE config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c6b5f9c..b8c1bf6 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -329,6 +329,8 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { + *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + if (Status == 0xFFFFFFFF) { warm_reset(); }

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New patch to review for coreboot: 0b217f7 FSP platforms: Clear area in CAR for cbmem
by Martin Roth 11 Jan '15

11 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8195 -gerrit commit 0b217f7fde4dddda107680e8ca5a1eabf4562dc5 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:58:47 2015 -0700 FSP platforms: Clear area in CAR for cbmem cbmem requires that the memory at DCACHE_RAM_BASE be cleared or it does not get used. This patch just clears CAR memory, leaving 4k untouched for stack. The stack is very small at this point, and obviously doesn't care whether the memory is cleared or not. The FSP has loaded a pattern into CAR, which helps to see the stack usage (and poisons the stack as well). Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/mainboard/intel/cougar_canyon2/romstage.c | 3 +++ src/soc/intel/fsp_baytrail/romstage/romstage.c | 2 ++ src/southbridge/intel/fsp_rangeley/romstage.c | 3 +++ 3 files changed, 8 insertions(+) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 72832ea..20d884c 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -180,6 +180,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) u32 pm1_cnt; u16 pm1_sts; + /* Clear CAR Memory for CBMEM */ + memset((void *)CONFIG_DCACHE_RAM_BASE,0,DCACHE_RAM_SIZE - 0x1000); + post_code(0x40); #if CONFIG_COLLECT_TIMESTAMPS diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index b0b8133..17b62ef 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -158,6 +158,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t fd2_mask = 0; + /* Clear CAR Memory for CBMEM */ + memset((void *)CONFIG_DCACHE_RAM_BASE,0,0x3000); post_code(0x40); program_base_addresses(); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fba9eb6..778c653 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -44,6 +44,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS; + /* Clear CAR Memory for CBMEM */ + memset((void *)CONFIG_DCACHE_RAM_BASE,0,DCACHE_RAM_SIZE - 0x1000); + /* * Do not use the Serial Console before it is setup. * This causes the I/O to clog and a side effect is

1 0

New patch to review for coreboot: 1e65b89 drivers/intel/fsp: Add find_saved_temp_mem()
by Martin Roth 11 Jan '15

11 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8194 -gerrit commit 1e65b89ce5b15ed8764f75c6cc44117bae85b2cf Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:11:55 2015 -0700 drivers/intel/fsp: Add find_saved_temp_mem() Add a function to retrieve the location of the CAR temporary memory that was saved by the FSP into the HOB structure. Change-Id: I2635de5207cd699740721d333a7706425b837651 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp/fsp_util.c | 18 ++++++++++++++++++ src/drivers/intel/fsp/fsp_util.h | 7 +++++++ 2 files changed, 25 insertions(+) diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index d0ed9cf..0844b37 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -177,6 +177,24 @@ volatile u8 * find_fsp () return (fsp_ptr); } +/** finds the saved temporary memory information in the FSP HOB list + * + * @param hob_list_ptr pointer to the start of the hob list + * @return pointer to saved CAR MEM or NULL if not found. + */ +void * find_saved_temp_mem(void *hob_list_ptr) +{ + EFI_GUID temp_hob_guid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; + EFI_HOB_GUID_TYPE *saved_mem_hob = + (EFI_HOB_GUID_TYPE *) find_hob_by_guid( + hob_list_ptr, &temp_hob_guid); + + if (saved_mem_hob == NULL) + return NULL; + + return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE)); +} + #ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ void print_fsp_info(void) { diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index 3c72f24..a39f5a2 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -37,6 +37,7 @@ void print_fsp_info(void); void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr); void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); +void * find_saved_temp_mem(void *hob_list_ptr); /* functions in hob.c */ void print_hob_mem_attributes(void *Hobptr); @@ -124,4 +125,10 @@ extern void *FspHobListPtr; UpdData->member?"Enabled":"Disabled"); \ break; + +#ifndef FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID +#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ + { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }; +#endif + #endif /* FSP_UTIL_H */

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coreboot-gerrit January 2015