coreboot-gerrit January 2015

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Patch set updated for coreboot: c84319a cbmem: [NOTFORMERGE] CBMEM_INIT_HOOK() API
by Kyösti Mälkki 11 Jan '15

11 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7878 -gerrit commit c84319a42eb2c80fce88d679c9526cd716312467 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jan 7 04:48:43 2015 +0200 cbmem: [NOTFORMERGE] CBMEM_INIT_HOOK() API Squashed two changes from chromium.git. cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API There are several use cases for performing a certain task when CBMEM is first set up (usually to migrate some data into it that was previously kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them differently: timestamp migration is called explicitly from cbmem_initialize(), certain x86-chipset-specific tasks use the CAR_MIGRATION() macro to register a hook, and the CBMEM console is migrated through a direct call from romstage (on non-x86 and SandyBridge boards). This patch decouples the CAR_MIGRATION() hook mechanism from cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer description of what it really does. All of the above use cases are ported to this new, consistent model, allowing us to have one less line of boilerplate in non-CAR romstages. BRANCH=None BUG=None TEST=Built and booted on Nyan_Blaze and Falco with and without CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after boot (and the resume log after S3 resume on Falco). Compiled for Parrot, Stout and Lumpy. Original-Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232612 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> cbmem: Extend hooks to ramstage, fix timestamp synching Commit 7dd5bbd71 (cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API) inadvertently broke ramstage timestamps since timestamp_sync() was no longer called there. Oops. This patch fixes the issue by extending the CBMEM_INIT_HOOK() mechanism to the cbmem_initialize() call in ramstage. The macro is split into explicit ROMSTAGE_/RAMSTAGE_ versions to make the behavior as clear as possible and prevent surprises (although just using a single macro and relying on the Makefiles to link an object into all appropriate stages would also work). This allows us to get rid of the explicit cbmemc_reinit() in ramstage (which I somehow accounted for in the last patch without realizing that timestamps work exactly the same way...), and replace the older and less flexible cbmem_arch_init() mechanism. Also added a size assertion for the pre-RAM CBMEM console to memlayout that could prevent a very unlikely buffer overflow I just noticed. BRANCH=None BUG=None TEST=Booted on Pinky and Falco, confirmed that ramstage timestamps once again show up. Compile-tested for Rambi and Samus. Original-Change-Id: If907266c3f20dc3d599b5c968ea5b39fe5c00e9c Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233533 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I1be89bafacfe85cba63426e2d91f5d8d4caa1800 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/include/arch/early_variables.h | 1 - src/arch/arm64/include/arch/early_variables.h | 1 - src/arch/x86/boot/cbmem.c | 22 ----- src/arch/x86/boot/gdt.c | 3 +- src/arch/x86/include/arch/early_variables.h | 14 --- src/arch/x86/init/romstage.ld | 9 +- src/cpu/x86/car.c | 21 +---- src/drivers/usb/ehci_debug.c | 2 +- src/include/cbmem.h | 20 ++++- src/include/cpu/x86/gdt.h | 3 - src/include/timestamp.h | 2 - src/lib/cbmem_common.c | 20 ++--- src/lib/cbmem_console.c | 6 +- src/lib/ramstage.ld | 117 +++++++++++++++++++++++++ src/lib/rmodule.ld | 3 + src/lib/romstage.ld | 62 +++++++++++++ src/lib/timestamp.c | 7 +- src/soc/intel/baytrail/romstage/romstage.c | 2 +- src/soc/intel/broadwell/romstage/power_state.c | 2 +- 19 files changed, 226 insertions(+), 91 deletions(-) diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 97bc0cd..f7266d4 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -22,7 +22,6 @@ #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 97bc0cd..f7266d4 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -22,7 +22,6 @@ #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 762d246..414782a 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -20,12 +20,6 @@ #include <cbmem.h> #include <arch/acpi.h> -/* FIXME: Remove after CBMEM_INIT_HOOKS. */ -#include <arch/early_variables.h> -#include <cpu/x86/gdt.h> -#include <console/cbmem_console.h> -#include <timestamp.h> - #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) @@ -55,22 +49,6 @@ void *cbmem_top(void) #endif /* LATE_CBMEM_INIT */ -void cbmem_run_init_hooks(void) -{ - /* Migrate car.global_data. */ - car_migrate_variables(); - -#if !defined(__PRE_RAM__) - /* Relocate CBMEM console. */ - cbmemc_reinit(); - - /* Relocate timestamps stash. */ - timestamp_reinit(); - - move_gdt(); -#endif -} - /* Something went wrong, our high memory area got wiped */ void cbmem_fail_resume(void) { diff --git a/src/arch/x86/boot/gdt.c b/src/arch/x86/boot/gdt.c index 7b64af7..b4cfbee 100644 --- a/src/arch/x86/boot/gdt.c +++ b/src/arch/x86/boot/gdt.c @@ -32,7 +32,7 @@ struct gdtarg { /* Copy GDT to new location and reload it. * FIXME: We only do this for BSP CPU. */ -void move_gdt(void) +static void move_gdt(void) { void *newgdt; u16 num_gdt_bytes = (u32)&gdt_end - (u32)&gdt; @@ -55,3 +55,4 @@ void move_gdt(void) __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg)); printk(BIOS_DEBUG, "ok\n"); } +RAMSTAGE_CBMEM_INIT_HOOK(move_gdt) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 2d5ae85..0f3c4f8 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -29,12 +29,6 @@ asm(".previous"); #endif #if defined(__PRE_RAM__) -#define CAR_MIGRATE_ATTR __attribute__ ((used,section (".car.migrate"))) - -/* Call migrate_fn_() when CAR globals are migrated. */ -#define CAR_MIGRATE(migrate_fn_) \ - static void (* const migrate_fn_ ## _ptr)(void) CAR_MIGRATE_ATTR = \ - migrate_fn_; /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); @@ -51,18 +45,10 @@ void *car_sync_var_ptr(void *var); do { car_get_var(var) = (val); } while(0) #else -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) #endif -#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) -/* Migrate the CAR variables to memory. */ -void car_migrate_variables(void); -#else -static inline void car_migrate_variables(void) { } -#endif - #endif diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 99bcc8e..3ade87f 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -31,15 +31,14 @@ SECTIONS _rom = .; *(.rom.text); *(.rom.data); + . = ALIGN(4); + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; *(.rodata); *(.rodata.*); *(.rom.data.*); . = ALIGN(16); - _car_migrate_start = .; - *(.car.migrate); - LONG(0); - _car_migrate_end = .; - . = ALIGN(16); _erom = .; } diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index cca9afd..4957b46 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -23,10 +23,6 @@ #include <cbmem.h> #include <arch/early_variables.h> -typedef void (* const car_migration_func_t)(void); - -extern car_migration_func_t _car_migrate_start; - extern char _car_data_start[]; extern char _car_data_end[]; @@ -127,22 +123,9 @@ static void do_car_migrate_variables(void) car_migrated = ~0; } -static void do_car_migrate_hooks(void) -{ - car_migration_func_t *migrate_func; - /* Call all the migration functions. */ - migrate_func = &_car_migrate_start; - while (*migrate_func != NULL) { - (*migrate_func)(); - migrate_func++; - } -} - -void car_migrate_variables(void) +static void car_migrate_variables(void) { if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) do_car_migrate_variables(); - - if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) - do_car_migrate_hooks(); } +ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 83c23a3..f89ea2f 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -683,7 +683,7 @@ static void migrate_ehci_debug(void) memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info)); car_set_var(glob_dbg_info_p, dbg_info_cbmem); } -CAR_MIGRATE(migrate_ehci_debug); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_ehci_debug); #endif int dbgp_ep_is_active(struct dbgp_pipe *pipe) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ca7a5f4..68a03ad 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -179,16 +179,32 @@ void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); -void cbmem_run_init_hooks(void); void cbmem_fail_resume(void); +typedef void (* const cbmem_init_hook_t)(void); +void cbmem_run_init_hooks(void); + #ifndef __PRE_RAM__ /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); void cbmem_list(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); -#endif /* __PRE_RAM__ */ +#endif + +#ifndef __PRE_RAM__ +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ + static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ + section(".rodata.cbmem_init_hooks"))) = init_fn_; +#else /* __PRE_RAM__ */ +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ + static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ + section(".rodata.cbmem_init_hooks"))) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#endif /* !__PRE_RAM__ */ /* These are for compatibility with old boards only. Any new chipset and board * must implement cbmem_top() for both romstage and ramstage to support diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h index 260b158..43a80fe 100644 --- a/src/include/cpu/x86/gdt.h +++ b/src/include/cpu/x86/gdt.h @@ -28,7 +28,4 @@ extern char _secondary_gdt_addr[]; extern char _secondary_start[]; extern char _secondary_start_end[]; -/* Defined in src/arch/x86/boot/gdt.c */ -void move_gdt(void); - #endif /* CPU_X86_GDT */ diff --git a/src/include/timestamp.h b/src/include/timestamp.h index ba73135..2be3217 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -64,12 +64,10 @@ enum timestamp_id { void timestamp_init(uint64_t base); void timestamp_add(enum timestamp_id id, uint64_t ts_time); void timestamp_add_now(enum timestamp_id id); -void timestamp_reinit(void); #else #define timestamp_init(base) #define timestamp_add(id, time) #define timestamp_add_now(id) -#define timestamp_reinit() #endif /* Implemented by the architecture code */ diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 33f16b5..6509c3f 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -20,10 +20,6 @@ #include <cbmem.h> #include <stdlib.h> -/* FIXME: Remove after CBMEM_INIT_HOOKS. */ -#include <console/cbmem_console.h> -#include <timestamp.h> - #ifndef __PRE_RAM__ static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; @@ -52,18 +48,18 @@ void cbmem_print_entry(int n, u32 id, u64 base, u64 size) #endif /* !__PRE_RAM__ */ -/* FIXME: Replace with CBMEM_INIT_HOOKS API. */ -#if !IS_ENABLED(CONFIG_ARCH_X86) +extern cbmem_init_hook_t _cbmem_init_hooks; +extern cbmem_init_hook_t _ecbmem_init_hooks; + void cbmem_run_init_hooks(void) { - /* Relocate CBMEM console. */ - cbmemc_reinit(); - - /* Relocate timestamps stash. */ - timestamp_reinit(); + cbmem_init_hook_t *init_hook_ptr = &_cbmem_init_hooks; + while (init_hook_ptr != &_ecbmem_init_hooks) { + (*init_hook_ptr)(); + init_hook_ptr++; + } } void __attribute__((weak)) cbmem_fail_resume(void) { } -#endif diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 0c2722c..7f13292 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -208,7 +208,7 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p, new_cons_p->buffer_cursor = cursor; } -void cbmemc_reinit(void) +static void cbmemc_reinit(void) { struct cbmem_console *cbm_cons_p = NULL; int flags = CBMEMC_APPEND; @@ -227,5 +227,5 @@ void cbmemc_reinit(void) init_console_ptr(cbm_cons_p, CONFIG_CONSOLE_CBMEM_BUFFER_SIZE, flags); } -/* Call cbmemc_reinit() at CAR migration time. */ -CAR_MIGRATE(cbmemc_reinit) +ROMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld new file mode 100644 index 0000000..732c8e9 --- /dev/null +++ b/src/lib/ramstage.ld @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file is included inside a SECTIONS block */ + +/* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ +.text : { + _program = .; + _ramstage = .; + _text = .; + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; +} : to_load + +#ifdef CONFIG_COVERAGE +.ctors : { + . = ALIGN(0x100); + __CTOR_LIST__ = .; + KEEP(*(.ctors)); + LONG(0); + LONG(0); + __CTOR_END__ = .; +} +#endif + +/* TODO: align data sections to cache lines? (is that really useful?) */ +.rodata : { + _rodata = .; + . = ALIGN(8); + + /* If any changes are made to the driver start/symbols or the + * section names the equivalent changes need to made to + * rmodule.ld. */ + console_drivers = .; + KEEP(*(.rodata.console_drivers)); + econsole_drivers = . ; + . = ALIGN(8); + pci_drivers = . ; + KEEP(*(.rodata.pci_driver)); + epci_drivers = . ; + cpu_drivers = . ; + KEEP(*(.rodata.cpu_driver)); + ecpu_drivers = . ; + _bs_init_begin = .; + KEEP(*(.bs_init)); + _bs_init_end = .; + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; + + *(.rodata) + *(.rodata.*) + /* kevinh/Ispiri - Added an align, because the objcopy tool + * incorrectly converts sections that are not long word aligned. + */ + . = ALIGN(8); + + _erodata = .; +} + +.data : { + /* Move to different cache line to avoid false sharing with .rodata. */ + . = ALIGN(64); /* May not be actual line size, not that important. */ + _data = .; + *(.data) + *(.data.*) + _edata = .; +} + +.bss . : { + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + _ebss = .; +} + +.heap . : { + _heap = .; + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . += CONFIG_HEAP_SIZE ; + . = ALIGN(4); + _eheap = .; + _eramstage = .; + _eprogram = .; +} + +/* Discard the sections we don't need/want */ + +/DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) +} diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f3e7cba..ad2c852 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -48,6 +48,9 @@ SECTIONS _bs_init_begin = .; *(.bs_init) _bs_init_end = .; + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; . = ALIGN(8); diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld new file mode 100644 index 0000000..bbad333 --- /dev/null +++ b/src/lib/romstage.ld @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file is included inside a SECTIONS block */ + +.text . : { + _program = .; + _romstage = .; + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); +} : to_load + +.data . : { + . = ALIGN(8); + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; + *(.rodata); + *(.rodata.*); + *(.data); + *(.data.*); + . = ALIGN(8); +} + +.bss . : { + . = ALIGN(8); + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + _ebss = .; + _eromstage = .; + _eprogram = .; +} + +/* Discard the sections we don't need/want */ +/DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.eh_frame); +} diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 67635f8..f94aaf7 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -143,7 +143,7 @@ void timestamp_init(uint64_t base) #endif } -void timestamp_reinit(void) +static void timestamp_reinit(void) { if (!boot_cpu()) return; @@ -158,5 +158,6 @@ void timestamp_reinit(void) timestamp_do_sync(); } -/* Call timestamp_reinit at CAR migration time. */ -CAR_MIGRATE(timestamp_reinit) +/* Call timestamp_reinit CBMEM init hooks. */ +ROMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index ac5afab..98987ff 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -164,7 +164,7 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) static struct chipset_power_state *fill_power_state(void) { diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 6e333c1..5871ad9 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -50,7 +50,7 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) /* Return 0, 3, or 5 to indicate the previous sleep state. */ static int prev_sleep_state(struct chipset_power_state *ps)

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Patch set updated for coreboot: dfcadf1 CBMEM: Implement cbmem_run_init_hooks() stub
by Kyösti Mälkki 11 Jan '15

11 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7876 -gerrit commit dfcadf158225c428efd3ebd2d4f8d507d841fb22 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 18 18:30:29 2014 +0200 CBMEM: Implement cbmem_run_init_hooks() stub Until we completely can unify early_variables, use these to handle CBMEM update hooks for both romstage and ramstage. For x86, CAR_MIGRATE serves the purpose of romstage hooks. Change-Id: I100ebc0e35e1b7091b4f287ca37f539fd7c9fa7a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/tables.c | 8 -------- src/arch/arm64/tables.c | 4 ---- src/arch/riscv/tables.c | 8 -------- src/arch/x86/boot/cbmem.c | 18 ++++++++++++------ src/arch/x86/boot/tables.c | 8 -------- src/include/cbmem.h | 8 +++----- src/lib/cbmem.c | 2 +- src/lib/cbmem_common.c | 11 +++++++++++ src/lib/dynamic_cbmem.c | 4 ++-- 9 files changed, 29 insertions(+), 42 deletions(-) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index a2b7b9b..09385b6 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -29,14 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void cbmem_arch_init(void) -{ -} - -void cbmem_fail_resume(void) -{ -} - void write_tables(void) { unsigned long table_pointer, new_table_pointer; diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index ce7ad5a..f71c215 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -29,10 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void cbmem_arch_init(void) -{ -} - struct lb_memory *write_tables(void) { unsigned long table_pointer, new_table_pointer; diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 6300f7b..124a659 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -29,10 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void cbmem_arch_init(void) -{ -} - // WTF. this does not agre with the prototype! static struct lb_memory *wtf_write_tables(void) { @@ -70,7 +66,3 @@ void write_tables(void) { wtf_write_tables(); } - -void cbmem_fail_resume(void) -{ -} diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 8b2b6da..bbf70a2 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -20,6 +20,9 @@ #include <cbmem.h> #include <arch/acpi.h> +/* FIXME: Remove after CBMEM_INIT_HOOKS. */ +#include <cpu/x86/gdt.h> + #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) { @@ -69,16 +72,19 @@ void *cbmem_top(void) #endif /* DYNAMIC_CBMEM */ +void cbmem_run_init_hooks(void) +{ #if !defined(__PRE_RAM__) + move_gdt(); +#endif +} -/* ACPI resume needs to be cleared in the fail-to-recover case, but that - * condition is only handled during ramstage. */ +/* Something went wrong, our high memory area got wiped */ void cbmem_fail_resume(void) { -#if CONFIG_HAVE_ACPI_RESUME - /* Something went wrong, our high memory area got wiped */ +#if !defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + /* ACPI resume needs to be cleared in the fail-to-recover case, but that + * condition is only handled during ramstage. */ acpi_fail_wakeup(); #endif } - -#endif /* !__PRE_RAM__ */ diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 8685ed4..c2265ea 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <cpu/cpu.h> -#include <cpu/x86/gdt.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <arch/pirq_routing.h> @@ -31,13 +30,6 @@ #include <cbmem.h> #include <smbios.h> - -void cbmem_arch_init(void) -{ - /* defined in gdt.c */ - move_gdt(); -} - void write_tables(void) { unsigned long low_table_start, low_table_end; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7de6e56..88d2bfe 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -213,17 +213,15 @@ void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); +void cbmem_run_init_hooks(void); +void cbmem_fail_resume(void); + #ifndef __PRE_RAM__ /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); void cbmem_list(void); -void cbmem_arch_init(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); -void cbmem_fail_resume(void); -#else -static inline void cbmem_arch_init(void) {} -static inline void cbmem_fail_resume(void) {} #endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 0b24ad2..5f834b7 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -243,7 +243,7 @@ int cbmem_recovery(int is_wakeup) cbmem_fail_resume(); } - cbmem_arch_init(); + cbmem_run_init_hooks(); car_migrate_variables(); return !found; } diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index a800173..438fd7f 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -47,3 +47,14 @@ void cbmem_print_entry(int n, u32 id, u64 base, u64 size) } #endif /* !__PRE_RAM__ */ + +/* FIXME: Replace with CBMEM_INIT_HOOKS API. */ +#if !IS_ENABLED(CONFIG_ARCH_X86) +void cbmem_run_init_hooks(void) +{ +} + +void __attribute__((weak)) cbmem_fail_resume(void) +{ +} +#endif diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 5eddbca..ce4e625 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -171,7 +171,7 @@ void cbmem_initialize_empty(void) printk(BIOS_DEBUG, "CBMEM: root @ %p %d entries.\n", root, root->max_entries); - cbmem_arch_init(); + cbmem_run_init_hooks(); /* Migrate cache-as-ram variables. */ car_migrate_variables(); @@ -249,7 +249,7 @@ int cbmem_initialize(void) root->locked = 1; #endif - cbmem_arch_init(); + cbmem_run_init_hooks(); /* Migrate cache-as-ram variables. */ car_migrate_variables();

1 0

Patch set updated for coreboot: ed1d024 CBMEM: Move cbmemc_reinit()
by Kyösti Mälkki 11 Jan '15

11 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7859 -gerrit commit ed1d0244e480cd7586bae94538d58c3a37b48da3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 19:29:02 2014 +0200 CBMEM: Move cbmemc_reinit() This replaces need for separate cbmemc_reinit() calls made via CAR_MIGRATE() and in ramstage. Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 4 ++++ src/lib/cbmem.c | 2 -- src/lib/cbmem_common.c | 5 +++++ src/lib/dynamic_cbmem.c | 2 -- src/mainboard/google/nyan/romstage.c | 5 ----- src/mainboard/google/nyan_big/romstage.c | 5 ----- src/mainboard/google/nyan_blaze/romstage.c | 5 ----- src/mainboard/via/epia-m850/romstage.c | 1 - src/soc/intel/fsp_baytrail/romstage/romstage.c | 1 - 9 files changed, 9 insertions(+), 21 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index bbf70a2..b53745b 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -22,6 +22,7 @@ /* FIXME: Remove after CBMEM_INIT_HOOKS. */ #include <cpu/x86/gdt.h> +#include <console/cbmem_console.h> #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) @@ -75,6 +76,9 @@ void *cbmem_top(void) void cbmem_run_init_hooks(void) { #if !defined(__PRE_RAM__) + /* Relocate CBMEM console. */ + cbmemc_reinit(); + move_gdt(); #endif } diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 5f834b7..ba6560c 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -23,7 +23,6 @@ #include <bootstate.h> #include <cbmem.h> #include <console/console.h> -#include <console/cbmem_console.h> #include <arch/early_variables.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) #include <arch/acpi.h> @@ -256,7 +255,6 @@ static void init_cbmem_post_device(void *unused) #else cbmem_recovery(0); #endif - cbmemc_reinit(); } BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 438fd7f..1630628 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -20,6 +20,9 @@ #include <cbmem.h> #include <stdlib.h> +/* FIXME: Remove after CBMEM_INIT_HOOKS. */ +#include <console/cbmem_console.h> + #ifndef __PRE_RAM__ static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; @@ -52,6 +55,8 @@ void cbmem_print_entry(int n, u32 id, u64 base, u64 size) #if !IS_ENABLED(CONFIG_ARCH_X86) void cbmem_run_init_hooks(void) { + /* Relocate CBMEM console. */ + cbmemc_reinit(); } void __attribute__((weak)) cbmem_fail_resume(void) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index ce4e625..a5f2fc2 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -21,7 +21,6 @@ #include <bootmem.h> #include <console/console.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> @@ -426,7 +425,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) static void init_cbmem_pre_device(void *unused) { cbmem_initialize(); - cbmemc_reinit(); } BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index b6e3635..8912d13 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -31,7 +31,6 @@ #include <cpu/x86/bist.h> #include <string.h> #include <timestamp.h> -#include <console/cbmem_console.h> #include <northbridge/via/vx900/early_vx900.h> #include <northbridge/via/vx900/raminit.h> diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index ad42e73..b0b8133 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -43,7 +43,6 @@ #include <version.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> -#include <console/cbmem_console.h> /* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ uint32_t chipset_prev_sleep_state(uint32_t clear)

1 0

Patch set updated for coreboot: 3d73bed CBMEM: Tidy up CAR migration
by Kyösti Mälkki 11 Jan '15

11 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7860 -gerrit commit 3d73bedef3ccd4ed62b5b8a5c5fedbf72146f613 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 20:55:19 2014 +0200 CBMEM: Tidy up CAR migration Move the CAR migration call to arch -specific part of CBMEM init, it is truly a x86 specific thing. Change-Id: I715417e54f197b8745e0670d6b900a5660178141 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 14 -------------- src/arch/arm/include/arch/early_variables.h | 1 - src/arch/arm64/include/arch/early_variables.h | 5 ----- src/arch/riscv/include/arch/early_variables.h | 5 ----- src/arch/x86/Kconfig | 15 +++++++++++++++ src/arch/x86/boot/cbmem.c | 4 ++++ src/cpu/x86/car.c | 8 +++++++- src/lib/cbmem.c | 3 ++- src/lib/dynamic_cbmem.c | 10 ++-------- 9 files changed, 30 insertions(+), 35 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 92714d5..a58e04a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,20 +159,6 @@ config INCLUDE_CONFIG_FILE config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT -config LATE_CBMEM_INIT - def_bool n - help - Enable this in chipset's Kconfig if northbridge does not implement - early get_top_of_ram() call for romstage. CBMEM tables will be - allocated late in ramstage, after PCI devices resources are known. - -config BROKEN_CAR_MIGRATE - def_bool LATE_CBMEM_INIT - help - Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and - manage CAR migration on S3 resume path only. Couple boards use - CAR_GLOBAL and never do CAR migration. - config DYNAMIC_CBMEM bool default n diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index cb0872e..97bc0cd 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -27,6 +27,5 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } #endif diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 4b7c05b..97bc0cd 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -20,10 +20,6 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H -#if CONFIG_CAR_MIGRATION - #error "This is ARM, silly... we don't have CAR here." -#endif - #define CAR_GLOBAL #define CAR_MIGRATE(migrate_fn_) @@ -31,6 +27,5 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } #endif diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h index f9516a4..97bc0cd 100644 --- a/src/arch/riscv/include/arch/early_variables.h +++ b/src/arch/riscv/include/arch/early_variables.h @@ -20,10 +20,6 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H -#if defined(CONFIG_CAR_MIGRATION) && CONFIG_CAR_MIGRATION - #error "This is RISCV, silly... we don't have CAR here." -#endif - #define CAR_GLOBAL #define CAR_MIGRATE(migrate_fn_) @@ -31,6 +27,5 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } #endif diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 56d8f88..b6791ed 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -47,6 +47,21 @@ config ROMCC bool default n +config BROKEN_CAR_MIGRATE + def_bool n + help + Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and + manage CAR migration on S3 resume path only. Couple boards use + CAR_GLOBAL and never do CAR migration. + +config LATE_CBMEM_INIT + def_bool n + select BROKEN_CAR_MIGRATE + help + Enable this in chipset's Kconfig if northbridge does not implement + early get_top_of_ram() call for romstage. CBMEM tables will be + allocated late in ramstage, after PCI devices resources are known. + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index af42edd..80588c3 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -21,6 +21,7 @@ #include <arch/acpi.h> /* FIXME: Remove after CBMEM_INIT_HOOKS. */ +#include <arch/early_variables.h> #include <cpu/x86/gdt.h> #include <console/cbmem_console.h> #include <timestamp.h> @@ -76,6 +77,9 @@ void *cbmem_top(void) void cbmem_run_init_hooks(void) { + /* Migrate car.global_data. */ + car_migrate_variables(); + #if !defined(__PRE_RAM__) /* Relocate CBMEM console. */ cbmemc_reinit(); diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index e757f09..cca9afd 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -108,7 +108,6 @@ void *car_sync_var_ptr(void *var) static void do_car_migrate_variables(void) { void *migrated_base; - car_migration_func_t *migrate_func; size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; /* Check if already migrated. */ @@ -126,7 +125,11 @@ static void do_car_migrate_variables(void) /* Mark that the data has been moved. */ car_migrated = ~0; +} +static void do_car_migrate_hooks(void) +{ + car_migration_func_t *migrate_func; /* Call all the migration functions. */ migrate_func = &_car_migrate_start; while (*migrate_func != NULL) { @@ -139,4 +142,7 @@ void car_migrate_variables(void) { if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) do_car_migrate_variables(); + + if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) + do_car_migrate_hooks(); } diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index ba6560c..d5f89a1 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -242,8 +242,9 @@ int cbmem_recovery(int is_wakeup) cbmem_fail_resume(); } + /* Complete migration to CBMEM. */ cbmem_run_init_hooks(); - car_migrate_variables(); + return !found; } diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index a5f2fc2..6455217 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -170,18 +170,14 @@ void cbmem_initialize_empty(void) printk(BIOS_DEBUG, "CBMEM: root @ %p %d entries.\n", root, root->max_entries); + /* Complete migration to CBMEM. */ cbmem_run_init_hooks(); - - /* Migrate cache-as-ram variables. */ - car_migrate_variables(); } static inline int cbmem_fail_recovery(void) { cbmem_initialize_empty(); cbmem_fail_resume(); - /* Migrate cache-as-ram variables. */ - car_migrate_variables(); return 1; } @@ -248,11 +244,9 @@ int cbmem_initialize(void) root->locked = 1; #endif + /* Complete migration to CBMEM. */ cbmem_run_init_hooks(); - /* Migrate cache-as-ram variables. */ - car_migrate_variables(); - /* Recovery successful. */ return 0; }

1 0

Patch set updated for coreboot: 6927760 CBMEM: Support DYNAMIC_CBMEM with LATE_CBMEM_INIT
by Kyösti Mälkki 11 Jan '15

11 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7861 -gerrit commit 6927760457bbecacf4f668743b0e3296407478f1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 19 08:20:45 2014 +0200 CBMEM: Support DYNAMIC_CBMEM with LATE_CBMEM_INIT We can now create CBMEM with dynamic allocation even if CBMEM location is resolved late in ramstage. Change-Id: I8529ccbcd4a0e567ebe0a46232ac5d16476e81a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 3 +-- src/arch/x86/boot/cbmem.c | 14 +++++++++----- src/include/cbmem.h | 19 +++++++++++++------ src/lib/cbmem_console.c | 2 +- src/lib/dynamic_cbmem.c | 38 ++++++++++++++++++++++++++++++++++---- 5 files changed, 58 insertions(+), 18 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index a58e04a..560f9e5 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -162,7 +162,6 @@ config EARLY_CBMEM_INIT config DYNAMIC_CBMEM bool default n - select EARLY_CBMEM_INIT help Instead of reserving a static amount of CBMEM space the CBMEM area grows dynamically. CBMEM can be used both in romstage (after @@ -201,7 +200,7 @@ config RELOCATABLE_MODULES loaded anywhere and all the relocations are handled automatically. config RELOCATABLE_RAMSTAGE - depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM) + depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM && EARLY_CBMEM_INIT) bool "Build the ramstage to be relocatable in 32-bit address space." default n help diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index a145223..1036adc 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -39,6 +39,9 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) *size = 0; } } +#endif /* !DYNAMIC_CBMEM */ + +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) @@ -46,14 +49,14 @@ void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ } -/* This is for compatibility with old boards only. Any new chipset and board - * must implement get_top_of_ram() for both romstage and ramstage to support - * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE. - */ void set_top_of_ram(uint64_t ramtop) { backup_top_of_ram(ramtop); +#if !CONFIG_DYNAMIC_CBMEM cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); +#else + cbmem_set_top((void*)(uintptr_t)ramtop); +#endif } #endif /* !__PRE_RAM__ */ @@ -70,7 +73,8 @@ void *cbmem_top(void) return (void *)get_top_of_ram(); } #endif -#endif /* !DYNAMIC_CBMEM */ + +#endif /* LATE_CBMEM_INIT */ void cbmem_run_init_hooks(void) { diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 05708da..c2e7314 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -151,6 +151,9 @@ void cbmem_initialize_empty(void); * below 4GiB. */ void *cbmem_top(void); +/* Set the top address for dynamic cbmem. Not for new designs. */ +void cbmem_set_top(void *ramtop); + /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original * size. */ @@ -168,7 +171,6 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry); - #else /* !CONFIG_DYNAMIC_CBMEM */ /* Allocation with static CBMEM is resolved at build time. We start @@ -183,15 +185,10 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry); #define HIGH_MEMORY_SIZE ALIGN_UP(_CBMEM_SZ_TOTAL, 0x10000) - #ifndef __PRE_RAM__ -void set_top_of_ram(uint64_t ramtop); -void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); #endif -unsigned long get_top_of_ram(void); - void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); @@ -224,6 +221,16 @@ void cbmem_list(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); #endif /* __PRE_RAM__ */ +/* These are for compatibility with old boards only. Any new chipset and board + * must implement cbmem_top() for both romstage and ramstage to support + * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE. + */ +#if IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_LATE_CBMEM_INIT) +unsigned long get_top_of_ram(void); +void set_top_of_ram(uint64_t ramtop); +void backup_top_of_ram(uint64_t ramtop); +#endif + #endif /* __ASSEMBLER__ */ diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 6783b30..0c2722c 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -58,7 +58,7 @@ extern struct cbmem_console preram_cbmem_console; * during the ROM stage, once CBMEM becomes available at RAM stage. */ -#if CONFIG_DYNAMIC_CBMEM +#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) #define STATIC_CONSOLE_SIZE 1024 #else #define STATIC_CONSOLE_SIZE CONFIG_CONSOLE_CBMEM_BUFFER_SIZE diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 1b46745..6ec56c7 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -24,10 +24,9 @@ #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) +#if IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) #include <arch/acpi.h> #endif - #ifndef UINT_MAX #define UINT_MAX 4294967295U #endif @@ -69,11 +68,18 @@ struct cbmem_root { } __attribute__((packed)); +#if !defined(__PRE_RAM__) +static void *cached_cbmem_top; + +void cbmem_set_top(void * ramtop) +{ + cached_cbmem_top = ramtop; +} +#endif + static inline void *cbmem_top_cached(void) { #if !defined(__PRE_RAM__) - static void *cached_cbmem_top; - if (cached_cbmem_top == NULL) cached_cbmem_top = cbmem_top(); @@ -100,6 +106,9 @@ static inline void *get_root(void) struct cbmem_root_pointer *pointer; pointer_addr = get_top_aligned(); + if (pointer_addr == 0) + return NULL; + pointer_addr -= sizeof(struct cbmem_root_pointer); pointer = (void *)pointer_addr; @@ -146,6 +155,9 @@ void cbmem_initialize_empty(void) * DYN_CBMEM_ALIGN_SIZE. The pointer falls just below the * address returned by get_top_aligned(). */ pointer_addr = get_top_aligned(); + if (pointer_addr == 0) + return; + root_addr = pointer_addr - ROOT_MIN_SIZE; root_addr &= ~(DYN_CBMEM_ALIGN_SIZE - 1); pointer_addr -= sizeof(struct cbmem_root_pointer); @@ -413,6 +425,8 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) #if !defined(__PRE_RAM__) + +#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) /* selected cbmem can be initialized early in ramstage. Additionally, that * means cbmem console can be reinitialized early as well. The post_device * function is empty since cbmem was initialized early in ramstage. */ @@ -426,6 +440,22 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { init_cbmem_pre_device, NULL), }; +#else + +static void init_cbmem_post_device(void *unused) +{ + if (acpi_is_wakeup()) + cbmem_initialize(); + else + cbmem_initialize_empty(); +} + +BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, + init_cbmem_post_device, NULL), +}; +#endif + void cbmem_add_bootmem(void) { uintptr_t base;

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Patch set updated for coreboot: a6a1a07 CBMEM console: Fix and enhance pre-RAM support
by Kyösti Mälkki 11 Jan '15

11 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7862 -gerrit commit a6a1a070b6146cba3e34eabb06085ed8f8441fe5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 21 08:55:47 2014 +0200 CBMEM console: Fix and enhance pre-RAM support Use the value of CONSOLE_PRERAM_BUFFER_SIZE to determine if we can do CBMEM console in bootblock and romstage. Kconfig forces it to zero if _BASE is unset or we cannot do CAR migration on x86. Add CBMEM console to bootblock, except for x86. Only one of bootblock and romstage clears the pre-RAM buffer. To start with empty console log on S3 wakeup, ramstage now clears previous contents of CBMEM buffer if there was no pre-RAM buffer. Unify Kconfig variable naming. TODO: ARM configurations do not define PRERAM_BUFFER_BASE values. Change-Id: I70d82da629529dbfd7bc9491223abd703cbc0115 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/Kconfig | 4 -- src/arch/arm/bootblock.ld | 2 +- src/arch/arm/romstage.ld | 2 +- src/arch/arm64/bootblock.ld | 2 + src/arch/arm64/romstage.ld | 2 +- src/arch/riscv/romstage.ld | 2 +- src/console/Kconfig | 14 +++++-- src/include/console/cbmem_console.h | 3 +- src/lib/Makefile.inc | 1 + src/lib/cbmem_console.c | 80 +++++++++++++++++++++---------------- 10 files changed, 65 insertions(+), 47 deletions(-) diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 156c8c2..60c8c8d 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -20,10 +20,6 @@ config ARM_BOOTBLOCK_CUSTOM bool default n -config CBMEM_CONSOLE_PRERAM_BASE - hex - depends on CONSOLE_CBMEM - config CPU_HAS_BOOTBLOCK_INIT bool default n diff --git a/src/arch/arm/bootblock.ld b/src/arch/arm/bootblock.ld index 150bf2d..c355348 100644 --- a/src/arch/arm/bootblock.ld +++ b/src/arch/arm/bootblock.ld @@ -49,7 +49,7 @@ SECTIONS *(.sbss.*); } : to_load = 0xff - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /DISCARD/ : { *(.comment) diff --git a/src/arch/arm/romstage.ld b/src/arch/arm/romstage.ld index 8c32046..34e9eaa 100644 --- a/src/arch/arm/romstage.ld +++ b/src/arch/arm/romstage.ld @@ -69,7 +69,7 @@ SECTIONS _end = .; - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/arch/arm64/bootblock.ld b/src/arch/arm64/bootblock.ld index acce1f1..907d009 100644 --- a/src/arch/arm64/bootblock.ld +++ b/src/arch/arm64/bootblock.ld @@ -49,6 +49,8 @@ SECTIONS *(.sbss.*); } : to_load = 0xff + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; + /DISCARD/ : { *(.comment) *(.note) diff --git a/src/arch/arm64/romstage.ld b/src/arch/arm64/romstage.ld index d05fdd1..a8d092c 100644 --- a/src/arch/arm64/romstage.ld +++ b/src/arch/arm64/romstage.ld @@ -76,7 +76,7 @@ SECTIONS _end = .; - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/arch/riscv/romstage.ld b/src/arch/riscv/romstage.ld index 839c285..a58aee3 100644 --- a/src/arch/riscv/romstage.ld +++ b/src/arch/riscv/romstage.ld @@ -76,7 +76,7 @@ SECTIONS _end = .; - /*preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;*/ + /*preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;*/ /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/console/Kconfig b/src/console/Kconfig index 0d32011..5974695 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -175,8 +175,9 @@ config CONSOLE_CBMEM Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space. +if CONSOLE_CBMEM + config CONSOLE_CBMEM_BUFFER_SIZE - depends on CONSOLE_CBMEM hex "Room allocated for console output in CBMEM" default 0x20000 help @@ -184,9 +185,14 @@ config CONSOLE_CBMEM_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. +config CONSOLE_PRERAM_BUFFER_BASE + hex + default 0xabadbeef if !CACHE_AS_RAM || BROKEN_CAR_MIGRATE + default 0x0 + config CONSOLE_PRERAM_BUFFER_SIZE - depends on CONSOLE_CBMEM - hex "Room allocated for console output before RAM is initialized" + hex + default 0x0 if CONSOLE_PRERAM_BUFFER_BASE = 0xabadbeef default 0xc00 help Console is used before RAM is initialized. This is the room reserved @@ -194,6 +200,8 @@ config CONSOLE_PRERAM_BUFFER_SIZE can be saved in a CBMEM buffer. 3K bytes should be enough even for the BIOS_SPEW level. +endif + config CONSOLE_QEMU_DEBUGCON bool "QEMU debug console output" depends on BOARD_EMULATION_QEMU_X86 diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 36d132c..81bc10f 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -32,7 +32,8 @@ static inline void cbmemc_reinit(void) {} #endif #define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \ - ((ENV_ROMSTAGE && !CONFIG_BROKEN_CAR_MIGRATE) || ENV_RAMSTAGE) + (ENV_RAMSTAGE || (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE && \ + ((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || ENV_ROMSTAGE))) #if __CBMEM_CONSOLE_ENABLE__ static inline void __cbmemc_init(void) { cbmemc_init(); } diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9b5f56b..7e23399 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -21,6 +21,7 @@ subdirs-y += loaders bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c bootblock-y += memchr.c bootblock-y += memcmp.c diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index a8195a6..6783b30 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -37,6 +37,9 @@ struct cbmem_console { static struct cbmem_console *cbmem_console_p CAR_GLOBAL; +static void copy_console_buffer(struct cbmem_console *old_cons_p, + struct cbmem_console *new_cons_p); + #ifdef __PRE_RAM__ /* * While running from ROM, before DRAM is initialized, some area in cache as @@ -63,6 +66,10 @@ extern struct cbmem_console preram_cbmem_console; static u8 static_console[STATIC_CONSOLE_SIZE]; #endif +/* flags for init */ +#define CBMEMC_RESET (1<<0) +#define CBMEMC_APPEND (1<<1) + static inline struct cbmem_console *current_console(void) { return car_sync_var(cbmem_console_p); @@ -73,27 +80,46 @@ static inline void current_console_set(struct cbmem_console *new_console_p) car_set_var(cbmem_console_p, new_console_p); } -static inline void init_console_ptr(void *storage, u32 total_space) +static inline void init_console_ptr(void *storage, u32 total_space, int flags) { struct cbmem_console *cbm_cons_p = storage; - /* Initialize the cache-as-ram pointer and underlying structure. */ - car_set_var(cbmem_console_p, cbm_cons_p); - cbm_cons_p->buffer_size = total_space - sizeof(struct cbmem_console); - cbm_cons_p->buffer_cursor = 0; + if (!cbm_cons_p) { + current_console_set(NULL); + return; + } + + if (flags & CBMEMC_RESET) { + cbm_cons_p->buffer_size = total_space - sizeof(struct cbmem_console); + cbm_cons_p->buffer_cursor = 0; + } + if (flags & CBMEMC_APPEND) { + struct cbmem_console *tmp_cons_p = current_console(); + if (tmp_cons_p) + copy_console_buffer(tmp_cons_p, cbm_cons_p); + } + + current_console_set(cbm_cons_p); } void cbmemc_init(void) { #ifdef __PRE_RAM__ + int flags = CBMEMC_RESET; + + /* Do not clear output from bootblock. */ + if (ENV_ROMSTAGE && !IS_ENABLED(CONFIG_CACHE_AS_RAM)) + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) + flags = 0; + init_console_ptr(&preram_cbmem_console, - CONFIG_CONSOLE_PRERAM_BUFFER_SIZE); + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE, flags); #else /* * Initializing before CBMEM is available, use static buffer to store * the log. */ - init_console_ptr(static_console, sizeof(static_console)); + init_console_ptr(static_console, sizeof(static_console), CBMEMC_RESET); #endif } @@ -119,13 +145,11 @@ void cbmemc_tx_byte(unsigned char data) * If there is overflow - add to the destination area a string, reporting the * overflow and the number of dropped characters. */ -static void copy_console_buffer(struct cbmem_console *new_cons_p) +static void copy_console_buffer(struct cbmem_console *old_cons_p, + struct cbmem_console *new_cons_p) { u32 copy_size, dropped_chars; u32 cursor = new_cons_p->buffer_cursor; - struct cbmem_console *old_cons_p; - - old_cons_p = current_console(); if (old_cons_p->buffer_cursor < old_cons_p->buffer_size) copy_size = old_cons_p->buffer_cursor; @@ -187,35 +211,21 @@ static void copy_console_buffer(struct cbmem_console *new_cons_p) void cbmemc_reinit(void) { struct cbmem_console *cbm_cons_p = NULL; + int flags = CBMEMC_APPEND; -#ifdef __PRE_RAM__ - if (IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) + if (ENV_ROMSTAGE && (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE == 0)) return; -#endif - -#ifndef __PRE_RAM__ - cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (!cbm_cons_p) { - cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, - CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); - - if (!cbm_cons_p) { - current_console_set(NULL); - return; - } - cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE - - sizeof(struct cbmem_console); + /* If CBMEM entry already existed, old contents is not altered. */ + cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); - cbm_cons_p->buffer_cursor = 0; - } + /* Clear old contents of CBMEM buffer. */ + if (ENV_ROMSTAGE || (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE == 0)) + flags |= CBMEMC_RESET; - copy_console_buffer(cbm_cons_p); - - current_console_set(cbm_cons_p); + init_console_ptr(cbm_cons_p, + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE, flags); } - /* Call cbmemc_reinit() at CAR migration time. */ CAR_MIGRATE(cbmemc_reinit)

1 0

Patch set updated for coreboot: 8df6e53 CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
by Kyösti Mälkki 11 Jan '15

11 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7888 -gerrit commit 8df6e538b3e4159f25749856cfd1160c4f6aaf45 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 22 12:28:07 2014 +0200 CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 9 ++--- src/cpu/intel/haswell/romstage.c | 4 +- src/include/cbmem.h | 4 +- src/mainboard/emulation/qemu-i440fx/memory.c | 4 +- src/northbridge/intel/fsp_rangeley/raminit.c | 14 ++++--- src/northbridge/intel/fsp_sandybridge/Makefile.inc | 2 + .../intel/fsp_sandybridge/northbridge.c | 10 ----- src/northbridge/intel/fsp_sandybridge/ram_calc.c | 38 +++++++++++++++++ src/northbridge/intel/fsp_sandybridge/raminit.c | 8 ---- src/northbridge/intel/gm45/ram_calc.c | 7 +++- src/northbridge/intel/haswell/ram_calc.c | 11 +++-- src/northbridge/intel/i945/ram_calc.c | 11 +++-- src/northbridge/intel/nehalem/ram_calc.c | 11 +++-- src/northbridge/intel/sandybridge/ram_calc.c | 11 +++-- src/soc/intel/baytrail/baytrail/smm.h | 2 +- src/soc/intel/baytrail/memmap.c | 8 ++-- src/soc/intel/broadwell/memmap.c | 13 ++++-- src/soc/intel/fsp_baytrail/Makefile.inc | 2 - src/soc/intel/fsp_baytrail/baytrail/smm.h | 2 +- src/soc/intel/fsp_baytrail/memmap.c | 22 +++++++++- src/soc/intel/fsp_baytrail/raminit.c | 47 ---------------------- 21 files changed, 131 insertions(+), 109 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 80588c3..a145223 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -57,23 +57,20 @@ void set_top_of_ram(uint64_t ramtop) } #endif /* !__PRE_RAM__ */ -#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) unsigned long __attribute__((weak)) get_top_of_ram(void) { printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); return 0; } -#endif - -#else +#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM) void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ return (void *)get_top_of_ram(); } - -#endif /* DYNAMIC_CBMEM */ +#endif +#endif /* !DYNAMIC_CBMEM */ void cbmem_run_init_hooks(void) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index bd2513f..1af5259 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -133,7 +133,7 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; - top_of_ram = get_top_of_ram(); + top_of_ram = (uint32_t)cbmem_top(); /* Cache 8MiB below the top of ram. On haswell systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later @@ -318,7 +318,7 @@ struct ramstage_cache *ramstage_cache_location(long *size) /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of ram is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET); + return (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); } void ramstage_cache_invalid(struct ramstage_cache *cache) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 88d2bfe..05708da 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -190,6 +190,8 @@ void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); #endif +unsigned long get_top_of_ram(void); + void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); @@ -201,8 +203,6 @@ static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id) /* Common API between cbmem and dynamic cbmem. */ -unsigned long get_top_of_ram(void); - /* Returns 0 if old cbmem was recovered. Recovery is only attempted if * s3resume is non-zero. */ int cbmem_recovery(int s3resume); diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index a189d75..d43b4e9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -40,7 +40,7 @@ static unsigned long qemu_get_memory_size(void) return tomk; } -unsigned long get_top_of_ram(void) +void *cbmem_top(void) { - return qemu_get_memory_size() * 1024; + return (void *) (qemu_get_memory_size() * 1024); } diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c index 3513c0f..ea750e7 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/raminit.c @@ -26,19 +26,23 @@ #include "northbridge.h" #include <drivers/intel/fsp/fsp_util.h> -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* * Calculate the top of usable (low) DRAM. * The FSP's reserved memory sits just below the SMM region, * allowing calculation of the top of usable memory. */ - u32 tom = sideband_read(B_UNIT, BMBOUND); - u32 bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; + uintptr_t tom = sideband_read(B_UNIT, BMBOUND); + uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; if (bsmmrrl) { tom = bsmmrrl; } - tom -= FSP_RESERVE_MEMORY_SIZE; - return (unsigned long) tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start() - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc index 080a7f4..ca6f345 100644 --- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc +++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc @@ -20,11 +20,13 @@ subdirs-y += fsp ramstage-y += northbridge.c +ramstage-y += ram_calc.c ramstage-y += gma.c ramstage-y += acpi.c romstage-y += raminit.c +romstage-y += ram_calc.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index a95d736..b39f4c9 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -245,16 +245,6 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -unsigned long get_top_of_ram(void) -{ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(dev, TSEG) & ~(1UL << 0); - tom -= 0x200000; /* 2MB for FSP HOB */ - return (unsigned long) tom; -} - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/fsp_sandybridge/ram_calc.c b/src/northbridge/intel/fsp_sandybridge/ram_calc.c new file mode 100644 index 0000000..bbfc874 --- /dev/null +++ b/src/northbridge/intel/fsp_sandybridge/ram_calc.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include <fsp_util.h> +#include "northbridge.h" + +static uintptr_t smm_region_start(void) +{ + /* Base of TSEG is top of usable DRAM */ + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start() - FSP_RESERVE_MEMORY_SIZE; +} diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c index 19b48ca..8689274 100644 --- a/src/northbridge/intel/fsp_sandybridge/raminit.c +++ b/src/northbridge/intel/fsp_sandybridge/raminit.c @@ -74,11 +74,3 @@ void report_memory_config(void) ((ch_conf >> 16) & 1) ? ", selected" : ""); } } - -unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0); - tom -= 0x200000; /* 2MB for FSP HOB */ - return (unsigned long) tom; -} diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c8c15d3..d9d3357 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -86,7 +86,7 @@ u32 decode_igd_gtt_size(const u32 gsm) } } -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); @@ -105,3 +105,8 @@ unsigned long get_top_of_ram(void) } return tor; } + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); +} diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index 99e7d67..01ad50d 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -24,12 +24,17 @@ #include <cbmem.h> #include "haswell.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* * Base of TSEG is top of usable DRAM below 4GiB. The register has * 1 MiB alignement. */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom & ~((1 << 20) - 1); + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom & ~((1 << 20) - 1); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); } diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index d09b2e1..4b7d895 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -24,9 +24,9 @@ #include <cbmem.h> #include "i945.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { - u32 tom; + uintptr_t tom; if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { /* IGD enabled, get top of Memory from BSM register */ @@ -53,5 +53,10 @@ unsigned long get_top_of_ram(void) /* TSEG either disabled or invalid */ break; } - return (unsigned long) tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index db57a3d..d36684e 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -23,9 +23,14 @@ #include <cbmem.h> #include "nehalem.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 3693a07..e147909 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -23,9 +23,14 @@ #include <cbmem.h> #include "sandybridge.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/soc/intel/baytrail/baytrail/smm.h b/src/soc/intel/baytrail/baytrail/smm.h index 5ead89f..0d920fb 100644 --- a/src/soc/intel/baytrail/baytrail/smm.h +++ b/src/soc/intel/baytrail/baytrail/smm.h @@ -31,7 +31,7 @@ static inline int smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *smm_region_start(void); +uintptr_t smm_region_start(void); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index f383d82..f2e14b3 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -22,12 +22,12 @@ #include <baytrail/iosf.h> #include <baytrail/smm.h> -void *smm_region_start(void) +uintptr_t smm_region_start(void) { - return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20); + return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -unsigned long get_top_of_ram(void) +void *cbmem_top(void) { - return (unsigned long)smm_region_start(); + return (void *) smm_region_start(); } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 046cc1d..28f4062 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -23,19 +23,24 @@ #include <broadwell/pci_devs.h> #include <broadwell/systemagent.h> -unsigned long get_top_of_ram(void) +static uintptr_t dpr_region_start(void) { /* * Base of DPR is top of usable DRAM below 4GiB. The register has * 1 MiB alignment and reports the TOP of the range, the base * must be calculated from the size in MiB in bits 11:4. */ - u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR); - u32 tom = dpr & ~((1 << 20) - 1); + uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR); + uintptr_t tom = dpr & ~((1 << 20) - 1); /* Subtract DMA Protected Range size if enabled */ if (dpr & DPR_EPM) tom -= (dpr & DPR_SIZE_MASK) << 16; - return (unsigned long)tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) dpr_region_start(); } diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index fcbe6e7..3896e85 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -44,8 +44,6 @@ ramstage-y += ramstage.c ramstage-y += gpio.c romstage-y += gpio.c ramstage-y += pmutil.c -romstage-y += raminit.c -ramstage-y += raminit.c ramstage-y += southcluster.c romstage-y += reset.c ramstage-y += reset.c diff --git a/src/soc/intel/fsp_baytrail/baytrail/smm.h b/src/soc/intel/fsp_baytrail/baytrail/smm.h index 0208c9f..136c2ca 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/smm.h +++ b/src/soc/intel/fsp_baytrail/baytrail/smm.h @@ -36,7 +36,7 @@ static inline int smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *smm_region_start(void); +uintptr_t smm_region_start(void); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 83858b8..615916b 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,25 @@ #include <cbmem.h> #include <baytrail/iosf.h> #include <baytrail/smm.h> +#include <drivers/intel/fsp/fsp_util.h> -void *smm_region_start(void) +uintptr_t smm_region_start(void) { - return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20); + return (iosf_bunit_read(BUNIT_SMRRL) << 20); +} + +/* + * Calculate the top of usable (low) DRAM. + * The FSP's reserved memory sits just below the SMM region, + * allowing calculation of the top of usable memory. + * + * The entire memory map is shown in northcluster.c + */ + +void *cbmem_top(void) +{ + uintptr_t tom = smm_region_start(); + if (!tom) + tom = iosf_bunit_read(BUNIT_BMBOUND); + return (void *) tom - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/soc/intel/fsp_baytrail/raminit.c b/src/soc/intel/fsp_baytrail/raminit.c deleted file mode 100644 index 55692d2..0000000 --- a/src/soc/intel/fsp_baytrail/raminit.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <arch/io.h> -#include <cbmem.h> -#include <device/device.h> -#include <baytrail/baytrail.h> -#include <baytrail/iosf.h> -#include <cpu/x86/msr.h> -#include <drivers/intel/fsp/fsp_util.h> - -unsigned long get_top_of_ram(void) -{ - /* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. - * - * The entire memory map is shown in northcluster.c - */ - u32 tom = iosf_bunit_read(BUNIT_BMBOUND); - u32 bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; - if (bsmmrrl) { - tom = bsmmrrl; - } - tom -= FSP_RESERVE_MEMORY_SIZE; - - return (unsigned long) tom; -}

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Patch set updated for coreboot: 0f59d9c asus/m4a785/Kconfig: Add vgabios pci id
by Nicolas Reinecke 10 Jan '15

10 Jan '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8177 -gerrit commit 0f59d9c2ce33694b4a76adb63f4834ff4541f56b Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Jan 4 16:26:08 2015 +0100 asus/m4a785/Kconfig: Add vgabios pci id Change-Id: I5ad91faec9c97f34c8ca48eee9198237e9ea8336 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/asus/m4a785-m/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index 5162e16..3abeb0b 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -61,4 +61,8 @@ config AMD_UCODE_PATCH_FILE string default "mc_patch_010000b6.h" +config VGA_BIOS_ID + string + default "1002,9710" + endif

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Patch set updated for coreboot: 9393810 Makefile: clang - ramp up some more warnings
by Edward O'Callaghan 10 Jan '15

10 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8136 -gerrit commit 9393810ccbfe2375b902aec3cc0d68ac6e8f68ad Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 14:58:31 2015 +1100 Makefile: clang - ramp up some more warnings Change-Id: I5262cba22d262f5d74d1edd958b59c2695271293 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 017ca47..51c0c58 100644 --- a/Makefile +++ b/Makefile @@ -119,7 +119,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # this means the triple is i386-linux-elf instead of i386-none-elf CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 # Tone down some clang warnings -CFLAGS_x86_32 += -Wno-unused-variable -Wno-unused-function -Wno-tautological-compare -Wno-shift-overflow +CFLAGS_x86_32 += -Wno-unused-variable -Wno-tautological-compare -Wno-shift-overflow CC_x86_32:=clang HOSTCC := clang

1 0

Patch set updated for coreboot: aaa12fb soc/intel/broadwell/spi_loading.c: Remove dead code
by Edward O'Callaghan 10 Jan '15

10 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8168 -gerrit commit aaa12fbf6ba766a276ffb53e5b83b79835cb402a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 8 02:05:21 2015 +1100 soc/intel/broadwell/spi_loading.c: Remove dead code I would appear from commit a6354a1 that this is now dead code. Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/spi_loading.c | 67 ----------------------------------- 2 files changed, 68 deletions(-) diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 43be95e..feead00 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -52,7 +52,6 @@ smm-y += smihandler.c ramstage-y += smmrelocate.c ramstage-y += spi.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += spi_loading.c ramstage-y += stage_cache.c romstage-y += stage_cache.c ramstage-y += systemagent.c diff --git a/src/soc/intel/broadwell/spi_loading.c b/src/soc/intel/broadwell/spi_loading.c deleted file mode 100644 index 9454d03..0000000 --- a/src/soc/intel/broadwell/spi_loading.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -}

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coreboot-gerrit January 2015