coreboot-gerrit January 2015

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Patch merged into coreboot/master: 2fcf6f1 haswell: Fix MRC cache to use CBFS
by gerrit＠coreboot.org 10 Jan '15

10 Jan '15

the following patch was just integrated into master: commit 2fcf6f1cafca99105f2ce7485c81d8c9eb74e2de Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Dec 27 21:04:53 2014 +0200 haswell: Fix MRC cache to use CBFS Place the mrc.cache file at top of CBFS. There is no real requirement for it to have a fixed location though. Change-Id: Ibebe848a573b41788c9d84388be8ced68957f367 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7962 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/7962 for details. -gerrit

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Patch set updated for coreboot: c0beff9 ACPI: Get S3 resume state from romstage_handoff
by Kyösti Mälkki 10 Jan '15

10 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8188 -gerrit commit c0beff9615f8f7dccb6ddc1486a75115bbb2fc3b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 ACPI: Get S3 resume state from romstage_handoff There is nothing platform specific in retrieving S3 resume state from romstage_handoff structure. Boards without EARLY_CBMEM_INIT update acpi_slp_type from ACPI power-management block or scratchpad registers. Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 20 +++++++++++++++++-- src/northbridge/intel/haswell/northbridge.c | 22 -------------------- src/soc/intel/baytrail/ramstage.c | 26 ++++++------------------ src/soc/intel/baytrail/southcluster.c | 3 +-- src/soc/intel/baytrail/xhci.c | 4 ++-- src/soc/intel/broadwell/lpc.c | 4 ++-- src/soc/intel/broadwell/me.c | 4 +--- src/soc/intel/broadwell/ramstage.c | 31 +++++++++-------------------- src/soc/intel/broadwell/refcode.c | 11 +--------- src/soc/intel/broadwell/systemagent.c | 23 --------------------- src/soc/intel/fsp_baytrail/ramstage.c | 23 ++++----------------- src/soc/intel/fsp_baytrail/southcluster.c | 1 - 12 files changed, 44 insertions(+), 128 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 621df2f..777053e 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -36,6 +36,7 @@ #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif +#include <romstage_handoff.h> /* FIXME: Kconfig doesn't support overridable defaults :-( */ #ifndef CONFIG_HPET_MIN_TICKS @@ -857,10 +858,25 @@ void acpi_resume(void *wake_vec) /* This is filled with acpi_is_wakeup() call early in ramstage. */ int acpi_slp_type = -1; -int __attribute__((weak)) acpi_get_sleep_type(void) +#if CONFIG_EARLY_CBMEM_INIT +int acpi_get_sleep_type(void) { - return 0; + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } } +#endif static void acpi_handoff_wakeup(void) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..7eb9f08 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -35,7 +35,6 @@ #include <cpu/x86/smm.h> #include <boot/tables.h> #include <cbmem.h> -#include <romstage_handoff.h> #include "chip.h" #include "haswell.h" @@ -433,26 +432,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -462,7 +441,6 @@ static struct device_operations mc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..9e429ab 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -27,8 +27,8 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <romstage_handoff.h> #include <stdlib.h> +#include <string.h> #include <baytrail/gpio.h> #include <baytrail/lpc.h> @@ -130,13 +130,6 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) { @@ -166,22 +159,15 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 5274b03..20cbbcf 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -29,7 +29,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> -#include <romstage_handoff.h> #include <drivers/uart/uart8250reg.h> #include <baytrail/iomap.h> @@ -215,7 +214,7 @@ static void sc_init(device_t dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) com1_configure_resume(dev); } diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..19339e4 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -184,7 +184,7 @@ static void xhci_route_all(device_t dev) /* Route ports to XHCI controller */ reg_script_run_on_dev(dev, xhci_route_all_script); - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) return; /* Reset enabled USB3 ports */ @@ -222,7 +222,7 @@ static void xhci_init(device_t dev) }; /* Initialize XHCI controller for boot or resume path */ - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 394a9d7..c670440 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -394,7 +394,7 @@ static void pch_cg_init(device_t dev) static void pch_set_acpi_mode(void) { #if CONFIG_HAVE_SMI_HANDLER - if (acpi_slp_type != 3) { + if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); @@ -551,7 +551,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (acpi_slp_type != 3 && gnvs) + if (!acpi_is_wakeup_s3() && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); } diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 2bdb1ed..9fc6a41 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -830,13 +830,11 @@ static void intel_me_init(device_t dev) static void intel_me_enable(device_t dev) { -#if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { dev->enabled = 0; pch_disable_devfn(dev); } -#endif } static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 0563064..2097f2f 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -21,8 +21,8 @@ #include <cbmem.h> #include <console/console.h> #include <device/device.h> -#include <romstage_handoff.h> #include <stdlib.h> +#include <string.h> #include <broadwell/nvs.h> #include <broadwell/pm.h> #include <broadwell/ramstage.h> @@ -54,31 +54,18 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) gnvs->pm1i); } -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - static void s3_resume_prepare(void) { - global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; + global_nvs_t *gnvs; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); - return; - } + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + if (gnvs == NULL) + return; - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void broadwell_init_pre_device(void *chip_info) diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index a745101..d66d036 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -30,15 +30,6 @@ #include <broadwell/pei_wrapper.h> #include <broadwell/ramstage.h> -static inline int is_s3_resume(void) -{ -#if CONFIG_HAVE_ACPI_RESUME - return acpi_slp_type == 3; -#else - return 0; -#endif -} - static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) { return (struct ramstage_cache *)&c->program[c->size]; @@ -136,7 +127,7 @@ static pei_wrapper_entry_t load_reference_code(void) }; int ret; - if (is_s3_resume()) { + if (acpi_is_wakeup_s3()) { return load_refcode_from_cache(); } diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 74c43f2..ac021fb 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -29,7 +29,6 @@ #include <stdlib.h> #include <string.h> #include <cbmem.h> -#include <romstage_handoff.h> #include <vendorcode/google/chromeos/chromeos.h> #include <broadwell/cpu.h> #include <broadwell/iomap.h> @@ -412,27 +411,6 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -451,7 +429,6 @@ static struct device_operations systemagent_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &systemagent_init, - .enable = &systemagent_enable, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..6742ce8 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -26,8 +26,8 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <romstage_handoff.h> #include <stdlib.h> +#include <string.h> #include <baytrail/gpio.h> #include <baytrail/lpc.h> @@ -125,31 +125,16 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } - -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - set_acpi_sleep_type(3); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); } void baytrail_init_pre_device(void) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index d87935b..9b1e42e 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -33,7 +33,6 @@ #include <pc80/i8254.h> #include <pc80/i8259.h> #include <pc80/isa-dma.h> -#include <romstage_handoff.h> #include <baytrail/baytrail.h> #include <baytrail/iomap.h>

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Patch set updated for coreboot: 9806ac6 intel: Fix S3 handoff state to ramstage
by Kyösti Mälkki 10 Jan '15

10 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8172 -gerrit commit 9806ac6d1e92028e6c583ec12500d5b598bc76d5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 intel: Fix S3 handoff state to ramstage TODO: missing romstage find_or_add_romstage_handoff() Global acpi_slp_type is now declared static. The change also guarantees it will always be initialized before use. Change-Id: I0f074bb80f06f6f0ddf4212cd8872e94ae57f949 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 2 +- src/arch/x86/include/arch/acpi.h | 2 -- src/mainboard/lenovo/t60/mainboard.c | 7 +++---- src/mainboard/lenovo/x200/romstage.c | 6 ------ src/mainboard/lenovo/x201/mainboard.c | 5 ++--- src/mainboard/lenovo/x201/romstage.c | 3 --- src/mainboard/lenovo/x60/mainboard.c | 7 +++---- src/mainboard/packardbell/ms2290/romstage.c | 3 --- src/mainboard/roda/rk9/romstage.c | 6 ------ src/northbridge/intel/gm45/northbridge.c | 17 ----------------- src/northbridge/intel/i945/early_init.c | 5 ----- src/northbridge/intel/i945/northbridge.c | 23 ----------------------- src/northbridge/intel/nehalem/nehalem.h | 4 ---- src/northbridge/intel/nehalem/northbridge.c | 21 --------------------- src/northbridge/intel/sandybridge/early_init.c | 4 ---- src/northbridge/intel/sandybridge/northbridge.c | 21 --------------------- src/southbridge/intel/i82801gx/i82801gx.h | 2 -- src/southbridge/intel/i82801gx/smi.c | 13 ++----------- src/southbridge/intel/i82801ix/i82801ix.h | 4 ---- src/southbridge/intel/i82801ix/smi.c | 13 ++----------- 20 files changed, 13 insertions(+), 155 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 777053e..50832e9 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -856,7 +856,7 @@ void acpi_resume(void *wake_vec) } /* This is filled with acpi_is_wakeup() call early in ramstage. */ -int acpi_slp_type = -1; +static int acpi_slp_type = -1; #if CONFIG_EARLY_CBMEM_INIT int acpi_get_sleep_type(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 771b51c..c2181d7 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -580,7 +580,6 @@ static inline int acpi_s3_resume_allowed(void) } #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -extern int acpi_slp_type; #ifdef __PRE_RAM__ static inline int acpi_is_wakeup_s3(void) @@ -593,7 +592,6 @@ int acpi_is_wakeup_s3(void); #endif #else -#define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } #endif diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index abda9ea..6647970 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -22,12 +22,12 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <arch/io.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> @@ -69,13 +69,12 @@ const char *smbios_mainboard_bios_version(void) static void mainboard_init(device_t dev) { struct southbridge_intel_i82801gx_config *config; - device_t dev0, idedev; + device_t idedev; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index f232642..76aa23a 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -192,12 +192,6 @@ void main(unsigned long bist) */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); } #endif printk(BIOS_SPEW, "exit main()\n"); diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 3cda4fa..40d52a4 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> @@ -116,7 +117,6 @@ static void fill_ssdt(void) static void mainboard_enable(device_t dev) { - device_t dev0; u16 pmbase; dev->ops->init = mainboard_init; @@ -136,8 +136,7 @@ static void mainboard_enable(device_t dev) 0x10); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 64011b1..bfe5f7f 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -304,10 +304,7 @@ void main(unsigned long bist) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); quick_ram_check(); } #endif diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 334c27d..778690b 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -22,13 +22,13 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <arch/interrupt.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> @@ -58,7 +58,7 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_init(device_t dev) { - device_t dev0, idedev, sdhci_dev; + device_t idedev, sdhci_dev; ec_clr_bit(0x03, 2); @@ -70,8 +70,7 @@ static void mainboard_init(device_t dev) install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index f702e9f..686a68e 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -291,10 +291,7 @@ void main(unsigned long bist) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); quick_ram_check(); } #endif diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index c8b75e0..a8937d4 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -206,12 +206,6 @@ void main(unsigned long bist) */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); } #endif printk(BIOS_SPEW, "exit main()\n"); diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index fc54a8c..6f9d4f9 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -220,28 +220,11 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; - static void enable_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 0b2acd7..6fb2385 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -195,7 +195,6 @@ static void i945_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); printk(BIOS_DEBUG, " done.\n"); /* Wait for MCH BAR to come up */ @@ -913,10 +912,6 @@ static void i945_prepare_resume(int s3resume) if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, - SKPAD_ACPI_S3_MAGIC); } } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 1aaeb3b..102b784 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -232,26 +232,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -#if CONFIG_HAVE_ACPI_RESUME -static void northbridge_init(struct device *dev) -{ - switch (pci_read_config32(dev, SKPAD)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -} -#endif - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -261,9 +241,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, -#if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, -#endif .scan_bus = 0, .ops_pci = &intel_pci_ops, }; diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 73137b2..c900904 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -226,10 +226,6 @@ enum { #define D0F0_TOLUD 0xb0 #define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe - - #define D0F0_CAPID0 0xe0 #define TSEG 0xac /* TSEG base */ diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 11d335a..b303882 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -283,26 +283,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; - case 0xcafed00d: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -312,7 +292,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 3156f86..e082a04 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -195,10 +195,6 @@ void northbridge_romstage_finalize(int s3resume) *(u32 *)CBMEM_BOOT_MODE = 2; *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } #endif } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 55395ea..8138b94 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -412,26 +412,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case 0xcafed00d: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -441,7 +421,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index ee13b7d..f96a491 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -365,7 +365,5 @@ int southbridge_detect_s3_resume(void); #define SS_CNT 0x50 #define C3_RES 0x54 -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 134c232..67fb5bf 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> @@ -320,16 +321,6 @@ static void smm_relocate(void) static int smm_handler_copied = 0; -static int is_wakeup(void) -{ - device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - - if (!dev0) - return 0; - - return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; -} - static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -343,7 +334,7 @@ static void smm_install(void) /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ - if (!is_wakeup()) { + if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index d8dc077..2ae6636 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -207,10 +207,6 @@ #define FD_SAD1 (1 << 2) /* SATA #1 */ -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe - - #ifndef __ACPI__ #ifndef __ASSEMBLER__ diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index de9931c..32d3ed0 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> @@ -319,16 +320,6 @@ static void smm_relocate(void) static int smm_handler_copied = 0; -static int is_wakeup(void) -{ - device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - - if (!dev0) - return 0; - - return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; -} - static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -342,7 +333,7 @@ static void smm_install(void) /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ - if (!is_wakeup()) { + if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);

1 0

Patch set updated for coreboot: 8037c9b ACPI: Prepare for HAVE_ACPI_RESUME changes
by Kyösti Mälkki 10 Jan '15

10 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8186 -gerrit commit 8037c9b8fffa46e9298debe45cf0b74c26d72a51 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 9 23:55:09 2015 +0200 ACPI: Prepare for HAVE_ACPI_RESUME changes Change-Id: I71d522b135dff8b3c287699cc649caece9e4342c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 12 ++++-------- src/arch/x86/include/arch/acpi.h | 22 ++++++++++------------ 2 files changed, 14 insertions(+), 20 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 61f0954..621df2f 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -854,8 +854,8 @@ void acpi_resume(void *wake_vec) acpi_jump_to_wakeup(wake_vec); } -/* This is to be filled by SB code - startup value what was found. */ -u8 acpi_slp_type = 0; +/* This is filled with acpi_is_wakeup() call early in ramstage. */ +int acpi_slp_type = -1; int __attribute__((weak)) acpi_get_sleep_type(void) { @@ -864,12 +864,8 @@ int __attribute__((weak)) acpi_get_sleep_type(void) static void acpi_handoff_wakeup(void) { - static int once = 0; - if (once) - return; - - acpi_slp_type = acpi_get_sleep_type(); - once = 1; + if (acpi_slp_type < 0) + acpi_slp_type = acpi_get_sleep_type(); } int acpi_is_wakeup(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 502c826..c497082 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -559,14 +559,10 @@ unsigned long acpi_fill_hest(acpi_hest_t *hest); void acpi_save_gnvs(u32 gnvs_address); -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -/* 0 = S0, 1 = S1 ...*/ -extern u8 acpi_slp_type; - -int acpi_is_wakeup(void); -int acpi_is_wakeup_s3(void); -int acpi_is_wakeup_early(void); +/* cpu/intel/speedstep/acpi.c */ +void generate_cpu_entries(void); +/* For ACPI S3 support. */ void acpi_fail_wakeup(void); void acpi_resume(void *wake_vec); void acpi_prepare_resume_backup(void); @@ -575,18 +571,20 @@ void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr); +/* Returns 0 = S0, 1 = S1 ... */ int acpi_get_sleep_type(void); -#endif /* IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) */ - -/* cpu/intel/speedstep/acpi.c */ -void generate_cpu_entries(void); static inline int acpi_s3_resume_allowed(void) { return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); } -#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +extern int acpi_slp_type; +int acpi_is_wakeup(void); +int acpi_is_wakeup_s3(void); +int acpi_is_wakeup_early(void); +#else #define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; }

1 0

Patch set updated for coreboot: 7ec8006 ACPI: Add acpi_is_wakeup_s3() for romstage
by Kyösti Mälkki 10 Jan '15

10 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8187 -gerrit commit 7ec80065b663bcd8280f80b170b99b4ab40d34fb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 9 23:48:47 2015 +0200 ACPI: Add acpi_is_wakeup_s3() for romstage This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/acpi.h | 11 ++++- src/cpu/amd/agesa/heapmanager.c | 6 +-- src/cpu/amd/car/post_cache_as_ram.c | 8 +--- src/mainboard/amd/olivehill/romstage.c | 2 +- src/mainboard/amd/olivehillplus/romstage.c | 2 +- src/mainboard/amd/parmer/romstage.c | 2 +- src/mainboard/amd/persimmon/romstage.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 2 +- src/mainboard/asrock/imb-a180/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/gizmosphere/gizmo/romstage.c | 2 +- src/mainboard/gizmosphere/gizmo2/romstage.c | 2 +- src/mainboard/hp/abm/romstage.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 +- src/mainboard/lenovo/g505s/romstage.c | 2 +- src/mainboard/lippert/frontrunner-af/romstage.c | 2 +- src/mainboard/lippert/toucan-af/romstage.c | 2 +- src/northbridge/amd/amdk8/raminit.c | 6 +-- src/northbridge/amd/amdk8/raminit_f.c | 7 +-- src/southbridge/amd/agesa/hudson/Makefile.inc | 4 +- src/southbridge/amd/agesa/hudson/early_setup.c | 28 ------------ src/southbridge/amd/agesa/hudson/hudson.c | 40 ----------------- src/southbridge/amd/agesa/hudson/ramtop.c | 59 +++++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/Makefile.inc | 3 ++ src/southbridge/amd/cimx/sb800/cfg.c | 47 +------------------- src/southbridge/amd/cimx/sb800/early.c | 8 ---- src/southbridge/amd/cimx/sb800/ramtop.c | 59 +++++++++++++++++++++++++ src/southbridge/amd/sb700/early_setup.c | 9 ++-- src/southbridge/amd/sb700/lpc.c | 17 +++---- src/southbridge/amd/sb800/early_setup.c | 9 ++-- src/southbridge/intel/i82371eb/smbus.c | 11 ----- src/southbridge/intel/i82371eb/wakeup.c | 3 +- src/southbridge/via/k8t890/early_car.c | 4 +- src/southbridge/via/vt8237r/early_smbus.c | 4 +- src/southbridge/via/vt8237r/lpc.c | 10 +++-- 36 files changed, 177 insertions(+), 206 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index c497082..771b51c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -581,14 +581,21 @@ static inline int acpi_s3_resume_allowed(void) #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) extern int acpi_slp_type; + +#ifdef __PRE_RAM__ +static inline int acpi_is_wakeup_s3(void) +{ + return (acpi_get_sleep_type() == 3); +} +#else int acpi_is_wakeup(void); int acpi_is_wakeup_s3(void); -int acpi_is_wakeup_early(void); +#endif + #else #define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } -static inline int acpi_is_wakeup_early(void) { return 0; } #endif #endif /* __ASM_ACPI_H */ diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index 50ec3ff..cc53d35 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -12,13 +12,11 @@ UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) { UINT32 heap = BIOS_HEAP_START_ADDRESS; -#if CONFIG_HAVE_ACPI_RESUME - /* Both romstage and ramstage has this S3 detect. */ - if (acpi_get_sleep_type() == 3) + if (acpi_is_wakeup_s3()) heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */ -#endif + return heap; } diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 8bc5cd3..6c32090 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -101,12 +101,10 @@ void post_cache_as_ram(void) { void *resume_backup_memory = NULL; - int s3resume = acpi_s3_resume_allowed() && acpi_is_wakeup_early(); + int s3resume = acpi_is_wakeup_s3(); if (s3resume) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) cbmem_recovery(s3resume); resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); -#endif } prepare_romstage_ramstack(resume_backup_memory); @@ -141,10 +139,8 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - if (acpi_s3_resume_allowed() && acpi_is_wakeup_early()) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + if (acpi_is_wakeup_s3()) { resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); -#endif } prepare_ramstage_region(resume_backup_memory); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 2262782..8286f0b 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 6fa3af6..63044ed 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -90,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); AGESAWRAPPER(amdinitpost); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 1fb709a..1d25736 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -71,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 2fdab41..bff9e14 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -86,7 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 30808a4..27d9680 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -85,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index efeed35..cb6d07a 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 95298d1..2332b4a 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index f420bf2..527ad26 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index 2262782..8286f0b 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 5e3044a..a55ec02 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index bc92e6d..87fcd4c 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -63,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 197c81d..c3ca947 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index bc92e6d..87fcd4c 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -63,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 0f718f2..cc03053 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -85,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 415cdbe..7a8e916 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -86,7 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 19f83b9..4213cfb 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2349,11 +2349,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; u32 whatWait = 0; -#if CONFIG_HAVE_ACPI_RESUME - int suspend = acpi_is_wakeup_early(); -#else - int suspend = 0; -#endif + int suspend = acpi_is_wakeup_s3(); /* Error if I don't have memory */ if (memory_end_k(ctrl, controllers) == 0) { diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index b8417a6..92d7f13 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -26,6 +26,7 @@ #include <cpu/amd/mtrr.h> #include <stdlib.h> +#include <arch/acpi.h> #include "raminit.h" #include "f.h" #include <spd_ddr2.h> @@ -3017,11 +3018,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int i; -#if CONFIG_HAVE_ACPI_RESUME - int suspend = acpi_is_wakeup_early(); -#else - int suspend = 0; -#endif + int suspend = acpi_is_wakeup_s3(); #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 unsigned cpu_f0_f1[8]; diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 84f0d3e..bcadd8d 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -19,7 +19,9 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-y += resume.c +ramstage-y += resume.c ramtop.c + +romstage-y += ramtop.c romstage-y += imc.c ramstage-y += imc.c diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 1b9b689..3816141 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -123,32 +123,4 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ - return (int)tmp; -} - -int acpi_is_wakeup_early(void) -{ - return (acpi_get_sleep_type() == 3); -} -#endif /* CONFIG_HAVE_ACPI_RESUME */ - -unsigned long get_top_of_ram(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} - #endif /* _HUDSON_EARLY_SETUP_C_ */ diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index be8aa69..fd2c268 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -38,30 +38,6 @@ */ #define PM_MMIO_BASE 0xfed80300 - -#if CONFIG_HAVE_ACPI_RESUME -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ - return (int)tmp; -} -#endif - -void backup_top_of_ram(uint64_t ramtop) -{ - u32 dword = (u32) ramtop; - int nvram_pos = 0xf8, i; /* temp */ - /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ - for (i = 0; i<4; i++) { - /* printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); */ - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); - nvram_pos++; - } -} - void pm_write8(u8 reg, u8 value) { write8(PM_MMIO_BASE + reg, value); @@ -160,22 +136,6 @@ void hudson_enable(device_t dev) } } -#if CONFIG_HAVE_ACPI_RESUME -unsigned long get_top_of_ram(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - if (acpi_get_sleep_type() != 3) - return 0; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} -#endif static void hudson_init_acpi_ports(void) { diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c new file mode 100644 index 0000000..182150f --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/ramtop.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include "hudson.h" + +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + tmp = ((tmp & (7 << 10)) >> 10); + return (int)tmp; +} + +#ifndef __PRE_RAM__ +void backup_top_of_ram(uint64_t ramtop) +{ + u32 dword = (u32) ramtop; + int nvram_pos = 0xf8, i; /* temp */ + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif + +unsigned long get_top_of_ram(void) +{ + uint32_t xdata = 0; + int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (unsigned long) xdata; +} diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index f4a84b7..ca3d86a 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -34,6 +34,9 @@ ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c + romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 9ddcf8f..ac6e6ae 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -26,48 +26,6 @@ #include <arch/io.h> #include <arch/acpi.h> -#if CONFIG_HAVE_ACPI_RESUME -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(PM1_CNT_BLK_ADDRESS); - tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ - return (int)tmp; -} -#endif - -#ifndef __PRE_RAM__ -void backup_top_of_ram(uint64_t ramtop) -{ - u32 dword = (u32) ramtop; - int nvram_pos = 0xf8, i; /* temp */ - printk(BIOS_DEBUG, "dword=%x\n", dword); - for (i = 0; i<4; i++) { - printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); - nvram_pos++; - } -} -#endif - -#if CONFIG_HAVE_ACPI_RESUME -unsigned long get_top_of_ram(void) -{ - u32 xdata = 0; - int xnvram_pos = 0xf8, xi; - if (acpi_get_sleep_type() != 3) - return 0; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} -#endif - /** * @brief South Bridge CIMx configuration * @@ -80,10 +38,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) if (!sb_config) return; -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_get_sleep_type() == 3) - sb_config->S3Resume = 1; -#endif + sb_config->S3Resume = acpi_is_wakeup_s3(); /* header */ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 7492f99..34375c5 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <device/pci_ids.h> #include <arch/io.h> /* inl, outl */ -#include <arch/acpi.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ @@ -74,10 +73,3 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } - -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) -{ - return (acpi_get_sleep_type() == 3); -} -#endif diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c new file mode 100644 index 0000000..7e9abae --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include "SBPLATFORM.h" + +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(PM1_CNT_BLK_ADDRESS); + tmp = ((tmp & (7 << 10)) >> 10); + return (int)tmp; +} + +#ifndef __PRE_RAM__ +void backup_top_of_ram(uint64_t ramtop) +{ + u32 dword = (u32) ramtop; + int nvram_pos = 0xf8, i; /* temp */ + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif + +unsigned long get_top_of_ram(void) +{ + u32 xdata = 0; + int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (unsigned long) xdata; +} diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 82d51e6..855cbc4 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -721,20 +721,18 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) +int acpi_get_sleep_type(void) { u16 tmp; tmp = inw(ACPI_PM1_CNT_BLK); - printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); - return (((tmp & (7 << 10)) >> 10) == 3); + return ((tmp & (7 << 10)) >> 10); } unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; - if (!acpi_is_wakeup_early()) + if (acpi_get_sleep_type() != 3) return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); @@ -744,6 +742,5 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } -#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 8ebc765..658e954 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -29,7 +29,6 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> -#include <arch/acpi.h> #include <cbmem.h> #include <cpu/amd/powernow.h> #include "sb700.h" @@ -80,19 +79,15 @@ static void lpc_init(device_t dev) #endif pci_write_config8(dev, 0x78, byte); - /* hack, but the whole sb700 startup lacks any device which - is doing the acpi init */ -#if CONFIG_HAVE_ACPI_RESUME - { - u16 tmp = inw(ACPI_PM1_CNT_BLK); - acpi_slp_type = ((tmp & (7 << 10)) >> 10); - printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); - } -#endif - cmos_check_update_date(); } +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + return ((tmp & (7 << 10)) >> 10); +} + void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 2b488d9..24aa200 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -666,20 +666,18 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) +int acpi_get_sleep_type(void) { u16 tmp; tmp = inw(ACPI_PM1_CNT_BLK); - printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); - return (((tmp & (7 << 10)) >> 10) == 3); + return ((tmp & (7 << 10)) >> 10); } unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; - if (!acpi_is_wakeup_early()) + if (acpi_get_sleep_type() != 3) return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); @@ -689,6 +687,5 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } -#endif #endif diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index d236cfa..6341751 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -31,11 +31,6 @@ #include "i82371eb.h" #include "smbus.h" -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -int acpi_get_sleep_type(void); -#endif - static void pwrmgt_enable(struct device *dev) { struct southbridge_intel_i82371eb_config *sb = dev->chip_info; @@ -92,12 +87,6 @@ static void pwrmgt_enable(struct device *dev) outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); -#if CONFIG_HAVE_ACPI_RESUME - /* this reads PMCNTRL, so we have to call it before writing the - * default value */ - acpi_slp_type = acpi_get_sleep_type(); -#endif - /* set PMCNTRL default */ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); } diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index dd4a28f..f9ca385 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -19,12 +19,11 @@ */ #include <stdint.h> +#include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> #include "i82371eb.h" -int acpi_get_sleep_type(void); - /* * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 * diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 7eba967..d41e0df 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -180,11 +180,9 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME unsigned long get_top_of_ram(void) { - if (!acpi_is_wakeup_early()) + if (acpi_get_sleep_type() != 3) return 0; return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } -#endif diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index bb06322..b766bd7 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -330,8 +330,7 @@ void enable_rom_decode(void) pci_write_config8(dev, 0x41, 0x7f); } -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) +int acpi_get_sleep_type(void) { device_t dev; u16 tmp; @@ -354,7 +353,6 @@ int acpi_is_wakeup_early(void) printk(BIOS_DEBUG, "%02x", tmp); return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; } -#endif #if defined(__GNUC__) void vt8237_early_spi_init(void) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 92eaa39..d3e3d32 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -244,10 +244,6 @@ static void setup_pm(device_t dev) /* SCI is generated for RTC/pwrBtn/slpBtn. */ tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; - printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); -#endif /* All SMI on, both IDE buses ON, PSON rising edge. */ outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c); @@ -258,6 +254,12 @@ static void setup_pm(device_t dev) outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); } +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; +} + static void vt8237r_init(struct device *dev) { u8 enables;

1 0

Patch set updated for coreboot: 97beda7 AMD binaryPI: Drop ramtop via nvram
by Kyösti Mälkki 10 Jan '15

10 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8185 -gerrit commit 97beda77f04c45f8694bbc077ec9cc854b0c2583 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 10 07:25:15 2015 +0200 AMD binaryPI: Drop ramtop via nvram If HAVE_ACPI_RESUME gets implemented, EARLY_CBMEM_INIT is required too. Change-Id: I8c7932297e0938eff629d1e46081ccf3e7690aea Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/pi/avalon/early_setup.c | 30 -------------------------- src/southbridge/amd/pi/avalon/hudson.c | 33 ----------------------------- 2 files changed, 63 deletions(-) diff --git a/src/southbridge/amd/pi/avalon/early_setup.c b/src/southbridge/amd/pi/avalon/early_setup.c index 039df20..9500d0e 100644 --- a/src/southbridge/amd/pi/avalon/early_setup.c +++ b/src/southbridge/amd/pi/avalon/early_setup.c @@ -123,34 +123,4 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ - return (int)tmp; -} -#endif - -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) -{ - return (acpi_get_sleep_type() == 3); -} -#endif - -unsigned long get_top_of_ram(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} - #endif diff --git a/src/southbridge/amd/pi/avalon/hudson.c b/src/southbridge/amd/pi/avalon/hudson.c index 84eaf30..3c07ed2 100644 --- a/src/southbridge/amd/pi/avalon/hudson.c +++ b/src/southbridge/amd/pi/avalon/hudson.c @@ -38,28 +38,12 @@ #define PM_MMIO_BASE 0xfed80300 -#if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void) { u16 tmp = inw(ACPI_PM1_CNT_BLK); tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ return (int)tmp; } -#endif - -void backup_top_of_ram(uint64_t ramtop) -{ - u32 dword = (u32) ramtop; - int nvram_pos = 0xf8, i; /* temp */ - /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ - for (i = 0; i<4; i++) { - /* printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); */ - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); - nvram_pos++; - } -} void pm_write8(u8 reg, u8 value) { @@ -113,23 +97,6 @@ void hudson_enable(device_t dev) } } -#if CONFIG_HAVE_ACPI_RESUME -unsigned long get_top_of_ram(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - if (acpi_get_sleep_type() != 3) - return 0; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} -#endif - static void hudson_init_acpi_ports(void) { /* We use some of these ports in SMM regardless of whether or not

1 0

Patch merged into coreboot/master: 1682b8d macbook21: Add CST entries
by gerrit＠coreboot.org 10 Jan '15

10 Jan '15

the following patch was just integrated into master: commit 1682b8d97a451b1ef96033a62f45b8196aa63715 Author: Axel Holewa <mono(a)posteo.de> Date: Thu Dec 25 08:11:54 2014 +0100 macbook21: Add CST entries Due to the CST entries the machine uses less power running GNU/Linux-libre. This can be seen by monitoring CPU temperature and time left the machine can run on battery. CPU temperature measurements have been done with lm_sensors, battery querying with acpi. Tests have been done before applying this patch and after. In both cases the battery was fully loaded and the machine powered up on battery, without AC. In both tests the machine was idleing for more than 1 hour. Without this patch battery was predicted to last 01:52:30 hours, CPU temperature first measurement showed 38 degrees. After 15 min idle, temperature has reached its maximum value in this test of 61 and 62 degrees (Core 0 and 1). Fan speed begins to increase shortly after 15 min. From its minimal value 1800 rpm it reaches 3100 rpm after 40 min. CPU temperature did not increase any further. After 60 min idle, the battery was predicted to still last 57 min. With this patch battery was predicted to last 02:22:40 hours. That is plus 30 min. CPU temperature begins at 35 degrees. After 15 min temperature has reached 45 degrees; after 30 min it has reached the maximal temperature during this test of about 50 degrees. That is 10 degrees improvement. The fan stayed at minimal speed. After 60 min idle, the battery was predicted to still last 01:22:48 hours; a 25 minute improvement. Change-Id: I6b2173df1dc09300329b61b51b79f4b9f4a8fb13 Signed-off-by: Axel Holewa <mono(a)posteo.de> Reviewed-on: http://review.coreboot.org/7923 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/7923 for details. -gerrit

1 0

Patch set updated for coreboot: 9aed9d7 x86 SMM: Replace weak prototypes with weak function stub
by Kyösti Mälkki 10 Jan '15

10 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7961 -gerrit commit 9aed9d7ef4ccdc4a54c03ffa8f7a0d2414264a91 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 26 10:21:26 2014 +0200 x86 SMM: Replace weak prototypes with weak function stub Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/smm/smihandler.c | 21 +++++++++++++++------ src/include/cpu/x86/smm.h | 16 ++++++---------- src/southbridge/amd/agesa/hudson/smihandler.c | 6 ++---- src/southbridge/amd/pi/avalon/smihandler.c | 6 ++---- src/southbridge/intel/bd82x6x/smihandler.c | 16 ++++++---------- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 16 ++++++---------- src/southbridge/intel/i82801dx/smihandler.c | 10 ++++------ src/southbridge/intel/i82801gx/smihandler.c | 12 +++++------- src/southbridge/intel/i82801ix/smihandler.c | 12 +++++------- src/southbridge/intel/ibexpeak/smihandler.c | 16 ++++++---------- 10 files changed, 57 insertions(+), 74 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index bd03030..cbd6d44 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -199,12 +199,9 @@ void smi_handler(u32 smm_revision) } /* Call chipset specific SMI handlers. */ - if (cpu_smi_handler) - cpu_smi_handler(node, &state_save); - if (northbridge_smi_handler) - northbridge_smi_handler(node, &state_save); - if (southbridge_smi_handler) - southbridge_smi_handler(node, &state_save); + cpu_smi_handler(node, &state_save); + northbridge_smi_handler(node, &state_save); + southbridge_smi_handler(node, &state_save); smi_restore_pci_address(); @@ -215,3 +212,15 @@ void smi_handler(u32 smm_revision) /* De-assert SMI# signal to allow another SMI */ smi_set_eos(); } + +/* Provide a default implementation for all weak handlers so that relocation + * entries in the modules make sense. Without default implementations the + * weak relocations w/o a symbol have a 0 address which is where the modules + * are linked at. */ +int __attribute__((weak)) mainboard_io_trap_handler(int smif) { return 0; } +void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) {} +void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts) {} +int __attribute__((weak)) mainboard_smi_apmc(u8 data) { return 0; } +void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ) {} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 7b529e0..c16a6c5 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -467,7 +467,7 @@ void smi_handler(u32 smm_revision); void io_trap_handler(int smif); int southbridge_io_trap_handler(int smif); -int __attribute__((weak)) mainboard_io_trap_handler(int smif); +int mainboard_io_trap_handler(int smif); void southbridge_smi_set_eos(void); @@ -475,18 +475,14 @@ void southbridge_smi_set_eos(void); void cpu_smi_handler(void); void northbridge_smi_handler(void); void southbridge_smi_handler(void); +#else +void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +#endif /* CONFIG_SMM_MODULES */ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); void mainboard_smi_sleep(u8 slp_typ); -#else -void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); - -void __attribute__((weak)) mainboard_smi_gpi(u32 gpi_sts); -int __attribute__((weak)) mainboard_smi_apmc(u8 data); -void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ); -#endif /* CONFIG_SMM_MODULES */ #if !CONFIG_SMM_TSEG void smi_release_lock(void); diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index d1b661b..af8c215 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -41,8 +41,7 @@ static void hudson_apmc_smi_handler(void) break; } - if (mainboard_smi_apmc) - mainboard_smi_apmc(cmd); + mainboard_smi_apmc(cmd); } int southbridge_io_trap_handler(int smif) @@ -66,8 +65,7 @@ static void process_gpe_smi(void) /* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { /* A GEVENT SMI occurred */ - if (mainboard_smi_gpi) - mainboard_smi_gpi(status & gevent_mask); + mainboard_smi_gpi(status & gevent_mask); } /* Clear events to prevent re-entering SMI if event isn't handled */ diff --git a/src/southbridge/amd/pi/avalon/smihandler.c b/src/southbridge/amd/pi/avalon/smihandler.c index e762d0b..6f2504b 100644 --- a/src/southbridge/amd/pi/avalon/smihandler.c +++ b/src/southbridge/amd/pi/avalon/smihandler.c @@ -41,8 +41,7 @@ static void hudson_apmc_smi_handler(void) break; } - if (mainboard_smi_apmc) - mainboard_smi_apmc(cmd); + mainboard_smi_apmc(cmd); } int southbridge_io_trap_handler(int smif) @@ -66,8 +65,7 @@ static void process_gpe_smi(void) /* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { /* A GEVENT SMI occured */ - if (mainboard_smi_gpi) - mainboard_smi_gpi(status & gevent_mask); + mainboard_smi_gpi(status & gevent_mask); } /* Clear events to prevent re-entering SMI if event isn't handled */ diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 45612d0..f69c1f4 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -419,8 +419,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -607,8 +606,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -650,12 +648,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); } diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index c98e267..8164e7e 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -353,8 +353,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -541,8 +540,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -584,12 +582,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); } diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index e5a3282..6375876 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -441,12 +441,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index e2505ce..e83c722 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -369,7 +369,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); - if (mainboard_smi_apmc && mainboard_smi_apmc(reg8)) + if (mainboard_smi_apmc(reg8)) return; switch (reg8) { @@ -454,12 +454,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 45a09df..611429f 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -235,7 +235,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); - if (mainboard_smi_apmc && mainboard_smi_apmc(reg8)) + if (mainboard_smi_apmc(reg8)) return; switch (reg8) { @@ -322,12 +322,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (mainboard_smi_gpi) { - mainboard_smi_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_smi_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e2032ad..019e6db 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -419,8 +419,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); - if (mainboard_sleep) - mainboard_sleep(slp_typ-2); + mainboard_sleep(slp_typ-2); #if CONFIG_ELOG_GSMI /* Log S3, S4, and S5 entry */ @@ -607,8 +606,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state } tseg_relocate((void **)&mainboard_apmc); - if (mainboard_apmc) - mainboard_apmc(reg8); + mainboard_apmc(reg8); } static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) @@ -650,12 +648,10 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ reg16 &= inw(pmbase + ALT_GP_SMI_EN); tseg_relocate((void **)&mainboard_gpi); - if (mainboard_gpi) { - mainboard_gpi(reg16); - } else { - if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); - } + mainboard_gpi(reg16); + + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); outw(reg16, pmbase + ALT_GP_SMI_STS); }

1 0

New patch to review for coreboot: 221b966 ACPI: Get S3 resume state from romstage_handoff
by Kyösti Mälkki 09 Jan '15

09 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8188 -gerrit commit 221b9661d750ebdef4ed753865b83d1023779ea0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 ACPI: Get S3 resume state from romstage_handoff There is nothing platform specific in retrieving S3 resume state from handoff structure. Boards without EARLY_CBMEM_INIT update acpi_slp_type from ACPI power-management block or scratchpad registers. Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 20 +++++++++++++++++-- src/northbridge/intel/haswell/northbridge.c | 22 --------------------- src/soc/intel/baytrail/ramstage.c | 25 +++++------------------- src/soc/intel/baytrail/southcluster.c | 3 +-- src/soc/intel/baytrail/xhci.c | 4 ++-- src/soc/intel/broadwell/lpc.c | 4 ++-- src/soc/intel/broadwell/me.c | 4 +--- src/soc/intel/broadwell/ramstage.c | 30 ++++++++--------------------- src/soc/intel/broadwell/refcode.c | 11 +---------- src/soc/intel/broadwell/systemagent.c | 23 ---------------------- src/soc/intel/fsp_baytrail/ramstage.c | 22 +++------------------ src/soc/intel/fsp_baytrail/southcluster.c | 1 - 12 files changed, 41 insertions(+), 128 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 621df2f..777053e 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -36,6 +36,7 @@ #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif +#include <romstage_handoff.h> /* FIXME: Kconfig doesn't support overridable defaults :-( */ #ifndef CONFIG_HPET_MIN_TICKS @@ -857,10 +858,25 @@ void acpi_resume(void *wake_vec) /* This is filled with acpi_is_wakeup() call early in ramstage. */ int acpi_slp_type = -1; -int __attribute__((weak)) acpi_get_sleep_type(void) +#if CONFIG_EARLY_CBMEM_INIT +int acpi_get_sleep_type(void) { - return 0; + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } } +#endif static void acpi_handoff_wakeup(void) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..7eb9f08 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -35,7 +35,6 @@ #include <cpu/x86/smm.h> #include <boot/tables.h> #include <cbmem.h> -#include <romstage_handoff.h> #include "chip.h" #include "haswell.h" @@ -433,26 +432,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -462,7 +441,6 @@ static struct device_operations mc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..970f9e4 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -27,7 +27,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <romstage_handoff.h> #include <stdlib.h> #include <baytrail/gpio.h> @@ -130,13 +129,6 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) { @@ -166,22 +158,15 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 5274b03..20cbbcf 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -29,7 +29,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> -#include <romstage_handoff.h> #include <drivers/uart/uart8250reg.h> #include <baytrail/iomap.h> @@ -215,7 +214,7 @@ static void sc_init(device_t dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) com1_configure_resume(dev); } diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..19339e4 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -184,7 +184,7 @@ static void xhci_route_all(device_t dev) /* Route ports to XHCI controller */ reg_script_run_on_dev(dev, xhci_route_all_script); - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) return; /* Reset enabled USB3 ports */ @@ -222,7 +222,7 @@ static void xhci_init(device_t dev) }; /* Initialize XHCI controller for boot or resume path */ - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 394a9d7..c670440 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -394,7 +394,7 @@ static void pch_cg_init(device_t dev) static void pch_set_acpi_mode(void) { #if CONFIG_HAVE_SMI_HANDLER - if (acpi_slp_type != 3) { + if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); @@ -551,7 +551,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (acpi_slp_type != 3 && gnvs) + if (!acpi_is_wakeup_s3() && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); } diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 2bdb1ed..9fc6a41 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -830,13 +830,11 @@ static void intel_me_init(device_t dev) static void intel_me_enable(device_t dev) { -#if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { dev->enabled = 0; pch_disable_devfn(dev); } -#endif } static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 0563064..1253d20 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -21,7 +21,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/device.h> -#include <romstage_handoff.h> #include <stdlib.h> #include <broadwell/nvs.h> #include <broadwell/pm.h> @@ -54,31 +53,18 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) gnvs->pm1i); } -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - static void s3_resume_prepare(void) { - global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; + global_nvs_t *gnvs; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); - return; - } + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + if (gnvs == NULL) + return; - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void broadwell_init_pre_device(void *chip_info) diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index a745101..d66d036 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -30,15 +30,6 @@ #include <broadwell/pei_wrapper.h> #include <broadwell/ramstage.h> -static inline int is_s3_resume(void) -{ -#if CONFIG_HAVE_ACPI_RESUME - return acpi_slp_type == 3; -#else - return 0; -#endif -} - static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) { return (struct ramstage_cache *)&c->program[c->size]; @@ -136,7 +127,7 @@ static pei_wrapper_entry_t load_reference_code(void) }; int ret; - if (is_s3_resume()) { + if (acpi_is_wakeup_s3()) { return load_refcode_from_cache(); } diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 74c43f2..ac021fb 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -29,7 +29,6 @@ #include <stdlib.h> #include <string.h> #include <cbmem.h> -#include <romstage_handoff.h> #include <vendorcode/google/chromeos/chromeos.h> #include <broadwell/cpu.h> #include <broadwell/iomap.h> @@ -412,27 +411,6 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -451,7 +429,6 @@ static struct device_operations systemagent_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &systemagent_init, - .enable = &systemagent_enable, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..4b1b753 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -26,7 +26,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <romstage_handoff.h> #include <stdlib.h> #include <baytrail/gpio.h> @@ -125,31 +124,16 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } - -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - set_acpi_sleep_type(3); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); } void baytrail_init_pre_device(void) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index d87935b..9b1e42e 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -33,7 +33,6 @@ #include <pc80/i8254.h> #include <pc80/i8259.h> #include <pc80/isa-dma.h> -#include <romstage_handoff.h> #include <baytrail/baytrail.h> #include <baytrail/iomap.h>

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New patch to review for coreboot: ce28a5e ACPI: Add acpi_is_wakeup_s3() for romstage
by Kyösti Mälkki 09 Jan '15

09 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8187 -gerrit commit ce28a5ed62281e5625ec4791f230866d84b24beb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 9 23:48:47 2015 +0200 ACPI: Add acpi_is_wakeup_s3() for romstage This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/acpi.h | 11 ++++- src/cpu/amd/agesa/heapmanager.c | 6 +-- src/cpu/amd/car/post_cache_as_ram.c | 8 +--- src/mainboard/amd/olivehill/romstage.c | 2 +- src/mainboard/amd/olivehillplus/romstage.c | 2 +- src/mainboard/amd/parmer/romstage.c | 2 +- src/mainboard/amd/persimmon/romstage.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 2 +- src/mainboard/asrock/imb-a180/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/gizmosphere/gizmo/romstage.c | 2 +- src/mainboard/gizmosphere/gizmo2/romstage.c | 2 +- src/mainboard/hp/abm/romstage.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 +- src/mainboard/lenovo/g505s/romstage.c | 2 +- src/mainboard/lippert/frontrunner-af/romstage.c | 2 +- src/mainboard/lippert/toucan-af/romstage.c | 2 +- src/northbridge/amd/amdk8/raminit.c | 6 +-- src/northbridge/amd/amdk8/raminit_f.c | 6 +-- src/southbridge/amd/agesa/hudson/Makefile.inc | 4 +- src/southbridge/amd/agesa/hudson/early_setup.c | 28 ------------ src/southbridge/amd/agesa/hudson/hudson.c | 40 ----------------- src/southbridge/amd/agesa/hudson/ramtop.c | 59 +++++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/Makefile.inc | 3 ++ src/southbridge/amd/cimx/sb800/cfg.c | 47 +------------------- src/southbridge/amd/cimx/sb800/early.c | 8 ---- src/southbridge/amd/cimx/sb800/ramtop.c | 59 +++++++++++++++++++++++++ src/southbridge/amd/sb700/early_setup.c | 9 ++-- src/southbridge/amd/sb700/lpc.c | 17 +++---- src/southbridge/amd/sb800/early_setup.c | 9 ++-- src/southbridge/intel/i82371eb/smbus.c | 11 ----- src/southbridge/intel/i82371eb/wakeup.c | 3 +- src/southbridge/via/k8t890/early_car.c | 4 +- src/southbridge/via/vt8237r/early_smbus.c | 4 +- src/southbridge/via/vt8237r/lpc.c | 10 +++-- 36 files changed, 176 insertions(+), 206 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index c497082..771b51c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -581,14 +581,21 @@ static inline int acpi_s3_resume_allowed(void) #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) extern int acpi_slp_type; + +#ifdef __PRE_RAM__ +static inline int acpi_is_wakeup_s3(void) +{ + return (acpi_get_sleep_type() == 3); +} +#else int acpi_is_wakeup(void); int acpi_is_wakeup_s3(void); -int acpi_is_wakeup_early(void); +#endif + #else #define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } -static inline int acpi_is_wakeup_early(void) { return 0; } #endif #endif /* __ASM_ACPI_H */ diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index 50ec3ff..cc53d35 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -12,13 +12,11 @@ UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) { UINT32 heap = BIOS_HEAP_START_ADDRESS; -#if CONFIG_HAVE_ACPI_RESUME - /* Both romstage and ramstage has this S3 detect. */ - if (acpi_get_sleep_type() == 3) + if (acpi_is_wakeup_s3()) heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */ -#endif + return heap; } diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 8bc5cd3..6c32090 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -101,12 +101,10 @@ void post_cache_as_ram(void) { void *resume_backup_memory = NULL; - int s3resume = acpi_s3_resume_allowed() && acpi_is_wakeup_early(); + int s3resume = acpi_is_wakeup_s3(); if (s3resume) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) cbmem_recovery(s3resume); resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); -#endif } prepare_romstage_ramstack(resume_backup_memory); @@ -141,10 +139,8 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - if (acpi_s3_resume_allowed() && acpi_is_wakeup_early()) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + if (acpi_is_wakeup_s3()) { resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); -#endif } prepare_ramstage_region(resume_backup_memory); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 2262782..8286f0b 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 6fa3af6..63044ed 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -90,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); AGESAWRAPPER(amdinitpost); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 1fb709a..1d25736 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -71,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 2fdab41..bff9e14 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -86,7 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 30808a4..27d9680 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -85,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index efeed35..cb6d07a 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 95298d1..2332b4a 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index f420bf2..527ad26 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index 2262782..8286f0b 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 5e3044a..a55ec02 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index bc92e6d..87fcd4c 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -63,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 197c81d..c3ca947 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index bc92e6d..87fcd4c 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -63,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 0f718f2..cc03053 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -85,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 415cdbe..7a8e916 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -86,7 +86,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 19f83b9..4213cfb 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2349,11 +2349,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; u32 whatWait = 0; -#if CONFIG_HAVE_ACPI_RESUME - int suspend = acpi_is_wakeup_early(); -#else - int suspend = 0; -#endif + int suspend = acpi_is_wakeup_s3(); /* Error if I don't have memory */ if (memory_end_k(ctrl, controllers) == 0) { diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index b8417a6..ed889e4 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -3017,11 +3017,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int i; -#if CONFIG_HAVE_ACPI_RESUME - int suspend = acpi_is_wakeup_early(); -#else - int suspend = 0; -#endif + int suspend = acpi_is_wakeup_s3(); #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 unsigned cpu_f0_f1[8]; diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 84f0d3e..bcadd8d 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -19,7 +19,9 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-y += resume.c +ramstage-y += resume.c ramtop.c + +romstage-y += ramtop.c romstage-y += imc.c ramstage-y += imc.c diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 1b9b689..3816141 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -123,32 +123,4 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ - return (int)tmp; -} - -int acpi_is_wakeup_early(void) -{ - return (acpi_get_sleep_type() == 3); -} -#endif /* CONFIG_HAVE_ACPI_RESUME */ - -unsigned long get_top_of_ram(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} - #endif /* _HUDSON_EARLY_SETUP_C_ */ diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index be8aa69..fd2c268 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -38,30 +38,6 @@ */ #define PM_MMIO_BASE 0xfed80300 - -#if CONFIG_HAVE_ACPI_RESUME -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ - return (int)tmp; -} -#endif - -void backup_top_of_ram(uint64_t ramtop) -{ - u32 dword = (u32) ramtop; - int nvram_pos = 0xf8, i; /* temp */ - /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ - for (i = 0; i<4; i++) { - /* printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); */ - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); - nvram_pos++; - } -} - void pm_write8(u8 reg, u8 value) { write8(PM_MMIO_BASE + reg, value); @@ -160,22 +136,6 @@ void hudson_enable(device_t dev) } } -#if CONFIG_HAVE_ACPI_RESUME -unsigned long get_top_of_ram(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - if (acpi_get_sleep_type() != 3) - return 0; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} -#endif static void hudson_init_acpi_ports(void) { diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c new file mode 100644 index 0000000..182150f --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/ramtop.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include "hudson.h" + +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + tmp = ((tmp & (7 << 10)) >> 10); + return (int)tmp; +} + +#ifndef __PRE_RAM__ +void backup_top_of_ram(uint64_t ramtop) +{ + u32 dword = (u32) ramtop; + int nvram_pos = 0xf8, i; /* temp */ + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif + +unsigned long get_top_of_ram(void) +{ + uint32_t xdata = 0; + int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (unsigned long) xdata; +} diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index f4a84b7..ca3d86a 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -34,6 +34,9 @@ ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c + romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 9ddcf8f..ac6e6ae 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -26,48 +26,6 @@ #include <arch/io.h> #include <arch/acpi.h> -#if CONFIG_HAVE_ACPI_RESUME -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(PM1_CNT_BLK_ADDRESS); - tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ - return (int)tmp; -} -#endif - -#ifndef __PRE_RAM__ -void backup_top_of_ram(uint64_t ramtop) -{ - u32 dword = (u32) ramtop; - int nvram_pos = 0xf8, i; /* temp */ - printk(BIOS_DEBUG, "dword=%x\n", dword); - for (i = 0; i<4; i++) { - printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); - nvram_pos++; - } -} -#endif - -#if CONFIG_HAVE_ACPI_RESUME -unsigned long get_top_of_ram(void) -{ - u32 xdata = 0; - int xnvram_pos = 0xf8, xi; - if (acpi_get_sleep_type() != 3) - return 0; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} -#endif - /** * @brief South Bridge CIMx configuration * @@ -80,10 +38,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) if (!sb_config) return; -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_get_sleep_type() == 3) - sb_config->S3Resume = 1; -#endif + sb_config->S3Resume = acpi_is_wakeup_s3(); /* header */ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 7492f99..34375c5 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <device/pci_ids.h> #include <arch/io.h> /* inl, outl */ -#include <arch/acpi.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ @@ -74,10 +73,3 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } - -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) -{ - return (acpi_get_sleep_type() == 3); -} -#endif diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c new file mode 100644 index 0000000..7e9abae --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include "SBPLATFORM.h" + +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(PM1_CNT_BLK_ADDRESS); + tmp = ((tmp & (7 << 10)) >> 10); + return (int)tmp; +} + +#ifndef __PRE_RAM__ +void backup_top_of_ram(uint64_t ramtop) +{ + u32 dword = (u32) ramtop; + int nvram_pos = 0xf8, i; /* temp */ + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif + +unsigned long get_top_of_ram(void) +{ + u32 xdata = 0; + int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (unsigned long) xdata; +} diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 82d51e6..855cbc4 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -721,20 +721,18 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) +int acpi_get_sleep_type(void) { u16 tmp; tmp = inw(ACPI_PM1_CNT_BLK); - printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); - return (((tmp & (7 << 10)) >> 10) == 3); + return ((tmp & (7 << 10)) >> 10); } unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; - if (!acpi_is_wakeup_early()) + if (acpi_get_sleep_type() != 3) return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); @@ -744,6 +742,5 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } -#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 8ebc765..658e954 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -29,7 +29,6 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> -#include <arch/acpi.h> #include <cbmem.h> #include <cpu/amd/powernow.h> #include "sb700.h" @@ -80,19 +79,15 @@ static void lpc_init(device_t dev) #endif pci_write_config8(dev, 0x78, byte); - /* hack, but the whole sb700 startup lacks any device which - is doing the acpi init */ -#if CONFIG_HAVE_ACPI_RESUME - { - u16 tmp = inw(ACPI_PM1_CNT_BLK); - acpi_slp_type = ((tmp & (7 << 10)) >> 10); - printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); - } -#endif - cmos_check_update_date(); } +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + return ((tmp & (7 << 10)) >> 10); +} + void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 2b488d9..24aa200 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -666,20 +666,18 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) +int acpi_get_sleep_type(void) { u16 tmp; tmp = inw(ACPI_PM1_CNT_BLK); - printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); - return (((tmp & (7 << 10)) >> 10) == 3); + return ((tmp & (7 << 10)) >> 10); } unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; - if (!acpi_is_wakeup_early()) + if (acpi_get_sleep_type() != 3) return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); @@ -689,6 +687,5 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } -#endif #endif diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index d236cfa..6341751 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -31,11 +31,6 @@ #include "i82371eb.h" #include "smbus.h" -#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -int acpi_get_sleep_type(void); -#endif - static void pwrmgt_enable(struct device *dev) { struct southbridge_intel_i82371eb_config *sb = dev->chip_info; @@ -92,12 +87,6 @@ static void pwrmgt_enable(struct device *dev) outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); -#if CONFIG_HAVE_ACPI_RESUME - /* this reads PMCNTRL, so we have to call it before writing the - * default value */ - acpi_slp_type = acpi_get_sleep_type(); -#endif - /* set PMCNTRL default */ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); } diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index dd4a28f..f9ca385 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -19,12 +19,11 @@ */ #include <stdint.h> +#include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> #include "i82371eb.h" -int acpi_get_sleep_type(void); - /* * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 * diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 7eba967..d41e0df 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -180,11 +180,9 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME unsigned long get_top_of_ram(void) { - if (!acpi_is_wakeup_early()) + if (acpi_get_sleep_type() != 3) return 0; return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } -#endif diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index bb06322..b766bd7 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -330,8 +330,7 @@ void enable_rom_decode(void) pci_write_config8(dev, 0x41, 0x7f); } -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) +int acpi_get_sleep_type(void) { device_t dev; u16 tmp; @@ -354,7 +353,6 @@ int acpi_is_wakeup_early(void) printk(BIOS_DEBUG, "%02x", tmp); return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; } -#endif #if defined(__GNUC__) void vt8237_early_spi_init(void) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 92eaa39..d3e3d32 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -244,10 +244,6 @@ static void setup_pm(device_t dev) /* SCI is generated for RTC/pwrBtn/slpBtn. */ tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; - printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); -#endif /* All SMI on, both IDE buses ON, PSON rising edge. */ outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c); @@ -258,6 +254,12 @@ static void setup_pm(device_t dev) outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); } +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; +} + static void vt8237r_init(struct device *dev) { u8 enables;

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coreboot-gerrit January 2015