coreboot-gerrit January 2015

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New patch to review for coreboot: 77c6cc8 cbfs: add cbfs_locate_file()
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8180 -gerrit commit 77c6cc87cc9ac279c22da9f1276075418ff50c22 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 27 15:06:02 2014 -0500 cbfs: add cbfs_locate_file() cbfs_locate_file() can be used to locate the data within the cbfs file. Based on the offset and length of the file it can then be read into any address without bringing the contents into another buffer (platforms without memory-mapped access to entire contents of cbfs at once). BUG=chrome-os-partner:29922 BRANCH=None TEST=Built and booted rush into romstage (stage load still works). Original-Change-Id: I2932f66478c74511ec1c876b09794d9a22a526b3 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206000 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 56c958facd379ca0eeebe1b689e3b80d5e692699) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0c4964132af615a069258c0eb37153bd84fbbfae --- src/include/cbfs_core.h | 7 ++++ src/lib/cbfs_core.c | 88 +++++++++++++++++++++++++++++++++---------------- 2 files changed, 66 insertions(+), 29 deletions(-) diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index e74d618..3cef903 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -217,6 +217,13 @@ struct cbfs_media { int (*close)(struct cbfs_media *media); }; +/* + * Locate file by name and fill in cbfs_file in host byte order. Returns + * < 0 on error, else the offset of the file data. + */ +ssize_t cbfs_locate_file(struct cbfs_media *media, struct cbfs_file *file, + const char *name); + /* returns pointer to a file entry inside CBFS or NULL */ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 0f97755..24e5998 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -93,25 +93,33 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) return header; } + +static int init_media(struct cbfs_media **media, struct cbfs_media *backing) +{ + if (*media == CBFS_DEFAULT_MEDIA) { + *media = backing; + if (init_default_cbfs_media(*media) != 0) { + ERROR("Failed to initialize default media.\n"); + return -1; + } + } + return 0; +} + /* public API starts here*/ -struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) +ssize_t cbfs_locate_file(struct cbfs_media *media, struct cbfs_file *file, + const char *name) { const char *file_name; uint32_t offset, align, romsize, name_len; const struct cbfs_header *header; - struct cbfs_file file, *file_ptr; struct cbfs_media default_media; - if (media == CBFS_DEFAULT_MEDIA) { - media = &default_media; - if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initialize default media.\n"); - return NULL; - } - } + if (init_media(&media, &default_media)) + return -1; if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media))) - return NULL; + return -1; // Logical offset (for source media) of first file. offset = ntohl(header->offset); @@ -139,9 +147,9 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) media->open(media); while (offset < romsize && - media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { - if (memcmp(CBFS_FILE_MAGIC, file.magic, - sizeof(file.magic)) != 0) { + media->read(media, file, offset, sizeof(*file)) == sizeof(*file)) { + if (memcmp(CBFS_FILE_MAGIC, file->magic, + sizeof(file->magic)) != 0) { uint32_t new_align = align; if (offset % align) new_align += align - (offset % align); @@ -151,30 +159,25 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) offset += new_align; continue; } - name_len = ntohl(file.offset) - sizeof(file); + + file->len = ntohl(file->len); + file->type= ntohl(file->type); + file->offset = ntohl(file->offset); + + name_len = file->offset - sizeof(*file); DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset, name_len); // load file name (arbitrary length). file_name = (const char *)media->map( - media, offset + sizeof(file), name_len); + media, offset + sizeof(*file), name_len); if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); } else if (strcmp(file_name, name) == 0) { - int file_offset = ntohl(file.offset), - file_len = ntohl(file.len); DEBUG("Found file (offset=0x%x, len=%d).\n", - offset + file_offset, file_len); + offset + file->offset, file->len); media->unmap(media, file_name); - file_ptr = media->map(media, offset, - file_offset + file_len); - media->close(media); - if (file_ptr == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("ERROR: Mapping %s failed (insufficient " - "buffer space?).\n", file_name); - return NULL; - } - return file_ptr; + return offset + file->offset; } else { DEBUG(" (unmatched file @0x%x: %s)\n", offset, file_name); @@ -182,13 +185,40 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) } // Move to next file. - offset += ntohl(file.len) + ntohl(file.offset); + offset += file->len + file->offset; if (offset % align) offset += align - (offset % align); } media->close(media); LOG("WARNING: '%s' not found.\n", name); - return NULL; + return -1; +} + +struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) +{ + struct cbfs_media default_media; + struct cbfs_file file, *file_ptr; + ssize_t offset; + + if (init_media(&media, &default_media)) + return NULL; + + offset = cbfs_locate_file(media, &file, name); + if (offset < 0) + return NULL; + + /* Map both the metadata and the file contents. */ + media->open(media); + offset -= file.offset; + file_ptr = media->map(media, offset, file.offset + file.len); + media->close(media); + + if (file_ptr == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + ERROR("ERROR: Mapping %s failed.\n", name); + return NULL; + } + + return file_ptr; } void *cbfs_get_file_content(struct cbfs_media *media, const char *name,

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New patch to review for coreboot: 8868433 cbfstool: Remove arch check for different stages
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8179 -gerrit commit 886843372eb64a40b268b57fefe59cbf1f23cf27 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 25 17:50:28 2014 -0700 cbfstool: Remove arch check for different stages Remove the arch check for each stage as the arch for different stages can be different based on the SoC. e.g.: Rush has arm32-based romstage whereas arm64-based ramstage BUG=None BRANCH=None TEST=Compiles succesfully for nyan, link and rush Original-Change-Id: I561dab5a5d87c6b93b8d667857d5e181ff72e35d Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205761 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 6a6a87b65fcab5a7e8163258c7e8d704fa8d97c3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ic412d60d8a72dac4f9807cae5d8c89499a157f96 --- util/cbfstool/elfheaders.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c index bee44d8..98a06c5 100644 --- a/util/cbfstool/elfheaders.c +++ b/util/cbfstool/elfheaders.c @@ -608,16 +608,6 @@ elf_headers(const struct buffer *pinput, /* Copy out the parsed elf header. */ memcpy(ehdr, &pelf.ehdr, sizeof(*ehdr)); - // The tool may work in architecture-independent way. - if (arch != CBFS_ARCHITECTURE_UNKNOWN && - !((ehdr->e_machine == EM_AARCH64) && (arch == CBFS_ARCHITECTURE_AARCH64)) && - !((ehdr->e_machine == EM_ARM) && (arch == CBFS_ARCHITECTURE_ARM)) && - !((ehdr->e_machine == EM_RISCV) && (arch == CBFS_ARCHITECTURE_RISCV)) && - !((ehdr->e_machine == EM_386) && (arch == CBFS_ARCHITECTURE_X86))) { - ERROR("The stage file has the wrong architecture\n"); - return -1; - } - *pphdr = calloc(ehdr->e_phnum, sizeof(Elf64_Phdr)); memcpy(*pphdr, pelf.phdr, ehdr->e_phnum * sizeof(Elf64_Phdr));

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Patch set updated for coreboot: 76937aa nyan*: I2C: Fix bus clear BC_TERMINATE naming.
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8152 -gerrit commit 76937aa70fd4ebae446768e5bf097dd1c8b38d18 Author: Tom Warren <twarren(a)nvidia.com> Date: Wed Jul 2 09:25:35 2014 -0700 nyan*: I2C: Fix bus clear BC_TERMINATE naming. In the original fix for the 'Lost arb' we were seeing on Nyan* during reboot stress testing, I had the name of BC_TERMINATE's bit setting wrong. Fix this to use the IMMEDIATE (1) setting. The setting didn't change, just the name. According to Julius this is the optimal setting for bus clear in this instance. Also widened the SCLK_THRESHOLD mask to 8 bits as per spec. BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Tested on nyan. Built for nyan and nyan_big. Original-Change-Id: I19588690924b83431d9f4d3d2eb64f4947849a33 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206409 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 76e08d0cb0fb87e2c75d3086930f272b645ecf4e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If187ddf53660feaceab96efe44a3aadad60c43ff --- src/soc/nvidia/tegra/i2c.c | 4 ++-- src/soc/nvidia/tegra/i2c.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 542d4f0..6f9142c 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -37,9 +37,9 @@ static void do_bus_clear(int bus) // 1. Reset the I2C controller (already done) // 2. Set the # of clock pulses required (using default of 9) // 3. Select STOP condition (using default of 1 = STOP) - // 4. Set TERMINATE condition (1 = THRESHOLD) + // 4. Set TERMINATE condition (1 = IMMEDIATE) bc = read32(&regs->bus_clear_config); - bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_THRESHOLD; + bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE; write32(bc, &regs->bus_clear_config); // 4.1 Set MSTR_CONFIG_LOAD and wait for clear write32(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load); diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h index 4b1bddd..9d7de14 100644 --- a/src/soc/nvidia/tegra/i2c.h +++ b/src/soc/nvidia/tegra/i2c.h @@ -115,9 +115,9 @@ enum { enum { I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT = 16, I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_MASK = - 0x7f << I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT, + 0xff << I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT, I2C_BUS_CLEAR_CONFIG_BC_STOP_COND_STOP = 0x1 << 2, - I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_THRESHOLD = 0x1 << 1, + I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE = 0x1 << 1, I2C_BUS_CLEAR_CONFIG_BC_ENABLE = 0x1 << 0, I2C_BUS_CLEAR_STATUS_CLEARED = 0x1 << 0,

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Patch set updated for coreboot: 1165a96 tegra124: fix and fine tune the warm boot code
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8151 -gerrit commit 1165a96fe6358588e5619cd47eb8370e23a5c6de Author: Joseph Lo <josephl(a)nvidia.com> Date: Fri Jun 27 11:22:41 2014 +0800 tegra124: fix and fine tune the warm boot code We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same as PLLP. But that is incorrect, BootROM had switched it to pllp_out2 with the rate 204MHz. So actually the warm boot procedure was running at the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz. And the CPU complex power on sequences were different with what we used in kernel and Coreboot. Fix up the sequence as below. * enable CPU clk * power on CPU complex * remove I/O clamps * remove CPU reset Update the time of the CPU complex power on function for record. * power_on_partition(PARTID_CRAIL): 528 uSec * power_on_partition(PARTID_CONC): 0 uSec * power_on_partition(PARTID_CE0): 4 uSec Finally, removing the redundant routine of a flow controller event with (20 | MSEC_EVENT | MODE_STOP). BUG=chrome-os-partner:29394 BRANCH=none TEST=manually test LP0 with lid switch quickly and make sure the last write to restore register successfully Original-Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8 Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205901 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Commit-Queue: Jimmy Zhang <jimmzhang(a)nvidia.com> (cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If21d17dc888b2c289970163e4f695423173ca03d --- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 27 +++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 0b519d6..9b1a4b5 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -419,6 +419,13 @@ static void config_tsc(void) setbits32(TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG, sysctr_cntcr_ptr); } +static void enable_cpu_clocks(void) +{ + // Enable the CPU complex clock. + write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); + write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); +} + /* Function unit configuration. */ @@ -505,15 +512,15 @@ static void power_on_main_cpu(void) * Note that PMC_CPUPWRGOOD_TIMER is running at pclk. * * We need to reprogram PMC_CPUPWRGOOD_TIMER based on the current pclk - * which is at 408Mhz (pclk = sclk = pllp_out0) after reset. Multiply - * PMC_CPUPWRGOOD_TIMER by 408M / 32K. + * which is at 204Mhz (pclk = sclk = pllp_out2) after BootROM. Multiply + * PMC_CPUPWRGOOD_TIMER by 204M / 32K. * * Save the original PMC_CPUPWRGOOD_TIMER register which we need to * restore after the CPU is powered up. */ uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); - write32(orig_timer * (408000000 / 32768), + write32(orig_timer * (204000000 / 32768), pmc_ctlr_cpupwrgood_timer_ptr); if (wakeup_on_lp()) { @@ -525,10 +532,6 @@ static void power_on_main_cpu(void) power_on_partition(PARTID_CE0); } - // Give I/O signals time to stablize. - write32(20 | EVENT_MSEC | FLOW_MODE_STOP, - flow_ctlr_halt_cop_events_ptr); - // Restore the original PMC_CPUPWRGOOD_TIMER. write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); } @@ -575,12 +578,6 @@ void lp0_resume(void) ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); - // Enable the CPU complex clock. - write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); - write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); - - clear_cpu_resets(); - config_tsc(); // Disable VPR. @@ -588,8 +585,12 @@ void lp0_resume(void) write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, mc_video_protect_reg_ctrl_ptr); + enable_cpu_clocks(); + power_on_main_cpu(); + clear_cpu_resets(); + // Halt the AVP. while (1) write32(FLOW_MODE_STOP | EVENT_JTAG,

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Patch set updated for coreboot: 1cdbaff tegra: i2c: re-init i2c controller after reset
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8145 -gerrit commit 1cdbaff963e1799ee8817660f5255674826f29b6 Author: Jimmy Zhang <jimmzhang(a)nvidia.com> Date: Thu Jun 5 15:20:56 2014 -0700 tegra: i2c: re-init i2c controller after reset This serves as supplemental patch to CL:197732. After clearing bus, we should also redo controller init (because controller has been reset before bus clear). On the upper layer, upon receiving error return status, it should just retry instead of simply call cpu_reset(). BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Built and tested on nyan and nyan_big. Original-Change-Id: Ib526bc730cb73ffef8696fc2a6a2769d6e71eb9e Original-Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/202784 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 06f8917c70ddca88c847d0f15ebe7f286a3f6338) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1d8bc43d730b53fe7f2dad8713831311e96e3984 --- src/soc/nvidia/tegra/i2c.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 26c2559..542d4f0 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -112,12 +112,14 @@ static int tegra_i2c_send_recv(int bus, int read, "%s: The address was not acknowledged.\n", __func__); info->reset_func(info->reset_bit); + i2c_init(bus); return -1; } else if (transfer_status & I2C_PKT_STATUS_NOACK_DATA) { printk(BIOS_ERR, "%s: The data was not acknowledged.\n", __func__); info->reset_func(info->reset_bit); + i2c_init(bus); return -1; } else if (transfer_status & I2C_PKT_STATUS_ARB_LOST) { printk(BIOS_ERR, @@ -128,6 +130,9 @@ static int tegra_i2c_send_recv(int bus, int read, /* Use Tegra bus clear registers to unlock SDA */ do_bus_clear(bus); + /* re-init i2c controller */ + i2c_init(bus); + /* Return w/error, let caller decide what to do */ return -1; }

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Patch set updated for coreboot: c7da88b tegra124: fix and fine tune the warm boot code
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8151 -gerrit commit c7da88b7370d4ebd79a3de35983cc30418c793da Author: Joseph Lo <josephl(a)nvidia.com> Date: Fri Jun 27 11:22:41 2014 +0800 tegra124: fix and fine tune the warm boot code We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same as PLLP. But that is incorrect, BootROM had switched it to pllp_out2 with the rate 204MHz. So actually the warm boot procedure was running at the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz. And the CPU complex power on sequences were different with what we used in kernel and coreboot. Fix up the sequence as below. * enable CPU clk * power on CPU complex * remove I/O clamps * remove CPU reset Update the time of the CPU complex power on function for record. * power_on_partition(PARTID_CRAIL): 528 uSec * power_on_partition(PARTID_CONC): 0 uSec * power_on_partition(PARTID_CE0): 4 uSec Finally, removing the redundant routine of a flow controller event with (20 | MSEC_EVENT | MODE_STOP). BUG=chrome-os-partner:29394 BRANCH=none TEST=manually test LP0 with lid switch quickly and make sure the last write to restore register is successful. Original-Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8 Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205901 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Commit-Queue: Jimmy Zhang <jimmzhang(a)nvidia.com> (cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If21d17dc888b2c289970163e4f695423173ca03d --- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 27 +++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 0b519d6..9b1a4b5 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -419,6 +419,13 @@ static void config_tsc(void) setbits32(TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG, sysctr_cntcr_ptr); } +static void enable_cpu_clocks(void) +{ + // Enable the CPU complex clock. + write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); + write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); +} + /* Function unit configuration. */ @@ -505,15 +512,15 @@ static void power_on_main_cpu(void) * Note that PMC_CPUPWRGOOD_TIMER is running at pclk. * * We need to reprogram PMC_CPUPWRGOOD_TIMER based on the current pclk - * which is at 408Mhz (pclk = sclk = pllp_out0) after reset. Multiply - * PMC_CPUPWRGOOD_TIMER by 408M / 32K. + * which is at 204Mhz (pclk = sclk = pllp_out2) after BootROM. Multiply + * PMC_CPUPWRGOOD_TIMER by 204M / 32K. * * Save the original PMC_CPUPWRGOOD_TIMER register which we need to * restore after the CPU is powered up. */ uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); - write32(orig_timer * (408000000 / 32768), + write32(orig_timer * (204000000 / 32768), pmc_ctlr_cpupwrgood_timer_ptr); if (wakeup_on_lp()) { @@ -525,10 +532,6 @@ static void power_on_main_cpu(void) power_on_partition(PARTID_CE0); } - // Give I/O signals time to stablize. - write32(20 | EVENT_MSEC | FLOW_MODE_STOP, - flow_ctlr_halt_cop_events_ptr); - // Restore the original PMC_CPUPWRGOOD_TIMER. write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); } @@ -575,12 +578,6 @@ void lp0_resume(void) ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); - // Enable the CPU complex clock. - write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); - write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); - - clear_cpu_resets(); - config_tsc(); // Disable VPR. @@ -588,8 +585,12 @@ void lp0_resume(void) write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, mc_video_protect_reg_ctrl_ptr); + enable_cpu_clocks(); + power_on_main_cpu(); + clear_cpu_resets(); + // Halt the AVP. while (1) write32(FLOW_MODE_STOP | EVENT_JTAG,

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Patch set updated for coreboot: 286f811 tegra: i2c: re-init i2c controller after reset
by Marc Jones 09 Jan '15

09 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8145 -gerrit commit 286f811ba44ba20ededf835b37d25f4ae75532ec Author: Jimmy Zhang <jimmzhang(a)nvidia.com> Date: Thu Jun 5 15:20:56 2014 -0700 tegra: i2c: re-init i2c controller after reset This serves as supplemental patch to chromium CL:197732. After clearing bus, we should also redo controller init (because controller has been reset before bus clear). On the upper layer, upon receiving error return status, it should just retry instead of simply call cpu_reset(). BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Built and tested on nyan and nyan_big. Original-Change-Id: Ib526bc730cb73ffef8696fc2a6a2769d6e71eb9e Original-Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/202784 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 06f8917c70ddca88c847d0f15ebe7f286a3f6338) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1d8bc43d730b53fe7f2dad8713831311e96e3984 --- src/soc/nvidia/tegra/i2c.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 26c2559..542d4f0 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -112,12 +112,14 @@ static int tegra_i2c_send_recv(int bus, int read, "%s: The address was not acknowledged.\n", __func__); info->reset_func(info->reset_bit); + i2c_init(bus); return -1; } else if (transfer_status & I2C_PKT_STATUS_NOACK_DATA) { printk(BIOS_ERR, "%s: The data was not acknowledged.\n", __func__); info->reset_func(info->reset_bit); + i2c_init(bus); return -1; } else if (transfer_status & I2C_PKT_STATUS_ARB_LOST) { printk(BIOS_ERR, @@ -128,6 +130,9 @@ static int tegra_i2c_send_recv(int bus, int read, /* Use Tegra bus clear registers to unlock SDA */ do_bus_clear(bus); + /* re-init i2c controller */ + i2c_init(bus); + /* Return w/error, let caller decide what to do */ return -1; }

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Patch merged into coreboot/master: b26fd99 cbfstool: Fix help display message
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit b26fd99087049d01920382a5d7875f9c50a07cb0 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 17 18:13:07 2014 -0700 cbfstool: Fix help display message For arm64, the machine type is arm64 in cbfstool, however it was displayed as aarch64 in help message. This patch corrects it. BUG=None BRANCH=None TEST=None Original-Change-Id: I0319907d6c9d136707ed35d6e9686ba67da7dfb2 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204379 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 1f5f4c853efac5d842147ca0373cf9b5dd9f0ad0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I00f51f1d4a9e336367f0619910fd8eb965b69bab Reviewed-on: http://review.coreboot.org/8144 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8144 for details. -gerrit

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Patch merged into coreboot/master: 9b1cb58 Set custom AR_ for each class
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit 9b1cb588690ad2775733f74897e20a4d370959f2 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Jun 19 19:01:34 2014 -0700 Set custom AR_ for each class TEST=Booted Nyan Blaze BUG=none BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I7e822e16117240f732ac55bb2c3816486a3e10cc Original-Reviewed-on: https://chromium-review.googlesource.com/204870 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> (cherry picked from commit 967455d6fed014f82198de4987ec103bb7c33d25) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I88025887fb0134f1e75028e0a4ed0c78af281c96 Reviewed-on: http://review.coreboot.org/8143 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8143 for details. -gerrit

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Patch merged into coreboot/master: 6a29e6c elog: Add ELOG_TYPE_BOOT event using fake boot count if necessary
by gerrit＠coreboot.org 09 Jan '15

09 Jan '15

the following patch was just integrated into master: commit 6a29e6c6b64753d080a483fbe581117dbb164262 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jun 18 13:03:03 2014 -0700 elog: Add ELOG_TYPE_BOOT event using fake boot count if necessary This makes it so that we always log the generic "system boot" event. If boot count support has not been implemented, fake it. BUG=chrome-os-partner:28772 BRANCH=nyan TEST=booted on Big, ran "mosys eventlog list" and saw "System boot" event logged with boot count == 0 Original-Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204525 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 2598dc63ddc0d76bcdf9814cadd4c75653fd9832) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ieb4e2e36870e97d9c5f88f0190291863a65a6351 Reviewed-on: http://review.coreboot.org/8142 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8142 for details. -gerrit

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coreboot-gerrit January 2015