coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

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922 discussions

Patch merged into coreboot/master: 12fcb86 sandybridge: Pass chip info to i915lightup.
by gerrit＠coreboot.org 02 Jun '14

02 Jun '14

the following patch was just integrated into master: commit 12fcb86bba5004ce1b6f8172a08e6d89de2cfed8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:09:48 2014 +0100 sandybridge: Pass chip info to i915lightup. Change-Id: I280441aadb0575dc0b99584cdcd48cc76a0289a2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/5284 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5284 for details. -gerrit

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New patch to review for coreboot: c6c8d37 Board kontron/986lcd-m: Non-local header treated as local
by HAOUAS Elyes 02 Jun '14

02 Jun '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5920 -gerrit commit c6c8d370e4f38b78084002827e525ef35c3c848a Author: Elyes <ehaouas(a)noos.fr> Date: Mon Jun 2 21:42:27 2014 +0200 Board kontron/986lcd-m: Non-local header treated as local Change-Id: Ie8f5837c7853ded0bce782f75b4cb5fb8b54488a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/kontron/986lcd-m/acpi_tables.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 8 ++++---- src/mainboard/kontron/986lcd-m/smihandler.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index e6a517e..8b9af6a 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -34,7 +34,7 @@ extern const unsigned char AmlCode[]; unsigned long acpi_create_slic(unsigned long current); #endif -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> static void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 4acd734..89c6f69 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -28,13 +28,13 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "option_table.h" +#include <option_table.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <superio/winbond/w83627thg/w83627thg.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) diff --git a/src/mainboard/kontron/986lcd-m/smihandler.c b/src/mainboard/kontron/986lcd-m/smihandler.c index 064109b..79e8f27 100644 --- a/src/mainboard/kontron/986lcd-m/smihandler.c +++ b/src/mainboard/kontron/986lcd-m/smihandler.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler

1 0

Patch set updated for coreboot: 5411ac6 nehalem: Remove fake_vbt copying.
by Vladimir Serbinenko 02 Jun '14

02 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5895 -gerrit commit 5411ac624764f3b593dc3d2f02f15537b03a191a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat May 31 22:26:42 2014 +0200 nehalem: Remove fake_vbt copying. Instead generate simple VBT in code. Tested on X201. Change-Id: I2244053edd24c22694161d9bf5f7f2f3eb4e2f57 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Makefile.inc | 1 - src/mainboard/lenovo/x201/gma.c | 514 -------------------------- src/mainboard/packardbell/ms2290/Makefile.inc | 1 - src/mainboard/packardbell/ms2290/gma.c | 272 -------------- src/northbridge/intel/nehalem/gma.c | 131 ++++++- 5 files changed, 120 insertions(+), 799 deletions(-) diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc index 285e0d0..db291f3 100644 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ b/src/mainboard/lenovo/x201/Makefile.inc @@ -21,5 +21,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += dock.c ramstage-y += dock.c -ramstage-y += gma.c diff --git a/src/mainboard/lenovo/x201/gma.c b/src/mainboard/lenovo/x201/gma.c deleted file mode 100644 index f417905..0000000 --- a/src/mainboard/lenovo/x201/gma.c +++ /dev/null @@ -1,514 +0,0 @@ -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - -#include "northbridge/intel/nehalem/nehalem.h" - -/* This array contains the information on flat panel. When using native - graphics init coreboot copies it to where VGA Option ROM would be so - that OS can find it and able to use internal display. This contains no - executable code and is just information on the panel. - */ - -unsigned char fake_vbt[] = { - 0x24, 0x56, 0x42, 0x54, 0x20, 0x49, 0x52, 0x4f, 0x4e, 0x4c, 0x41, 0x4b, - 0x45, 0x2d, 0x4d, 0x4f, - 0x42, 0x49, 0x4c, 0x45, 0x64, 0x00, 0x30, 0x00, 0x8e, 0x0f, 0x48, 0x00, - 0x30, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x42, 0x49, 0x4f, 0x53, 0x5f, 0x44, 0x41, 0x54, 0x41, 0x5f, 0x42, 0x4c, - 0x4f, 0x43, 0x4b, 0x20, - 0x9c, 0x00, 0x16, 0x00, 0x5e, 0x0f, 0xfe, 0xea, 0x00, 0x00, 0x64, 0x01, - 0x01, 0x0f, 0x0d, 0x32, - 0x30, 0x32, 0x36, 0x44, 0x43, 0x49, 0x20, 0x49, 0x6e, 0x74, 0x65, 0x6c, - 0x28, 0x52, 0x29, 0x49, - 0x72, 0x6f, 0x6e, 0x6c, 0x61, 0x6b, 0x65, 0x20, 0x4d, 0x6f, 0x62, 0x69, - 0x6c, 0x65, 0x20, 0x50, - 0x43, 0x49, 0x20, 0x41, 0x63, 0x63, 0x65, 0x6c, 0x65, 0x72, 0x61, 0x74, - 0x65, 0x64, 0x20, 0x53, - 0x56, 0x47, 0x41, 0x20, 0x42, 0x49, 0x4f, 0x53, 0x0d, 0x0a, 0x42, 0x75, - 0x69, 0x6c, 0x64, 0x20, - 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-#include "northbridge/intel/nehalem/nehalem.h" - -/* This array contains the information on flat panel. When using native - graphics init coreboot copies it to where VGA Option ROM would be so - that OS can find it and able to use internal display. This contains no - executable code and is just information on the panel. - */ - -unsigned char fake_vbt[] = { -0x24, 0x56, 0x42, 0x54, 0x20, 0x49, 0x52, 0x4f, 0x4e, 0x4c, 0x41, 0x4b, 0x45, 0x2d, 0x4d, 0x4f, -0x42, 0x49, 0x4c, 0x45, 0x64, 0x00, 0x30, 0x00, 0xc3, 0x10, 0xa4, 0x00, 0x30, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x42, 0x49, 0x4f, 0x53, 0x5f, 0x44, 0x41, 0x54, 0x41, 0x5f, 0x42, 0x4c, 0x4f, 0x43, 0x4b, 0x20, -0x9b, 0x00, 0x16, 0x00, 0x93, 0x10, 0xfe, 0xea, 0x00, 0x00, 0x64, 0x01, 0x01, 0x0f, 0x0d, 0x31, -0x39, 0x39, 0x34, 0x49, 0x6e, 0x74, 0x65, 0x6c, 0x28, 0x52, 0x29, 0x49, 0x72, 0x6f, 0x6e, 0x6c, -0x61, 0x6b, 0x65, 0x20, 0x4d, 0x6f, 0x62, 0x69, 0x6c, 0x65, 0x20, 0x50, 0x43, 0x49, 0x20, 0x41, -0x63, 0x63, 0x65, 0x6c, 0x65, 0x72, 0x61, 0x74, 0x65, 0x64, 0x20, 0x53, 0x56, 0x47, 0x41, 0x20, -0x42, 0x49, 0x4f, 0x53, 0x0d, 0x0a, 0x42, 0x75, 0x69, 0x6c, 0x64, 0x20, 0x4e, 0x75, 0x6d, 0x62, -0x65, 0x72, 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b/src/northbridge/intel/nehalem/gma.c index 3a9dcf5..544b813 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -1046,6 +1046,114 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, #endif +/* VBT definitions copied from Linux. */ +struct vbt_header { + u8 signature[20]; + u16 version; + u16 header_size; + u16 vbt_size; + u8 vbt_checksum; + u8 reserved0; + u32 bdb_offset; + u32 aim_offset[4]; +} __attribute__((packed)); + +struct bdb_header { + u8 signature[16]; + u16 version; + u16 header_size; + u16 bdb_size; +} __attribute__((packed)); + +#define BDB_GENERAL_FEATURES 1 + +struct bdb_general_features { + /* bits 1 */ + u8 panel_fitting:2; + u8 flexaim:1; + u8 msg_enable:1; + u8 clear_screen:3; + u8 color_flip:1; + + /* bits 2 */ + u8 download_ext_vbt:1; + u8 enable_ssc:1; + u8 ssc_freq:1; + u8 enable_lfp_on_override:1; + u8 disable_ssc_ddt:1; + u8 rsvd7:1; + u8 display_clock_mode:1; + u8 rsvd8:1; /* finish byte */ + + /* bits 3 */ + u8 disable_smooth_vision:1; + u8 single_dvi:1; + u8 rsvd9:1; + u8 fdi_rx_polarity_inverted:1; + u8 rsvd10:4; /* finish byte */ + + /* bits 4 */ + u8 legacy_monitor_detect; + + /* bits 5 */ + u8 int_crt_support:1; + u8 int_tv_support:1; + u8 int_efp_support:1; + u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ + u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ + u8 rsvd11:3; /* finish byte */ +} __attribute__((packed)); + + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT +static size_t generate_vbt(const struct northbridge_intel_nehalem_config *conf, + void *vbt) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset (head, 0, sizeof (*head)); + + memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset (bdb_head, 0, sizeof (*bdb_head)); + memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset (genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} +#endif static void gma_func0_init(struct device *dev) { @@ -1080,23 +1188,21 @@ static void gma_func0_init(struct device *dev) intel_gma_init(conf, gtt_res->base, physbase, pio_res->base, lfb_res->base); } -#endif /* Linux relies on VBT for panel info. */ - if (read16(0xc0000) != 0xaa55) { - optionrom_header_t *oh = (void *)0xc0000; + if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) { + optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; optionrom_pcir_t *pcir; - int sz; + size_t vbt_size; + size_t fake_oprom_size; - memset(oh->reserved, 0, 8192); + memset(oh, 0, 8192); - sz = (0x80 + sizeof(fake_vbt) + 511) / 512; - oh->signature = 0xaa55; - oh->size = sz; + oh->signature = OPROM_SIGNATURE; oh->pcir_offset = 0x40; oh->vbt_offset = 0x80; - pcir = (void *)0xc0040; + pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); pcir->signature = 0x52494350; // PCIR pcir->vendor = dev->vendor; pcir->device = dev->device; @@ -1105,11 +1211,14 @@ static void gma_func0_init(struct device *dev) pcir->classcode[0] = dev->class >> 8; pcir->classcode[1] = dev->class >> 16; pcir->classcode[2] = dev->class >> 24; - pcir->imagelength = sz; pcir->indicator = 0x80; - memcpy((void *)0xc0080, fake_vbt, sizeof(fake_vbt)); + vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; } +#endif /* Post VBIOS init */

1 0

Patch set updated for coreboot: 56f5a4f x230: Deploy VBT
by Vladimir Serbinenko 02 Jun '14

02 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5396 -gerrit commit 56f5a4f684e46bd186643ede557b3f0e21e8a4bf Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:13:56 2014 +0100 x230: Deploy VBT Change-Id: Ide31a56bfdbc31cd3b87993dfb4ed8ef0107cdba Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/intel_bios.h | 733 +++++++++++++++++++++ .../intel/sandybridge/gma_ivybridge_lvds.c | 84 +++ 2 files changed, 817 insertions(+) diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h new file mode 100644 index 0000000..36426d8 --- /dev/null +++ b/src/drivers/intel/gma/intel_bios.h @@ -0,0 +1,733 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Eric Anholt <eric(a)anholt.net> + * + */ + +#ifndef _I830_BIOS_H_ +#define _I830_BIOS_H_ + +struct vbt_header { + u8 signature[20]; /**< Always starts with 'VBT$' */ + u16 version; /**< decimal */ + u16 header_size; /**< in bytes */ + u16 vbt_size; /**< in bytes */ + u8 vbt_checksum; + u8 reserved0; + u32 bdb_offset; /**< from beginning of VBT */ + u32 aim_offset[4]; /**< from beginning of VBT */ +} __attribute__((packed)); + +struct bdb_header { + u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ + u16 version; /**< decimal */ + u16 header_size; /**< in bytes */ + u16 bdb_size; /**< in bytes */ +}; + +/* strictly speaking, this is a "skip" block, but it has interesting info */ +struct vbios_data { + u8 type; /* 0 == desktop, 1 == mobile */ + u8 relstage; + u8 chipset; + u8 lvds_present:1; + u8 tv_present:1; + u8 rsvd2:6; /* finish byte */ + u8 rsvd3[4]; + u8 signon[155]; + u8 copyright[61]; + u16 code_segment; + u8 dos_boot_mode; + u8 bandwidth_percent; + u8 rsvd4; /* popup memory size */ + u8 resize_pci_bios; + u8 rsvd5; /* is crt already on ddc2 */ +} __attribute__((packed)); + +/* + * There are several types of BIOS data blocks (BDBs), each block has + * an ID and size in the first 3 bytes (ID in first, size in next 2). + * Known types are listed below. + */ +#define BDB_GENERAL_FEATURES 1 +#define BDB_GENERAL_DEFINITIONS 2 +#define BDB_OLD_TOGGLE_LIST 3 +#define BDB_MODE_SUPPORT_LIST 4 +#define BDB_GENERIC_MODE_TABLE 5 +#define BDB_EXT_MMIO_REGS 6 +#define BDB_SWF_IO 7 +#define BDB_SWF_MMIO 8 +#define BDB_DOT_CLOCK_TABLE 9 +#define BDB_MODE_REMOVAL_TABLE 10 +#define BDB_CHILD_DEVICE_TABLE 11 +#define BDB_DRIVER_FEATURES 12 +#define BDB_DRIVER_PERSISTENCE 13 +#define BDB_EXT_TABLE_PTRS 14 +#define BDB_DOT_CLOCK_OVERRIDE 15 +#define BDB_DISPLAY_SELECT 16 +/* 17 rsvd */ +#define BDB_DRIVER_ROTATION 18 +#define BDB_DISPLAY_REMOVE 19 +#define BDB_OEM_CUSTOM 20 +#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ +#define BDB_SDVO_LVDS_OPTIONS 22 +#define BDB_SDVO_PANEL_DTDS 23 +#define BDB_SDVO_LVDS_PNP_IDS 24 +#define BDB_SDVO_LVDS_POWER_SEQ 25 +#define BDB_TV_OPTIONS 26 +#define BDB_EDP 27 +#define BDB_LVDS_OPTIONS 40 +#define BDB_LVDS_LFP_DATA_PTRS 41 +#define BDB_LVDS_LFP_DATA 42 +#define BDB_LVDS_BACKLIGHT 43 +#define BDB_LVDS_POWER 44 +#define BDB_MIPI 50 +#define BDB_SKIP 254 /* VBIOS private block, ignore */ + +struct bdb_general_features { + /* bits 1 */ + u8 panel_fitting:2; + u8 flexaim:1; + u8 msg_enable:1; + u8 clear_screen:3; + u8 color_flip:1; + + /* bits 2 */ + u8 download_ext_vbt:1; + u8 enable_ssc:1; + u8 ssc_freq:1; + u8 enable_lfp_on_override:1; + u8 disable_ssc_ddt:1; + u8 rsvd7:1; + u8 display_clock_mode:1; + u8 rsvd8:1; /* finish byte */ + + /* bits 3 */ + u8 disable_smooth_vision:1; + u8 single_dvi:1; + u8 rsvd9:1; + u8 fdi_rx_polarity_inverted:1; + u8 rsvd10:4; /* finish byte */ + + /* bits 4 */ + u8 legacy_monitor_detect; + + /* bits 5 */ + u8 int_crt_support:1; + u8 int_tv_support:1; + u8 int_efp_support:1; + u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ + u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ + u8 rsvd11:3; /* finish byte */ +} __attribute__((packed)); + +/* pre-915 */ +#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ +#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ +#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ +#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ + +/* Pre 915 */ +#define DEVICE_TYPE_NONE 0x00 +#define DEVICE_TYPE_CRT 0x01 +#define DEVICE_TYPE_TV 0x09 +#define DEVICE_TYPE_EFP 0x12 +#define DEVICE_TYPE_LFP 0x22 +/* On 915+ */ +#define DEVICE_TYPE_CRT_DPMS 0x6001 +#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 +#define DEVICE_TYPE_TV_COMPOSITE 0x0209 +#define DEVICE_TYPE_TV_MACROVISION 0x0289 +#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c +#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 +#define DEVICE_TYPE_TV_SCART 0x0209 +#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 +#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 +#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 +#define DEVICE_TYPE_EFP_DVI_I 0x6053 +#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 +#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 +#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 +#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 +#define DEVICE_TYPE_LFP_PANELLINK 0x5012 +#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 +#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 +#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 +#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 + +#define DEVICE_CFG_NONE 0x00 +#define DEVICE_CFG_12BIT_DVOB 0x01 +#define DEVICE_CFG_12BIT_DVOC 0x02 +#define DEVICE_CFG_24BIT_DVOBC 0x09 +#define DEVICE_CFG_24BIT_DVOCB 0x0a +#define DEVICE_CFG_DUAL_DVOB 0x11 +#define DEVICE_CFG_DUAL_DVOC 0x12 +#define DEVICE_CFG_DUAL_DVOBC 0x13 +#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 +#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a + +#define DEVICE_WIRE_NONE 0x00 +#define DEVICE_WIRE_DVOB 0x01 +#define DEVICE_WIRE_DVOC 0x02 +#define DEVICE_WIRE_DVOBC 0x03 +#define DEVICE_WIRE_DVOBB 0x05 +#define DEVICE_WIRE_DVOCC 0x06 +#define DEVICE_WIRE_DVOB_MASTER 0x0d +#define DEVICE_WIRE_DVOC_MASTER 0x0e + +#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ +#define DEVICE_PORT_DVOB 0x01 +#define DEVICE_PORT_DVOC 0x02 + +/* We used to keep this struct but without any version control. We should avoid + * using it in the future, but it should be safe to keep using it in the old + * code. */ +struct old_child_dev_config { + u16 handle; + u16 device_type; + u8 device_id[10]; /* ascii string */ + u16 addin_offset; + u8 dvo_port; /* See Device_PORT_* above */ + u8 i2c_pin; + u8 slave_addr; + u8 ddc_pin; + u16 edid_ptr; + u8 dvo_cfg; /* See DEVICE_CFG_* above */ + u8 dvo2_port; + u8 i2c2_pin; + u8 slave2_addr; + u8 ddc2_pin; + u8 capabilities; + u8 dvo_wiring;/* See DEVICE_WIRE_* above */ + u8 dvo2_wiring; + u16 extended_type; + u8 dvo_function; +} __attribute__((packed)); + +/* This one contains field offsets that are known to be common for all BDB + * versions. Notice that the meaning of the contents contents may still change, + * but at least the offsets are consistent. */ +struct common_child_dev_config { + u16 handle; + u16 device_type; + u8 not_common1[12]; + u8 dvo_port; + u8 not_common2[2]; + u8 ddc_pin; + u16 edid_ptr; +} __attribute__((packed)); + +/* This field changes depending on the BDB version, so the most reliable way to + * read it is by checking the BDB version and reading the raw pointer. */ +union child_device_config { + /* This one is safe to be used anywhere, but the code should still check + * the BDB version. */ + u8 raw[33]; + /* This one should only be kept for legacy code. */ + struct old_child_dev_config old; + /* This one should also be safe to use anywhere, even without version + * checks. */ + struct common_child_dev_config common; +}; + +struct bdb_general_definitions { + /* DDC GPIO */ + u8 crt_ddc_gmbus_pin; + + /* DPMS bits */ + u8 dpms_acpi:1; + u8 skip_boot_crt_detect:1; + u8 dpms_aim:1; + u8 rsvd1:5; /* finish byte */ + + /* boot device bits */ + u8 boot_display[2]; + u8 child_dev_size; + + /* + * Device info: + * If TV is present, it'll be at devices[0]. + * LVDS will be next, either devices[0] or [1], if present. + * On some platforms the number of device is 6. But could be as few as + * 4 if both TV and LVDS are missing. + * And the device num is related with the size of general definition + * block. It is obtained by using the following formula: + * number = (block_size - sizeof(bdb_general_definitions))/ + * sizeof(child_device_config); + */ + union child_device_config devices[0]; +} __attribute__((packed)); + +struct bdb_lvds_options { + u8 panel_type; + u8 rsvd1; + /* LVDS capabilities, stored in a dword */ + u8 pfit_mode:2; + u8 pfit_text_mode_enhanced:1; + u8 pfit_gfx_mode_enhanced:1; + u8 pfit_ratio_auto:1; + u8 pixel_dither:1; + u8 lvds_edid:1; + u8 rsvd2:1; + u8 rsvd4; +} __attribute__((packed)); + +/* LFP pointer table contains entries to the struct below */ +struct bdb_lvds_lfp_data_ptr { + u16 fp_timing_offset; /* offsets are from start of bdb */ + u8 fp_table_size; + u16 dvo_timing_offset; + u8 dvo_table_size; + u16 panel_pnp_id_offset; + u8 pnp_table_size; +} __attribute__((packed)); + +struct bdb_lvds_lfp_data_ptrs { + u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ + struct bdb_lvds_lfp_data_ptr ptr[16]; +} __attribute__((packed)); + +/* LFP data has 3 blocks per entry */ +struct lvds_fp_timing { + u16 x_res; + u16 y_res; + u32 lvds_reg; + u32 lvds_reg_val; + u32 pp_on_reg; + u32 pp_on_reg_val; + u32 pp_off_reg; + u32 pp_off_reg_val; + u32 pp_cycle_reg; + u32 pp_cycle_reg_val; + u32 pfit_reg; + u32 pfit_reg_val; + u16 terminator; +} __attribute__((packed)); + +struct lvds_dvo_timing { + u16 clock; /**< In 10khz */ + u8 hactive_lo; + u8 hblank_lo; + u8 hblank_hi:4; + u8 hactive_hi:4; + u8 vactive_lo; + u8 vblank_lo; + u8 vblank_hi:4; + u8 vactive_hi:4; + u8 hsync_off_lo; + u8 hsync_pulse_width; + u8 vsync_pulse_width:4; + u8 vsync_off:4; + u8 rsvd0:6; + u8 hsync_off_hi:2; + u8 h_image; + u8 v_image; + u8 max_hv; + u8 h_border; + u8 v_border; + u8 rsvd1:3; + u8 digital:2; + u8 vsync_positive:1; + u8 hsync_positive:1; + u8 rsvd2:1; +} __attribute__((packed)); + +struct lvds_pnp_id { + u16 mfg_name; + u16 product_code; + u32 serial; + u8 mfg_week; + u8 mfg_year; +} __attribute__((packed)); + +struct bdb_lvds_lfp_data_entry { + struct lvds_fp_timing fp_timing; + struct lvds_dvo_timing dvo_timing; + struct lvds_pnp_id pnp_id; +} __attribute__((packed)); + +struct bdb_lvds_lfp_data { + struct bdb_lvds_lfp_data_entry data[16]; +} __attribute__((packed)); + +struct aimdb_header { + char signature[16]; + char oem_device[20]; + u16 aimdb_version; + u16 aimdb_header_size; + u16 aimdb_size; +} __attribute__((packed)); + +struct aimdb_block { + u8 aimdb_id; + u16 aimdb_size; +} __attribute__((packed)); + +struct vch_panel_data { + u16 fp_timing_offset; + u8 fp_timing_size; + u16 dvo_timing_offset; + u8 dvo_timing_size; + u16 text_fitting_offset; + u8 text_fitting_size; + u16 graphics_fitting_offset; + u8 graphics_fitting_size; +} __attribute__((packed)); + +struct vch_bdb_22 { + struct aimdb_block aimdb_block; + struct vch_panel_data panels[16]; +} __attribute__((packed)); + +struct bdb_sdvo_lvds_options { + u8 panel_backlight; + u8 h40_set_panel_type; + u8 panel_type; + u8 ssc_clk_freq; + u16 als_low_trip; + u16 als_high_trip; + u8 sclalarcoeff_tab_row_num; + u8 sclalarcoeff_tab_row_size; + u8 coefficient[8]; + u8 panel_misc_bits_1; + u8 panel_misc_bits_2; + u8 panel_misc_bits_3; + u8 panel_misc_bits_4; +} __attribute__((packed)); + + +#define BDB_DRIVER_FEATURE_NO_LVDS 0 +#define BDB_DRIVER_FEATURE_INT_LVDS 1 +#define BDB_DRIVER_FEATURE_SDVO_LVDS 2 +#define BDB_DRIVER_FEATURE_EDP 3 + +struct bdb_driver_features { + u8 boot_dev_algorithm:1; + u8 block_display_switch:1; + u8 allow_display_switch:1; + u8 hotplug_dvo:1; + u8 dual_view_zoom:1; + u8 int15h_hook:1; + u8 sprite_in_clone:1; + u8 primary_lfp_id:1; + + u16 boot_mode_x; + u16 boot_mode_y; + u8 boot_mode_bpp; + u8 boot_mode_refresh; + + u16 enable_lfp_primary:1; + u16 selective_mode_pruning:1; + u16 dual_frequency:1; + u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ + u16 nt_clone_support:1; + u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ + u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ + u16 cui_aspect_scaling:1; + u16 preserve_aspect_ratio:1; + u16 sdvo_device_power_down:1; + u16 crt_hotplug:1; + u16 lvds_config:2; + u16 tv_hotplug:1; + u16 hdmi_config:2; + + u8 static_display:1; + u8 reserved2:7; + u16 legacy_crt_max_x; + u16 legacy_crt_max_y; + u8 legacy_crt_max_refresh; + + u8 hdmi_termination; + u8 custom_vbt_version; +} __attribute__((packed)); + +#define EDP_18BPP 0 +#define EDP_24BPP 1 +#define EDP_30BPP 2 +#define EDP_RATE_1_62 0 +#define EDP_RATE_2_7 1 +#define EDP_LANE_1 0 +#define EDP_LANE_2 1 +#define EDP_LANE_4 3 +#define EDP_PREEMPHASIS_NONE 0 +#define EDP_PREEMPHASIS_3_5dB 1 +#define EDP_PREEMPHASIS_6dB 2 +#define EDP_PREEMPHASIS_9_5dB 3 +#define EDP_VSWING_0_4V 0 +#define EDP_VSWING_0_6V 1 +#define EDP_VSWING_0_8V 2 +#define EDP_VSWING_1_2V 3 + +struct edp_power_seq { + u16 t1_t3; + u16 t8; + u16 t9; + u16 t10; + u16 t11_t12; +} __attribute__ ((packed)); + +struct edp_link_params { + u8 rate:4; + u8 lanes:4; + u8 preemphasis:4; + u8 vswing:4; +} __attribute__ ((packed)); + +struct bdb_edp { + struct edp_power_seq power_seqs[16]; + u32 color_depth; + struct edp_link_params link_params[16]; + u32 sdrrs_msa_timing_delay; + + /* ith bit indicates enabled/disabled for (i+1)th panel */ + u16 edp_s3d_feature; + u16 edp_t3_optimization; +} __attribute__ ((packed)); + +/* + * Driver<->VBIOS interaction occurs through scratch bits in + * GR18 & SWF*. + */ + +/* GR18 bits are set on display switch and hotkey events */ +#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ +#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ +#define GR18_HK_NONE (0x0<<3) +#define GR18_HK_LFP_STRETCH (0x1<<3) +#define GR18_HK_TOGGLE_DISP (0x2<<3) +#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ +#define GR18_HK_POPUP_DISABLED (0x6<<3) +#define GR18_HK_POPUP_ENABLED (0x7<<3) +#define GR18_HK_PFIT (0x8<<3) +#define GR18_HK_APM_CHANGE (0xa<<3) +#define GR18_HK_MULTIPLE (0xc<<3) +#define GR18_USER_INT_EN (1<<2) +#define GR18_A0000_FLUSH_EN (1<<1) +#define GR18_SMM_EN (1<<0) + +/* Set by driver, cleared by VBIOS */ +#define SWF00_YRES_SHIFT 16 +#define SWF00_XRES_SHIFT 0 +#define SWF00_RES_MASK 0xffff + +/* Set by VBIOS at boot time and driver at runtime */ +#define SWF01_TV2_FORMAT_SHIFT 8 +#define SWF01_TV1_FORMAT_SHIFT 0 +#define SWF01_TV_FORMAT_MASK 0xffff + +#define SWF10_VBIOS_BLC_I2C_EN (1<<29) +#define SWF10_GTT_OVERRIDE_EN (1<<28) +#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ +#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) +#define SWF10_OLD_TOGGLE 0x0 +#define SWF10_TOGGLE_LIST_1 0x1 +#define SWF10_TOGGLE_LIST_2 0x2 +#define SWF10_TOGGLE_LIST_3 0x3 +#define SWF10_TOGGLE_LIST_4 0x4 +#define SWF10_PANNING_EN (1<<23) +#define SWF10_DRIVER_LOADED (1<<22) +#define SWF10_EXTENDED_DESKTOP (1<<21) +#define SWF10_EXCLUSIVE_MODE (1<<20) +#define SWF10_OVERLAY_EN (1<<19) +#define SWF10_PLANEB_HOLDOFF (1<<18) +#define SWF10_PLANEA_HOLDOFF (1<<17) +#define SWF10_VGA_HOLDOFF (1<<16) +#define SWF10_ACTIVE_DISP_MASK 0xffff +#define SWF10_PIPEB_LFP2 (1<<15) +#define SWF10_PIPEB_EFP2 (1<<14) +#define SWF10_PIPEB_TV2 (1<<13) +#define SWF10_PIPEB_CRT2 (1<<12) +#define SWF10_PIPEB_LFP (1<<11) +#define SWF10_PIPEB_EFP (1<<10) +#define SWF10_PIPEB_TV (1<<9) +#define SWF10_PIPEB_CRT (1<<8) +#define SWF10_PIPEA_LFP2 (1<<7) +#define SWF10_PIPEA_EFP2 (1<<6) +#define SWF10_PIPEA_TV2 (1<<5) +#define SWF10_PIPEA_CRT2 (1<<4) +#define SWF10_PIPEA_LFP (1<<3) +#define SWF10_PIPEA_EFP (1<<2) +#define SWF10_PIPEA_TV (1<<1) +#define SWF10_PIPEA_CRT (1<<0) + +#define SWF11_MEMORY_SIZE_SHIFT 16 +#define SWF11_SV_TEST_EN (1<<15) +#define SWF11_IS_AGP (1<<14) +#define SWF11_DISPLAY_HOLDOFF (1<<13) +#define SWF11_DPMS_REDUCED (1<<12) +#define SWF11_IS_VBE_MODE (1<<11) +#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ +#define SWF11_DPMS_MASK 0x07 +#define SWF11_DPMS_OFF (1<<2) +#define SWF11_DPMS_SUSPEND (1<<1) +#define SWF11_DPMS_STANDBY (1<<0) +#define SWF11_DPMS_ON 0 + +#define SWF14_GFX_PFIT_EN (1<<31) +#define SWF14_TEXT_PFIT_EN (1<<30) +#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ +#define SWF14_POPUP_EN (1<<28) +#define SWF14_DISPLAY_HOLDOFF (1<<27) +#define SWF14_DISP_DETECT_EN (1<<26) +#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ +#define SWF14_DRIVER_STATUS (1<<24) +#define SWF14_OS_TYPE_WIN9X (1<<23) +#define SWF14_OS_TYPE_WINNT (1<<22) +/* 21:19 rsvd */ +#define SWF14_PM_TYPE_MASK 0x00070000 +#define SWF14_PM_ACPI_VIDEO (0x4 << 16) +#define SWF14_PM_ACPI (0x3 << 16) +#define SWF14_PM_APM_12 (0x2 << 16) +#define SWF14_PM_APM_11 (0x1 << 16) +#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ + /* if GR18 indicates a display switch */ +#define SWF14_DS_PIPEB_LFP2_EN (1<<15) +#define SWF14_DS_PIPEB_EFP2_EN (1<<14) +#define SWF14_DS_PIPEB_TV2_EN (1<<13) +#define SWF14_DS_PIPEB_CRT2_EN (1<<12) +#define SWF14_DS_PIPEB_LFP_EN (1<<11) +#define SWF14_DS_PIPEB_EFP_EN (1<<10) +#define SWF14_DS_PIPEB_TV_EN (1<<9) +#define SWF14_DS_PIPEB_CRT_EN (1<<8) +#define SWF14_DS_PIPEA_LFP2_EN (1<<7) +#define SWF14_DS_PIPEA_EFP2_EN (1<<6) +#define SWF14_DS_PIPEA_TV2_EN (1<<5) +#define SWF14_DS_PIPEA_CRT2_EN (1<<4) +#define SWF14_DS_PIPEA_LFP_EN (1<<3) +#define SWF14_DS_PIPEA_EFP_EN (1<<2) +#define SWF14_DS_PIPEA_TV_EN (1<<1) +#define SWF14_DS_PIPEA_CRT_EN (1<<0) + /* if GR18 indicates a panel fitting request */ +#define SWF14_PFIT_EN (1<<0) /* 0 means disable */ + /* if GR18 indicates an APM change request */ +#define SWF14_APM_HIBERNATE 0x4 +#define SWF14_APM_SUSPEND 0x3 +#define SWF14_APM_STANDBY 0x1 +#define SWF14_APM_RESTORE 0x0 + +/* Add the device class for LFP, TV, HDMI */ +#define DEVICE_TYPE_INT_LFP 0x1022 +#define DEVICE_TYPE_INT_TV 0x1009 +#define DEVICE_TYPE_HDMI 0x60D2 +#define DEVICE_TYPE_DP 0x68C6 +#define DEVICE_TYPE_eDP 0x78C6 + +#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) +#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) +#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) +#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) +#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) +#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) +#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) +#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) +#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) +#define DEVICE_TYPE_LVDS_SINGALING (1 << 5) +#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) +#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) +#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) +#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) +#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) + +/* + * Bits we care about when checking for DEVICE_TYPE_eDP + * Depending on the system, the other bits may or may not + * be set for eDP outputs. + */ +#define DEVICE_TYPE_eDP_BITS \ + (DEVICE_TYPE_INTERNAL_CONNECTOR | \ + DEVICE_TYPE_NOT_HDMI_OUTPUT | \ + DEVICE_TYPE_MIPI_OUTPUT | \ + DEVICE_TYPE_COMPOSITE_OUTPUT | \ + DEVICE_TYPE_DUAL_CHANNEL | \ + DEVICE_TYPE_LVDS_SINGALING | \ + DEVICE_TYPE_TMDS_DVI_SIGNALING | \ + DEVICE_TYPE_VIDEO_SIGNALING | \ + DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ + DEVICE_TYPE_DIGITAL_OUTPUT | \ + DEVICE_TYPE_ANALOG_OUTPUT) + +/* define the DVO port for HDMI output type */ +#define DVO_B 1 +#define DVO_C 2 +#define DVO_D 3 + +/* define the PORT for DP output type */ +#define PORT_IDPB 7 +#define PORT_IDPC 8 +#define PORT_IDPD 9 + +/* Possible values for the "DVO Port" field for versions >= 155: */ +#define DVO_PORT_HDMIA 0 +#define DVO_PORT_HDMIB 1 +#define DVO_PORT_HDMIC 2 +#define DVO_PORT_HDMID 3 +#define DVO_PORT_LVDS 4 +#define DVO_PORT_TV 5 +#define DVO_PORT_CRT 6 +#define DVO_PORT_DPB 7 +#define DVO_PORT_DPC 8 +#define DVO_PORT_DPD 9 +#define DVO_PORT_DPA 10 + +/* MIPI DSI panel info */ +struct bdb_mipi { + u16 panel_id; + u16 bridge_revision; + + /* General params */ + u32 dithering:1; + u32 bpp_pixel_format:1; + u32 rsvd1:1; + u32 dphy_valid:1; + u32 resvd2:28; + + u16 port_info; + u16 rsvd3:2; + u16 num_lanes:2; + u16 rsvd4:12; + + /* DSI config */ + u16 virt_ch_num:2; + u16 vtm:2; + u16 rsvd5:12; + + u32 dsi_clock; + u32 bridge_ref_clk; + u16 rsvd_pwr; + + /* Dphy Params */ + u32 prepare_cnt:5; + u32 rsvd6:3; + u32 clk_zero_cnt:8; + u32 trail_cnt:5; + u32 rsvd7:3; + u32 exit_zero_cnt:6; + u32 rsvd8:2; + + u32 hl_switch_cnt; + u32 lp_byte_clk; + u32 clk_lane_switch_cnt; +} __attribute__((packed)); + +#endif /* _I830_BIOS_H_ */ diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 1f53a74..2a03054 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -26,13 +26,64 @@ #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/intel_bios.h> #include "gma.h" #include "chip.h" #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <device/pci_def.h> +#include <device/pci_rom.h> #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) +static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, + void *vbt) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset(head, 0, sizeof (*head)); + + memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset(bdb_head, 0, sizeof (*bdb_head)); + memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset(genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} + static void link_train(u32 mmio) { write32(mmio+0xf000c,0x40); @@ -509,6 +560,39 @@ int i915lightup(const struct northbridge_intel_sandybridge_config *info, memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); set_vbe_mode_info_valid(&edid, lfb); #endif + + /* Linux relies on VBT for panel info. */ + if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) { + optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; + optionrom_pcir_t *pcir; + size_t vbt_size; + size_t fake_oprom_size; + struct device *dev; + + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + + memset(oh, 0, 8192); + + oh->signature = OPROM_SIGNATURE; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->indicator = 0x80; + + vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; + } return 1; }

1 0

New patch to review for coreboot: 1b7a68d Board lenovo t60 & x60: Non-local header treated as local
by HAOUAS Elyes 02 Jun '14

02 Jun '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5919 -gerrit commit 1b7a68d3a55ae3e477ee716081dbdf95eca62320 Author: Elyes <ehaouas(a)noos.fr> Date: Mon Jun 2 19:07:17 2014 +0200 Board lenovo t60 & x60: Non-local header treated as local Change-Id: I8629cd3bb59943f25e53cb06d52c192a2f405166 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/lenovo/t60/acpi_tables.c | 2 +- src/mainboard/lenovo/t60/dock.c | 8 ++++---- src/mainboard/lenovo/t60/romstage.c | 6 +++--- src/mainboard/lenovo/t60/smihandler.c | 4 ++-- src/mainboard/lenovo/x60/acpi_tables.c | 2 +- src/mainboard/lenovo/x60/dock.c | 4 ++-- src/mainboard/lenovo/x60/romstage.c | 6 +++--- src/mainboard/lenovo/x60/smihandler.c | 4 ++-- 8 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index f6ed4ae..2c8ff8c 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -35,7 +35,7 @@ extern const unsigned char AmlCode[]; unsigned long acpi_create_slic(unsigned long current); #endif -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> static void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index b01f8e8..e319ec3 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -24,10 +24,10 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include "superio/nsc/pc87384/pc87384.h" -#include "ec/acpi/ec.h" -#include "ec/lenovo/pmh7/pmh7.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <superio/nsc/pc87384/pc87384.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/pmh7/pmh7.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #define DLPC_CONTROL 0x164c diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index dae917c..4697ef9 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -34,9 +34,9 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "dock.h" void setup_ich7_gpios(void) diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 093996b..5d40e7f 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -22,8 +22,8 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/nvs.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/nvs.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include <ec/acpi/ec.h> #include "dock.h" #include "smi.h" diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index f6ed4ae..2c8ff8c 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -35,7 +35,7 @@ extern const unsigned char AmlCode[]; unsigned long acpi_create_slic(unsigned long current); #endif -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> static void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index 1f85281..5ddb8aa 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -25,8 +25,8 @@ #include <delay.h> #include <arch/io.h> #include "dock.h" -#include "southbridge/intel/i82801gx/i82801gx.h" -#include "superio/nsc/pc87392/pc87392.h" +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/nsc/pc87392/pc87392.h> static void dlpc_write_register(int reg, int value) { diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1198fb2..b355799 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -34,9 +34,9 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "dock.h" void setup_ich7_gpios(void) diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index 090f037..89b3d97 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -22,8 +22,8 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/nvs.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/nvs.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h>

1 0

New patch to review for coreboot: ac684a5 Board Intel/d945gclf: Non-local header treated as local
by HAOUAS Elyes 02 Jun '14

02 Jun '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5918 -gerrit commit ac684a5e81d160970f0d46531ab46606b542cae9 Author: Elyes <ehaouas(a)noos.fr> Date: Mon Jun 2 18:57:27 2014 +0200 Board Intel/d945gclf: Non-local header treated as local Change-Id: I7a1bdc78ef68b3d4dc1bf6a9616a49b1733ac76d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/intel/d945gclf/acpi_tables.c | 2 +- src/mainboard/intel/d945gclf/romstage.c | 8 ++++---- src/mainboard/intel/d945gclf/smihandler.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c index fba2b42..82aba40 100644 --- a/src/mainboard/intel/d945gclf/acpi_tables.c +++ b/src/mainboard/intel/d945gclf/acpi_tables.c @@ -34,7 +34,7 @@ extern const unsigned char AmlCode[]; unsigned long acpi_create_slic(unsigned long current); #endif -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> static void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 69d4232..b93e8c0 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -27,14 +27,14 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <cbmem.h> -#include "superio/smsc/lpc47m15x/lpc47m15x.h" +#include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include "superio/smsc/lpc47m15x/early_serial.c" -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) diff --git a/src/mainboard/intel/d945gclf/smihandler.c b/src/mainboard/intel/d945gclf/smihandler.c index 0643ad9..2542a70 100644 --- a/src/mainboard/intel/d945gclf/smihandler.c +++ b/src/mainboard/intel/d945gclf/smihandler.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler

1 0

Patch merged into coreboot/master: fd2501b i945: Fix TSEG size allocation for get_top_of_ram()
by gerrit＠coreboot.org 02 Jun '14

02 Jun '14

the following patch was just integrated into master: commit fd2501b3f1af1d649484dcdae562cd0694eb61ee Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat May 31 16:36:29 2014 +0300 i945: Fix TSEG size allocation for get_top_of_ram() Seems boards with i945 had TSEG disabled so this had gone unnoticed. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Change-Id: I6a00ea9121847ce2fede22538e1b53a870d761f1 Reviewed-on: http://review.coreboot.org/5892 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5892 for details. -gerrit

1 0

Patch merged into coreboot/master: 15935eb i945: Fix resource bases for UMA and TSEG
by gerrit＠coreboot.org 02 Jun '14

02 Jun '14

the following patch was just integrated into master: commit 15935ebe242bcdd6c84f5f2e9fb8a573e69a1c60 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat May 31 16:07:14 2014 +0300 i945: Fix resource bases for UMA and TSEG TSEG appears in memory below graphics UMA region. Seems boards with i945 had TSEG disabled, so the incorrect order did not make a difference. Change-Id: Ie293aab17b60b5f06a871a773cd42577c7dc7c7b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5891 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5891 for details. -gerrit

1 0

New patch to review for coreboot: 894c656 mainboard/jetway/nf81-t56n-lf: Implement Super I/O DSDT
by Edward O'Callaghan 02 Jun '14

02 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5917 -gerrit commit 894c65617eb3e8bf6fd2e9604c99dcecb1bfa837 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jun 2 16:13:18 2014 +1000 mainboard/jetway/nf81-t56n-lf: Implement Super I/O DSDT NOTFORMERGE Change-Id: Ica356352774f2d095faa3a7a7b3679db760b2ca5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl | 938 ++++++++++++++++++++- 1 file changed, 937 insertions(+), 1 deletion(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl index 6dcb877..e6dd158 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl @@ -19,4 +19,940 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "../../../../drivers/pc80/ps2_controller.asl" +Name (SP1O, 0x2E) +Name (IO1B, 0x0A00) +Name (IO1L, 0x20) +Name (IO2B, 0x0225) +Name (IO2L, 0x10) +Name (IO3B, Zero) +Name (IO3L, Zero) +Name (IOES, Zero) + +Device (SIO1) +{ + Name (_HID, EisaId ("PNP0C02")) // _HID: Hardware ID + Name (_UID, 0x0111) // _UID: Unique ID + Name (CRS, ResourceTemplate () + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x00, // Alignment + 0x00, // Length + _Y15) + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x00, // Alignment + 0x00, // Length + _Y16) + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x00, // Alignment + 0x00, // Length + _Y17) + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x00, // Alignment + 0x00, // Length + ) + }) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + If (LAnd (LLess (SP1O, 0x03F0), LGreater (SP1O, 0xF0))) + { + CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y15._MIN, GPI0) // _MIN: Minimum Base Address + CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y15._MAX, GPI1) // _MAX: Maximum Base Address + CreateByteField (CRS, \_SB.PCI0.SBRG.SIO1._Y15._LEN, GPIL) // _LEN: Length + Store (SP1O, GPI0) + Store (SP1O, GPI1) + Store (0x02, GPIL) + } + + If (IO1B) + { + CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y16._MIN, GP10) // _MIN: Minimum Base Address + CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y16._MAX, GP11) // _MAX: Maximum Base Address + CreateByteField (CRS, \_SB.PCI0.SBRG.SIO1._Y16._LEN, GPL1) // _LEN: Length + Store (IO1B, GP10) + Store (IO1B, GP11) + Store (IO1L, GPL1) + } + + If (IO2B) + { + CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y17._MIN, GP20) // _MIN: Minimum Base Address + CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y17._MAX, GP21) // _MAX: Maximum Base Address + CreateByteField (CRS, \_SB.PCI0.SBRG.SIO1._Y17._LEN, GPL2) // _LEN: Length + Store (IO2B, GP20) + Store (IO2B, GP21) + Store (IO2L, GPL2) + } + + If (IO3B) + { + CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y17._MIN, GP30) // _MIN: Minimum Base Address + CreateWordField (CRS, \_SB.PCI0.SBRG.SIO1._Y17._MAX, GP31) // _MAX: Maximum Base Address + CreateByteField (CRS, \_SB.PCI0.SBRG.SIO1._Y17._LEN, GPL3) // _LEN: Length + Store (IO3B, GP30) + Store (IO2B, GP31) + Store (IO3L, GPL3) + } + + Return (CRS) + } + + Name (DCAT, Package (0x15) + { + One, + 0x02, + 0x03, + Zero, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x05, + 0xFF, + 0xFF, + 0xFF, + 0x05, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0xFF + }) + Mutex (MUT0, 0x00) + Method (ENFG, 1, NotSerialized) + { + Acquire (MUT0, 0x0FFF) + Store (0x87, INDX) + Store (0x87, INDX) + Store (Arg0, LDN) + } + + Method (EXFG, 0, NotSerialized) + { + Store (0xAA, INDX) + Release (MUT0) + } + + Method (LPTM, 0, NotSerialized) + { + ENFG (CGLD (0x02)) + And (OPT0, 0x02, Local0) + EXFG () + Return (Local0) + } + + Method (UHID, 1, NotSerialized) + { + ENFG (CGLD (Arg0)) + And (OPT1, 0x80, Local0) + EXFG () + If (Local0) + { + Return (0x1005D041) + } + Else + { + Return (0x0105D041) + } + } + + OperationRegion (IOID, SystemIO, SP1O, 0x02) + Field (IOID, ByteAcc, NoLock, Preserve) + { + INDX, 8, + DATA, 8 + } + + IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + LDN, 8, + Offset (0x21), + SCF1, 8, + SCF2, 8, + SCF3, 8, + SCF4, 8, + SCF5, 8, + SCF6, 8, + Offset (0x29), + CKCF, 8, + Offset (0x30), + ACTR, 8, + Offset (0x60), + IOAH, 8, + IOAL, 8, + IOH2, 8, + IOL2, 8, + Offset (0x70), + INTR, 8, + Offset (0x74), + DMCH, 8, + Offset (0xE0), + RGE0, 8, + RGE1, 8, + RGE2, 8, + RGE3, 8, + RGE4, 8, + RGE5, 8, + RGE6, 8, + RGE7, 8, + RGE8, 8, + RGE9, 8, + Offset (0xF0), + OPT0, 8, + OPT1, 8, + OPT2, 8, + OPT3, 8, + OPT4, 8, + OPT5, 8, + OPT6, 8, + OPT7, 8, + OPT8, 8, + OPT9, 8 + } + + OperationRegion (RNTR, SystemIO, IO2B, IO2L) + Field (RNTR, ByteAcc, NoLock, Preserve) + { + PMES, 8, + Offset (0x04), + PMEE, 1, + Offset (0x05), + Offset (0x08), + PMS3, 8, + PMS2, 8, + PMS1, 8, + Offset (0x0C), + PME3, 8, + PME2, 8, + PME1, 8 + } + + Method (CGLD, 1, NotSerialized) + { + Return (DerefOf (Index (DCAT, Arg0))) + } + + Method (DSTA, 1, NotSerialized) + { + ENFG (CGLD (Arg0)) + Store (ACTR, Local0) + EXFG () + If (LEqual (Local0, 0xFF)) + { + Return (Zero) + } + + And (Local0, One, Local0) + If (LGreaterEqual (Arg0, 0x10)) + { + Or (IOES, ShiftLeft (Local0, And (Arg0, 0x0F)), IOES) + } + Else + { + Or (IOST, ShiftLeft (Local0, Arg0), IOST) + } + + If (Local0) + { + Return (0x0F) + } + Else + { + If (LGreaterEqual (Arg0, 0x10)) + { + Store (IOES, Local0) + } + Else + { + Store (IOST, Local0) + } + + And (Arg0, 0x0F, Local1) + If (And (ShiftLeft (One, Local1), Local0)) + { + Return (0x0D) + } + Else + { + Return (Zero) + } + } + } + + Method (DCNT, 2, NotSerialized) + { + ENFG (CGLD (Arg0)) + If (LAnd (LLess (DMCH, 0x04), LNotEqual (And (DMCH, 0x03, + Local1), Zero))) + { + RDMA (Arg0, Arg1, Increment (Local1)) + } + + Store (Arg1, ACTR) + ShiftLeft (IOAH, 0x08, Local1) + Or (IOAL, Local1, Local1) + RRIO (Arg0, Arg1, Local1, 0x08) + EXFG () + } + + Name (CRS1, ResourceTemplate () + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x01, // Alignment + 0x00, // Length + _Y1A) + IRQNoFlags (_Y18) + {} + DMA (Compatibility, NotBusMaster, Transfer8, _Y19) + {} + }) + CreateWordField (CRS1, \_SB.PCI0.SBRG.SIO1._Y18._INT, IRQM) // _INT: Interrupts + CreateByteField (CRS1, \_SB.PCI0.SBRG.SIO1._Y19._DMA, DMAM) // _DMA: Direct Memory Access + CreateWordField (CRS1, \_SB.PCI0.SBRG.SIO1._Y1A._MIN, IO11) // _MIN: Minimum Base Address + CreateWordField (CRS1, \_SB.PCI0.SBRG.SIO1._Y1A._MAX, IO12) // _MAX: Maximum Base Address + CreateByteField (CRS1, \_SB.PCI0.SBRG.SIO1._Y1A._LEN, LEN1) // _LEN: Length + Name (CRS2, ResourceTemplate () + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x01, // Alignment + 0x00, // Length + _Y1D) + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x01, // Alignment + 0x00, // Length + _Y1E) + IRQNoFlags (_Y1B) + {} + DMA (Compatibility, NotBusMaster, Transfer8, _Y1C) + {2} + }) + CreateWordField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1B._INT, IRQE) // _INT: Interrupts + CreateByteField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1C._DMA, DMAE) // _DMA: Direct Memory Access + CreateWordField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1D._MIN, IO21) // _MIN: Minimum Base Address + CreateWordField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1D._MAX, IO22) // _MAX: Maximum Base Address + CreateByteField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1D._LEN, LEN2) // _LEN: Length + CreateWordField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1E._MIN, IO31) // _MIN: Minimum Base Address + CreateWordField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1E._MAX, IO32) // _MAX: Maximum Base Address + CreateByteField (CRS2, \_SB.PCI0.SBRG.SIO1._Y1E._LEN, LEN3) // _LEN: Length + Name (CRS4, ResourceTemplate () + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x01, // Alignment + 0x00, // Length + _Y20) + IRQ (Edge, ActiveLow, Shared, _Y1F) + {} + }) + CreateWordField (CRS4, \_SB.PCI0.SBRG.SIO1._Y1F._INT, IRQL) // _INT: Interrupts + CreateWordField (CRS4, \_SB.PCI0.SBRG.SIO1._Y20._MIN, IOHL) // _MIN: Minimum Base Address + CreateWordField (CRS4, \_SB.PCI0.SBRG.SIO1._Y20._MAX, IORL) // _MAX: Maximum Base Address + CreateByteField (CRS4, \_SB.PCI0.SBRG.SIO1._Y20._ALN, ALMN) // _ALN: Alignment + CreateByteField (CRS4, \_SB.PCI0.SBRG.SIO1._Y20._LEN, LENG) // _LEN: Length + Method (DCRS, 2, NotSerialized) + { + ENFG (CGLD (Arg0)) + ShiftLeft (IOAH, 0x08, IO11) + Or (IOAL, IO11, IO11) + Store (IO11, IO12) + Store (0x08, LEN1) + If (INTR) + { + ShiftLeft (One, INTR, IRQM) + } + Else + { + Store (Zero, IRQM) + } + + If (LOr (LGreater (DMCH, 0x03), LEqual (Arg1, Zero))) + { + Store (Zero, DMAM) + } + Else + { + And (DMCH, 0x03, Local1) + ShiftLeft (One, Local1, DMAM) + } + + EXFG () + Return (CRS1) + } + + Method (DCR2, 2, NotSerialized) + { + ENFG (CGLD (Arg0)) + ShiftLeft (IOAH, 0x08, IO21) + Or (IOAL, IO21, IO21) + Store (IO21, IO22) + Store (0x08, LEN2) + ShiftLeft (IOH2, 0x08, IO31) + Or (IOL2, IO31, IO31) + Store (IO21, IO32) + Store (0x08, LEN3) + If (INTR) + { + ShiftLeft (One, INTR, IRQE) + } + Else + { + Store (Zero, IRQE) + } + + If (LOr (LGreater (DMCH, 0x03), LEqual (Arg1, Zero))) + { + Store (Zero, DMAE) + } + Else + { + And (DMCH, 0x03, Local1) + ShiftLeft (One, Local1, DMAE) + } + + EXFG () + Return (CRS2) + } + + Method (DCR4, 2, NotSerialized) + { + ENFG (CGLD (Arg0)) + ShiftLeft (IOAH, 0x08, IOHL) + Or (IOAL, IOHL, IOHL) + Store (IOHL, IORL) + Store (0x08, LENG) + If (INTR) + { + And (INTR, 0x0F, INTR) + ShiftLeft (One, INTR, IRQL) + } + Else + { + Store (Zero, IRQL) + } + + EXFG () + Return (CRS4) + } + + Method (DSRS, 2, NotSerialized) + { + If (LEqual (Arg1, 0x02)) + { + If (LPTM ()) + { + DSR2 (Arg0, Arg1) + } + } + Else + { + CreateWordField (Arg0, 0x09, IRQM) + CreateByteField (Arg0, 0x0C, DMAM) + CreateWordField (Arg0, 0x02, IO11) + ENFG (CGLD (Arg1)) + And (IO11, 0xFF, IOAL) + ShiftRight (IO11, 0x08, IOAH) + If (IRQM) + { + FindSetRightBit (IRQM, Local0) + Subtract (Local0, One, INTR) + } + Else + { + Store (Zero, INTR) + } + + If (DMAM) + { + FindSetRightBit (DMAM, Local0) + Subtract (Local0, One, DMCH) + } + Else + { + Store (0x04, DMCH) + } + + EXFG () + DCNT (Arg1, One) + Store (Arg1, Local2) + If (LGreater (Local2, Zero)) + { + Subtract (Local2, One, Local2) + } + } + } + + Method (DSR2, 2, NotSerialized) + { + CreateWordField (Arg0, 0x11, IRQT) + CreateByteField (Arg0, 0x14, DMAT) + CreateWordField (Arg0, 0x02, IOT1) + CreateWordField (Arg0, 0x0A, IOT2) + ENFG (CGLD (Arg1)) + And (IOT1, 0xFF, IOAL) + ShiftRight (IOT1, 0x08, IOAH) + And (IOT2, 0xFF, IOL2) + ShiftRight (IOT2, 0x08, IOH2) + If (IRQT) + { + FindSetRightBit (IRQT, Local0) + Subtract (Local0, One, INTR) + } + Else + { + Store (Zero, INTR) + } + + If (DMAT) + { + FindSetRightBit (DMAT, Local0) + Subtract (Local0, One, DMCH) + } + Else + { + Store (0x04, DMCH) + } + + EXFG () + DCNT (Arg1, One) + Store (Arg1, Local2) + If (LGreater (Local2, Zero)) + { + Subtract (Local2, One, Local2) + } + } + + Method (DSR4, 2, NotSerialized) + { + CreateWordField (Arg0, 0x02, IOHL) + CreateWordField (Arg0, 0x09, IRQL) + ENFG (CGLD (Arg1)) + And (IOHL, 0xFF, IOAL) + ShiftRight (IOHL, 0x08, IOAH) + If (IRQL) + { + FindSetRightBit (IRQL, Local0) + Subtract (Local0, One, INTR) + } + Else + { + Store (Zero, INTR) + } + + EXFG () + DCNT (Arg1, One) + Store (Arg1, Local2) + If (LGreater (Local2, Zero)) + { + Subtract (Local2, One, Local2) + } + } +} + +Name (PMFG, Zero) +Method (SIOS, 1, NotSerialized) +{ + Store ("SIOS", Debug) + ^SIO1.ENFG (0x06) + Or (^SIO1.RGE1, 0x20, ^SIO1.RGE1) +} + +Method (SIOW, 1, NotSerialized) +{ + Store ("SIOW", Debug) +} + +Device (PS2K) +{ + Name (_HID, EisaId ("PNP0303")) // _HID: Hardware ID + Name (_CID, EisaId ("PNP030B")) // _CID: Compatible ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (And (IOST, 0x0400)) + { + Return (0x0F) + } + Else + { + Return (Zero) + } + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + FixedIO ( + 0x0060, // Address + 0x01, // Length + ) + FixedIO ( + 0x0064, // Address + 0x01, // Length + ) + IRQNoFlags () + {1} + } + EndDependentFn () + }) + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + Store (Arg0, KBFG) + } +} + +Scope (\) +{ + Name (KBFG, One) +} + +Method (PS2K._PRW, 0, NotSerialized) // _PRW: Power Resources for Wake +{ + Return (GPRW (0x1D, 0x03)) +} + +Device (PS2M) +{ + Name (_HID, EisaId ("PNP0F03")) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0F13")) // _CID: Compatible ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (And (IOST, 0x4000)) + { + Return (0x0F) + } + Else + { + Return (Zero) + } + } + + Name (CRS1, ResourceTemplate () + { + IRQNoFlags () + {12} + }) + Name (CRS2, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {12} + }) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + If (And (IOST, 0x0400)) + { + Return (CRS1) + } + Else + { + Return (CRS2) + } + } + + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IRQNoFlags () + {12} + } + EndDependentFn () + }) + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + Store (Arg0, MSFG) + } +} + +Scope (\) +{ + Name (MSFG, One) +} + +Method (PS2M._PRW, 0, NotSerialized) // _PRW: Power Resources for Wake +{ + Return (GPRW (0x1D, 0x03)) +} + +Device (UAR1) +{ + Name (_HID, EisaId ("PNP0501")) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (^^SIO1.DSTA (Zero)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + ^^SIO1.DCNT (Zero, Zero) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (^^SIO1.DCRS (Zero, Zero)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + ^^SIO1.DSRS (Arg0, Zero) + } + + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + StartDependentFnNoPri () + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {3,4,5,6,7,9,10,11,12} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + StartDependentFnNoPri () + { + IO (Decode16, + 0x02F8, // Range Minimum + 0x02F8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {3,4,5,6,7,9,10,11,12} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + StartDependentFnNoPri () + { + IO (Decode16, + 0x03E8, // Range Minimum + 0x03E8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {3,4,5,6,7,9,10,11,12} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + StartDependentFnNoPri () + { + IO (Decode16, + 0x02E8, // Range Minimum + 0x02E8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {3,4,5,6,7,9,10,11,12} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {} + } + EndDependentFn () + }) +} + +Device (CIR) +{ + Name (_UID, Zero) // _UID: Unique ID + Name (_HID, EisaId ("FIT0002")) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IRST (0x08)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + ^^SIO1.DCNT (0x08, Zero) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IRCR (0x08)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + IRSR (Arg0, 0x08) + } + + Method (IRST, 1, NotSerialized) + { + ^^SIO1.ENFG (^^SIO1.CGLD (Arg0)) + If (^^SIO1.ACTR) + { + Store (0x0F, Local0) + } + Else + { + If (^^SIO1.IOAH) + { + Store (0x0D, Local0) + } + Else + { + Store (Zero, Local0) + } + } + + ^^SIO1.EXFG () + Return (Local0) + } + + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IO (Decode16, + 0x4700, // Range Minimum + 0x4700, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {5} + } + StartDependentFnNoPri () + { + IO (Decode16, + 0x4700, // Range Minimum + 0x4700, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {3,4,5,6,7,9,10,11,12} + } + StartDependentFnNoPri () + { + IO (Decode16, + 0x02E0, // Range Minimum + 0x02E0, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {3,4,5,6,7,9,10,11,12} + } + StartDependentFnNoPri () + { + IO (Decode16, + 0x0298, // Range Minimum + 0x0298, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {3,4,5,6,7,9,10,11,12} + } + EndDependentFn () + }) + Name (PBUF, ResourceTemplate () + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x01, // Alignment + 0x08, // Length + _Y21) + IRQNoFlags () + {0} + }) + Method (IRCR, 1, NotSerialized) + { + CreateByteField (PBUF, \_SB.PCI0.SBRG.CIR._Y21._MIN, IOLO) // _MIN: Minimum Base Address + CreateByteField (PBUF, 0x03, IOHI) + CreateWordField (PBUF, \_SB.PCI0.SBRG.CIR._Y21._MIN, IOHL) // _MIN: Minimum Base Address + CreateWordField (PBUF, \_SB.PCI0.SBRG.CIR._Y21._MAX, IORL) // _MAX: Maximum Base Address + CreateByteField (PBUF, \_SB.PCI0.SBRG.CIR._Y21._ALN, ALMN) // _ALN: Alignment + CreateByteField (PBUF, \_SB.PCI0.SBRG.CIR._Y21._LEN, LENG) // _LEN: Length + CreateWordField (PBUF, 0x05, IRQL) + ^^SIO1.ENFG (^^SIO1.CGLD (Arg0)) + Store (^^SIO1.IOAH, IOHI) + Store (^^SIO1.IOAL, IOLO) + Store (IOHL, IORL) + Store (One, ALMN) + Store (0x08, LENG) + Store (One, Local0) + ShiftLeft (Local0, ^^SIO1.INTR, IRQL) + ^^SIO1.EXFG () + Return (PBUF) + } + + Method (IRSR, 2, NotSerialized) + { + CreateByteField (Arg0, 0x02, POLB) + CreateByteField (Arg0, 0x03, POHB) + CreateWordField (Arg0, 0x05, PIRQ) + ^^SIO1.ENFG (^^SIO1.CGLD (Arg1)) + Store (POLB, ^^SIO1.IOAL) + Store (POHB, ^^SIO1.IOAH) + FindSetRightBit (PIRQ, Local0) + Subtract (Local0, One, ^^SIO1.INTR) + Store (One, ^^SIO1.ACTR) + ^^SIO1.EXFG () + } +}

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Patch set updated for coreboot: 5f666c8 superio/smsc/kbc1100: Virtually rewrite support and fix mainboards
by Edward O'Callaghan 02 Jun '14

02 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5916 -gerrit commit 5f666c87a0b11072f33c87f98a1b9666e3d8a173 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jun 2 12:20:11 2014 +1000 superio/smsc/kbc1100: Virtually rewrite support and fix mainboards 1. Remove #include .c in romstage. 2. Make romstage component symbols linker-time. 3. Provide header guards and prototypes in superio romstage support. 4. Correct function type-signatures to be static/non-static where appropriate, avoid 'pretend optimisations' by unnecessarily inlining functions. 5. Separate out UART enable from various other PNP hard coding Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/inagua/Kconfig | 4 -- src/mainboard/amd/inagua/romstage.c | 7 ++- src/mainboard/amd/torpedo/Kconfig | 4 -- src/mainboard/amd/torpedo/romstage.c | 6 +- src/superio/smsc/kbc1100/Makefile.inc | 1 + src/superio/smsc/kbc1100/early_init.c | 80 +++++++++++++++++++++++++++ src/superio/smsc/kbc1100/kbc1100.h | 10 ++++ src/superio/smsc/kbc1100/kbc1100_early_init.c | 75 ------------------------- 8 files changed, 100 insertions(+), 87 deletions(-) diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 1e11f9f..279c7ef 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -69,10 +69,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x2e - config DRIVERS_PS2_KEYBOARD bool default y diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index a304d31..a7b8a40 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -33,11 +33,13 @@ #include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/smsc/kbc1100/kbc1100_early_init.c" +#include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h" +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -57,7 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - kbc1100_early_init(CONFIG_SIO_PORT); + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 62ce043..6013df7 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -79,10 +79,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x2e - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index dcab52b..e3416c7 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -30,13 +30,14 @@ #include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/smsc/kbc1100/kbc1100_early_init.c" +#include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" #include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> #include "platform_cfg.h" +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -57,7 +58,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x31); - kbc1100_early_init(CONFIG_SIO_PORT); + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); post_code(0x32); post_code(0x33); diff --git a/src/superio/smsc/kbc1100/Makefile.inc b/src/superio/smsc/kbc1100/Makefile.inc index 603d24e..c3385a6 100644 --- a/src/superio/smsc/kbc1100/Makefile.inc +++ b/src/superio/smsc/kbc1100/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += superio.c diff --git a/src/superio/smsc/kbc1100/early_init.c b/src/superio/smsc/kbc1100/early_init.c new file mode 100644 index 0000000..efb76a0 --- /dev/null +++ b/src/superio/smsc/kbc1100/early_init.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> + +#include "kbc1100.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +void kbc1100_early_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + /* Serial IRQ enabled */ + u16 port = dev >> 8; + outb(0x25, port); + outb(0x04, port + 1); + /* .. */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} + +void kbc1100_early_init(u16 port) +{ + device_t dev; + dev = PNP_DEV (port, KBC1100_KBC); + pnp_enter_conf_state(dev); + + /* Enable keyboard */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + /* Enable EC Channel 0 */ + dev = PNP_DEV (port, KBC1100_EC0); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); + + /* disable the 1s timer */ + outb(0xE7, 0x64); +} diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h index 3fe6327..2b588f9 100644 --- a/src/superio/smsc/kbc1100/kbc1100.h +++ b/src/superio/smsc/kbc1100/kbc1100.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_KBC1100_H +#define SUPERIO_SMSC_KBC1100_H + +#include <arch/io.h> +#include <stdint.h> + #define KBC1100_PM1 1 /* PM1 */ #define SMSCSUPERIO_SP1 4 /* Com1 */ #define SMSCSUPERIO_SP2 5 /* Com2 */ @@ -29,4 +36,7 @@ #define KBC1100_EC1 0x0D /* EC Channel 1 */ #define KBC1100_EC2 0x0E /* EC Channel 2 */ +void kbc1100_early_serial(device_t dev, u16 iobase); +void kbc1100_early_init(u16 port); +#endif /* SUPERIO_SMSC_KBC1100_H */ diff --git a/src/superio/smsc/kbc1100/kbc1100_early_init.c b/src/superio/smsc/kbc1100/kbc1100_early_init.c deleted file mode 100644 index 5d74c32..0000000 --- a/src/superio/smsc/kbc1100/kbc1100_early_init.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ - -#include <arch/io.h> -#include "kbc1100.h" - -static inline void pnp_enter_conf_state(device_t dev) -{ - unsigned port = dev>>8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - unsigned port = dev>>8; - outb(0xaa, port); -} - -static inline void kbc1100_early_init(unsigned port) -{ - device_t dev; - dev = PNP_DEV (port, KBC1100_KBC); - - pnp_enter_conf_state(dev); - - /* Serial IRQ enabled */ - outb(0x25, port); - outb(0x04, port + 1); - - /* Enable SMSC UART 0 */ - dev = PNP_DEV (port, SMSCSUPERIO_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); - pnp_set_enable(dev, 1); - - /* Enable keyboard */ - dev = PNP_DEV (port, KBC1100_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ - pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ - pnp_set_enable(dev, 1); - - /* Enable EC Channel 0 */ - dev = PNP_DEV (port, KBC1100_EC0); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); - - pnp_exit_conf_state(dev); - - /* disable the 1s timer */ - outb(0xE7, 0x64); -} -

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coreboot-gerrit June 2014