coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

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922 discussions

Patch set updated for coreboot: 2bbcdd3 Intel 945 boards: romstage.c: Use define for `BSM`
by Paul Menzel 05 Jun '14

05 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5929 -gerrit commit 2bbcdd3771efe471dbbc785847796ff51499cb6e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 08:50:17 2014 +0200 Intel 945 boards: romstage.c: Use define for `BSM` Change-Id: Ia58d8b410a145f27f0b267c115714580c366e063 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/getac/p470/romstage.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/intel/d945gclf/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 2 +- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index a081a8a..33b6726 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -347,7 +347,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 418b6e4..9dfd364 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -298,7 +298,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 69d4232..a0621ce 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -258,7 +258,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 4acd734..0ad7a2a 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -410,7 +410,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index dae917c..c5bb2f3 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -309,7 +309,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1198fb2..1fed5f5 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -311,7 +311,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index ad323f5..2af294c 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -334,7 +334,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000);

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New patch to review for coreboot: 1a7e9cf gm45: Move spd address map to board-specific config.
by Vladimir Serbinenko 05 Jun '14

05 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5931 -gerrit commit 1a7e9cf474bc1cf5151df80fd6da0f0dcabbc6e8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jun 5 09:14:48 2014 +0200 gm45: Move spd address map to board-specific config. Change-Id: I8f45a821ecd414dbd0129ae6d583d4e7dc06bc5a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/roda/rk9/romstage.c | 2 + src/northbridge/intel/gm45/gm45.h | 1 + src/northbridge/intel/gm45/raminit.c | 81 +++++++++++++++++++----------------- 3 files changed, 46 insertions(+), 38 deletions(-) diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 90392b9..69a5875 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -170,6 +170,8 @@ void main(unsigned long bist) /* RAM initialization */ enter_raminit_or_reset(); get_gmch_info(&sysinfo); + sysinfo.spd_map[0] = 0x50; + sysinfo.spd_map[2] = 0x52; raminit(&sysinfo, s3resume); raminit_thermal(&sysinfo); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 227baef..edcb56b 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -143,6 +143,7 @@ typedef struct { int spd_type; timings_t selected_timings; dimminfo_t dimms[2]; + u8 spd_map[4]; } sysinfo_t; #define TOTAL_CHANNELS 2 #define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d607f84..d795ab7 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -234,61 +234,62 @@ void enter_raminit_or_reset(void) /* For a detected DIMM, test the value of an SPD byte to match the expected value after masking some bits. */ -static int test_dimm(int dimm, int addr, int bitmask, int expected) +static int test_dimm(sysinfo_t *const sysinfo, + int dimm, int addr, int bitmask, int expected) { - return (smbus_read_byte(DIMM0 + dimm, addr) & bitmask) == expected; + return (smbus_read_byte(sysinfo->spd_map[dimm], addr) & bitmask) == expected; } /* This function dies if dimm is unsuitable for the chipset. */ -static void verify_ddr3_dimm(int dimm) +static void verify_ddr3_dimm(sysinfo_t *const sysinfo, int dimm) { - if (!test_dimm(dimm, 3, 15, 3)) + if (!test_dimm(sysinfo, dimm, 3, 15, 3)) die("Chipset only supports SO-DIMM\n"); - if (!test_dimm(dimm, 8, 0x18, 0)) + if (!test_dimm(sysinfo, dimm, 8, 0x18, 0)) die("Chipset doesn't support ECC RAM\n"); - if (!test_dimm(dimm, 7, 0x38, 0) && - !test_dimm(dimm, 7, 0x38, 8)) + if (!test_dimm(sysinfo, dimm, 7, 0x38, 0) && + !test_dimm(sysinfo, dimm, 7, 0x38, 8)) die("Chipset wants single or double sided DIMMs\n"); - if (!test_dimm(dimm, 7, 7, 1) && - !test_dimm(dimm, 7, 7, 2)) + if (!test_dimm(sysinfo, dimm, 7, 7, 1) && + !test_dimm(sysinfo, dimm, 7, 7, 2)) die("Chipset requires x8 or x16 width\n"); - if (!test_dimm(dimm, 4, 0x0f, 0) && - !test_dimm(dimm, 4, 0x0f, 1) && - !test_dimm(dimm, 4, 0x0f, 2) && - !test_dimm(dimm, 4, 0x0f, 3)) + if (!test_dimm(sysinfo, dimm, 4, 0x0f, 0) && + !test_dimm(sysinfo, dimm, 4, 0x0f, 1) && + !test_dimm(sysinfo, dimm, 4, 0x0f, 2) && + !test_dimm(sysinfo, dimm, 4, 0x0f, 3)) die("Chipset requires 256Mb, 512Mb, 1Gb or 2Gb chips."); - if (!test_dimm(dimm, 4, 0x70, 0)) + if (!test_dimm(sysinfo, dimm, 4, 0x70, 0)) die("Chipset requires 8 banks on DDR3\n"); /* How to check if burst length is 8? Other values are not supported, are they even possible? */ - if (!test_dimm(dimm, 10, 0xff, 1)) + if (!test_dimm(sysinfo, dimm, 10, 0xff, 1)) die("Code assumes 1/8ns MTB\n"); - if (!test_dimm(dimm, 11, 0xff, 8)) + if (!test_dimm(sysinfo, dimm, 11, 0xff, 8)) die("Code assumes 1/8ns MTB\n"); - if (!test_dimm(dimm, 62, 0x9f, 0) && - !test_dimm(dimm, 62, 0x9f, 1) && - !test_dimm(dimm, 62, 0x9f, 2) && - !test_dimm(dimm, 62, 0x9f, 3) && - !test_dimm(dimm, 62, 0x9f, 5)) + if (!test_dimm(sysinfo, dimm, 62, 0x9f, 0) && + !test_dimm(sysinfo, dimm, 62, 0x9f, 1) && + !test_dimm(sysinfo, dimm, 62, 0x9f, 2) && + !test_dimm(sysinfo, dimm, 62, 0x9f, 3) && + !test_dimm(sysinfo, dimm, 62, 0x9f, 5)) die("Only raw card types A, B, C, D and F are supported.\n"); } /* For every detected DIMM, test if it's suitable for the chipset. */ -static void verify_ddr3(int mask) +static void verify_ddr3(sysinfo_t *const sysinfo, int mask) { int cur = 0; while (mask) { if (mask & 1) { - verify_ddr3_dimm(cur); + verify_ddr3_dimm(sysinfo, cur); } mask >>= 1; cur++; @@ -320,14 +321,15 @@ typedef struct { * This function collects RAM characteristics from SPD, assuming that RAM * is generally within chipset's requirements, since verify_ddr3() passed. */ -static void collect_ddr3(spdinfo_t *const config) +static void collect_ddr3(sysinfo_t *const sysinfo, spdinfo_t *const config) { int mask = config->dimm_mask; int cur = 0; while (mask != 0) { - if (mask & 1) { + /* FIXME: support several dimms on same channel. */ + if ((mask & 1) && sysinfo->spd_map[2 * cur]) { int tmp; - const int smb_addr = DIMM0 + cur*2; + const int smb_addr = sysinfo->spd_map[2 * cur]; config->channel[cur].rows = ((smbus_read_byte(smb_addr, 5) >> 3) & 7) + 12; config->channel[cur].cols = (smbus_read_byte(smb_addr, 5) & 7) + 9; @@ -357,7 +359,7 @@ static void collect_ddr3(spdinfo_t *const config) config->channel[cur].raw_card = smbus_read_byte(smb_addr, 62) & 0x1f; } cur++; - mask >>= 2; /* Only every other address is used. */ + mask >>= 2; } } @@ -590,17 +592,20 @@ static void collect_dimm_config(sysinfo_t *const sysinfo) spdinfo.dimm_mask = 0; sysinfo->spd_type = 0; - /* at most 2 dimms, on even slots */ - for (i = 0; i < 4; i += 2) { - const u8 spd = smbus_read_byte(DIMM0 + i, 2); - if ((spd == 7) || (spd == 8) || (spd == 0xb)) { - spdinfo.dimm_mask |= 1 << i; - if (sysinfo->spd_type && sysinfo->spd_type != spd) { - die("Multiple types of DIMM installed in the system, don't do that!\n"); + for (i = 0; i < 4; i++) + if (sysinfo->spd_map[i]) { + const u8 spd = smbus_read_byte(sysinfo->spd_map[i], 2); + printk (BIOS_DEBUG, "%x:%x:%x\n", + i, sysinfo->spd_map[i], + spd); + if ((spd == 7) || (spd == 8) || (spd == 0xb)) { + spdinfo.dimm_mask |= 1 << i; + if (sysinfo->spd_type && sysinfo->spd_type != spd) { + die("Multiple types of DIMM installed in the system, don't do that!\n"); + } + sysinfo->spd_type = spd; } - sysinfo->spd_type = spd; } - } if (spdinfo.dimm_mask == 0) { die("Could not find any DIMM.\n"); } @@ -612,8 +617,8 @@ static void collect_dimm_config(sysinfo_t *const sysinfo) if (sysinfo->spd_type == DDR2) { die("DDR2 not supported at this time.\n"); } else if (sysinfo->spd_type == DDR3) { - verify_ddr3(spdinfo.dimm_mask); - collect_ddr3(&spdinfo); + verify_ddr3(sysinfo, spdinfo.dimm_mask); + collect_ddr3(sysinfo, &spdinfo); } else { die("Will never support DDR1.\n"); }

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New patch to review for coreboot: 9d14750 lenovo/x60/i915.c: Remove one of the two `PGETBL_CTL` defines
by Paul Menzel 05 Jun '14

05 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5930 -gerrit commit 9d14750aee3265d6fdeff27acf77d4dcc78d5bc6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 09:04:40 2014 +0200 lenovo/x60/i915.c: Remove one of the two `PGETBL_CTL` defines Change-Id: I459c2576d91e80accaae313b34875cc7b8c446ad Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 8fbd2a1..05137f8 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -48,8 +48,6 @@ enum { vmsg = 1, vio = 2, vspin = 4, }; -#define PGETLB_CTL 0x2020 - static int verbose = 0; static unsigned int *mmio;

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New patch to review for coreboot: e16f315 Intel 945 boards: Use define for `BSM`
by Paul Menzel 05 Jun '14

05 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5929 -gerrit commit e16f315d0615d0003eec5649f06b0716f75eb94c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 08:50:17 2014 +0200 Intel 945 boards: Use define for `BSM` Change-Id: Ia58d8b410a145f27f0b267c115714580c366e063 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/getac/p470/romstage.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/intel/d945gclf/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 2 +- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x60/i915.c | 2 +- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index a081a8a..33b6726 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -347,7 +347,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 418b6e4..9dfd364 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -298,7 +298,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 69d4232..a0621ce 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -258,7 +258,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 4acd734..0ad7a2a 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -410,7 +410,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index dae917c..c5bb2f3 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -309,7 +309,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index b41a0ba..8fbd2a1 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -138,7 +138,7 @@ int gtt_setup(unsigned int mmiobase) PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; PGETBL_save |= PGETBL_ENABLED; - PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; PGETBL_save |= 2; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1198fb2..1fed5f5 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -311,7 +311,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index ad323f5..2af294c 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -334,7 +334,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000);

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New patch to review for coreboot: 60459bb superio/nuvoton: Use official spelling of Nuvoton in `CHIP_NAME`
by Paul Menzel 05 Jun '14

05 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5928 -gerrit commit 60459bb81c17c6accfd011da2608ce158093c96e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 07:52:49 2014 +0200 superio/nuvoton: Use official spelling of Nuvoton in `CHIP_NAME` The official spelling of Nuvoton is not all uppercase. Only the first letter is uppercase. See the footer of the Nuvoton Web site [1]. ©2008 Nuvoton Technology Corporation [1] http://www.nuvoton.com/ Change-Id: I6ccd4194d7be0c89f8b332fcca5feb2420a4de1e Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/superio/nuvoton/nct5104d/superio.c | 2 +- src/superio/nuvoton/wpcm450/superio.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 5eb8991..4205d75 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -53,6 +53,6 @@ static void enable_dev(struct device *dev) } struct chip_operations superio_nuvoton_nct5104d_ops = { - CHIP_NAME("NUVOTON NCT5104D Super I/O") + CHIP_NAME("Nuvoton NCT5104D Super I/O") .enable_dev = enable_dev, }; diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index ff815cf..2e355d3 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -60,6 +60,6 @@ static void enable_dev(struct device *dev) } struct chip_operations superio_nuvoton_wpcm450_ops = { - CHIP_NAME("NUVOTON WPCM450 Super I/O") + CHIP_NAME("Nuvoton WPCM450 Super I/O") .enable_dev = enable_dev, };

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Patch set updated for coreboot: ca9eee2 superio/nuvoton: Add support for Nuvoton NCT6776
by Felix Held 04 Jun '14

04 Jun '14

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5450 -gerrit commit ca9eee2e23e7d850ce73421fe631ad4a6e03ba94 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Wed Jun 4 23:15:26 2014 +0200 superio/nuvoton: Add support for Nuvoton NCT6776 Add support for both NCT6776D and NCT6776F devices. Change-Id: If6686ea0a1cd6be537e286699b4ee8f88ba8ad7c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/superio/nuvoton/Kconfig | 4 ++ src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/nct6776/Makefile.inc | 22 +++++++++ src/superio/nuvoton/nct6776/nct6776.h | 62 ++++++++++++++++++++++++ src/superio/nuvoton/nct6776/superio.c | 82 ++++++++++++++++++++++++++++++++ 5 files changed, 171 insertions(+) diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index 350c8dd..8c70520 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -28,3 +28,7 @@ config SUPERIO_NUVOTON_WPCM450 config SUPERIO_NUVOTON_NCT5104D bool select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT6776 + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 1ce6963..57ce02f 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -22,3 +22,4 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776 diff --git a/src/superio/nuvoton/nct6776/Makefile.inc b/src/superio/nuvoton/nct6776/Makefile.inc new file mode 100755 index 0000000..45bd755 --- /dev/null +++ b/src/superio/nuvoton/nct6776/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += superio.c diff --git a/src/superio/nuvoton/nct6776/nct6776.h b/src/superio/nuvoton/nct6776/nct6776.h new file mode 100755 index 0000000..f6f31ef --- /dev/null +++ b/src/superio/nuvoton/nct6776/nct6776.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Both NCT6776D and NCT6776F package variants are supported. */ + +#ifndef SUPERIO_NUVOTON_NCT6776_H +#define SUPERIO_NUVOTON_NCT6776_H + +/* Logical Device Numbers (LDN). */ +#define NCT6776_FDC 0x00 /* Floppy */ +#define NCT6776_PP 0x01 /* Parallel port */ +#define NCT6776_SP1 0x02 /* Com1 */ +#define NCT6776_SP2 0x03 /* Com2 & IR */ +#define NCT6776_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT6776_CIR 0x06 +#define NCT6776_GPIO6789_V 0x07 +#define NCT6776_WDT1_GPIO01A_V 0x08 +#define NCT6776_GPIO1234567_V 0x09 +#define NCT6776_ACPI 0x0A +#define NCT6776_HWM_FPLED 0x0B /* Hardware monitor & front LED */ +#define NCT6776_VID 0x0D +#define NCT6776_CIRWKUP 0x0E /* CIR wakeup */ +#define NCT6776_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ +#define NCT6776_SVID 0x14 +#define NCT6776_DSLP 0x16 /* Deep sleep */ +#define NCT6776_GPIOA_LDN 0x17 + +/* virtual LDN for GPIO and WDT */ +#define NCT6776_WDT1 ((0 << 8) | NCT6776_WDT1_GPIO01A_V) + +#define NCT6776_GPIOBASE ((0 << 8) | NCT6776_WDT1_GPIO01A_V) //? + +#define NCT6776_GPIO0 ((1 << 8) | NCT6776_WDT1_GPIO01A_V) +#define NCT6776_GPIO1 ((1 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO2 ((2 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO3 ((3 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO4 ((4 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO5 ((5 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO6 ((6 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO7 ((7 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO8 ((0 << 8) | NCT6776_GPIO6789_V) +#define NCT6776_GPIO9 ((1 << 8) | NCT6776_GPIO6789_V) +#define NCT6776_GPIOA ((2 << 8) | NCT6776_WDT1_GPIO01A_V) + +#endif /* SUPERIO_NUVOTON_NCT6776_H */ diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c new file mode 100755 index 0000000..6712750 --- /dev/null +++ b/src/superio/nuvoton/nct6776/superio.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <stdlib.h> +#include "nct6776.h" + +/* Both NCT6776D and NCT6776F package variants are supported. */ + +static void nct6776_init(device_t dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6776_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + //TODO: set field from struct io_info seems to be unused. why set this to 0 or 4? + { &ops, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, NCT6776_CIR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_ACPI}, + { &ops, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ffe, 0}, {0x0ffe, 4}, }, + { &ops, NCT6776_VID}, + { &ops, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_GPIO_PP_OD}, + { &ops, NCT6776_SVID}, + { &ops, NCT6776_DSLP}, + { &ops, NCT6776_GPIOA_LDN}, + { &ops, NCT6776_WDT1}, + { &ops, NCT6776_GPIOBASE, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776_GPIO0}, + { &ops, NCT6776_GPIO1}, + { &ops, NCT6776_GPIO2}, + { &ops, NCT6776_GPIO3}, + { &ops, NCT6776_GPIO4}, + { &ops, NCT6776_GPIO5}, + { &ops, NCT6776_GPIO6}, + { &ops, NCT6776_GPIO7}, + { &ops, NCT6776_GPIO8}, + { &ops, NCT6776_GPIO9}, + { &ops, NCT6776_GPIOA}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6776_ops = { + CHIP_NAME("NUVOTON NCT6776 Super I/O") + .enable_dev = enable_dev, +};

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Patch set updated for coreboot: b610b66 [NOTFORMERGE] mainboard/lenovo/x60/i915.c: Set PGETBL_CTL to VBIOS value
by Paul Menzel 04 Jun '14

04 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927 -gerrit commit b610b66d1ad0f72f4b25ae89e8e960312584733a Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jun 3 22:05:33 2014 +0200 [NOTFORMERGE] mainboard/lenovo/x60/i915.c: Set PGETBL_CTL to VBIOS value PGETBL_CTL differs between VBIOS (-) and native graphics init (+). - PGETBL_CTL: 0x3ffc0001 + PGETBL_CTL: 0x3f800001 Also print what is written to PGETBL_CTL. Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index b41a0ba..0c15aaa 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -135,19 +135,29 @@ int gtt_setup(unsigned int mmiobase) { unsigned long PGETBL_save; - PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + PGETBL_save = read32(mmiobase + PGETBL_CTL); + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register (original): 0x%lx\n", __func__, PGETBL_save); + PGETBL_save &= ~PGETBL_ENABLED; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register (&= ~PGETBL_ENABLED): 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= PGETBL_ENABLED; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= 2; /* set GTT to 256kb */ + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); + + PGETBL_save += 0x7c0000; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register (added 0x7c0000 for VBIOS value): 0x%lx\n", __func__, PGETBL_save); write32(mmiobase + GFX_FLSH_CNTL, 0); write32(mmiobase + PGETBL_CTL, PGETBL_save); /* verify */ - if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { - printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); + PGETBL_save = read32(mmiobase + PGETBL_CTL); + if (PGETBL_save & PGETBL_ENABLED) { + printk(BIOS_DEBUG, "gtt_setup is enabled: GTT PGETLB_CTL register: 0x%lx\n", PGETBL_save); } else { printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); return 1;

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Patch set updated for coreboot: f8e6a2a [NOTFORMERGE] mainboard/lenovo/x60/i915.c: Set PGETBL_CTL to VBIOS value
by Paul Menzel 04 Jun '14

04 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927 -gerrit commit f8e6a2afdb63e0df3185b13206fdf2e09c68308e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jun 3 22:05:33 2014 +0200 [NOTFORMERGE] mainboard/lenovo/x60/i915.c: Set PGETBL_CTL to VBIOS value PGETBL_CTL differs between VBIOS (-) and native graphics init (+). - PGETBL_CTL: 0x3ffc0001 + PGETBL_CTL: 0x3f800001 Also print what is written to PGETBL_CTL. Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index b41a0ba..dba62a9 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -136,18 +136,26 @@ int gtt_setup(unsigned int mmiobase) unsigned long PGETBL_save; PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= PGETBL_ENABLED; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= 2; /* set GTT to 256kb */ + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); + + PGETBL_save += 0x7c0000; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register (added 0x7c0000 for VBIOS value): 0x%lx\n", __func__, PGETBL_save); write32(mmiobase + GFX_FLSH_CNTL, 0); write32(mmiobase + PGETBL_CTL, PGETBL_save); /* verify */ - if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { - printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); + PGETBL_save = read32(mmiobase + PGETBL_CTL); + if (PGETBL_save & PGETBL_ENABLED) { + printk(BIOS_DEBUG, "gtt_setup is enabled: GTT PGETLB_CTL register: 0x%lx\n", PGETBL_save); } else { printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); return 1;

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Patch set updated for coreboot: 04528e8 mainboard/supermicro/h8dme: Drop unused code
by Kyösti Mälkki 04 Jun '14

04 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5828 -gerrit commit 04528e8f35b711c031ed75e3ba517c207ae498fe Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 01:45:41 2014 +1000 mainboard/supermicro/h8dme: Drop unused code Clang complains about a unused debug function, so remove dead code. We have copy of dump_smbus_registers() in amdk8/debug.c. Change-Id: I5a9a785fcd90761789aaa029f712f1feddd2afd1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/supermicro/h8dme/romstage.c | 31 +++---------------------------- 1 file changed, 3 insertions(+), 28 deletions(-) diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 47f5806..4a77e6c 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -45,33 +45,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void dump_smbus_registers(void) -{ - u32 device; - - print_debug("\n"); - for (device = 1; device < 0x80; device++) { - int j; - if (smbus_read_byte(device, 0) < 0) - continue; - printk(BIOS_DEBUG, "smbus: %02x", device); - for (j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ", j); - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - print_debug("\n"); - } -} - static inline void activate_spd_rom(const struct mem_controller *ctrl) { #if 0 @@ -202,7 +175,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("\n"); set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram -/* dump_smbus_registers(); */ +#if CONFIG_DEBUG_SMBUS + dump_smbus_registers(); +#endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started();

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New patch to review for coreboot: 3d0607f [NOTFORMERGE] mainboard/lenovo/x60/i915.c: Increase end from 800 to 1600
by Paul Menzel 03 Jun '14

03 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927 -gerrit commit 3d0607f5130179763f867c2fdd28db42e88674f4 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jun 3 22:05:33 2014 +0200 [NOTFORMERGE] mainboard/lenovo/x60/i915.c: Increase end from 800 to 1600 PGETBL_CTL differs between VBIOS (-) and native graphics init (+). - PGETBL_CTL: 0x3ffc0001 + PGETBL_CTL: 0x3f800001 Also print what is written to PGETBL_CTL. Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index b41a0ba..8b5f1d9 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -136,18 +136,23 @@ int gtt_setup(unsigned int mmiobase) unsigned long PGETBL_save; PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= PGETBL_ENABLED; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); PGETBL_save |= 2; /* set GTT to 256kb */ + printk(BIOS_DEBUG, "%s: GTT PGETLB_CTL register: 0x%lx\n", __func__, PGETBL_save); write32(mmiobase + GFX_FLSH_CNTL, 0); write32(mmiobase + PGETBL_CTL, PGETBL_save); /* verify */ - if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { - printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); + PGETBL_save = read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED; + if (PGETBL_save) { + printk(BIOS_DEBUG, "gtt_setup is enabled: GTT PGETLB_CTL register: 0x%lx\n", PGETBL_save); } else { printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); return 1; @@ -351,7 +356,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; } - setgtt(0, 800 , physbase, 4096); + setgtt(0, 1600 , physbase, 4096); temp = READ32(PGETLB_CTL); printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp);

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coreboot-gerrit June 2014