coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

1 participants
922 discussions

Patch set updated for coreboot: 16761f3 mainboard/supermicro/h8dme: Unused func warn
by Edward O'Callaghan 06 Jun '14

06 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5828 -gerrit commit 16761f3397d61832b0e6f472150b131cdaf2e45d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 01:45:41 2014 +1000 mainboard/supermicro/h8dme: Unused func warn Clang complains about a unused debug function, so #if 0 it out so abuilds move forward with Clang. Change-Id: I5a9a785fcd90761789aaa029f712f1feddd2afd1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/supermicro/h8dme/romstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 47f5806..8d690c4 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -45,6 +45,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } +#if 0 static inline void dump_smbus_registers(void) { u32 device; @@ -71,6 +72,7 @@ static inline void dump_smbus_registers(void) print_debug("\n"); } } +#endif static inline void activate_spd_rom(const struct mem_controller *ctrl) {

1 0

New patch to review for coreboot: 1db5572 amd/agesa/f15tn: Invalid inline asm in gcc-intrin.h
by Edward O'Callaghan 06 Jun '14

06 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5941 -gerrit commit 1db5572d23dff23f23b3ec7ced470a67305d0868 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jun 6 09:51:23 2014 +1000 amd/agesa/f15tn: Invalid inline asm in gcc-intrin.h Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: I87bf101b15bac7c06afa9cec10e2bd4e0cdfd6c7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../amd/agesa/f15tn/Include/gcc-intrin.h | 197 ++++++++++++--------- 1 file changed, 112 insertions(+), 85 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h index ea80746..7d90f8b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. + * Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2014, Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -34,9 +34,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned unsigned char value; __asm__ __volatile__ ( - "in %%dx, %%al" + "in %1, %0" : "=a" (value) - : "d" (Port) + : "Nd" (Port) ); return value; @@ -47,9 +47,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne unsigned short value; __asm__ __volatile__ ( - "in %%dx, %%ax" + "in %1, %0" : "=a" (value) - : "d" (Port) + : "Nd" (Port) ); return value; @@ -60,9 +60,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne unsigned long value; __asm__ __volatile__ ( - "in %%dx, %%eax" + "in %1, %0" : "=a" (value) - : "d" (Port) + : "Nd" (Port) ); return value; @@ -71,81 +71,81 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data) { __asm__ __volatile__ ( - "out %%al, %%dx" + "out %0, %1" : - : "a" (Data), "d" (Port) + : "a" (Data), "Nd" (Port) ); } static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data) { __asm__ __volatile__ ( - "out %%ax, %%dx" + "out %0, %1" : - : "a" (Data), "d" (Port) + : "a" (Data), "Nd" (Port) ); } static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data) { __asm__ __volatile__ ( - "out %%eax, %%dx" + "out %0, %1" : - : "a" (Data), "d" (Port) + : "a" (Data), "Nd" (Port) ); } static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; insb " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; insb" + : "+D" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; insw " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; insw" + : "+D" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; insl " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; insl" + : "+D" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; outsb " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; outsb" + : "+S" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; outsw " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; outsw" + : "+S" (Buffer), "+c" (Count) + : "d"(Port) ); } static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) { __asm__ __volatile__ ( - "cld ; rep ; outsl " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) + "rep ; outsl" + : "+S" (Buffer), "+c" (Count) + : "d"(Port) ); } @@ -154,7 +154,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr0, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -164,7 +164,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr1, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -174,7 +174,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr2, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -184,7 +184,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr3, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -194,7 +194,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void) unsigned long value; __asm__ __volatile__ ( "mov %%dr7, %[value]" - : [value] "=a" (value) + : [value] "=r" (value) ); return value; } @@ -230,45 +230,45 @@ static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr0" + "mov %0, %%dr0" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr1" + "mov %0, %%dr1" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr2" + "mov %0, %%dr2" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr3" + "mov %0, %%dr3" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%dr7" + "mov %0, %%dr7" : - : "a" (Data) + : "r" (Data) ); } @@ -305,7 +305,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr0, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -314,7 +314,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr2, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -323,7 +323,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr3, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -332,7 +332,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr4, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -341,7 +341,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr8, %[value]" - : [value] "=a" (value)); + : [value] "=r" (value)); return value; } @@ -376,45 +376,46 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr0" + "mov %0, %%cr0" : - : "a" (Data) + : "r" (Data) + : "memory" ); } static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr2" + "mov %0, %%cr2" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr3" + "mov %0, %%cr3" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr4" + "mov %0, %%cr4" : - : "a" (Data) + : "r" (Data) ); } static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data) { __asm__ __volatile__ ( - "mov %%eax, %%cr8" + "mov %0, %%cr8" : - : "a" (Data) + : "r" (Data) ); } @@ -450,7 +451,7 @@ static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr) { UINT64 retval; __asm__ __volatile__( - "rdmsr\n\t" + "rdmsr" : "=A" (retval) : "c" (msr) ); @@ -460,7 +461,7 @@ static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr) static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value) { __asm__ __volatile__ ( - "wrmsr\n\t" + "wrmsr" : : "c" (msr), "A" (Value) ); @@ -484,26 +485,35 @@ static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], con ); } + static __inline__ __attribute__((always_inline)) void _disable(void) { __asm__ __volatile__ ("cli"); } + static __inline__ __attribute__((always_inline)) void _enable(void) { __asm__ __volatile__ ("sti"); } + static __inline__ __attribute__((always_inline)) void __halt(void) { __asm__ __volatile__ ("hlt"); } + static __inline__ __attribute__((always_inline)) void __debugbreak(void) { __asm__ __volatile__ ("int3"); } +static __inline__ __attribute__((always_inline)) void __invd(void) +{ + __asm__ __volatile__ ("invd"); +} + static __inline__ __attribute__((always_inline)) void __wbinvd(void) { __asm__ __volatile__ ("wbinvd"); @@ -514,39 +524,57 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source) __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); } -static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data) +static __inline__ __attribute__((always_inline)) void +__writefsbyte(const unsigned long Offset, const unsigned char Data) { - __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movb %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "iq" (Data)); } -static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data) +static __inline__ __attribute__((always_inline)) void +__writefsword(const unsigned long Offset, const unsigned short Data) { - __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movw %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data) +static __inline__ __attribute__((always_inline)) void +__writefsdword(const unsigned long Offset, const unsigned long Data) { - __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movl %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned char +__readfsbyte(const unsigned long Offset) { unsigned char value; - __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movb %%fs:%a[Offset], %[value]" + : [value] "=q" (value) + : [Offset] "ir" (Offset)); return value; } -static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned short +__readfsword(const unsigned long Offset) { unsigned short value; - __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movw %%fs:%a[Offset], %[value]" + : [value] "=q" (value) + : [Offset] "ir" (Offset)); return value; } -static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset) +static __inline__ __attribute__((always_inline)) unsigned long +__readfsdword(unsigned long Offset) { - unsigned long long value; - __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + unsigned long value; + __asm__ ("movl %%fs:%a[Offset], %[value]" + : [value] "=r" (value) + : [Offset] "ir" (Offset)); return value; } @@ -582,23 +610,22 @@ static __inline __attribute__(( __always_inline__)) void _mm_sfence (void) { __builtin_ia32_sfence (); } -#endif +#endif /* __SSE3__ */ static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) { __asm__ __volatile__ ( - "cld ; rep ; stosb " - : "=D" (dest), "=c" (count) - : "a"(data), "0"(dest), "1" (count) + "rep ; stosb " + : "+D" (dest), "+c" (count) + : "a"(data) ); } static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count) { __asm__ __volatile__ ( - "cld ; rep ; movsb " - : "=D" (dest), "=S"(data), "=c" (count) - : "S"(data), "0"(dest), "1" (count) + "movsb " + : "+D" (dest), "+S"(data), "+c" (count) ); } @@ -621,4 +648,4 @@ void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayT Index ++; } } -#endif // defined (__GNUC__) +#endif /* defined (__GNUC__) */

1 0

Patch merged into coreboot/master: f5bde44 superio/smsc/kbc1100: Virtually rewrite support and fix mainboards
by gerrit＠coreboot.org 06 Jun '14

06 Jun '14

the following patch was just integrated into master: commit f5bde44df2ff954c8af9fd6ab50453f491983dab Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jun 2 12:20:11 2014 +1000 superio/smsc/kbc1100: Virtually rewrite support and fix mainboards 1. Remove #include .c in romstage. 2. Make romstage component symbols linker-time. 3. Provide header guards and prototypes in superio romstage support. 4. Correct function type-signatures to be static/non-static where appropriate, avoid 'pretend optimisations' by unnecessarily inlining functions. 5. Separate out UART enable from various other PNP hard coding Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5916 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5916 for details. -gerrit

1 0

Patch merged into coreboot/master: 4ba8ba4 build: Drop libgcc runtime wrapper in Clang builds
by gerrit＠coreboot.org 06 Jun '14

06 Jun '14

the following patch was just integrated into master: commit 4ba8ba4654aef66283db5a69e40586fb9e186b5a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 23 01:29:00 2014 +1000 build: Drop libgcc runtime wrapper in Clang builds This GCC specific workaround of wrapping of libgcc runtime symbols with gcc.c is not nessary with libcompiler-rt linkage. Change-Id: I50a2bc99d97f68a2ad2b51a92ea0e7086bab35fe Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5812 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5812 for details. -gerrit

1 0

New patch to review for coreboot: d921e9a lenovo/x60/i915.c: Add defines for GTT sizes and use them
by Paul Menzel 05 Jun '14

05 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5940 -gerrit commit d921e9a7f1eb6ce30f08af8af310a1e825cc03a9 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 22:22:24 2014 +0200 lenovo/x60/i915.c: Add defines for GTT sizes and use them Change-Id: Ia0de8802c6f48eefe1d48e30b5bc07290a407667 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 9300b2b..ba82423 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -59,6 +59,13 @@ static unsigned int physbase; #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001 +#define PGETBL_GTT_SIZE 0x00001110 +#define PGETBL_GTT_SIZE_512KB 0x0 +#define PGETBL_GTT_SIZE_256KB 0x1 +#define PGETBL_GTT_SIZE_128KB 0x2 +#define PGETBL_GTT_SIZE_1MB 0x3 +#define PGETBL_GTT_SIZE_2MB 0x4 +#define PGETBL_GTT_SIZE_1_5MB 0x5 static u32 htotal, hblank, hsync, vtotal, vblank, vsync; @@ -138,7 +145,7 @@ int gtt_setup(unsigned int mmiobase) pgetbl_ctl |= PGETBL_ENABLED; pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000; - pgetbl_ctl |= 2; /* set GTT to 256kb */ + pgetbl_ctl |= PGETBL_GTT_SIZE_256KB << 1; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0);

1 0

New patch to review for coreboot: ca3f202 lenovo/x60/i915.c: Mask BSM register correctly
by Paul Menzel 05 Jun '14

05 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5939 -gerrit commit ca3f202edbea1b55b18473c2c3bab22228295c9d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 22:27:24 2014 +0200 lenovo/x60/i915.c: Mask BSM register correctly Base of Stolen Memory are (BSM) are bits 31:20. This does make any difference as the bits 19:0 are read only and 0 by default. Change-Id: I82d087184a8550e95dca2ac2991ed48b06031536 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 12bcf5c..9300b2b 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -137,7 +137,7 @@ int gtt_setup(unsigned int mmiobase) pgetbl_ctl = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; pgetbl_ctl |= PGETBL_ENABLED; - pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; + pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000; pgetbl_ctl |= 2; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0);

1 0

New patch to review for coreboot: b098ce0 lenovo/x60/i915.c: Use `FRAME_BUFFER_PAGES` in `set_gtt()`
by Paul Menzel 05 Jun '14

05 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5938 -gerrit commit b098ce008541cc1416e89d13e508d8761133a739 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 21:36:18 2014 +0200 lenovo/x60/i915.c: Use `FRAME_BUFFER_PAGES` in `set_gtt()` The define FRAME_BUFFER_PAGES = (1024 * 768)/1024 is exactly the amount of needed pages. Change-Id: Ifae2a50080b0fbcdd0d3489c8da1535cbbb05eef Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 62a8252..12bcf5c 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -353,7 +353,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; } - setgtt(0, 800, physbase, 4096); + setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); temp = READ32(PGETLB_CTL); printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp);

1 0

New patch to review for coreboot: 9f911b9 lenovo/x60/i915.c: Fix coding style and embellish log messages
by Paul Menzel 05 Jun '14

05 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5937 -gerrit commit 9f911b9be616ddac1410b1dbf861c772ee924a4d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 21:29:13 2014 +0200 lenovo/x60/i915.c: Fix coding style and embellish log messages Change-Id: I4227832dba439469f738f7894e1c73e2a5bd5e7a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index ac37467..62a8252 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -349,19 +349,19 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, */ if (gtt_setup(pmmio)) { - printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + printk(BIOS_ERR, "ERROR: GTT setup failed!!!\n"); return 0; } - setgtt(0, 800 , physbase, 4096); + setgtt(0, 800, physbase, 4096); temp = READ32(PGETLB_CTL); printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp); if (temp & 1) - printk(BIOS_INFO, "GTT Enabled\n"); + printk(BIOS_INFO, "GTT enabled.\n"); else - printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + printk(BIOS_ERR, "ERROR: GTT is still disabled!!!\n"); printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", (void *)graphics, FRAME_BUFFER_BYTES);

1 0

Patch set updated for coreboot: d57515f lenovo/x60/i915.c: Place GTT below top of memory
by Paul Menzel 05 Jun '14

05 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927 -gerrit commit d57515f0acd9ea9081b2ace819f999abe3c08758 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 22:45:35 2014 +0200 lenovo/x60/i915.c: Place GTT below top of memory PGETBL_CTL differs between Video BIOS (-) and native graphics init (+). - PGETBL_CTL: 0x3ffc0001 + PGETBL_CTL: 0x3f800001 Currently it is set above the base address of stolen memory. The Video BIOS sets it below. The Linux Intel driver expects it to be below top of memory so do it this way. Also adapt setgtt() to use the new address. There is still an error thrown but 3D works with Linux 3.12+. Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index ba82423..bf266ad 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -140,11 +140,19 @@ int gtt_setup(unsigned int mmiobase); int gtt_setup(unsigned int mmiobase) { unsigned long pgetbl_ctl; + unsigned long tom; pgetbl_ctl = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; pgetbl_ctl |= PGETBL_ENABLED; - pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000; + /* The Video BIOS places the GTT right below top of memory. + * It is not documented in the datasheet, but the Intel developers said + * that it is normally placed there. + * + * TODO: Add option table value to make the GTT size runtime configurable. + */ + tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; + pgetbl_ctl |= tom - 256 * KiB; pgetbl_ctl |= PGETBL_GTT_SIZE_256KB << 1; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0); @@ -360,11 +368,11 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; } - setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); - temp = READ32(PGETLB_CTL); printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp); + setgtt(0, FRAME_BUFFER_PAGES, temp & 0xfffff000, 4096); + if (temp & 1) printk(BIOS_INFO, "GTT enabled.\n"); else

1 0

New patch to review for coreboot: 8eca4ce google/link, lenovo/x60: i915io.c: Use define `ARRAY_SIZE`
by Paul Menzel 05 Jun '14

05 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5936 -gerrit commit 8eca4cee7890f6d254d62de5e7daa65f0b72ee2e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 22:12:06 2014 +0200 google/link, lenovo/x60: i915io.c: Use define `ARRAY_SIZE` Change-Id: I8ddd46a573b61eba685efcc15456f288645d214d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/google/link/i915io.c | 2 +- src/mainboard/lenovo/x60/i915io.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c index f553acc..abceb05 100644 --- a/src/mainboard/google/link/i915io.c +++ b/src/mainboard/google/link/i915io.c @@ -355,4 +355,4 @@ struct iodef iodefs[] = { {I,}, }; -int niodefs = sizeof (iodefs) / sizeof (iodefs[0]); +int niodefs = ARRAY_SIZE(iodefs); diff --git a/src/mainboard/lenovo/x60/i915io.c b/src/mainboard/lenovo/x60/i915io.c index 3552867..b3c47b7 100644 --- a/src/mainboard/lenovo/x60/i915io.c +++ b/src/mainboard/lenovo/x60/i915io.c @@ -2270,4 +2270,4 @@ struct iodef iodefs[] = { {0,}, }; -int niodefs = sizeof(iodefs) / sizeof(iodefs[0]); +int niodefs = ARRAY_SIZE(iodefs);

1 0

← Newer
1
...
79
80
81
82
83
84
85
...
93
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2014