coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

1 participants
922 discussions

New patch to review for coreboot: 3b7c130 [NOTFORMERGE] northbridge/intel/i945/gma.c: Output GMADR and GTTADR after VBIOS/native init
by Paul Menzel 03 Jun '14

03 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5926 -gerrit commit 3b7c130a3ebeb7ba28ec7f77c1c611d53d2c0a38 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jun 3 16:43:49 2014 +0200 [NOTFORMERGE] northbridge/intel/i945/gma.c: Output GMADR and GTTADR after VBIOS/native init Change-Id: Ib78eb346b4546b4407164ca60b611b884892de0c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/i945/gma.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 1cf80a9..fd1645d 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -69,6 +69,12 @@ static void gma_func0_init(struct device *dev) gfx_set_init_done(1); #endif + printk(BIOS_SPEW, "%s: After VBIOS/native init: GMADR=0x%08x GTTADR=0x%08x\n", + __func__, + pci_read_config32(dev, GMADR), + pci_read_config32(dev, GTTADR) + ); + } /* This doesn't reclaim stolen UMA memory, but IGD could still

1 0

Patch set updated for coreboot: 3de8ef3 superio/smsc/kbc1100: Virtually rewrite support and fix mainboards
by Edward O'Callaghan 03 Jun '14

03 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5916 -gerrit commit 3de8ef3af04c744c65ef7c1d1c844defbebd4709 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jun 2 12:20:11 2014 +1000 superio/smsc/kbc1100: Virtually rewrite support and fix mainboards 1. Remove #include .c in romstage. 2. Make romstage component symbols linker-time. 3. Provide header guards and prototypes in superio romstage support. 4. Correct function type-signatures to be static/non-static where appropriate, avoid 'pretend optimisations' by unnecessarily inlining functions. 5. Separate out UART enable from various other PNP hard coding Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/inagua/Kconfig | 4 -- src/mainboard/amd/inagua/romstage.c | 7 ++- src/mainboard/amd/torpedo/Kconfig | 4 -- src/mainboard/amd/torpedo/romstage.c | 6 +- src/superio/smsc/kbc1100/Makefile.inc | 1 + src/superio/smsc/kbc1100/early_init.c | 79 +++++++++++++++++++++++++++ src/superio/smsc/kbc1100/kbc1100.h | 10 ++++ src/superio/smsc/kbc1100/kbc1100_early_init.c | 75 ------------------------- 8 files changed, 99 insertions(+), 87 deletions(-) diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 1e11f9f..279c7ef 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -69,10 +69,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x2e - config DRIVERS_PS2_KEYBOARD bool default y diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index a304d31..a7b8a40 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -33,11 +33,13 @@ #include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/smsc/kbc1100/kbc1100_early_init.c" +#include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h" +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -57,7 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - kbc1100_early_init(CONFIG_SIO_PORT); + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 62ce043..6013df7 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -79,10 +79,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x2e - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index dcab52b..e3416c7 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -30,13 +30,14 @@ #include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/smsc/kbc1100/kbc1100_early_init.c" +#include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" #include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> #include "platform_cfg.h" +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -57,7 +58,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x31); - kbc1100_early_init(CONFIG_SIO_PORT); + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); post_code(0x32); post_code(0x33); diff --git a/src/superio/smsc/kbc1100/Makefile.inc b/src/superio/smsc/kbc1100/Makefile.inc index 603d24e..c3385a6 100644 --- a/src/superio/smsc/kbc1100/Makefile.inc +++ b/src/superio/smsc/kbc1100/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += superio.c diff --git a/src/superio/smsc/kbc1100/early_init.c b/src/superio/smsc/kbc1100/early_init.c new file mode 100644 index 0000000..d075f9c --- /dev/null +++ b/src/superio/smsc/kbc1100/early_init.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> + +#include "kbc1100.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +void kbc1100_early_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} + +void kbc1100_early_init(u16 port) +{ + device_t dev; + dev = PNP_DEV (port, KBC1100_KBC); + pnp_enter_conf_state(dev); + + /* Serial IRQ enabled */ + outb(0x25, port); + outb(0x04, port + 1); + + /* Enable keyboard */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + /* Enable EC Channel 0 */ + dev = PNP_DEV (port, KBC1100_EC0); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); + + /* disable the 1s timer */ + outb(0xE7, 0x64); +} diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h index 3fe6327..2b588f9 100644 --- a/src/superio/smsc/kbc1100/kbc1100.h +++ b/src/superio/smsc/kbc1100/kbc1100.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_KBC1100_H +#define SUPERIO_SMSC_KBC1100_H + +#include <arch/io.h> +#include <stdint.h> + #define KBC1100_PM1 1 /* PM1 */ #define SMSCSUPERIO_SP1 4 /* Com1 */ #define SMSCSUPERIO_SP2 5 /* Com2 */ @@ -29,4 +36,7 @@ #define KBC1100_EC1 0x0D /* EC Channel 1 */ #define KBC1100_EC2 0x0E /* EC Channel 2 */ +void kbc1100_early_serial(device_t dev, u16 iobase); +void kbc1100_early_init(u16 port); +#endif /* SUPERIO_SMSC_KBC1100_H */ diff --git a/src/superio/smsc/kbc1100/kbc1100_early_init.c b/src/superio/smsc/kbc1100/kbc1100_early_init.c deleted file mode 100644 index 5d74c32..0000000 --- a/src/superio/smsc/kbc1100/kbc1100_early_init.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ - -#include <arch/io.h> -#include "kbc1100.h" - -static inline void pnp_enter_conf_state(device_t dev) -{ - unsigned port = dev>>8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - unsigned port = dev>>8; - outb(0xaa, port); -} - -static inline void kbc1100_early_init(unsigned port) -{ - device_t dev; - dev = PNP_DEV (port, KBC1100_KBC); - - pnp_enter_conf_state(dev); - - /* Serial IRQ enabled */ - outb(0x25, port); - outb(0x04, port + 1); - - /* Enable SMSC UART 0 */ - dev = PNP_DEV (port, SMSCSUPERIO_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); - pnp_set_enable(dev, 1); - - /* Enable keyboard */ - dev = PNP_DEV (port, KBC1100_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ - pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ - pnp_set_enable(dev, 1); - - /* Enable EC Channel 0 */ - dev = PNP_DEV (port, KBC1100_EC0); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); - - pnp_exit_conf_state(dev); - - /* disable the 1s timer */ - outb(0xE7, 0x64); -} -

1 0

Patch set updated for coreboot: 71e4b1f superio/smsc/kbc1100: Virtually rewrite support and fix mainboards
by Edward O'Callaghan 03 Jun '14

03 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5916 -gerrit commit 71e4b1f53a7a3ef1722fbd5fec2dbd7bf9752f12 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jun 2 12:20:11 2014 +1000 superio/smsc/kbc1100: Virtually rewrite support and fix mainboards 1. Remove #include .c in romstage. 2. Make romstage component symbols linker-time. 3. Provide header guards and prototypes in superio romstage support. 4. Correct function type-signatures to be static/non-static where appropriate, avoid 'pretend optimisations' by unnecessarily inlining functions. 5. Separate out UART enable from various other PNP hard coding Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/inagua/Kconfig | 4 -- src/mainboard/amd/inagua/romstage.c | 7 ++- src/mainboard/amd/torpedo/Kconfig | 4 -- src/mainboard/amd/torpedo/romstage.c | 6 +- src/superio/smsc/kbc1100/Makefile.inc | 1 + src/superio/smsc/kbc1100/early_init.c | 80 +++++++++++++++++++++++++++ src/superio/smsc/kbc1100/kbc1100.h | 10 ++++ src/superio/smsc/kbc1100/kbc1100_early_init.c | 75 ------------------------- 8 files changed, 100 insertions(+), 87 deletions(-) diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 1e11f9f..279c7ef 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -69,10 +69,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x2e - config DRIVERS_PS2_KEYBOARD bool default y diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index a304d31..a7b8a40 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -33,11 +33,13 @@ #include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/smsc/kbc1100/kbc1100_early_init.c" +#include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h" +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -57,7 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - kbc1100_early_init(CONFIG_SIO_PORT); + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 62ce043..6013df7 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -79,10 +79,6 @@ config RAMBASE hex default 0x200000 -config SIO_PORT - hex - default 0x2e - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index dcab52b..e3416c7 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -30,13 +30,14 @@ #include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/smsc/kbc1100/kbc1100_early_init.c" +#include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" #include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> #include "platform_cfg.h" +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -57,7 +58,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x31); - kbc1100_early_init(CONFIG_SIO_PORT); + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); post_code(0x32); post_code(0x33); diff --git a/src/superio/smsc/kbc1100/Makefile.inc b/src/superio/smsc/kbc1100/Makefile.inc index 603d24e..c3385a6 100644 --- a/src/superio/smsc/kbc1100/Makefile.inc +++ b/src/superio/smsc/kbc1100/Makefile.inc @@ -17,4 +17,5 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += early_init.c ramstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += superio.c diff --git a/src/superio/smsc/kbc1100/early_init.c b/src/superio/smsc/kbc1100/early_init.c new file mode 100644 index 0000000..9d545a1 --- /dev/null +++ b/src/superio/smsc/kbc1100/early_init.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> + +#include "kbc1100.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +void kbc1100_early_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} + +void kbc1100_early_init(u16 port) +{ + device_t dev; + dev = PNP_DEV (port, KBC1100_KBC); + pnp_enter_conf_state(dev); + + /* Serial IRQ enabled */ + u16 port = dev >> 8; + outb(0x25, port); + outb(0x04, port + 1); + + /* Enable keyboard */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + /* Enable EC Channel 0 */ + dev = PNP_DEV (port, KBC1100_EC0); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); + + /* disable the 1s timer */ + outb(0xE7, 0x64); +} diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h index 3fe6327..2b588f9 100644 --- a/src/superio/smsc/kbc1100/kbc1100.h +++ b/src/superio/smsc/kbc1100/kbc1100.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_KBC1100_H +#define SUPERIO_SMSC_KBC1100_H + +#include <arch/io.h> +#include <stdint.h> + #define KBC1100_PM1 1 /* PM1 */ #define SMSCSUPERIO_SP1 4 /* Com1 */ #define SMSCSUPERIO_SP2 5 /* Com2 */ @@ -29,4 +36,7 @@ #define KBC1100_EC1 0x0D /* EC Channel 1 */ #define KBC1100_EC2 0x0E /* EC Channel 2 */ +void kbc1100_early_serial(device_t dev, u16 iobase); +void kbc1100_early_init(u16 port); +#endif /* SUPERIO_SMSC_KBC1100_H */ diff --git a/src/superio/smsc/kbc1100/kbc1100_early_init.c b/src/superio/smsc/kbc1100/kbc1100_early_init.c deleted file mode 100644 index 5d74c32..0000000 --- a/src/superio/smsc/kbc1100/kbc1100_early_init.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ - -#include <arch/io.h> -#include "kbc1100.h" - -static inline void pnp_enter_conf_state(device_t dev) -{ - unsigned port = dev>>8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - unsigned port = dev>>8; - outb(0xaa, port); -} - -static inline void kbc1100_early_init(unsigned port) -{ - device_t dev; - dev = PNP_DEV (port, KBC1100_KBC); - - pnp_enter_conf_state(dev); - - /* Serial IRQ enabled */ - outb(0x25, port); - outb(0x04, port + 1); - - /* Enable SMSC UART 0 */ - dev = PNP_DEV (port, SMSCSUPERIO_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); - pnp_set_enable(dev, 1); - - /* Enable keyboard */ - dev = PNP_DEV (port, KBC1100_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ - pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ - pnp_set_enable(dev, 1); - - /* Enable EC Channel 0 */ - dev = PNP_DEV (port, KBC1100_EC0); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); - - pnp_exit_conf_state(dev); - - /* disable the 1s timer */ - outb(0xE7, 0x64); -} -

1 0

New patch to review for coreboot: 54d8a1d Drop unused change_i2c_mux()
by Kyösti Mälkki 03 Jun '14

03 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5925 -gerrit commit 54d8a1df4f31bacb00ae9736134f3c923390f011 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 3 12:04:37 2014 +0300 Drop unused change_i2c_mux() Change-Id: I3ac39441746d739ac19e831bb67c76405c24ba27 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/serengeti_cheetah/romstage.c | 23 ----------------------- src/mainboard/broadcom/blast/romstage.c | 19 ------------------- src/mainboard/msi/ms9185/romstage.c | 18 ------------------ src/mainboard/msi/ms9282/romstage.c | 18 ------------------ src/mainboard/supermicro/h8dme/romstage.c | 24 ------------------------ src/mainboard/tyan/s4880/romstage.c | 12 ------------ src/mainboard/tyan/s4882/romstage.c | 16 ---------------- 7 files changed, 130 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 14320a5..ec0682a 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -45,22 +45,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB, 0x03, 0); } -#if 0 -static inline void change_i2c_mux(unsigned device) -{ -#define SMBUS_HUB 0x18 - int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); - } while ((ret!=0) && (i-->0)); - ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); -} -#endif - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -209,13 +193,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif -#if 0 - for(i=1;i<256;i<<=1) { - change_i2c_mux(i); - dump_smbus_registers(); - } -#endif - memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index fcdac69..03cdc1d 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -32,17 +32,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_send_byte(SMBUS_HUB, device); } -#if 0 -static inline void change_i2c_mux(unsigned device) -{ -#define SMBUS_HUB 0x71 - int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - ret = smbus_send_byte(SMBUS_HUB, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); -} -#endif - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -125,14 +114,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); -#if 0 - int i; - for(i=4;i<8;i++) { - change_i2c_mux(i); - dump_smbus_registers(); - } -#endif - memreset_setup(); // init_timer(); diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 2cb38a4..aabc826 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -59,16 +59,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); } -#if 0 -static inline void change_i2c_mux(unsigned device) -{ -#define SMBUS_SWITCH1 0x70 -#define SMBUS_SWITCH2 0x72 - smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); -} -#endif - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -201,14 +191,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif -#if 0 - int i; - for(i=1;i<256;i<<=1) { - change_i2c_mux(i); - dump_smbus_registers(); - } -#endif - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 3048542..9e4a227 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -58,16 +58,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); } -#if 0 -static inline void change_i2c_mux(unsigned device) -{ -#define SMBUS_SWITCH1 0x70 -#define SMBUS_SWITHC2 0x72 - smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); -} -#endif - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -174,14 +164,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); -#if 0 - int i; - for(i=4;i<8;i++) { - change_i2c_mux(i); - dump_smbus_registers(); - } -#endif - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 237e043..87ae1ac 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -57,30 +57,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #endif } -#if 0 -static int smbus_send_byte_one(unsigned device, unsigned char val) -{ - return do_smbus_send_byte(SMBUS1_IO_BASE, device, val); -} - -static inline void change_i2c_mux(unsigned device) -{ -#define SMBUS_SWITCH1 0x48 -#define SMBUS_SWITHC2 0x49 - smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f); - int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - dump_smbus_registers(); - ret = smbus_send_byte(SMBUS_SWITCH1, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); - dump_smbus_registers(); - ret = smbus_send_byte_one(SMBUS_SWITCH2, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); - dump_smbus_registers(); -} -#endif - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 543fcf0..c106b1c 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -48,18 +48,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB, 0x03, 0); } -#if 0 -static inline void change_i2c_mux(unsigned device) -{ -#define SMBUS_HUB 0x18 - int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); - ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); -} -#endif static inline int spd_read_byte(unsigned device, unsigned address) { diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index b4100fb..17379b5 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -53,22 +53,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB, 0x03, 0); } -#if 0 -static inline void change_i2c_mux(unsigned device) -{ -#define SMBUS_HUB 0x18 - int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); - } while ((ret!=0) && (i-->0)); - ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); -} -#endif - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address);

1 0

Patch set updated for coreboot: 0bbff3a mainboard/supermicro/h8dme: Drop unused code
by Kyösti Mälkki 03 Jun '14

03 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5828 -gerrit commit 0bbff3a78e691c7ef43208175aaf48c09d870367 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 01:45:41 2014 +1000 mainboard/supermicro/h8dme: Drop unused code Clang complains about a unused debug function, so remove dead code. We have copy of dump_smbus_registers() in amdk8/debug.c. Change-Id: I5a9a785fcd90761789aaa029f712f1feddd2afd1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/supermicro/h8dme/romstage.c | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 47f5806..237e043 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -45,33 +45,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void dump_smbus_registers(void) -{ - u32 device; - - print_debug("\n"); - for (device = 1; device < 0x80; device++) { - int j; - if (smbus_read_byte(device, 0) < 0) - continue; - printk(BIOS_DEBUG, "smbus: %02x", device); - for (j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ", j); - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - print_debug("\n"); - } -} - static inline void activate_spd_rom(const struct mem_controller *ctrl) { #if 0

1 0

Patch set updated for coreboot: da56592 mainboard/supermicro/h8dme: Drop unused code
by Kyösti Mälkki 03 Jun '14

03 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5828 -gerrit commit da565920f3fff63432746e14cf511450423174c2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 01:45:41 2014 +1000 mainboard/supermicro/h8dme: Drop unused code Clang complains about a unused debug function, so remove dead code. We have copy of dump_smbus_registers() in amdk8/debug.c. Change-Id: I5a9a785fcd90761789aaa029f712f1feddd2afd1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/supermicro/h8dme/romstage.c | 63 ------------------------------- 1 file changed, 63 deletions(-) diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 47f5806..100a0e8 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -45,69 +45,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void dump_smbus_registers(void) -{ - u32 device; - - print_debug("\n"); - for (device = 1; device < 0x80; device++) { - int j; - if (smbus_read_byte(device, 0) < 0) - continue; - printk(BIOS_DEBUG, "smbus: %02x", device); - for (j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = smbus_read_byte(device, j); - if (status < 0) { - break; - } - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ", j); - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - print_debug("\n"); - } -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -#if 0 -/* We don't do any switching yet. */ -#define SMBUS_SWITCH1 0x48 -#define SMBUS_SWITCH2 0x49 - unsigned device=(ctrl->channel0[0])>>8; - smbus_send_byte(SMBUS_SWITCH1, device); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); -#endif -} - -#if 0 -static int smbus_send_byte_one(unsigned device, unsigned char val) -{ - return do_smbus_send_byte(SMBUS1_IO_BASE, device, val); -} - -static inline void change_i2c_mux(unsigned device) -{ -#define SMBUS_SWITCH1 0x48 -#define SMBUS_SWITHC2 0x49 - smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f); - int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - dump_smbus_registers(); - ret = smbus_send_byte(SMBUS_SWITCH1, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); - dump_smbus_registers(); - ret = smbus_send_byte_one(SMBUS_SWITCH2, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); - dump_smbus_registers(); -} -#endif - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address);

1 0

Patch set updated for coreboot: 17507dc ASRock E350M1: Disable absent IDE device 0:14.1
by Kyösti Mälkki 03 Jun '14

03 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2574 -gerrit commit 17507dc682cc6db36aa5b9648ee4ff43dc96aae5 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 2 11:21:06 2013 +0100 ASRock E350M1: Disable absent IDE device 0:14.1 The ASRock E350M1 does not have any IDE connectors, so disable that PCI device, which coreboot also does not find. coreboot-4.0-3583-gf91c8f2 Sat Mar 2 09:04:55 CET 2013 starting... […] PCI: 00:14.0 [1002/4385] enabled sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it. sb800_enable() hda enabled PCI: 00:14.2 [1002/4383] ops Change-Id: I2bbc683b1faccc513bb4c24dce05f3a9892b817b Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index e2096c0..654138b 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -52,7 +52,7 @@ chip northbridge/amd/agesa/family14/root_complex device i2c 51 on end end end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/winbond/w83627hf

1 0

Patch set updated for coreboot: cfc0932 mainboard/*/devicetree.cb: Toggle lacking IDE off
by Kyösti Mälkki 03 Jun '14

03 Jun '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5498 -gerrit commit cfc0932e93a91b5eb0c69c2ae1f1127016d112f5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 13 17:57:31 2014 +1000 mainboard/*/devicetree.cb: Toggle lacking IDE off These boards do not have 'IDE' or emulation of IDE/PATA on the 6 chipset supported SATA channels. Many of these boards only have =<4 AHCI ports mapped off the SATA channels. Change-Id: I1c529eb94a90a97ddc51aece1be3df9f4728a309 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advansus/a785e-i/devicetree.cb | 2 +- src/mainboard/avalue/eax-785e/devicetree.cb | 2 +- src/mainboard/gizmosphere/gizmo/devicetree.cb | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb index f7db1cc..1c8b690 100644 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ b/src/mainboard/advansus/a785e-i/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/amd/amdfam10/root_complex device i2c 53 on end end end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on chip superio/winbond/w83627hf diff --git a/src/mainboard/avalue/eax-785e/devicetree.cb b/src/mainboard/avalue/eax-785e/devicetree.cb index 42ddf01..f392a2a 100644 --- a/src/mainboard/avalue/eax-785e/devicetree.cb +++ b/src/mainboard/avalue/eax-785e/devicetree.cb @@ -41,7 +41,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on chip superio/winbond/w83627hf diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb index 301f79a..bdbe3dc 100755 --- a/src/mainboard/gizmosphere/gizmo/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb @@ -45,7 +45,7 @@ chip northbridge/amd/agesa/family14/root_complex device pci 13.1 on end # USB device pci 13.2 on end # USB device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed

1 0

Patch merged into coreboot/master: fdceb48 superio/smsc/smscsuperio: Make romstage linkable with header
by gerrit＠coreboot.org 03 Jun '14

03 Jun '14

the following patch was just integrated into master: commit fdceb48b3623f8d342c9138feb8ee0db61a79f24 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jun 2 07:58:14 2014 +1000 superio/smsc/smscsuperio: Make romstage linkable with header Rewrite smsc/smscsuperio romstage component to be more consistent and provide header there-by removing #include's of early_serial.c's in mainboard's. Change-Id: I572e0c76422f09d4de88935a36c0a59e5350e6e0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5915 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5915 for details. -gerrit

1 0

Patch merged into coreboot/master: 8f45761 superio/ite/it8661f: Make early_serial into romstage sym
by gerrit＠coreboot.org 03 Jun '14

03 Jun '14

the following patch was just integrated into master: commit 8f45761a67347050058537f6a6cd75489af6c1d8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 15 20:30:49 2014 +1000 superio/ite/it8661f: Make early_serial into romstage sym Following similar reasoning as commit: d304331 superio/fintek/f81865f: Avoid .c includes Avoid any mistaken future inclusion of early_serial.c in mainboard.c code by providing symbols in romstage. Change-Id: I9e763a7ad9de090e35acdcf4d6a280d8227c6015 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5508 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5508 for details. -gerrit

1 0

← Newer
1
...
82
83
84
85
86
87
88
...
93
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2014