coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

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922 discussions

Patch merged into coreboot/master: 6fb379a mainboard: Remove #include early_serial.c from w83977tf boards
by gerrit＠coreboot.org 03 Jun '14

03 Jun '14

the following patch was just integrated into master: commit 6fb379a1dbd60fcdd8ad30550b708ed1b9e3fa7d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 1 17:38:22 2014 +1000 mainboard: Remove #include early_serial.c from w83977tf boards These non-ROMCC boards #include the model specific w83977tf Super I/O romstage component. The generic winbond_early_serial() function serves well here to further tighten integration into the new Super I/O framework and drop dependence on #include'ing .c files, leaving only ROMCC boards. Change-Id: Ib63c0f29f994c54e6112702506f288535799706c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5898 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5898 for details. -gerrit

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Patch merged into coreboot/master: aef5594 superio/ite/it8772f: Depreciate early wdt functions
by gerrit＠coreboot.org 03 Jun '14

03 Jun '14

the following patch was just integrated into master: commit aef5594f7409636cfbe2c7ebb23da041e36cd7f6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 1 20:30:28 2014 +1000 superio/ite/it8772f: Depreciate early wdt functions We have better written generic implementations of these functions introduced in commit: a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers Change-Id: Ic93d78fce18c68d1d1bf3b537e8985a2532a8fcf Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5901 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5901 for details. -gerrit

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Patch merged into coreboot/master: 1b3acb1 superio/ite/it8772f: Move towards removing #include .c
by gerrit＠coreboot.org 03 Jun '14

03 Jun '14

the following patch was just integrated into master: commit 1b3acb13e49753e53192d3e5b939713329d0d205 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 1 18:04:05 2014 +1000 superio/ite/it8772f: Move towards removing #include .c Move samsung/stumpy board towards generic romstage component and away from poorly written hard-coded model specific Super I/O component. This is an incremental step towards getting obj-level abstraction between board and Super I/O. Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5899 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5899 for details. -gerrit

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Patch merged into coreboot/master: d235da1 northbridge/intel/i945/gma.c: Add and use defines for `GMADR` and `GTTADR`
by gerrit＠coreboot.org 03 Jun '14

03 Jun '14

the following patch was just integrated into master: commit d235da108b38ad45f20c3e556e630b10fb16634e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jun 3 00:15:30 2014 +0200 northbridge/intel/i945/gma.c: Add and use defines for `GMADR` and `GTTADR` Change-Id: I0f39b35fbf8e053ba21454a2847d6bb3ac5d2e1c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5923 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5923 for details. -gerrit

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Patch merged into coreboot/master: 5068463 northbridge/intel/i945/i945.h: Move define `BSM` to section D2F0
by gerrit＠coreboot.org 03 Jun '14

03 Jun '14

the following patch was just integrated into master: commit 50684638bea678d6aec94c1345b45684a627fded Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jun 3 00:26:03 2014 +0200 northbridge/intel/i945/i945.h: Move define `BSM` to section D2F0 The Base of Stolen Memory (BSM) register belongs to device 2, function 0. Change-Id: I2381f87ffaccb2f8034c160fc30c1d92f8b19402 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5922 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5922 for details. -gerrit

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New patch to review for coreboot: dd949df src/superio/smsc/lpc47m15x: Avoid #include early_serial.c
by Edward O'Callaghan 03 Jun '14

03 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5924 -gerrit commit dd949df83576a8d67cfdf3e4db057ce84f9404e9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jun 3 08:40:34 2014 +1000 src/superio/smsc/lpc47m15x: Avoid #include early_serial.c Provide proper header and function type-signatures for Super I/O romstage component. Change-Id: Icd02199690d0c428b2daadf702d50714dc367692 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/d945gclf/romstage.c | 3 +-- src/superio/smsc/lpc47m15x/Makefile.inc | 2 +- src/superio/smsc/lpc47m15x/early_serial.c | 5 ++++- src/superio/smsc/lpc47m15x/lpc47m15x.h | 11 ++++++++--- 4 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 69d4232..0345c10 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -27,11 +27,10 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <cbmem.h> -#include "superio/smsc/lpc47m15x/lpc47m15x.h" +#include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include "superio/smsc/lpc47m15x/early_serial.c" #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" diff --git a/src/superio/smsc/lpc47m15x/Makefile.inc b/src/superio/smsc/lpc47m15x/Makefile.inc index d5b69e4..610d87c 100644 --- a/src/superio/smsc/lpc47m15x/Makefile.inc +++ b/src/superio/smsc/lpc47m15x/Makefile.inc @@ -17,5 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += superio.c - diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c index 7d75bae..5686f52 100644 --- a/src/superio/smsc/lpc47m15x/early_serial.c +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -20,6 +20,9 @@ /* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> + #include "lpc47m15x.h" static void pnp_enter_conf_state(device_t dev) @@ -34,7 +37,7 @@ static void pnp_exit_conf_state(device_t dev) outb(0xaa, port); } -static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase) +void lpc47m15x_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m15x/lpc47m15x.h b/src/superio/smsc/lpc47m15x/lpc47m15x.h index 04f1729..32cff48 100644 --- a/src/superio/smsc/lpc47m15x/lpc47m15x.h +++ b/src/superio/smsc/lpc47m15x/lpc47m15x.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_SMSC_LPC47M15X_LPC47M15X_H -#define SUPERIO_SMSC_LPC47M15X_LPC47M15X_H +#ifndef SUPERIO_SMSC_LPC47M15X_H +#define SUPERIO_SMSC_LPC47M15X_H #define LPC47M15X_FDC 0 /* Floppy */ #define LPC47M15X_PP 3 /* Parallel Port */ @@ -31,4 +31,9 @@ #define LPC47M15X2_MAX_CONFIG_REGISTER 0x5F -#endif +#include <arch/io.h> +#include <stdint.h> + +void lpc47m15x_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_SMSC_LPC47M15X_H */

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New patch to review for coreboot: f229c91 northbridge/intel/i945/gma.c: Add and use defines for `GMADR` and `GTTADR`
by Paul Menzel 03 Jun '14

03 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5923 -gerrit commit f229c91710742c9ee49af71e865e67210deae739 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jun 3 00:15:30 2014 +0200 northbridge/intel/i945/gma.c: Add and use defines for `GMADR` and `GTTADR` Change-Id: I0f39b35fbf8e053ba21454a2847d6bb3ac5d2e1c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/i945/gma.c | 4 ++-- src/northbridge/intel/i945/i945.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 453e9c8..1cf80a9 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -59,8 +59,8 @@ static void gma_func0_init(struct device *dev) graphics_base = dev->resource_list[2].base + 0x20000; printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", - pci_read_config32(dev, 0x18), - pci_read_config32(dev, 0x1c) + pci_read_config32(dev, GMADR), + pci_read_config32(dev, GTTADR) ); int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 8212386..9be9379 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -87,6 +87,8 @@ /* Device 0:2.0 PCI configuration space (Graphics Device) */ +#define GMADR 0x18 +#define GTTADR 0x1c #define BSM 0x5c #define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */

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New patch to review for coreboot: 07b4765 northbridge/intel/i945/i945.h: Move define `BSM` to section D2F0
by Paul Menzel 03 Jun '14

03 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5922 -gerrit commit 07b4765dbda919091fa51b3ccf400c1ca3bc0645 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jun 3 00:26:03 2014 +0200 northbridge/intel/i945/i945.h: Move define `BSM` to section D2F0 The Base of Stolen Memory (BSM) register belongs to device 2, function 0. Change-Id: I2381f87ffaccb2f8034c160fc30c1d92f8b19402 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/i945/i945.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 728fe0a..8212386 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -63,8 +63,6 @@ #define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) #endif /* BOARD_DEVEN */ -#define BSM 0x5c - #define PAM0 0x90 #define PAM1 0x91 #define PAM2 0x92 @@ -89,6 +87,7 @@ /* Device 0:2.0 PCI configuration space (Graphics Device) */ +#define BSM 0x5c #define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */

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New patch to review for coreboot: cfaf169 Board lenovo t530 & x230: Non-local header treated as local
by HAOUAS Elyes 02 Jun '14

02 Jun '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5921 -gerrit commit cfaf169afa946615ac386ba7d59197ea300d59d8 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Jun 2 22:35:33 2014 +0200 Board lenovo t530 & x230: Non-local header treated as local Change-Id: I40864bfeb7deccb459386b7201ad76eefc815253 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/lenovo/t530/gpio.h | 2 +- src/mainboard/lenovo/t530/romstage.c | 8 ++++---- src/mainboard/lenovo/x230/gpio.h | 2 +- src/mainboard/lenovo/x230/romstage.c | 8 ++++---- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.h index 70e4c09..93a3113 100644 --- a/src/mainboard/lenovo/t530/gpio.h +++ b/src/mainboard/lenovo/t530/gpio.h @@ -21,7 +21,7 @@ #ifndef T530_GPIO_H #define T530_GPIO_H -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 96b5205..6279dc9 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -31,10 +31,10 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/lenovo/x230/gpio.h b/src/mainboard/lenovo/x230/gpio.h index f0a32a8..6aae1ce 100644 --- a/src/mainboard/lenovo/x230/gpio.h +++ b/src/mainboard/lenovo/x230/gpio.h @@ -21,7 +21,7 @@ #ifndef X230_GPIO_H #define X230_GPIO_H -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 6e4e685..d3266e6 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -31,10 +31,10 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h>

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Patch set updated for coreboot: 6aaf1a8 superio/nuvoton: Add support for Nuvoton NCT6776D
by Felix Held 02 Jun '14

02 Jun '14

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5450 -gerrit commit 6aaf1a8eb7907fc756a34a78e67a38f4b8f1cf07 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Mon Jun 2 22:01:54 2014 +0200 superio/nuvoton: Add support for Nuvoton NCT6776D The NCT6776F is the same chip in a different package. Change-Id: If6686ea0a1cd6be537e286699b4ee8f88ba8ad7c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/superio/nuvoton/Kconfig | 4 ++ src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/nct6776d/Makefile.inc | 22 +++++++++ src/superio/nuvoton/nct6776d/nct6776d.h | 60 +++++++++++++++++++++++ src/superio/nuvoton/nct6776d/superio.c | 80 +++++++++++++++++++++++++++++++ 5 files changed, 167 insertions(+) diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index 350c8dd..f644259 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -28,3 +28,7 @@ config SUPERIO_NUVOTON_WPCM450 config SUPERIO_NUVOTON_NCT5104D bool select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT6776D + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 1ce6963..ad7cac7 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -22,3 +22,4 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776D) += nct6776d diff --git a/src/superio/nuvoton/nct6776d/Makefile.inc b/src/superio/nuvoton/nct6776d/Makefile.inc new file mode 100755 index 0000000..aacfa31 --- /dev/null +++ b/src/superio/nuvoton/nct6776d/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6776D) += superio.c diff --git a/src/superio/nuvoton/nct6776d/nct6776d.h b/src/superio/nuvoton/nct6776d/nct6776d.h new file mode 100755 index 0000000..abd908e --- /dev/null +++ b/src/superio/nuvoton/nct6776d/nct6776d.h @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_NCT6776D_H +#define SUPERIO_NUVOTON_NCT6776D_H + +/* Logical Device Numbers (LDN). */ +#define NCT6776D_FDC 0x00 /* Floppy */ +#define NCT6776D_PP 0x01 /* Parallel port */ +#define NCT6776D_SP1 0x02 /* Com1 */ +#define NCT6776D_SP2 0x03 /* Com2 & IR */ +#define NCT6776D_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT6776D_CIR 0x06 +#define NCT6776D_GPIO6789_V 0x07 +#define NCT6776D_WDT1_GPIO01A_V 0x08 +#define NCT6776D_GPIO1234567_V 0x09 +#define NCT6776D_ACPI 0x0A +#define NCT6776D_HWM_FPLED 0x0B /* Hardware monitor & front LED */ +#define NCT6776D_VID 0x0D +#define NCT6776D_CIRWKUP 0x0E /* CIR wakeup */ +#define NCT6776D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ +#define NCT6776D_SVID 0x14 +#define NCT6776D_DSLP 0x16 /* Deep sleep */ +#define NCT6776D_GPIOA_LDN 0x17 + +/* virtual LDN for GPIO and WDT */ +#define NCT6776D_WDT1 ((0 << 8) | NCT6776D_WDT1_GPIO01A_V) + +#define NCT6776D_GPIOBASE ((0 << 8) | NCT6776D_WDT1_GPIO01A_V) //? + +#define NCT6776D_GPIO0 ((1 << 8) | NCT6776D_WDT1_GPIO01A_V) +#define NCT6776D_GPIO1 ((1 << 8) | NCT6776D_GPIO1234567_V) +#define NCT6776D_GPIO2 ((2 << 8) | NCT6776D_GPIO1234567_V) +#define NCT6776D_GPIO3 ((3 << 8) | NCT6776D_GPIO1234567_V) +#define NCT6776D_GPIO4 ((4 << 8) | NCT6776D_GPIO1234567_V) +#define NCT6776D_GPIO5 ((5 << 8) | NCT6776D_GPIO1234567_V) +#define NCT6776D_GPIO6 ((6 << 8) | NCT6776D_GPIO1234567_V) +#define NCT6776D_GPIO7 ((7 << 8) | NCT6776D_GPIO1234567_V) +#define NCT6776D_GPIO8 ((0 << 8) | NCT6776D_GPIO6789_V) +#define NCT6776D_GPIO9 ((1 << 8) | NCT6776D_GPIO6789_V) +#define NCT6776D_GPIOA ((2 << 8) | NCT6776D_WDT1_GPIO01A_V) + +#endif /* SUPERIO_NUVOTON_NCT6776D_H */ diff --git a/src/superio/nuvoton/nct6776d/superio.c b/src/superio/nuvoton/nct6776d/superio.c new file mode 100755 index 0000000..0c840f9 --- /dev/null +++ b/src/superio/nuvoton/nct6776d/superio.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <stdlib.h> +#include "nct6776d.h" + +static void nct6776d_init(device_t dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6776d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + //TODO: set field from struct io_info seems to be unused. why set this to 0 or 4? + { &ops, NCT6776D_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776D_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776D_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, NCT6776D_CIR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776D_ACPI}, + { &ops, NCT6776D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ffe, 0}, {0x0ffe, 4}, }, + { &ops, NCT6776D_VID}, + { &ops, NCT6776D_CIRWKUP, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776D_GPIO_PP_OD}, + { &ops, NCT6776D_SVID}, + { &ops, NCT6776D_DSLP}, + { &ops, NCT6776D_GPIOA_LDN}, + { &ops, NCT6776D_WDT1}, + { &ops, NCT6776D_GPIOBASE, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, NCT6776D_GPIO0}, + { &ops, NCT6776D_GPIO1}, + { &ops, NCT6776D_GPIO2}, + { &ops, NCT6776D_GPIO3}, + { &ops, NCT6776D_GPIO4}, + { &ops, NCT6776D_GPIO5}, + { &ops, NCT6776D_GPIO6}, + { &ops, NCT6776D_GPIO7}, + { &ops, NCT6776D_GPIO8}, + { &ops, NCT6776D_GPIO9}, + { &ops, NCT6776D_GPIOA}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6776d_ops = { + CHIP_NAME("NUVOTON NCT6776D Super I/O") + .enable_dev = enable_dev, +};

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coreboot-gerrit June 2014