coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 1a100f7 Board Google: butterfly, link, parrot, peppy, slippy and stout Non-local header treated as local.
by HAOUAS Elyes 01 Jun '14

01 Jun '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5910 -gerrit commit 1a100f7c7446675877839a603b8449ac1086eab8 Author: Elyes <ehaouas(a)noos.fr> Date: Sun Jun 1 19:04:01 2014 +0200 Board Google: butterfly, link, parrot,peppy, slippy and stout Non-local header treated as local. Change-Id: I1a0ed50724ca4f1c783a578cc7c7661c8221b181 Signed-off-by: Elyes <ehaouas(a)noos.fr> --- src/mainboard/google/butterfly/gpio.h | 2 +- src/mainboard/google/butterfly/romstage.c | 8 ++++---- src/mainboard/google/link/gpio.h | 2 +- src/mainboard/google/link/romstage.c | 10 +++++----- src/mainboard/google/parrot/gpio.h | 2 +- src/mainboard/google/parrot/romstage.c | 10 +++++----- src/mainboard/google/peppy/romstage.c | 12 ++++++------ src/mainboard/google/slippy/romstage.c | 10 +++++----- src/mainboard/google/stout/gpio.h | 2 +- src/mainboard/google/stout/romstage.c | 8 ++++---- 10 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/mainboard/google/butterfly/gpio.h b/src/mainboard/google/butterfly/gpio.h index b592e6a..ec68bf8 100644 --- a/src/mainboard/google/butterfly/gpio.h +++ b/src/mainboard/google/butterfly/gpio.h @@ -20,7 +20,7 @@ #ifndef BUTTERFLY_GPIO_H #define BUTTERFLY_GPIO_H -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NONE, /* Unused */ diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index d32f3f0..418cb71 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -30,10 +30,10 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/google/link/gpio.h b/src/mainboard/google/link/gpio.h index 6caa48b..2b91c6c 100644 --- a/src/mainboard/google/link/gpio.h +++ b/src/mainboard/google/link/gpio.h @@ -20,7 +20,7 @@ #ifndef LINK_GPIO_H #define LINK_GPIO_H -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f17880..3ca61cd 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -31,11 +31,11 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" -#include "ec/google/chromeec/ec.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> +#include <ec/google/chromeec/ec.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/google/parrot/gpio.h b/src/mainboard/google/parrot/gpio.h index a9eb99b..40fa096 100644 --- a/src/mainboard/google/parrot/gpio.h +++ b/src/mainboard/google/parrot/gpio.h @@ -20,7 +20,7 @@ #ifndef PARROT_GPIO_H #define PARROT_GPIO_H -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_NONE, /* NOT USED */ diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 1799aec..6eb73a2 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -30,10 +30,10 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> @@ -42,7 +42,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #endif #include <cbfs.h> -#include "ec/compal/ene932/ec.h" +#include <ec/compal/ene932/ec.h> static void pch_enable_lpc(void) { diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 38c224b..8b3516c 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -24,12 +24,12 @@ #include <string.h> #include <cbfs.h> #include <console/console.h> -#include "cpu/intel/haswell/haswell.h" -#include "ec/google/chromeec/ec.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include <cpu/intel/haswell/haswell.h> +#include <ec/google/chromeec/ec.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> #include "gpio.h" #include "onboard.h" diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index fd190ed..6feebac 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -24,11 +24,11 @@ #include <string.h> #include <cbfs.h> #include <console/console.h> -#include "cpu/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> #include "gpio.h" const struct rcba_config_instruction rcba_config[] = { diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h index 7bc4667..af3ad12 100644 --- a/src/mainboard/google/stout/gpio.h +++ b/src/mainboard/google/stout/gpio.h @@ -20,7 +20,7 @@ #ifndef STOUT_GPIO_H #define STOUT_GPIO_H -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index f53c07d..76a90ed 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -30,10 +30,10 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h>

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Patch set updated for coreboot: 5939596 superio/nuvoton: factor out generic romstage components
by Felix Held 01 Jun '14

01 Jun '14

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5909 -gerrit commit 59395967b5f93269e78992060dedab5393fd1962 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Sun Jun 1 19:01:36 2014 +0200 superio/nuvoton: factor out generic romstage components The romstage of Nuvoton SuperIO chips (but not Nuvoton BMC chips) is identical, so the early_serial.c file can be moved under nuvoton/common. The Nuvoton BMC chip WPCM450 is however left untouched. Change-Id: I4663176c1003b24a49a9fe5f9ebd27a1963b5565 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/superio/nuvoton/Kconfig | 7 +++ src/superio/nuvoton/Makefile.inc | 3 ++ src/superio/nuvoton/common/early_serial.c | 74 +++++++++++++++++++++++++++++++ src/superio/nuvoton/common/nuvoton.h | 30 +++++++++++++ src/superio/nuvoton/nct5104d/Makefile.inc | 1 - src/superio/nuvoton/nct5104d/early_init.c | 46 ------------------- src/superio/nuvoton/nct5104d/nct5104d.h | 2 - 7 files changed, 114 insertions(+), 49 deletions(-) diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index 142738d..350c8dd 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -17,7 +17,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# Generic Nuvoton romstage driver - Just enough UART initialisation code for +# romstage. +config SUPERIO_NUVOTON_COMMON_ROMSTAGE + bool + config SUPERIO_NUVOTON_WPCM450 bool + config SUPERIO_NUVOTON_NCT5104D bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 18025c9..1ce6963 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -17,5 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## include generic nuvoton pre-ram stage driver +romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c + subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c new file mode 100644 index 0000000..8dabe66 --- /dev/null +++ b/src/superio/nuvoton/common/early_serial.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * A generic romstage (pre-ram) driver for Nuvoton variant Super I/O chips. + * + * The following is derived directly from the vendor Nuvoton's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Nuvoton Super I/O's we are required to + * pass magic numbers `passwords keys`. + * + * NUVOTON_ENTRY_KEY := enable configuration : 0x87 + * NUVOTON_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then write to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "nuvoton.h" + +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void nuvoton_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h new file mode 100644 index 0000000..e9e8d4b --- /dev/null +++ b/src/superio/nuvoton/common/nuvoton.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_COMMON_ROMSTAGE_H +#define SUPERIO_NUVOTON_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +void nuvoton_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_NUVOTON_COMMON_ROMSTAGE_H */ diff --git a/src/superio/nuvoton/nct5104d/Makefile.inc b/src/superio/nuvoton/nct5104d/Makefile.inc index 7c97d05..fcb5ec2 100644 --- a/src/superio/nuvoton/nct5104d/Makefile.inc +++ b/src/superio/nuvoton/nct5104d/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += early_init.c ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += superio.c diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c deleted file mode 100644 index f3d8990..0000000 --- a/src/superio/nuvoton/nct5104d/early_init.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "nct5104d.h" - -static void pnp_enter_extended_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87,port); - outb(0x87,port); -} - -static void pnp_exit_extended_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa,port); -} - -void nct5104d_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_extended_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev,0); - pnp_set_iobase(dev,PNP_IDX_IO0, iobase); - pnp_set_enable(dev,1); - pnp_exit_extended_mode(dev); -} diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index 98baf81..5c30e02 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -37,6 +37,4 @@ #define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V) #define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V) -void nct5104d_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_NUVOTON_NCT5104D_NCT5104D_H */

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New patch to review for coreboot: 85474a7 superio/nuvoton: factor out generic romstage components
by Felix Held 01 Jun '14

01 Jun '14

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5909 -gerrit commit 85474a7b97353f27819d8d776d489a62a7b3fc10 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Sun Jun 1 18:57:20 2014 +0200 superio/nuvoton: factor out generic romstage components The romstage of Nuvoton SuperIO chips (but not Nuvoton BMC chips) is identical, so the early_serial.c file can be moved under nuvoton/common. The Nuvoton BMC chip WPCM450 is however left untouched. Change-Id: I4663176c1003b24a49a9fe5f9ebd27a1963b5565 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- 3rdparty | 2 +- src/superio/nuvoton/Kconfig | 7 +++ src/superio/nuvoton/Makefile.inc | 3 ++ src/superio/nuvoton/common/early_serial.c | 74 +++++++++++++++++++++++++++++++ src/superio/nuvoton/common/nuvoton.h | 30 +++++++++++++ src/superio/nuvoton/nct5104d/Makefile.inc | 1 - src/superio/nuvoton/nct5104d/early_init.c | 46 ------------------- src/superio/nuvoton/nct5104d/nct5104d.h | 2 - 8 files changed, 115 insertions(+), 50 deletions(-) diff --git a/3rdparty b/3rdparty index 45f0c04..324ec3c 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit 45f0c04fd788fb29d9e303b2b2d1657ddb03448a +Subproject commit 324ec3cb642a278d6d97ae809bc6098045bc6e65 diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index 142738d..350c8dd 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -17,7 +17,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# Generic Nuvoton romstage driver - Just enough UART initialisation code for +# romstage. +config SUPERIO_NUVOTON_COMMON_ROMSTAGE + bool + config SUPERIO_NUVOTON_WPCM450 bool + config SUPERIO_NUVOTON_NCT5104D bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 18025c9..1ce6963 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -17,5 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## include generic nuvoton pre-ram stage driver +romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c + subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c new file mode 100644 index 0000000..8dabe66 --- /dev/null +++ b/src/superio/nuvoton/common/early_serial.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * A generic romstage (pre-ram) driver for Nuvoton variant Super I/O chips. + * + * The following is derived directly from the vendor Nuvoton's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Nuvoton Super I/O's we are required to + * pass magic numbers `passwords keys`. + * + * NUVOTON_ENTRY_KEY := enable configuration : 0x87 + * NUVOTON_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then write to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "nuvoton.h" + +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void nuvoton_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h new file mode 100644 index 0000000..e9e8d4b --- /dev/null +++ b/src/superio/nuvoton/common/nuvoton.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_COMMON_ROMSTAGE_H +#define SUPERIO_NUVOTON_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +void nuvoton_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_NUVOTON_COMMON_ROMSTAGE_H */ diff --git a/src/superio/nuvoton/nct5104d/Makefile.inc b/src/superio/nuvoton/nct5104d/Makefile.inc index 7c97d05..fcb5ec2 100644 --- a/src/superio/nuvoton/nct5104d/Makefile.inc +++ b/src/superio/nuvoton/nct5104d/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += early_init.c ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += superio.c diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c deleted file mode 100644 index f3d8990..0000000 --- a/src/superio/nuvoton/nct5104d/early_init.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "nct5104d.h" - -static void pnp_enter_extended_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87,port); - outb(0x87,port); -} - -static void pnp_exit_extended_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa,port); -} - -void nct5104d_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_extended_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev,0); - pnp_set_iobase(dev,PNP_IDX_IO0, iobase); - pnp_set_enable(dev,1); - pnp_exit_extended_mode(dev); -} diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index 98baf81..5c30e02 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -37,6 +37,4 @@ #define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V) #define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V) -void nct5104d_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_NUVOTON_NCT5104D_NCT5104D_H */

1 0

Patch set updated for coreboot: 1438c3f x230: Deploy VBT
by Vladimir Serbinenko 01 Jun '14

01 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5396 -gerrit commit 1438c3f4e863ddd7f31e6005dc3f126db750ac05 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:13:56 2014 +0100 x230: Deploy VBT Change-Id: Ide31a56bfdbc31cd3b87993dfb4ed8ef0107cdba Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- .../intel/sandybridge/gma_ivybridge_lvds.c | 142 +++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 1f53a74..709a0ba 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -30,9 +30,118 @@ #include "chip.h" #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <device/pci_def.h> #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) +/* VBT definitions copied from Linux. */ +struct vbt_header { + u8 signature[20]; + u16 version; + u16 header_size; + u16 vbt_size; + u8 vbt_checksum; + u8 reserved0; + u32 bdb_offset; + u32 aim_offset[4]; +} __attribute__((packed)); + +struct bdb_header { + u8 signature[16]; + u16 version; + u16 header_size; + u16 bdb_size; +} __attribute__((packed)); + +#define BDB_GENERAL_FEATURES 1 + +struct bdb_general_features { + /* bits 1 */ + u8 panel_fitting:2; + u8 flexaim:1; + u8 msg_enable:1; + u8 clear_screen:3; + u8 color_flip:1; + + /* bits 2 */ + u8 download_ext_vbt:1; + u8 enable_ssc:1; + u8 ssc_freq:1; + u8 enable_lfp_on_override:1; + u8 disable_ssc_ddt:1; + u8 rsvd7:1; + u8 display_clock_mode:1; + u8 rsvd8:1; /* finish byte */ + + /* bits 3 */ + u8 disable_smooth_vision:1; + u8 single_dvi:1; + u8 rsvd9:1; + u8 fdi_rx_polarity_inverted:1; + u8 rsvd10:4; /* finish byte */ + + /* bits 4 */ + u8 legacy_monitor_detect; + + /* bits 5 */ + u8 int_crt_support:1; + u8 int_tv_support:1; + u8 int_efp_support:1; + u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ + u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ + u8 rsvd11:3; /* finish byte */ +} __attribute__((packed)); + + +static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, + void *vbt) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset (head, 0, sizeof (*head)); + + memcpy (head->signature, "$VBT SNB/IVB-MOBILE ", 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset (bdb_head, 0, sizeof (*bdb_head)); + memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset (genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} + + static void link_train(u32 mmio) { write32(mmio+0xf000c,0x40); @@ -509,6 +618,39 @@ int i915lightup(const struct northbridge_intel_sandybridge_config *info, memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); set_vbe_mode_info_valid(&edid, lfb); #endif + + /* Linux relies on VBT for panel info. */ + if (read16(0xc0000) != 0xaa55) { + optionrom_header_t *oh = (void *)0xc0000; + optionrom_pcir_t *pcir; + size_t vbt_size; + size_t fake_oprom_size; + struct device *dev; + + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + + memset(oh->reserved, 0, 8192); + + oh->signature = 0xaa55; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)0xc0040; + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->indicator = 0x80; + + vbt_size = generate_vbt (info, (void *)0xc0080); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; + } return 1; }

1 0

Patch set updated for coreboot: 57e5acf x230: Deploy VBT
by Vladimir Serbinenko 01 Jun '14

01 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5396 -gerrit commit 57e5acfcfeff0b904e3a875139074f91eb92603e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:13:56 2014 +0100 x230: Deploy VBT Change-Id: Ide31a56bfdbc31cd3b87993dfb4ed8ef0107cdba Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/gma.c | 1 + src/northbridge/intel/sandybridge/gma.h | 2 + .../intel/sandybridge/gma_ivybridge_lvds.c | 142 +++++++++++++++++++++ 3 files changed, 145 insertions(+) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index d271a1a..a01fe9f 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <bootmode.h> #include <delay.h> +#include <string.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 63368f1..c7c2863 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -166,6 +166,8 @@ typedef struct { #define VBT_SIGNATURE 0x54425624 +extern u8 fake_vbt[8192]; + struct northbridge_intel_sandybridge_config; int i915lightup(const struct northbridge_intel_sandybridge_config *info, diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 1f53a74..709a0ba 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -30,9 +30,118 @@ #include "chip.h" #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <device/pci_def.h> #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) +/* VBT definitions copied from Linux. */ +struct vbt_header { + u8 signature[20]; + u16 version; + u16 header_size; + u16 vbt_size; + u8 vbt_checksum; + u8 reserved0; + u32 bdb_offset; + u32 aim_offset[4]; +} __attribute__((packed)); + +struct bdb_header { + u8 signature[16]; + u16 version; + u16 header_size; + u16 bdb_size; +} __attribute__((packed)); + +#define BDB_GENERAL_FEATURES 1 + +struct bdb_general_features { + /* bits 1 */ + u8 panel_fitting:2; + u8 flexaim:1; + u8 msg_enable:1; + u8 clear_screen:3; + u8 color_flip:1; + + /* bits 2 */ + u8 download_ext_vbt:1; + u8 enable_ssc:1; + u8 ssc_freq:1; + u8 enable_lfp_on_override:1; + u8 disable_ssc_ddt:1; + u8 rsvd7:1; + u8 display_clock_mode:1; + u8 rsvd8:1; /* finish byte */ + + /* bits 3 */ + u8 disable_smooth_vision:1; + u8 single_dvi:1; + u8 rsvd9:1; + u8 fdi_rx_polarity_inverted:1; + u8 rsvd10:4; /* finish byte */ + + /* bits 4 */ + u8 legacy_monitor_detect; + + /* bits 5 */ + u8 int_crt_support:1; + u8 int_tv_support:1; + u8 int_efp_support:1; + u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ + u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ + u8 rsvd11:3; /* finish byte */ +} __attribute__((packed)); + + +static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, + void *vbt) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset (head, 0, sizeof (*head)); + + memcpy (head->signature, "$VBT SNB/IVB-MOBILE ", 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset (bdb_head, 0, sizeof (*bdb_head)); + memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset (genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} + + static void link_train(u32 mmio) { write32(mmio+0xf000c,0x40); @@ -509,6 +618,39 @@ int i915lightup(const struct northbridge_intel_sandybridge_config *info, memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); set_vbe_mode_info_valid(&edid, lfb); #endif + + /* Linux relies on VBT for panel info. */ + if (read16(0xc0000) != 0xaa55) { + optionrom_header_t *oh = (void *)0xc0000; + optionrom_pcir_t *pcir; + size_t vbt_size; + size_t fake_oprom_size; + struct device *dev; + + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + + memset(oh->reserved, 0, 8192); + + oh->signature = 0xaa55; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)0xc0040; + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->indicator = 0x80; + + vbt_size = generate_vbt (info, (void *)0xc0080); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; + } return 1; }

1 0

Patch set updated for coreboot: 9cf736d ivybridge: LVDS gfx init.
by Vladimir Serbinenko 01 Jun '14

01 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5285 -gerrit commit 9cf736d1c0db32fc112ff0fdf607d7ec1f0553d8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:10:35 2014 +0100 ivybridge: LVDS gfx init. Change-Id: If71e9c94922cd4283d5e175dfd8757d398a72be1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/Kconfig | 5 + src/mainboard/lenovo/x230/devicetree.cb | 6 + src/northbridge/intel/sandybridge/Kconfig | 4 + src/northbridge/intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/chip.h | 5 + .../intel/sandybridge/gma_ivybridge_lvds.c | 515 +++++++++++++++++++++ 6 files changed, 536 insertions(+) diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 54270d3..d3aa6e9 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -14,6 +14,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select EARLY_CBMEM_INIT + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a76de5f..1a93ad8 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -10,6 +10,12 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gpu_use_spread_spectrum_clock" = "1" + register "gpu_lvds_dual_channel" = "0" + register "gpu_link_frequency_270_mhz" = "1" + register "gpu_lvds_num_lanes" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 83da527..fb92e40 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -41,6 +41,10 @@ config CACHE_MRC_SIZE_KB int default 512 +config IVYBRIDGE_LVDS + bool + default n + config MRC_CACHE_SIZE hex depends on !CHROMEOS diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a201745..6655e2a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c +ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 16df91b..e55d593 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -38,5 +38,10 @@ struct northbridge_intel_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + + int gpu_use_spread_spectrum_clock; + int gpu_lvds_dual_channel; + int gpu_link_frequency_270_mhz; + int gpu_lvds_num_lanes; }; diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c new file mode 100644 index 0000000..1f53a74 --- /dev/null +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -0,0 +1,515 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013, 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <string.h> + +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915.h> +#include "gma.h" +#include "chip.h" +#include <pc80/vga.h> +#include <pc80/vga_io.h> + +#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) + +static void link_train(u32 mmio) +{ + write32(mmio+0xf000c,0x40); + write32(mmio+0x60100,0x40000); + write32(mmio+0xf0018,0x8ff); + write32(mmio+0xf1018,0x8ff); + write32(mmio+0xf000c,0x2040); + mdelay(1); + write32(mmio+0xf000c,0x2050); + write32(mmio+0x60100,0x44000); + mdelay(1); + write32(mmio+0x70008,0x40); + write32(mmio+0xe0300,0x60000418); + write32(mmio+0xf000c,0x22050); + write32(mmio+0x70008,0x50); + write32(mmio+0x70008,0x80000050); +} + +static void link_normal_operation(u32 mmio) +{ + write32(mmio + FDI_TX_CTL(0), 0x80044f02); + write32(mmio + FDI_RX_CTL(0), + FDI_RX_ENABLE | FDI_6BPC + | 0x2f50); +} + +static void enable_port(u32 mmio) +{ + write32(mmio + 0xec008, 0x2c010000); + write32(mmio + 0xec020, 0x2c010000); + write32(mmio + 0xec038, 0x2c010000); + write32(mmio + 0xec050, 0x2c010000); + write32(mmio + 0xec408, 0x2c010000); + write32(mmio + 0xec420, 0x2c010000); + write32(mmio + 0xec438, 0x2c010000); + write32(mmio + 0xec450, 0x2c010000); + write32(mmio + 0xf0010, 0x200090); + write32(mmio + 0xf1010, 0x200090); + write32(mmio + 0xf2010, 0x200090); + write32(mmio + 0xfd034, 0x8420000); + write32(mmio + 0x45010, 0x3); + write32(mmio + 0xf0060, 0x10); + write32(mmio + 0xf1060, 0x10); + write32(mmio + 0xf2060, 0x10); + write32(mmio + 0x9840, 0x0); + write32(mmio + 0x42000, 0xa0000000); + write32(mmio + 0xe4f00, 0x100030c); + write32(mmio + 0xe4f04, 0xb8230c); + write32(mmio + 0xe4f08, 0x6f8930c); + write32(mmio + 0xe4f0c, 0x5f8e38e); + write32(mmio + 0xe4f10, 0xb8030c); + write32(mmio + 0xe4f14, 0xb78830c); + write32(mmio + 0xe4f18, 0x9f8d3cf); + write32(mmio + 0xe4f1c, 0x1e8030c); + write32(mmio + 0xe4f20, 0x9f863cf); + write32(mmio + 0xe4f24, 0xff803cf); + read32(mmio + 0xe4100); + write32(mmio + 0xc4030, 0x10); + write32(mmio + 0xe4110, 0x8004003e); + write32(mmio + 0xe4114, 0x80060000); + write32(mmio + 0xe4118, 0x1000000); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xc4000); + read32(mmio + 0xe1140); + write32(mmio + 0xc4030, 0x10); + read32(mmio + 0xc4000); + write32(mmio + 0xe4f00, 0x100030c); + write32(mmio + 0xe4f04, 0xb8230c); + write32(mmio + 0xe4f08, 0x6f8930c); + write32(mmio + 0xe4f0c, 0x5f8e38e); + write32(mmio + 0xe4f10, 0xb8030c); + write32(mmio + 0xe4f14, 0xb78830c); + write32(mmio + 0xe4f18, 0x9f8d3cf); + write32(mmio + 0xe4f1c, 0x1e8030c); + write32(mmio + 0xe4f20, 0x9f863cf); + write32(mmio + 0xe4f24, 0xff803cf); + read32(mmio + 0xe4200); + write32(mmio + 0xc4030, 0x1010); + write32(mmio + 0xe4210, 0x8004003e); + write32(mmio + 0xe4214, 0x80060000); + write32(mmio + 0xe4218, 0x1002000); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xc4000); +} + +int i915lightup(const struct northbridge_intel_sandybridge_config *info, + u32 physbase, u16 piobase, u32 mmio, u32 lfb) +{ + int i; + u8 edid_data[128]; + struct edid edid; + + write32(mmio + 0x00070080, 0x00000000); + write32(mmio + DSPCNTR(0), 0x00000000); + write32(mmio + 0x00071180, 0x00000000); + write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE); + write32(mmio + 0x0007019c, 0x00000000); + write32(mmio + 0x0007119c, 0x00000000); + write32(mmio + 0x000fc008, 0x2c010000); + write32(mmio + 0x000fc020, 0x2c010000); + write32(mmio + 0x000fc038, 0x2c010000); + write32(mmio + 0x000fc050, 0x2c010000); + write32(mmio + 0x000fc408, 0x2c010000); + write32(mmio + 0x000fc420, 0x2c010000); + write32(mmio + 0x000fc438, 0x2c010000); + write32(mmio + 0x000fc450, 0x2c010000); + vga_gr_write(0x18, 0); + write32(mmio + 0x00042004, 0x02000000); + write32(mmio + 0x000fd034, 0x8421ffe0); + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + vga_misc_write(0x67); + + u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + enable_port(mmio); + + intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128); + decode_edid(edid_data, + sizeof(edid_data), &edid); + + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + u32 hactive = edid.x_resolution; + u32 vactive = edid.y_resolution; + u32 right_border = edid.hborder; + u32 bottom_border = edid.vborder; + int hpolarity = (edid.phsync == '-'); + int vpolarity = (edid.pvsync == '-'); + u32 vsync = edid.vspw; + u32 hsync = edid.hspw; + u32 vblank = edid.vbl; + u32 hblank = edid.hbl; + u32 hfront_porch = edid.hso; + u32 vfront_porch = edid.vso; + + u32 candp1, candn; + u32 best_delta = 0xffffffff; + + u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + : (2 * edid.pixel_clock); + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + +#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + vga_textmode_init(); +#else + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); +#endif + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return 0; + } + + u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00080000; + + link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; + + data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1)); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, + info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); + + write32(mmio + PCH_LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); + write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + ? 0x1002 : 0x400)); + mdelay(1); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(mmio + _PCH_FP0(0), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(mmio + _PCH_DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + + mdelay(1); + write32(mmio + 0xc7000, 0x8); + + mdelay(1); + write32(mmio + _PCH_DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + /* Re-lock the registers. */ + write32(mmio + PCH_PP_CONTROL, + (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(mmio + PCH_LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + + write32(mmio + HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + 0xf0008, 0); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); + write32(mmio + PF_CTL(0),0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PF_WIN_POS(0), 0); +#else + write32(mmio + PIPESRC(0), (719 << 16) | 399); + write32(mmio + PF_WIN_POS(0), 0); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +#endif + + mdelay(1); + + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + + link_train(mmio); +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE); +#else + write32(mmio+CPU_VGACNTRL,0x298e); +#endif + write32(mmio+0x60100,0x44300); + write32(mmio+0x60100,0x80044f00); + + mdelay(1); + read32(mmio + 0x000f0014); // = 0x00000600 + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); +#endif + + write32(mmio + TRANS_HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + TRANS_HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + TRANS_HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + TRANS_VTOTAL(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + TRANS_VBLANK(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + TRANS_VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + link_normal_operation(mmio); + + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + + mdelay(1); + + write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + | TRANS_STATE_MASK +#endif + ); + write32(mmio + PCH_LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) + { + u32 reg32; + reg32 = read32(mmio + PCH_PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); + + write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); +#endif + return 1; +} + +#endif

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Patch set updated for coreboot: 7380110 sandybridge: Pass chip info to i915lightup.
by Vladimir Serbinenko 01 Jun '14

01 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5284 -gerrit commit 7380110c5bdafb024f16c9f724d5b6a1133cf185 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:09:48 2014 +0100 sandybridge: Pass chip info to i915lightup. Change-Id: I280441aadb0575dc0b99584cdcd48cc76a0289a2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/link/i915.c | 8 +++----- src/northbridge/intel/sandybridge/gma.c | 4 ++-- src/northbridge/intel/sandybridge/gma.h | 5 +++++ 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 2b62bf4..233148c 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -35,6 +35,7 @@ #include "onboard.h" #include "ec.h" #include <southbridge/intel/bd82x6x/pch.h> +#include <northbridge/intel/sandybridge/gma.h> #include <smbios.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h> @@ -235,11 +236,8 @@ static int run(int index) return i+1; } -int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, - unsigned int gfx); - -int i915lightup(unsigned int pphysbase, unsigned int piobase, - unsigned int pmmio, unsigned int pgfx) +int i915lightup(const struct northbridge_intel_sandybridge_config *info, + u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) { static struct edid edid; int edid_ok; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 2d8bd77..d271a1a 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -644,13 +644,13 @@ static void gma_func0_init(struct device *dev) /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); u32 iobase, mmiobase, physbase, graphics_base; + struct northbridge_intel_sandybridge_config *conf = dev->chip_info; iobase = dev->resource_list[2].base; mmiobase = dev->resource_list[0].base; physbase = pci_read_config32(dev, 0x5c) & ~0xf; graphics_base = dev->resource_list[1].base; - int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); - int lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base); + int lightup_ok = i915lightup(conf, physbase, iobase, mmiobase, graphics_base); if (lightup_ok) gfx_set_init_done(1); #endif diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index bfa43ef..63368f1 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -166,3 +166,8 @@ typedef struct { #define VBT_SIGNATURE 0x54425624 +struct northbridge_intel_sandybridge_config; + +int i915lightup(const struct northbridge_intel_sandybridge_config *info, + u32 physbase, u16 pio, u32 mmio, u32 lfb); +

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New patch to review for coreboot: beacde1 Board lenovo/t530 x230: Non-local header treated as local
by HAOUAS Elyes 01 Jun '14

01 Jun '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5908 -gerrit commit beacde1c2d92579b2545854811706cf063f55df1 Author: Elyes <ehaouas(a)noos.fr> Date: Sun Jun 1 15:29:40 2014 +0200 Board lenovo/t530 x230: Non-local header treated as local Change-Id: I307ca2e8b27378b7b1e2b49961c7d760d660f280 Signed-off-by: Elyes <ehaouas(a)noos.fr> --- src/mainboard/lenovo/t530/gpio.h | 2 +- src/mainboard/lenovo/t530/romstage.c | 8 ++++---- src/mainboard/lenovo/x230/gpio.h | 2 +- src/mainboard/lenovo/x230/romstage.c | 8 ++++---- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.h index 70e4c09..93a3113 100644 --- a/src/mainboard/lenovo/t530/gpio.h +++ b/src/mainboard/lenovo/t530/gpio.h @@ -21,7 +21,7 @@ #ifndef T530_GPIO_H #define T530_GPIO_H -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 96b5205..6279dc9 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -31,10 +31,10 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/lenovo/x230/gpio.h b/src/mainboard/lenovo/x230/gpio.h index f0a32a8..6aae1ce 100644 --- a/src/mainboard/lenovo/x230/gpio.h +++ b/src/mainboard/lenovo/x230/gpio.h @@ -21,7 +21,7 @@ #ifndef X230_GPIO_H #define X230_GPIO_H -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 6e4e685..d3266e6 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -31,10 +31,10 @@ #include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h>

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New patch to review for coreboot: 83e240c board lenovo/x60: Non-local header treated as local
by HAOUAS Elyes 01 Jun '14

01 Jun '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5907 -gerrit commit 83e240c85637d5e0be2fdd3f3fc187cf5b375337 Author: Elyes <ehaouas(a)noos.fr> Date: Sun Jun 1 15:25:21 2014 +0200 board lenovo/x60: Non-local header treated as local Change-Id: Ia39d0107151c3979b6dbfa04aaf3023e52d3fae2 Signed-off-by: Elyes <ehaouas(a)noos.fr> --- src/mainboard/lenovo/x60/acpi_tables.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index f6ed4ae..2c8ff8c 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -35,7 +35,7 @@ extern const unsigned char AmlCode[]; unsigned long acpi_create_slic(unsigned long current); #endif -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> static void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs));

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New patch to review for coreboot: e533e83 Board lenovo/x201 : Non-local header treated as local
by HAOUAS Elyes 01 Jun '14

01 Jun '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5906 -gerrit commit e533e83bfadcc83ec8bf38ce965031b76a2ab2a1 Author: Elyes <ehaouas(a)noos.fr> Date: Sun Jun 1 15:22:42 2014 +0200 Board lenovo/x201 : Non-local header treated as local Change-Id: I62d0fc66263ed23e70322df9eeaa9acd7ecf314d Signed-off-by: Elyes <ehaouas(a)noos.fr> --- src/mainboard/lenovo/x201/acpi_tables.c | 2 +- src/mainboard/lenovo/x201/dock.c | 4 ++-- src/mainboard/lenovo/x201/gpio.h | 2 +- src/mainboard/lenovo/x201/romstage.c | 10 +++++----- src/mainboard/lenovo/x201/smihandler.c | 6 +++--- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 165de0d..10adb86 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -30,7 +30,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include "southbridge/intel/ibexpeak/nvs.h" +#include <southbridge/intel/ibexpeak/nvs.h> extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index fbcf99e..dfc29a6 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -27,8 +27,8 @@ #include <device/pci.h> #include <delay.h> #include "dock.h" -#include "southbridge/intel/ibexpeak/pch.h" -#include "ec/lenovo/h8/h8.h" +#include <southbridge/intel/ibexpeak/pch.h> +#include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h> void h8_mainboard_init_dock (void) diff --git a/src/mainboard/lenovo/x201/gpio.h b/src/mainboard/lenovo/x201/gpio.h index d9e9ff2..66bc547 100644 --- a/src/mainboard/lenovo/x201/gpio.h +++ b/src/mainboard/lenovo/x201/gpio.h @@ -20,7 +20,7 @@ #ifndef LENOVO_X201_GPIO_H #define LENOVO_X201_GPIO_H -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 1237a5c..dc2caff 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -40,12 +40,12 @@ #include "gpio.h" #include "dock.h" -#include "arch/early_variables.h" -#include "southbridge/intel/ibexpeak/pch.h" -#include "northbridge/intel/nehalem/nehalem.h" +#include <arch/early_variables.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <northbridge/intel/nehalem/nehalem.h> -#include "northbridge/intel/nehalem/raminit.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/ibexpeak/me.h> static void pch_enable_lpc(void) { diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 0529818..76a53cd 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -22,9 +22,9 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/ibexpeak/nvs.h" -#include "southbridge/intel/ibexpeak/pch.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <southbridge/intel/ibexpeak/nvs.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/ibexpeak/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h>

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coreboot-gerrit June 2014