coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

1 participants
922 discussions

Patch set updated for coreboot: c602778 mainboard: Remove #include early_serial.c from w83977tf boards
by Edward O'Callaghan 01 Jun '14

01 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5898 -gerrit commit c602778ac06617c9588717f1ec94fa2a47bc83a1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 1 17:38:22 2014 +1000 mainboard: Remove #include early_serial.c from w83977tf boards These non-ROMCC boards #include the model specific w83977tf Super I/O romstage component. The generic winbond_early_serial() function serves well here to further tighten integration into the new Super I/O framework and drop dependence on #include'ing .c files, leaving only ROMCC boards. Change-Id: Ib63c0f29f994c54e6112702506f288535799706c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/a-trend/atc-6220/romstage.c | 6 ++++-- src/mainboard/abit/be6-ii_v2_0/romstage.c | 6 +++--- src/mainboard/asus/p2b-d/romstage.c | 5 +++-- src/mainboard/asus/p2b-ds/romstage.c | 5 +++-- src/mainboard/asus/p2b-f/romstage.c | 6 +++--- src/mainboard/asus/p2b-ls/romstage.c | 6 +++--- src/mainboard/asus/p2b/romstage.c | 6 ++++-- src/mainboard/asus/p3b-f/romstage.c | 6 +++--- src/mainboard/azza/pt-6ibd/romstage.c | 6 +++--- src/mainboard/msi/ms6119/romstage.c | 5 +++-- src/mainboard/msi/ms6147/romstage.c | 5 +++-- src/mainboard/msi/ms6156/romstage.c | 5 +++-- 12 files changed, 38 insertions(+), 29 deletions(-) diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 63d34b2..22d3270 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -30,7 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> + #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +44,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 74f8404..510c8ce 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -30,8 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" +#include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> /* FIXME: It's a Winbond W83977EF, actually. */ @@ -44,8 +45,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - /* FIXME: It's a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 213120d..b03dfd5 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 20c4b3f..b4dbe32 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 93849c2..b857754 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -30,8 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" +#include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ @@ -44,8 +45,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index f6daa5e..d046c4b 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -30,8 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" +#include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -43,8 +44,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 63d34b2..22d3270 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -30,7 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> + #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +44,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 3762948..e7a7f43 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -30,8 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" +#include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ @@ -75,8 +76,7 @@ static void disable_spd(void) void main(unsigned long bist) { - /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index c138d00..b4252a6 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -30,8 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" +#include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> /* FIXME: It's a Winbond W83977EF, actually. */ @@ -44,8 +45,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - /* FIXME: It's a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index f597b26..813e855 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index 67fbdc7..b7f99f5 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include <cpu/x86/bist.h> -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index f1f4a67..09713d4 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist);

1 0

Patch set updated for coreboot: db52d42 superio/ite/it8772f: Move towards removing #include .c
by Edward O'Callaghan 01 Jun '14

01 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5899 -gerrit commit db52d426956e1b55e814aeea0eb669875198fce8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 1 18:04:05 2014 +1000 superio/ite/it8772f: Move towards removing #include .c Move samsung/stumpy board towards generic romstage component and away from poorly written hard-coded model specific Super I/O component. This is an incremental step towards getting obj-level abstraction between board and Super I/O. Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/samsung/stumpy/romstage.c | 12 ++++++++---- src/superio/ite/it8772f/early_serial.c | 19 ------------------- src/superio/ite/it8772f/it8772f.h | 10 +++++----- 3 files changed, 13 insertions(+), 28 deletions(-) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 0067cb5..0ae71a8 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -31,7 +31,9 @@ #include <cbmem.h> #include <console/console.h> #include <bootmode.h> -#include "superio/ite/it8772f/it8772f.h" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8772f/it8772f.h> +/* FIXME: SUPERIO include.c */ #include "superio/ite/it8772f/early_serial.c" #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit.h" @@ -58,6 +60,9 @@ #endif #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */ +#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) + static void pch_enable_lpc(void) { /* Set COM1/COM2 decode range */ @@ -233,10 +238,9 @@ void main(unsigned long bist) setup_sio_gpios(); /* Early SuperIO setup */ - it8772f_kill_watchdog(); it8772f_ac_resume_southbridge(); - it8772f_enable_serial(PNP_DEV(IT8772F_BASE, IT8772F_SP1), - CONFIG_TTYS0_BASE); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); init_bootmode_straps(); diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c index 8bf2964..6fed4dd 100644 --- a/src/superio/ite/it8772f/early_serial.c +++ b/src/superio/ite/it8772f/early_serial.c @@ -85,25 +85,6 @@ void it8772f_enable_3vsbsw(void) it8772f_exit_conf(); } -void it8772f_kill_watchdog(void) -{ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); - it8772f_sio_write(IT8772F_CONFIG_REG_WATCHDOG, 0x00); - it8772f_exit_conf(); -} - -/* Enable the serial port(s). */ -void it8772f_enable_serial(device_t dev, u16 iobase) -{ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, dev & 0xff); - it8772f_sio_write(PNP_IDX_IO0, (iobase >> 8) & 0xff); - it8772f_sio_write(PNP_IDX_IO0+1, iobase & 0xff); - it8772f_sio_write(PNP_IDX_EN, 1); - it8772f_exit_conf(); -} - /* Set AC resume to be up to the Southbridge */ void it8772f_ac_resume_southbridge(void) { diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index f881d7a..3d45f09 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -18,9 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8772F_IT8772F_H -#define SUPERIO_ITE_IT8772F_IT8772F_H +#ifndef SUPERIO_ITE_IT8772F_H +#define SUPERIO_ITE_IT8772F_H +/* FIXME: SUPERIO include.c */ #define IT8772F_BASE 0x2e #define IT8772F_FDC 0x00 /* Floppy disk controller */ @@ -107,11 +108,10 @@ u8 it8772f_sio_read(u8 index); void it8772f_sio_write(u8 index, u8 value); -void it8772f_enable_serial(device_t dev, u16 iobase); -void it8772f_kill_watchdog(void); void it8772f_24mhz_clkin(void); void it8772f_enable_3vsbsw(void); void it8772f_ac_resume_southbridge(void); void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup, u8 output, u8 enable); -#endif + +#endif /* SUPERIO_ITE_IT8772F_H */

1 0

Patch set updated for coreboot: dd8ae50 superio/ite/it8772f: Move towards removing #include .c
by Edward O'Callaghan 01 Jun '14

01 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5899 -gerrit commit dd8ae5034019196fee096479e69e9d01bbe1be26 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 1 18:04:05 2014 +1000 superio/ite/it8772f: Move towards removing #include .c Move samsung/stumpy board towards generic romstage component and away from poorly written hard-coded model specific Super I/O component. This is an incremental step towards getting obj-level abstraction between board and Super I/O. Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/samsung/stumpy/romstage.c | 12 ++++++++---- src/superio/ite/it8772f/early_serial.c | 19 ------------------- src/superio/ite/it8772f/it8772f.h | 10 +++++----- 3 files changed, 13 insertions(+), 28 deletions(-) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 0067cb5..efc6f5b 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -31,7 +31,9 @@ #include <cbmem.h> #include <console/console.h> #include <bootmode.h> -#include "superio/ite/it8772f/it8772f.h" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8772f/it8772f.h> +/* FIXME: SUPERIO include.c */ #include "superio/ite/it8772f/early_serial.c" #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit.h" @@ -58,6 +60,9 @@ #endif #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */ +#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO) + static void pch_enable_lpc(void) { /* Set COM1/COM2 decode range */ @@ -233,10 +238,9 @@ void main(unsigned long bist) setup_sio_gpios(); /* Early SuperIO setup */ - it8772f_kill_watchdog(); it8772f_ac_resume_southbridge(); - it8772f_enable_serial(PNP_DEV(IT8772F_BASE, IT8772F_SP1), - CONFIG_TTYS0_BASE); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); init_bootmode_straps(); diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c index 8bf2964..6fed4dd 100644 --- a/src/superio/ite/it8772f/early_serial.c +++ b/src/superio/ite/it8772f/early_serial.c @@ -85,25 +85,6 @@ void it8772f_enable_3vsbsw(void) it8772f_exit_conf(); } -void it8772f_kill_watchdog(void) -{ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); - it8772f_sio_write(IT8772F_CONFIG_REG_WATCHDOG, 0x00); - it8772f_exit_conf(); -} - -/* Enable the serial port(s). */ -void it8772f_enable_serial(device_t dev, u16 iobase) -{ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, dev & 0xff); - it8772f_sio_write(PNP_IDX_IO0, (iobase >> 8) & 0xff); - it8772f_sio_write(PNP_IDX_IO0+1, iobase & 0xff); - it8772f_sio_write(PNP_IDX_EN, 1); - it8772f_exit_conf(); -} - /* Set AC resume to be up to the Southbridge */ void it8772f_ac_resume_southbridge(void) { diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index f881d7a..3d45f09 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -18,9 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8772F_IT8772F_H -#define SUPERIO_ITE_IT8772F_IT8772F_H +#ifndef SUPERIO_ITE_IT8772F_H +#define SUPERIO_ITE_IT8772F_H +/* FIXME: SUPERIO include.c */ #define IT8772F_BASE 0x2e #define IT8772F_FDC 0x00 /* Floppy disk controller */ @@ -107,11 +108,10 @@ u8 it8772f_sio_read(u8 index); void it8772f_sio_write(u8 index, u8 value); -void it8772f_enable_serial(device_t dev, u16 iobase); -void it8772f_kill_watchdog(void); void it8772f_24mhz_clkin(void); void it8772f_enable_3vsbsw(void); void it8772f_ac_resume_southbridge(void); void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup, u8 output, u8 enable); -#endif + +#endif /* SUPERIO_ITE_IT8772F_H */

1 0

New patch to review for coreboot: cff52aa superio/ite/it8772f: Move towards removing #include .c
by Edward O'Callaghan 01 Jun '14

01 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5899 -gerrit commit cff52aa664988ca60083ae26c599f88c78958acd Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 1 18:04:05 2014 +1000 superio/ite/it8772f: Move towards removing #include .c Move samsung/stumpy board towards generic romstage component and away from poorly written hard-coded model specific Super I/O component. This is an incremental step towards getting obj-level abstraction between board and Super I/O. Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/samsung/stumpy/romstage.c | 11 +++++++---- src/superio/ite/it8772f/early_serial.c | 19 ------------------- src/superio/ite/it8772f/it8772f.h | 10 +++++----- 3 files changed, 12 insertions(+), 28 deletions(-) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 0067cb5..4ebb971 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -31,7 +31,9 @@ #include <cbmem.h> #include <console/console.h> #include <bootmode.h> -#include "superio/ite/it8772f/it8772f.h" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8772f/it8772f.h> +/* FIXME: SUPERIO include.c */ #include "superio/ite/it8772f/early_serial.c" #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit.h" @@ -58,6 +60,8 @@ #endif #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */ +#define SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) + static void pch_enable_lpc(void) { /* Set COM1/COM2 decode range */ @@ -233,10 +237,9 @@ void main(unsigned long bist) setup_sio_gpios(); /* Early SuperIO setup */ - it8772f_kill_watchdog(); + ite_kill_watchdog(); it8772f_ac_resume_southbridge(); - it8772f_enable_serial(PNP_DEV(IT8772F_BASE, IT8772F_SP1), - CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); init_bootmode_straps(); diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c index 8bf2964..6fed4dd 100644 --- a/src/superio/ite/it8772f/early_serial.c +++ b/src/superio/ite/it8772f/early_serial.c @@ -85,25 +85,6 @@ void it8772f_enable_3vsbsw(void) it8772f_exit_conf(); } -void it8772f_kill_watchdog(void) -{ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); - it8772f_sio_write(IT8772F_CONFIG_REG_WATCHDOG, 0x00); - it8772f_exit_conf(); -} - -/* Enable the serial port(s). */ -void it8772f_enable_serial(device_t dev, u16 iobase) -{ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, dev & 0xff); - it8772f_sio_write(PNP_IDX_IO0, (iobase >> 8) & 0xff); - it8772f_sio_write(PNP_IDX_IO0+1, iobase & 0xff); - it8772f_sio_write(PNP_IDX_EN, 1); - it8772f_exit_conf(); -} - /* Set AC resume to be up to the Southbridge */ void it8772f_ac_resume_southbridge(void) { diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index f881d7a..3d45f09 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -18,9 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8772F_IT8772F_H -#define SUPERIO_ITE_IT8772F_IT8772F_H +#ifndef SUPERIO_ITE_IT8772F_H +#define SUPERIO_ITE_IT8772F_H +/* FIXME: SUPERIO include.c */ #define IT8772F_BASE 0x2e #define IT8772F_FDC 0x00 /* Floppy disk controller */ @@ -107,11 +108,10 @@ u8 it8772f_sio_read(u8 index); void it8772f_sio_write(u8 index, u8 value); -void it8772f_enable_serial(device_t dev, u16 iobase); -void it8772f_kill_watchdog(void); void it8772f_24mhz_clkin(void); void it8772f_enable_3vsbsw(void); void it8772f_ac_resume_southbridge(void); void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup, u8 output, u8 enable); -#endif + +#endif /* SUPERIO_ITE_IT8772F_H */

1 0

New patch to review for coreboot: 2b50e15 mainboard: Remove #include early_serial.c from w83977tf boards
by Edward O'Callaghan 01 Jun '14

01 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5898 -gerrit commit 2b50e1581019b275b7ff94272d0ccb2124d4a770 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 1 17:38:22 2014 +1000 mainboard: Remove #include early_serial.c from w83977tf boards These non-ROMCC boards #include the model specific w83977tf Super I/O romstage component. The generic winbond_early_serial() function serves well here to further tighten integration into the new Super I/O framework and drop dependence on #include'ing .c files, leaving only ROMCC boards. Change-Id: Ib63c0f29f994c54e6112702506f288535799706c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/a-trend/atc-6220/romstage.c | 6 ++++-- src/mainboard/abit/be6-ii_v2_0/romstage.c | 6 +++--- src/mainboard/asus/p2b-d/romstage.c | 5 +++-- src/mainboard/asus/p2b-ds/romstage.c | 5 +++-- src/mainboard/asus/p2b-f/romstage.c | 6 +++--- src/mainboard/asus/p2b-ls/romstage.c | 6 +++--- src/mainboard/asus/p2b/romstage.c | 6 ++++-- src/mainboard/asus/p3b-f/romstage.c | 6 +++--- src/mainboard/azza/pt-6ibd/romstage.c | 6 +++--- src/mainboard/msi/ms6119/romstage.c | 5 +++-- src/mainboard/msi/ms6147/romstage.c | 5 +++-- src/mainboard/msi/ms6156/romstage.c | 5 +++-- 12 files changed, 38 insertions(+), 29 deletions(-) diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 63d34b2..35034e6 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -30,7 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> + #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +44,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 74f8404..843aba9 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -30,8 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" +#include <superio/winbond/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> /* FIXME: It's a Winbond W83977EF, actually. */ @@ -44,8 +45,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - /* FIXME: It's a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 213120d..e60f476 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 20c4b3f..67fdad5 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 93849c2..50da9fc 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -30,8 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" +#include <superio/winbond/winbond.h> /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ @@ -44,8 +45,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index f6daa5e..706b360 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -30,8 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" +#include <superio/winbond/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -43,8 +44,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 63d34b2..35034e6 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -30,7 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> + #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +44,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 3762948..87c16f3 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -30,8 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" +#include <superio/winbond/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ @@ -75,8 +76,7 @@ static void disable_spd(void) void main(unsigned long bist) { - /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index c138d00..75dd833 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -30,8 +30,9 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" +#include <superio/winbond/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> /* FIXME: It's a Winbond W83977EF, actually. */ @@ -44,8 +45,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - /* FIXME: It's a Winbond W83977EF, actually. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index f597b26..173942f 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index 67fbdc7..e756734 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include <cpu/x86/bist.h> -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index f1f4a67..a721c9e 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977tf/early_serial.c" +#include <superio/winbond/winbond.h> +#include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist);

1 0

Patch set updated for coreboot: d38a857 mainboard/advantech/pcm-5820: Convert uart to generic winbond
by Edward O'Callaghan 01 Jun '14

01 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5703 -gerrit commit d38a8571303ce3b02bdced9798fe92ba6ca04418 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 9 05:07:17 2014 +1000 mainboard/advantech/pcm-5820: Convert uart to generic winbond Take advantage of generic winbond early_serial init driver link-time symbols instead of #including model specific .c implementation. Change-Id: I2fe7ecb11e10262d11c68017a00843f99a35b734 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advantech/pcm-5820/romstage.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index b710aad..6865f1a 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -25,14 +25,15 @@ #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83977f/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83977f/w83977f.h> #include "southbridge/amd/cs5530/enable_rom.c" #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) static void main(unsigned long bist) { - w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); cs5530_enable_rom();

1 0

Patch set updated for coreboot: 6e8edb4 superio/ite/it8661f: Make early_serial into romstage sym
by Edward O'Callaghan 01 Jun '14

01 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5508 -gerrit commit 6e8edb4e4c5c891a871bb4f0a65ede29dca3cbc8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 15 20:30:49 2014 +1000 superio/ite/it8661f: Make early_serial into romstage sym Following similar reasoning as commit: d304331 superio/fintek/f81865f: Avoid .c includes Avoid any mistaken future inclusion of early_serial.c in mainboard.c code by providing symbols in romstage. Change-Id: I9e763a7ad9de090e35acdcf4d6a280d8227c6015 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8661f/Makefile.inc | 2 +- src/superio/ite/it8661f/early_serial.c | 3 ++- src/superio/ite/it8661f/it8661f.h | 8 +++++--- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/superio/ite/it8661f/Makefile.inc b/src/superio/ite/it8661f/Makefile.inc index f6f30db..af4e878 100644 --- a/src/superio/ite/it8661f/Makefile.inc +++ b/src/superio/ite/it8661f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8661F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8661F) += superio.c - diff --git a/src/superio/ite/it8661f/early_serial.c b/src/superio/ite/it8661f/early_serial.c index ee132fa..7373f71 100644 --- a/src/superio/ite/it8661f/early_serial.c +++ b/src/superio/ite/it8661f/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "it8661f.h" /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ @@ -68,7 +69,7 @@ static void it8661f_set_clkin(device_t dev, u8 clkin) pnp_exit_ext_func_mode(dev); } -static void it8661f_enable_serial(device_t dev, u16 iobase) +void it8661f_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/ite/it8661f/it8661f.h b/src/superio/ite/it8661f/it8661f.h index 5a51f02..045a54c 100644 --- a/src/superio/ite/it8661f/it8661f.h +++ b/src/superio/ite/it8661f/it8661f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8661F_IT8661F_H -#define SUPERIO_ITE_IT8661F_IT8661F_H +#ifndef SUPERIO_ITE_IT8661F_H +#define SUPERIO_ITE_IT8661F_H /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */ @@ -52,4 +52,6 @@ static const u8 init_values[] = { 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -#endif +void it8661f_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_ITE_IT8661F_H */

1 0

Patch set updated for coreboot: 79e0dd3 superio/winbond/w83627ehg: Remove pnp_enter symbol from global
by Edward O'Callaghan 01 Jun '14

01 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5871 -gerrit commit 79e0dd3f3291d77054809ec57808d6b937575462 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon May 26 04:35:48 2014 +1000 superio/winbond/w83627ehg: Remove pnp_enter symbol from global Part 2/2: Break this poor relationship between boards and Super I/O support to be more well-defined. The Super I/O pnp_entry/exit functions should not be exposed into the global name-space, rather should be static-local. Provide Winbond w83627eh(f/g) input clock rate selection. This is selected by bit 6 of CR 24h by mask & 0xbf map (1 = 48MHz default) -> (0 = 24MHz), see data-sheet page 98. Change-Id: Ie39235f2926a2165092319a6b1375e505b7dac14 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 13 +++++++++++++ src/mainboard/asus/a8v-e_se/romstage.c | 13 +++++++++++++ src/mainboard/ibase/mb899/romstage.c | 13 +++++++++++++ src/mainboard/msi/ms7260/romstage.c | 5 +---- src/mainboard/msi/ms9652_fam10/romstage.c | 7 +------ src/mainboard/nvidia/l1_2pvv/romstage.c | 4 +--- src/superio/winbond/w83627ehg/early_serial.c | 16 ++++++++++++---- src/superio/winbond/w83627ehg/w83627ehg.h | 6 ++++-- 8 files changed, 58 insertions(+), 19 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 1dea57b..ce8bec0 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -97,6 +97,19 @@ unsigned int get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + static void sio_init(void) { u8 reg; diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index abe5f84..bc159c2 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -97,6 +97,19 @@ unsigned int get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + static void sio_init(void) { u8 reg; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 418b6e4..6848e51 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -69,6 +69,19 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index fd8fbfb..072bae9 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -119,12 +119,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ - pnp_write_config(SERIAL_DEV, 0x24, 0); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); console_init(); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3993bae..eff291b 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -103,7 +103,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; - u8 reg; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { @@ -121,11 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ - reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627ehg_serial_clk(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index df78a0c..75bdb6f 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -118,9 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627ehg_serial_clk(SERIAL_DEV); setup_mb_resource_map(); diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 346d6cf..efeb1f6 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,15 +22,24 @@ #include <device/pnp.h> #include "w83627ehg.h" -void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0xaa, port); } + +void w83627ehg_serial_clk(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + /* We have 24MHz input. */ + u8 reg = pnp_read_config(dev, 0x24); + pnp_write_config(dev, 0x24, (reg & 0xbf)); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 221de7b..b514488 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,9 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +#include <arch/io.h> +#include <device/pnp.h> + +void w83627ehg_serial_clk(device_t); #endif /* SUPERIO_WINBOND_W83627EHG_H */

1 0

New patch to review for coreboot: ba9b698 mainboard/ibase/mb899: Trivial, Non-local header treated as local
by Edward O'Callaghan 01 Jun '14

01 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5897 -gerrit commit ba9b6986ed56330b1c09506a35d27324353f873c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 1 16:31:48 2014 +1000 mainboard/ibase/mb899: Trivial, Non-local header treated as local Change-Id: I5cb496d0d582d3dc5c0c0635f632561f8a3dd853 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/ibase/mb899/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 0957795..418b6e4 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -28,7 +28,7 @@ #include <lib.h> #include <cbmem.h> #include <superio/winbond/common/winbond.h> -#include "superio/winbond/w83627ehg/w83627ehg.h" +#include <superio/winbond/w83627ehg/w83627ehg.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h>

1 0

New patch to review for coreboot: 0efacc4 northbridge/intel/i945/i945.h: Trivial, fixup header guards
by Edward O'Callaghan 01 Jun '14

01 Jun '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5896 -gerrit commit 0efacc42d4732fd540fccdaeca3ef4f74667d2e9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jun 1 16:09:21 2014 +1000 northbridge/intel/i945/i945.h: Trivial, fixup header guards Change-Id: Iff15ab436e5b7b4e189c7341e7c508faaef07a3a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/i945/i945.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index d4d35a2..728fe0a 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __NORTHBRIDGE_INTEL_I945_I945_H__ -#define __NORTHBRIDGE_INTEL_I945_I945_H__ 1 +#ifndef NORTHBRIDGE_INTEL_I945_H +#define NORTHBRIDGE_INTEL_I945_H /* Northbridge BARs */ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ @@ -58,9 +58,10 @@ #define DEVEN_D1F0 (1 << 1) #define DEVEN_D2F0 (1 << 3) #define DEVEN_D2F1 (1 << 4) + #ifndef BOARD_DEVEN #define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) -#endif +#endif /* BOARD_DEVEN */ #define BSM 0x5c @@ -360,5 +361,6 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); -#endif -#endif +#endif /* __ACPI__ */ + +#endif /* NORTHBRIDGE_INTEL_I945_H */

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2014