coreboot-gerrit February 2014

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Patch set updated for coreboot: 4468adb Remove CACHE_ROM.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146 -gerrit commit 4468adb4b5e27196f006e7f5713947f7a2f0d1a4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the improvements down in this patch stack, speed up by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs on all systems I tried it on, hence screwing up I/O access and cahce coherency in worst cases. Remove this as a buggy feature until we figure out how todo it properly if necessarry. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/haswell_init.c | 3 - src/cpu/x86/Kconfig | 7 --- src/cpu/x86/mtrr/mtrr.c | 76 ------------------------- src/include/cpu/x86/mtrr.h | 20 +------ src/lib/coreboot_table.c | 20 ------- src/mainboard/google/Kconfig | 5 -- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 4 -- src/northbridge/intel/nehalem/northbridge.c | 2 - src/northbridge/intel/sandybridge/northbridge.c | 2 - src/soc/intel/baytrail/Kconfig | 1 - 15 files changed, 2 insertions(+), 143 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index f8d295e..6e6428b 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -782,9 +782,6 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); - - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 21282c3..4425ed3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -76,13 +76,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool "Allow for caching system ROM." - default n - help - When selected a variable range MTRR is allocated for coreboot and - the bootloader enables caching of the system ROM for faster access. - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dbedf0f..54fdfd8 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -185,16 +185,6 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); -#if CONFIG_CACHE_ROM - /* Add a write-protect region covering the ROM size - * when CONFIG_CACHE_ROM is enabled. The ROM is assumed - * to be located at 4GiB - rom size. */ - resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); -#endif - /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -366,61 +356,6 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } -/* Keep track of the MTRR that covers the ROM for caching purposes. */ -#if CONFIG_CACHE_ROM -static long rom_cache_mtrr = -1; - -long x86_mtrr_rom_cache_var_index(void) -{ - return rom_cache_mtrr; -} - -void x86_mtrr_enable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - msr_val.lo |= MTRR_TYPE_WRPROT; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -void x86_mtrr_disable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -static void disable_cache_rom(void *unused) -{ - x86_mtrr_disable_rom_caching(); -} - -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), -}; -#endif - struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -468,17 +403,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; -#if CONFIG_CACHE_ROM - /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing - * one to turn on caching for faster ROM access. However, it is - * left to the MTRR callers to enable it. */ - if (mtrr_type == MTRR_TYPE_WRPROT) { - mtrr_type = MTRR_TYPE_UNCACHEABLE; - if (rom_cache_mtrr < 0) - rom_cache_mtrr = var_state->mtrr_index; - } -#endif - printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9414687..d6cf039 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,10 +52,6 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. - * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling - * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsibility of the caller to enable it by calling - * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -71,24 +67,12 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); -/* ROM caching can be used after variable MTRRs are set up. Beware that - * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on - * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that +/* ROM caching can be used after variable MTRRs are set up. + * Be sure to check the console log when adding WRCOMB resources. Beware that * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the * rom caching will be disabled if all threads run the MTRR code. Therefore, * one needs to call x86_mtrr_enable_rom_caching() after all threads of the * same core have run the MTRR code. */ -#if CONFIG_CACHE_ROM -void x86_mtrr_enable_rom_caching(void); -void x86_mtrr_disable_rom_caching(void); -/* Return the variable range MTRR index of the ROM cache. */ -long x86_mtrr_rom_cache_var_index(void); -#else -static inline void x86_mtrr_enable_rom_caching(void) {} -static inline void x86_mtrr_disable_rom_caching(void) {} -static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } -#endif /* CONFIG_CACHE_ROM */ #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14c..904185a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -235,24 +235,6 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ -static void lb_x86_rom_cache(struct lb_header *header) -{ -#if CONFIG_ARCH_X86 - long mtrr_index; - struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; - - mtrr_index = x86_mtrr_rom_cache_var_index(); - - if (mtrr_index < 0) - return; - - lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); - lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; - lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); - lb_x86_rom_mtrr->index = mtrr_index; -#endif -} - static void add_cbmem_pointers(struct lb_header *header) { /* @@ -529,8 +511,6 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - /* Communicate x86 variable MTRR ROM cache information. */ - lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index b86b0ad..85c8592 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -18,11 +18,6 @@ ## if VENDOR_GOOGLE -# Auto select common options -config VENDOR_SPECIFIC_OPTIONS - def_bool y - select CACHE_ROM - choice prompt "Mainboard model" diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 1d2b259..3004443 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index b372c47..893c4e5 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 7a406e1..59fb8c0 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 065830a..3ffacde 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 99ed53c..7ff66ed 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5..ce366ef 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index f9386de..d94bc09 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -340,8 +340,6 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7db9301..5440140 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 613593e..d3311ef 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS - select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_MICROCODE_IN_CBFS

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Patch set updated for coreboot: d91bffc Remove CACHE_ROM.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146 -gerrit commit d91bffc8bf50a90b7ac7da4423e270bdaed1fec1 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the improvements down in this patch stack, speed up by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs on all systems I tried it on, hence screwing up I/O access and cahce coherency in worst cases. Remove this as a buggy feature until we figure out how todo it properly if necessarry. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/x86/Kconfig | 7 --- src/cpu/x86/mtrr/mtrr.c | 76 ------------------------- src/include/cpu/x86/mtrr.h | 20 +------ src/lib/coreboot_table.c | 20 ------- src/mainboard/google/Kconfig | 5 -- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 4 -- src/northbridge/intel/sandybridge/northbridge.c | 2 - src/soc/intel/baytrail/Kconfig | 1 - 13 files changed, 2 insertions(+), 138 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 21282c3..4425ed3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -76,13 +76,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool "Allow for caching system ROM." - default n - help - When selected a variable range MTRR is allocated for coreboot and - the bootloader enables caching of the system ROM for faster access. - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dbedf0f..54fdfd8 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -185,16 +185,6 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); -#if CONFIG_CACHE_ROM - /* Add a write-protect region covering the ROM size - * when CONFIG_CACHE_ROM is enabled. The ROM is assumed - * to be located at 4GiB - rom size. */ - resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); -#endif - /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -366,61 +356,6 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } -/* Keep track of the MTRR that covers the ROM for caching purposes. */ -#if CONFIG_CACHE_ROM -static long rom_cache_mtrr = -1; - -long x86_mtrr_rom_cache_var_index(void) -{ - return rom_cache_mtrr; -} - -void x86_mtrr_enable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - msr_val.lo |= MTRR_TYPE_WRPROT; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -void x86_mtrr_disable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -static void disable_cache_rom(void *unused) -{ - x86_mtrr_disable_rom_caching(); -} - -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), -}; -#endif - struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -468,17 +403,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; -#if CONFIG_CACHE_ROM - /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing - * one to turn on caching for faster ROM access. However, it is - * left to the MTRR callers to enable it. */ - if (mtrr_type == MTRR_TYPE_WRPROT) { - mtrr_type = MTRR_TYPE_UNCACHEABLE; - if (rom_cache_mtrr < 0) - rom_cache_mtrr = var_state->mtrr_index; - } -#endif - printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9414687..d6cf039 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,10 +52,6 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. - * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling - * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsibility of the caller to enable it by calling - * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -71,24 +67,12 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); -/* ROM caching can be used after variable MTRRs are set up. Beware that - * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on - * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that +/* ROM caching can be used after variable MTRRs are set up. + * Be sure to check the console log when adding WRCOMB resources. Beware that * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the * rom caching will be disabled if all threads run the MTRR code. Therefore, * one needs to call x86_mtrr_enable_rom_caching() after all threads of the * same core have run the MTRR code. */ -#if CONFIG_CACHE_ROM -void x86_mtrr_enable_rom_caching(void); -void x86_mtrr_disable_rom_caching(void); -/* Return the variable range MTRR index of the ROM cache. */ -long x86_mtrr_rom_cache_var_index(void); -#else -static inline void x86_mtrr_enable_rom_caching(void) {} -static inline void x86_mtrr_disable_rom_caching(void) {} -static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } -#endif /* CONFIG_CACHE_ROM */ #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14c..904185a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -235,24 +235,6 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ -static void lb_x86_rom_cache(struct lb_header *header) -{ -#if CONFIG_ARCH_X86 - long mtrr_index; - struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; - - mtrr_index = x86_mtrr_rom_cache_var_index(); - - if (mtrr_index < 0) - return; - - lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); - lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; - lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); - lb_x86_rom_mtrr->index = mtrr_index; -#endif -} - static void add_cbmem_pointers(struct lb_header *header) { /* @@ -529,8 +511,6 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - /* Communicate x86 variable MTRR ROM cache information. */ - lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index b86b0ad..85c8592 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -18,11 +18,6 @@ ## if VENDOR_GOOGLE -# Auto select common options -config VENDOR_SPECIFIC_OPTIONS - def_bool y - select CACHE_ROM - choice prompt "Mainboard model" diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 1d2b259..3004443 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index b372c47..893c4e5 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 7a406e1..59fb8c0 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 065830a..3ffacde 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 99ed53c..7ff66ed 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5..ce366ef 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7db9301..5440140 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 613593e..d3311ef 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS - select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_MICROCODE_IN_CBFS

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New patch to review for coreboot: 85edbea Remove CACHE_ROM.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146 -gerrit commit 85edbea369ed55b3a071862d5d4182219376be22 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the improvements down in this patch stack, speed up by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs on all systems I tried it on, hence screwing up I/O access and cahce coherency in worst cases. Remove this as a buggy feature until we figure out how todo it properly if necessarry. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/x86/Kconfig | 7 --- src/cpu/x86/mtrr/mtrr.c | 76 --------------------------- src/include/cpu/x86/mtrr.h | 20 +------ src/mainboard/google/Kconfig | 5 -- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 4 -- src/soc/intel/baytrail/Kconfig | 1 - 11 files changed, 2 insertions(+), 116 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 21282c3..4425ed3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -76,13 +76,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool "Allow for caching system ROM." - default n - help - When selected a variable range MTRR is allocated for coreboot and - the bootloader enables caching of the system ROM for faster access. - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dbedf0f..54fdfd8 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -185,16 +185,6 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); -#if CONFIG_CACHE_ROM - /* Add a write-protect region covering the ROM size - * when CONFIG_CACHE_ROM is enabled. The ROM is assumed - * to be located at 4GiB - rom size. */ - resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); -#endif - /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -366,61 +356,6 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } -/* Keep track of the MTRR that covers the ROM for caching purposes. */ -#if CONFIG_CACHE_ROM -static long rom_cache_mtrr = -1; - -long x86_mtrr_rom_cache_var_index(void) -{ - return rom_cache_mtrr; -} - -void x86_mtrr_enable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - msr_val.lo |= MTRR_TYPE_WRPROT; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -void x86_mtrr_disable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -static void disable_cache_rom(void *unused) -{ - x86_mtrr_disable_rom_caching(); -} - -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), -}; -#endif - struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -468,17 +403,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; -#if CONFIG_CACHE_ROM - /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing - * one to turn on caching for faster ROM access. However, it is - * left to the MTRR callers to enable it. */ - if (mtrr_type == MTRR_TYPE_WRPROT) { - mtrr_type = MTRR_TYPE_UNCACHEABLE; - if (rom_cache_mtrr < 0) - rom_cache_mtrr = var_state->mtrr_index; - } -#endif - printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9414687..d6cf039 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,10 +52,6 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. - * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling - * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsibility of the caller to enable it by calling - * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -71,24 +67,12 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); -/* ROM caching can be used after variable MTRRs are set up. Beware that - * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on - * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that +/* ROM caching can be used after variable MTRRs are set up. + * Be sure to check the console log when adding WRCOMB resources. Beware that * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the * rom caching will be disabled if all threads run the MTRR code. Therefore, * one needs to call x86_mtrr_enable_rom_caching() after all threads of the * same core have run the MTRR code. */ -#if CONFIG_CACHE_ROM -void x86_mtrr_enable_rom_caching(void); -void x86_mtrr_disable_rom_caching(void); -/* Return the variable range MTRR index of the ROM cache. */ -long x86_mtrr_rom_cache_var_index(void); -#else -static inline void x86_mtrr_enable_rom_caching(void) {} -static inline void x86_mtrr_disable_rom_caching(void) {} -static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } -#endif /* CONFIG_CACHE_ROM */ #endif diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index b86b0ad..85c8592 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -18,11 +18,6 @@ ## if VENDOR_GOOGLE -# Auto select common options -config VENDOR_SPECIFIC_OPTIONS - def_bool y - select CACHE_ROM - choice prompt "Mainboard model" diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 1d2b259..3004443 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index b372c47..893c4e5 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 7a406e1..59fb8c0 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 065830a..3ffacde 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 99ed53c..7ff66ed 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5..ce366ef 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 613593e..d3311ef 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS - select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_MICROCODE_IN_CBFS

1 0

New patch to review for coreboot: 9127a78 lenovo/x201: Enable flash prefetching.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5145 -gerrit commit 9127a780c425f0cf42ef3ebc7ce575e5d3a666b7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:10:03 2014 +0100 lenovo/x201: Enable flash prefetching. Speeds up coreboot and especially payload load. Before: 90:load payload 4,530,979 (17,728) 99:selfboot jump 5,103,408 (572,429) After: 90:load payload 4,390,051 (14,849) 99:selfboot jump 4,505,966 (115,915) Change-Id: I45c3042594cda16ab3adde6472e00ec1b2d2a688 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index e3e0a62..f0874d3 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -63,7 +63,7 @@ static void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); - pci_write_config32(PCH_LPC_DEV, 0xdc, 0x0); + pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);

1 0

Patch set updated for coreboot: 51c6758 console: Remove DEBUG_SMI temporarily
by Kyösti Mälkki 05 Feb '14

05 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5142 -gerrit commit 51c67586ae42d3c29227d38b17d5a3b32c7329b8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jan 26 11:32:51 2014 +0200 console: Remove DEBUG_SMI temporarily Existing code compiled serial communication in SMM even when DEBUG_SMI was not selected, if serial console was enabled. Followup will re-enable DEBUG_SMI output with tighter security policy and possibly wider support for consoles. Change-Id: Ic5e25cd7453cb2243f7ac592b093fba752a299f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Makefile.inc | 3 +- src/cpu/x86/smm/Makefile.inc | 2 -- src/cpu/x86/smm/smihandler.c | 3 +- src/cpu/x86/smm/smiutil.c | 67 ------------------------------------ src/cpu/x86/smm/smm_module_handler.c | 4 +++ src/include/console/console.h | 1 + src/mainboard/lenovo/x60/dock.c | 3 ++ 7 files changed, 11 insertions(+), 72 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 62be1d2..54d59cd 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -5,8 +5,7 @@ ramstage-y += vsprintf.c ramstage-y += post.c ramstage-y += die.c -smm-y += printk.c -smm-y += vtxprintf.c +smm-$(CONFIG_DEBUG_SMI) += vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index b595a36..06ba2a3 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -21,7 +21,6 @@ ifeq ($(CONFIG_SMM_MODULES),y) smmstub-y += smm_stub.S smmstub-y += smm_module_header.c -smm-y += smiutil.c smm-y += smm_module_header.c smm-y += smm_module_handler.c @@ -79,7 +78,6 @@ SMM_LDSCRIPT := smm.ld endif smm-y += smihandler.c -smm-y += smiutil.c $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME) $(CC) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index fc30909..e8f79fe 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -148,8 +148,9 @@ void smi_handler(u32 smm_revision) node=nodeid(); +#if CONFIG_DEBUG_SMI console_init(); - +#endif printk(BIOS_SPEW, "\nSMI# #%d\n", node); switch (smm_revision) { diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c deleted file mode 100644 index 13ee12e..0000000 --- a/src/cpu/x86/smm/smiutil.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <console/console.h> -#include <console/vtxprintf.h> - -#if CONFIG_CONSOLE_SERIAL8250MEM -static u32 serial8250mem_base_address = 0; -#endif - -void console_tx_flush(void) -{ -} - -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - console_tx_byte('\r'); - -#if CONFIG_CONSOLE_SERIAL8250MEM - if (serial8250mem_base_address) - uart8250_mem_tx_byte(serial8250mem_base_address, byte); -#endif -#if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -} - -void console_init(void) -{ -#if CONFIG_DEBUG_SMI - console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -#if CONFIG_CONSOLE_SERIAL8250 - uart_init(); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM - serial8250mem_base_address = uart_mem_init(); -#endif -#else - console_loglevel = 1; -#endif -} - diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 444e335..cbfdf79 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -121,7 +121,9 @@ void smm_handler_start(void *arg, int cpu, const struct smm_runtime *runtime) smm_runtime = runtime; if (cpu >= CONFIG_MAX_CPUS) { +#if CONFIG_DEBUG_SMI console_init(); +#endif printk(BIOS_CRIT, "Invalid CPU number assigned in SMM stub: %d\n", cpu); return; @@ -141,7 +143,9 @@ void smm_handler_start(void *arg, int cpu, const struct smm_runtime *runtime) smi_backup_pci_address(); +#if CONFIG_DEBUG_SMI console_init(); +#endif printk(BIOS_SPEW, "\nSMI# #%d\n", cpu); diff --git a/src/include/console/console.h b/src/include/console/console.h index c5f5297..78307a3 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -89,6 +89,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, void hexdump32(char LEVEL, const void *d, int len); #if defined(__BOOT_BLOCK__) && !CONFIG_BOOTBLOCK_CONSOLE || \ + defined(__SMM__) && !CONFIG_DEBUG_SMI || \ (defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__)) && !CONFIG_EARLY_CONSOLE static inline void printk(int LEVEL, const char *fmt, ...); diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index 1b15a6c..a880263 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -237,7 +237,10 @@ int dock_connect(void) dock_write_register(0x07, 0x03); dock_write_register(0x30, 0x01); +#if !defined(__SMM__) || CONFIG_DEBUG_SMI + /* FIXME: Do not touch consoles outside the dock. */ console_init(); +#endif return 0; }

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Patch set updated for coreboot: e3f1177 Kill ALT_CBFS_LOAD_PAYLOAD
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5132 -gerrit commit e3f11777d7833941072154ee1e5e303b8848831c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:27:22 2014 +0100 Kill ALT_CBFS_LOAD_PAYLOAD Not used anymore. Change-Id: Icf3a4a7f932776981048b805478582ad2b784182 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 9 --------- src/lib/cbfs.c | 2 -- 2 files changed, 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 31a41ab..e6b237a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -47,15 +47,6 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. -config ALT_CBFS_LOAD_PAYLOAD - bool "Use alternative cbfs_load_payload() implementation." - default n - help - Either board or southbridge provide an alternative cbfs_load_payload() - implementation. This may be used, for example, if accessing the ROM - through memory-mapped I/O is slow and a faster alternative can be - provided. - choice prompt "Compiler to use" default COMPILER_GCC diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..30e7949 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -213,7 +213,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) } #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ -#if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) { struct cbfs_payload *payload; @@ -226,7 +225,6 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) media, name, CBFS_TYPE_PAYLOAD, NULL); return payload; } -#endif /* Simple buffer */

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Patch set updated for coreboot: 1765253 lynxpoint: Kill alternative cbfs_load_payload.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5131 -gerrit commit 1765253b02e770c87e67747e0d64f6798c3268d0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:23:56 2014 +0100 lynxpoint: Kill alternative cbfs_load_payload. The only thing which this file does differently to increase the speed is usage of cache but since MTRR is covering ROM already anyway, this makes no difference and only increases maintenance efforts and cache usage. Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/lynxpoint/Kconfig | 1 - src/southbridge/intel/lynxpoint/Makefile.inc | 1 - src/southbridge/intel/lynxpoint/spi_loading.c | 90 --------------------------- 3 files changed, 92 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5ff00db..970a11d 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -32,7 +32,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH - select ALT_CBFS_LOAD_PAYLOAD config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 7be2d03..b691e6f 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -41,7 +41,6 @@ ramstage-y += me_status.c ramstage-y += reset.c ramstage-y += watchdog.c ramstage-y += acpi.c -ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += spi.c diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c deleted file mode 100644 index 57e3af8..0000000 --- a/src/southbridge/intel/lynxpoint/spi_loading.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 ChromeOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#if CONFIG_VBOOT_VERIFY_FIRMWARE -#include <vendorcode/google/chromeos/chromeos.h> -#else -static inline void *vboot_get_payload(size_t *len) { return NULL; } -#endif - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -} - -void *cbfs_load_payload(struct cbfs_media *media, const char *name) -{ - size_t file_len; - void *file_start; - - file_start = vboot_get_payload(&file_len); - - if (file_start != NULL) - return spi_mirror(file_start, file_len); - - file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len); - - if (file_start == NULL) - return NULL; - - return spi_mirror(file_start, file_len); -}

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Patch set updated for coreboot: 972091a load_payload: Use 32-bit accesses to speed up decompression.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5144 -gerrit commit 972091a6a62387669739608d751c74306c26865e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 17:00:40 2014 +0100 load_payload: Use 32-bit accesses to speed up decompression. Flash prefers 32-bit sequential access. On some platforms ROM is not cached due to i.a. MTRR shortage. Moreover ROM caching is not currently enabled by default. With this patch payload decompression is sped up by theoretical factor of 4. Test on X201, with caching disabled: Before: 90:load payload 4,470,841 (24,505) 99:selfboot jump 6,073,812 (1,602,971) After: 90:load payload 4,530,979 (17,728) 99:selfboot jump 5,103,408 (572,429) Change-Id: Id17e61316dbbf73f4a837bf173f88bf26c01c62b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/lib/cbfs_core.c | 6 ++++++ src/lib/lzmadecode.c | 11 ++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 839b994..50c037e 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -202,6 +202,12 @@ int cbfs_decompress(int algo, void *src, void *dst, int len) { switch (algo) { case CBFS_COMPRESS_NONE: + /* Reads need to be aligned at 4 bytes to avoid + poor flash performance. */ + while (len && ((u32)src & 3)) { + *(u8*)dst++ = *(u8*)src++; + len--; + } memmove(dst, src, len); return len; #ifdef CBFS_CORE_WITH_LZMA diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index 1cf647d..fb57f4f 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -28,7 +28,10 @@ #define kBitModelTotal (1 << kNumBitModelTotalBits) #define kNumMoveBits 5 -#define RC_READ_BYTE (*Buffer++) +/* Use 32-bit reads whenever possible to avoid bad flash performance. */ +#define RC_READ_BYTE (look_ahead_ptr < 4 ? look_ahead.raw[look_ahead_ptr++] \ + : ((((UInt32) Buffer & 3) || ((SizeT) (BufferLim - Buffer) < 4)) ? (*Buffer++) \ + : ((look_ahead.dw = *(UInt32 *)Buffer), (Buffer += 4), (look_ahead_ptr = 1), look_ahead.raw[0]))) #define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} @@ -149,6 +152,12 @@ int LzmaDecode(CLzmaDecoderState *vs, int len = 0; const Byte *Buffer; const Byte *BufferLim; + int look_ahead_ptr = 4; + union + { + Byte raw[4]; + UInt32 dw; + } look_ahead; UInt32 Range; UInt32 Code;

1 0

Patch set updated for coreboot: 7ca7503 load_payload: Use 32-bit accesses to speed up decompression.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5144 -gerrit commit 7ca750324cfeedaafc72e6bc21dc9aa4d0524982 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 17:00:40 2014 +0100 load_payload: Use 32-bit accesses to speed up decompression. Flash prefers 32-bit sequential access. On some platforms ROM is not cached due to i.a. MTRR shortage. Moreover ROM caching is not currently enabled by default. With this patch payload decompress is sped up by theoretical factor of 4. Test on X201, with caching disabled: Before: 90:load payload 4,470,841 (24,505) 99:selfboot jump 6,073,812 (1,602,971) After: 90:load payload 4,530,979 (17,728) 99:selfboot jump 5,103,408 (572,429) Change-Id: Id17e61316dbbf73f4a837bf173f88bf26c01c62b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/lib/cbfs_core.c | 6 ++++++ src/lib/lzmadecode.c | 11 ++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 839b994..50c037e 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -202,6 +202,12 @@ int cbfs_decompress(int algo, void *src, void *dst, int len) { switch (algo) { case CBFS_COMPRESS_NONE: + /* Reads need to be aligned at 4 bytes to avoid + poor flash performance. */ + while (len && ((u32)src & 3)) { + *(u8*)dst++ = *(u8*)src++; + len--; + } memmove(dst, src, len); return len; #ifdef CBFS_CORE_WITH_LZMA diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index 1cf647d..b27e811 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -28,7 +28,10 @@ #define kBitModelTotal (1 << kNumBitModelTotalBits) #define kNumMoveBits 5 -#define RC_READ_BYTE (*Buffer++) +/* Use 32-bit reads whenever possible to avoid bad flash performance. */ +#define RC_READ_BYTE (look_ahead_ptr < 4 ? look_ahead.raw[look_ahead_ptr++] \ + : ((((UInt32) Buffer & 3) || ((unsigned long long) (BufferLim - Buffer) < 4)) ? (*Buffer++) \ + : ((look_ahead.dw = *(UInt32 *)Buffer), (Buffer += 4), (look_ahead_ptr = 1), look_ahead.raw[0]))) #define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} @@ -149,6 +152,12 @@ int LzmaDecode(CLzmaDecoderState *vs, int len = 0; const Byte *Buffer; const Byte *BufferLim; + int look_ahead_ptr = 4; + union + { + Byte raw[4]; + UInt32 dw; + } look_ahead; UInt32 Range; UInt32 Code;

1 0

Patch set updated for coreboot: 9554270 Kill ALT_CBFS_LOAD_PAYLOAD
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5132 -gerrit commit 95542700cb9446234d9405a3c159552ec2381d40 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:27:22 2014 +0100 Kill ALT_CBFS_LOAD_PAYLOAD Not used anymore. Change-Id: Icf3a4a7f932776981048b805478582ad2b784182 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 9 --------- src/lib/cbfs.c | 2 -- 2 files changed, 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 31a41ab..e6b237a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -47,15 +47,6 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. -config ALT_CBFS_LOAD_PAYLOAD - bool "Use alternative cbfs_load_payload() implementation." - default n - help - Either board or southbridge provide an alternative cbfs_load_payload() - implementation. This may be used, for example, if accessing the ROM - through memory-mapped I/O is slow and a faster alternative can be - provided. - choice prompt "Compiler to use" default COMPILER_GCC diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..30e7949 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -213,7 +213,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) } #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ -#if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) { struct cbfs_payload *payload; @@ -226,7 +225,6 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) media, name, CBFS_TYPE_PAYLOAD, NULL); return payload; } -#endif /* Simple buffer */

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coreboot-gerrit February 2014