coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 2c31b70 lynxpoint: Kill alternative cbfs_load_payload.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5131 -gerrit commit 2c31b70fec8f12448e5c6618c51c8f977e514e2f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:23:56 2014 +0100 lynxpoint: Kill alternative cbfs_load_payload. The only thing which this file does differently to increase the speed is usage of cache but since MTRR is covering ROM already anyway, this makes no difference and only increases maintenance efforts and cache usage. Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/lynxpoint/Kconfig | 1 - src/southbridge/intel/lynxpoint/Makefile.inc | 1 - src/southbridge/intel/lynxpoint/spi_loading.c | 90 --------------------------- 3 files changed, 92 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5ff00db..970a11d 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -32,7 +32,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH - select ALT_CBFS_LOAD_PAYLOAD config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 7be2d03..b691e6f 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -41,7 +41,6 @@ ramstage-y += me_status.c ramstage-y += reset.c ramstage-y += watchdog.c ramstage-y += acpi.c -ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += spi.c diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c deleted file mode 100644 index 57e3af8..0000000 --- a/src/southbridge/intel/lynxpoint/spi_loading.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 ChromeOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#if CONFIG_VBOOT_VERIFY_FIRMWARE -#include <vendorcode/google/chromeos/chromeos.h> -#else -static inline void *vboot_get_payload(size_t *len) { return NULL; } -#endif - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -} - -void *cbfs_load_payload(struct cbfs_media *media, const char *name) -{ - size_t file_len; - void *file_start; - - file_start = vboot_get_payload(&file_len); - - if (file_start != NULL) - return spi_mirror(file_start, file_len); - - file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len); - - if (file_start == NULL) - return NULL; - - return spi_mirror(file_start, file_len); -}

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Patch set updated for coreboot: 71d4d0c load_payload: Use 32-bit accesses to speed up decompression.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5144 -gerrit commit 71d4d0c78051334134af4af7d937df007017160d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 17:00:40 2014 +0100 load_payload: Use 32-bit accesses to speed up decompression. Flash prefers 32-bit sequential access. On some platforms ROM is not cached due to i.a. MTRR shortage. Moreover ROM caching is not currently enabled by default. With this patch payload decompress is sped up by factor of 4. Test on X201, with caching disabled: Before: 90:load payload 4,470,841 (24,505) 99:selfboot jump 6,073,812 (1,602,971) After: 90:load payload 4,530,979 (17,728) 99:selfboot jump 5,103,408 (572,429) Change-Id: Id17e61316dbbf73f4a837bf173f88bf26c01c62b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/lib/cbfs_core.c | 6 ++++++ src/lib/lzmadecode.c | 11 ++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 839b994..50c037e 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -202,6 +202,12 @@ int cbfs_decompress(int algo, void *src, void *dst, int len) { switch (algo) { case CBFS_COMPRESS_NONE: + /* Reads need to be aligned at 4 bytes to avoid + poor flash performance. */ + while (len && ((u32)src & 3)) { + *(u8*)dst++ = *(u8*)src++; + len--; + } memmove(dst, src, len); return len; #ifdef CBFS_CORE_WITH_LZMA diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index 1cf647d..b27e811 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -28,7 +28,10 @@ #define kBitModelTotal (1 << kNumBitModelTotalBits) #define kNumMoveBits 5 -#define RC_READ_BYTE (*Buffer++) +/* Use 32-bit reads whenever possible to avoid bad flash performance. */ +#define RC_READ_BYTE (look_ahead_ptr < 4 ? look_ahead.raw[look_ahead_ptr++] \ + : ((((UInt32) Buffer & 3) || ((unsigned long long) (BufferLim - Buffer) < 4)) ? (*Buffer++) \ + : ((look_ahead.dw = *(UInt32 *)Buffer), (Buffer += 4), (look_ahead_ptr = 1), look_ahead.raw[0]))) #define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} @@ -149,6 +152,12 @@ int LzmaDecode(CLzmaDecoderState *vs, int len = 0; const Byte *Buffer; const Byte *BufferLim; + int look_ahead_ptr = 4; + union + { + Byte raw[4]; + UInt32 dw; + } look_ahead; UInt32 Range; UInt32 Code;

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New patch to review for coreboot: 647507e load_payload: Use 32-bit accesses to speed up decompression.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5144 -gerrit commit 647507ee168359b3bfad0370e5536f355ce25fae Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 17:00:40 2014 +0100 load_payload: Use 32-bit accesses to speed up decompression. Flash prefers 32-bit sequential access. On some platforms ROM is not cached due to i.a. MTRR shortage. Moreover ROM caching is not currently enabled by default. With this patch payload decompress is sped up by factor of 4. Change-Id: Id17e61316dbbf73f4a837bf173f88bf26c01c62b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/lib/cbfs_core.c | 6 ++++++ src/lib/lzmadecode.c | 11 ++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 839b994..50c037e 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -202,6 +202,12 @@ int cbfs_decompress(int algo, void *src, void *dst, int len) { switch (algo) { case CBFS_COMPRESS_NONE: + /* Reads need to be aligned at 4 bytes to avoid + poor flash performance. */ + while (len && ((u32)src & 3)) { + *(u8*)dst++ = *(u8*)src++; + len--; + } memmove(dst, src, len); return len; #ifdef CBFS_CORE_WITH_LZMA diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index 1cf647d..b27e811 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -28,7 +28,10 @@ #define kBitModelTotal (1 << kNumBitModelTotalBits) #define kNumMoveBits 5 -#define RC_READ_BYTE (*Buffer++) +/* Use 32-bit reads whenever possible to avoid bad flash performance. */ +#define RC_READ_BYTE (look_ahead_ptr < 4 ? look_ahead.raw[look_ahead_ptr++] \ + : ((((UInt32) Buffer & 3) || ((unsigned long long) (BufferLim - Buffer) < 4)) ? (*Buffer++) \ + : ((look_ahead.dw = *(UInt32 *)Buffer), (Buffer += 4), (look_ahead_ptr = 1), look_ahead.raw[0]))) #define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} @@ -149,6 +152,12 @@ int LzmaDecode(CLzmaDecoderState *vs, int len = 0; const Byte *Buffer; const Byte *BufferLim; + int look_ahead_ptr = 4; + union + { + Byte raw[4]; + UInt32 dw; + } look_ahead; UInt32 Range; UInt32 Code;

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Patch set updated for coreboot: e4ef370 Kill ALT_CBFS_LOAD_PAYLOAD
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5132 -gerrit commit e4ef370192c65574b72144fdc0715e2c4ecd7345 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:27:22 2014 +0100 Kill ALT_CBFS_LOAD_PAYLOAD Not used anymore. Change-Id: Icf3a4a7f932776981048b805478582ad2b784182 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 9 --------- src/lib/cbfs.c | 2 -- 2 files changed, 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 31a41ab..e6b237a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -47,15 +47,6 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. -config ALT_CBFS_LOAD_PAYLOAD - bool "Use alternative cbfs_load_payload() implementation." - default n - help - Either board or southbridge provide an alternative cbfs_load_payload() - implementation. This may be used, for example, if accessing the ROM - through memory-mapped I/O is slow and a faster alternative can be - provided. - choice prompt "Compiler to use" default COMPILER_GCC diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..30e7949 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -213,7 +213,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) } #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ -#if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) { struct cbfs_payload *payload; @@ -226,7 +225,6 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) media, name, CBFS_TYPE_PAYLOAD, NULL); return payload; } -#endif /* Simple buffer */

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Patch set updated for coreboot: 74322ee lynxpoint: Kill alternative cbfs_load_payload.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5131 -gerrit commit 74322ee7cf4b02ac5611de74d434816c880aea35 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:23:56 2014 +0100 lynxpoint: Kill alternative cbfs_load_payload. The only thing which this file does differently to increase the speed is usage of cache but since MTRR is covering ROM already anyway, this makes no difference and only increases maintenance efforts and cache usage. Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/lynxpoint/Kconfig | 1 - src/southbridge/intel/lynxpoint/Makefile.inc | 1 - src/southbridge/intel/lynxpoint/spi_loading.c | 90 --------------------------- 3 files changed, 92 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5ff00db..970a11d 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -32,7 +32,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH - select ALT_CBFS_LOAD_PAYLOAD config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 7be2d03..b691e6f 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -41,7 +41,6 @@ ramstage-y += me_status.c ramstage-y += reset.c ramstage-y += watchdog.c ramstage-y += acpi.c -ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += spi.c diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c deleted file mode 100644 index 57e3af8..0000000 --- a/src/southbridge/intel/lynxpoint/spi_loading.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 ChromeOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#if CONFIG_VBOOT_VERIFY_FIRMWARE -#include <vendorcode/google/chromeos/chromeos.h> -#else -static inline void *vboot_get_payload(size_t *len) { return NULL; } -#endif - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -} - -void *cbfs_load_payload(struct cbfs_media *media, const char *name) -{ - size_t file_len; - void *file_start; - - file_start = vboot_get_payload(&file_len); - - if (file_start != NULL) - return spi_mirror(file_start, file_len); - - file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len); - - if (file_start == NULL) - return NULL; - - return spi_mirror(file_start, file_len); -}

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Patch set updated for coreboot: 7e81347 rambi: add per-sku SPD support
by Aaron Durbin 05 Feb '14

05 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4872 -gerrit commit 7e81347408ea2dcc4af366a363abf46037fc6b9e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 8 15:33:39 2013 -0500 rambi: add per-sku SPD support There are currently 4 SKUs: 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz Add each of the 4 spds to the build, and use the proper parameters to MRC to use the in-memory SPD information. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built. Noted 1024 bytes of SPD content. Change-Id: Ife96650f9b0032b6bd0d1bdd63b8970e29868365 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172280 --- src/mainboard/google/rambi/Kconfig | 4 ++ src/mainboard/google/rambi/Makefile.inc | 2 + src/mainboard/google/rambi/romstage.c | 45 ++++++++++++++++++++- src/mainboard/google/rambi/spd/Makefile.inc | 46 ++++++++++++++++++++++ .../spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex | 32 +++++++++++++++ .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 +++++++++++++++ .../spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex | 32 +++++++++++++++ .../spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex | 32 +++++++++++++++ 8 files changed, 223 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 4d149c9..efaa000 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -33,4 +33,8 @@ config HAVE_ME_BIN bool default n +config SPD_CBFS_ADDRESS + hex "Location of SPD in CBFS" + default 0xfffec000 + endif # BOARD_INTEL_BAYLEYBAY diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index d3c6f0d..98e566b 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +subdirs-y += spd + romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += gpio.c diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index f845173..d15a21d 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -19,19 +19,60 @@ #include <stdint.h> #include <string.h> +#include <cbfs.h> #include <console/console.h> +#include <baytrail/gpio.h> #include <baytrail/mrc_wrapper.h> #include <baytrail/romstage.h> +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + */ +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +static void *get_spd_pointer(char *spd_file_content, int total_spds) +{ + int ram_id = 0; + + ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); + ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); + ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); + + if (ram_id >= total_spds) + return NULL; + + return &spd_file_content[SPD_SIZE * ram_id]; +} + void mainboard_romstage_entry(struct romstage_params *rp) { + struct cbfs_file *spd_file; + void *spd_content; + struct mrc_params mp = { .mainboard = { .dram_type = DRAM_DDR3L, - .dram_info_location = DRAM_INFO_SPD_SMBUS, - .spd_addrs = { 0xa0, 0xa2 }, + .dram_info_location = DRAM_INFO_SPD_MEM, }, }; + + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + + /* Both channels are always present. */ + spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), + ntohl(spd_file->len) / SPD_SIZE); + mp.mainboard.dram_data[0] = spd_content; + mp.mainboard.dram_data[1] = spd_content; + rp->mrc_params = &mp; romstage_common(rp); } diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc new file mode 100644 index 0000000..84695ab --- /dev/null +++ b/src/mainboard/google/rambi/spd/Makefile.inc @@ -0,0 +1,46 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do echo -e -n "\\x$$c"; \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab +spd.bin-position := $(CONFIG_SPD_CBFS_ADDRESS) diff --git a/src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex b/src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex new file mode 100644 index 0000000..4bd8e0e --- /dev/null +++ b/src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex @@ -0,0 +1,32 @@ +92 12 0b 03 03 11 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +00 05 3c 3c 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 22 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ad 01 +00 00 00 00 00 00 41 5f +48 4d 54 33 31 32 53 36 +44 46 52 36 41 2d 50 42 +20 20 4e 30 80 ad 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex new file mode 100644 index 0000000..ff4fd29 --- /dev/null +++ b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex @@ -0,0 +1,32 @@ +92 12 0b 03 04 19 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +20 08 3c 3c 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ad 01 +00 00 00 00 00 00 ff ab +48 4d 54 34 32 35 53 36 +41 46 52 36 41 2d 50 42 +20 20 4e 30 80 ad 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex b/src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex new file mode 100644 index 0000000..f99c92a --- /dev/null +++ b/src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex @@ -0,0 +1,32 @@ +92 11 0b 03 03 11 02 02 +03 11 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 86 +50 00 3c 3c 01 40 83 05 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 6a 15 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 36 45 +31 20 45 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex new file mode 100644 index 0000000..f3bcb56 --- /dev/null +++ b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex @@ -0,0 +1,32 @@ +92 11 0b 03 04 19 02 02 +03 11 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 86 +20 08 3c 3c 01 40 83 05 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 19 d2 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 36 45 +31 20 45 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff

1 0

Patch set updated for coreboot: a434dba rambi: Add ncore GPIO config tables
by Aaron Durbin 05 Feb '14

05 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4874 -gerrit commit a434dbaa5f21ab02eafa845abd284ffcc1f981ce Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Oct 9 15:29:46 2013 -0700 rambi: Add ncore GPIO config tables gpncore config tables were previously missing -- add them. Also, make the baytrail GPIO/PAD LUTs easier to read. TEST=Manual. Build + boot on bayleybay. BUG=chrome-os-partner:22865 Change-Id: I49a1b23c7ad4fb5f4c86618e8c78ea9a1a42f79d Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172510 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 34 +++++++++++++++- src/soc/intel/baytrail/baytrail/gpio.h | 38 ++++++++++++++---- src/soc/intel/baytrail/gpio.c | 72 ++++++++++++++++++---------------- 3 files changed, 102 insertions(+), 42 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 8393e33..3f91366 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -20,6 +20,38 @@ #include <stdlib.h> #include <baytrail/gpio.h> +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_DEFAULT, /* GPIO 0 */ + GPIO_DEFAULT, /* GPIO 1 */ + GPIO_DEFAULT, /* GPIO 2 */ + GPIO_DEFAULT, /* GPIO 3 */ + GPIO_DEFAULT, /* GPIO 4 */ + GPIO_DEFAULT, /* GPIO 5 */ + GPIO_DEFAULT, /* GPIO 6 */ + GPIO_DEFAULT, /* GPIO 7 */ + GPIO_DEFAULT, /* GPIO 8 */ + GPIO_DEFAULT, /* GPIO 9 */ + GPIO_DEFAULT, /* GPIO 10 */ + GPIO_DEFAULT, /* GPIO 11 */ + GPIO_DEFAULT, /* GPIO 12 */ + GPIO_DEFAULT, /* GPIO 13 */ + GPIO_DEFAULT, /* GPIO 14 */ + GPIO_DEFAULT, /* GPIO 15 */ + GPIO_DEFAULT, /* GPIO 16 */ + GPIO_DEFAULT, /* GPIO 17 */ + GPIO_DEFAULT, /* GPIO 18 */ + GPIO_DEFAULT, /* GPIO 19 */ + GPIO_DEFAULT, /* GPIO 20 */ + GPIO_DEFAULT, /* GPIO 21 */ + GPIO_DEFAULT, /* GPIO 22 */ + GPIO_DEFAULT, /* GPIO 23 */ + GPIO_DEFAULT, /* GPIO 24 */ + GPIO_DEFAULT, /* GPIO 25 */ + GPIO_DEFAULT, /* GPIO 26 */ + GPIO_END +}; + /* SCORE GPIOs */ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_DEFAULT, /* GPIO 0 */ @@ -177,7 +209,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { }; static struct soc_gpio_config gpio_config = { - .ncore = NULL, + .ncore = gpncore_gpio_map, .score = gpscore_gpio_map, .ssus = gpssus_gpio_map }; diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index bdd36c1..f62f5c8 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -142,25 +142,47 @@ * if not set correctly, even if the pin isn't configured as GPIO. */ #define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) +/* Configure GPIOs as legacy by default. GPNCORE doesn't support + * legacy config -- so also configure the pad regs as GPIO. We rely upon + * the fact that all GPNCORE pads are function 0 GPIO. */ #define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PU_UP | PAD_CONFIG0_DEFAULT, \ + { .pad_conf0 = PAD_PU_10K | PAD_PU_UP | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT_ENABLE, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT } + +#define GPIO_INPUT_PD_10K \ + { .pad_conf0 = PAD_PU_10K | PAD_PU_DOWN | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT_ENABLE, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT } + +#define GPIO_INPUT_NOPU \ + { .pad_conf0 = PAD_PU_10K | PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT_ENABLE, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT } #define GPIO_OUT_LOW \ - { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \ + { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT_ENABLE, \ + .pad_val = PAD_VAL_OUTPUT_ENABLE | PAD_VAL_LOW, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_LOW } #define GPIO_OUT_HIGH \ - { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \ + { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT_ENABLE, \ + .pad_val = PAD_VAL_OUTPUT_ENABLE | PAD_VAL_HIGH, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_HIGH } @@ -214,8 +236,10 @@ { .pad_conf0 = GPIO_LIST_END } /* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_PU_10K -#define GPIO_UNUSED GPIO_INPUT_PU_10K +#define GPIO_INPUT GPIO_INPUT_NOPU +#define GPIO_INPUT_PU GPIO_INPUT_PU_10K +#define GPIO_INPUT_PD GPIO_INPUT_PD_10K +#define GPIO_NC GPIO_INPUT_PU_10K #define GPIO_DEFAULT GPIO_FUNC0 struct soc_gpio_map { diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 9ae79c9..2916c99 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -23,53 +23,57 @@ /* GPIO-to-Pad LUTs */ static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = - { 25, 24, 23, 32, 33, 34, 36, 37, 35, 22, - 20, 21, 18, 38, 39, 1, 4, 8, 17, 0, - 3, 6, 16, 19, 2, 5, 9 }; + { 25, 24, 23, 32, 33, 34, 36, 37, /* [ 0: 7] */ + 35, 22, 20, 21, 18, 38, 39, 1, /* [ 8:15] */ + 4, 8, 17, 0, 3, 6, 16, 19, /* [16:23] */ + 2, 5, 9 }; /* [24:26] */ static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = - { 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, - 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, - 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, - 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, - 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, - 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, - 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, - 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, - 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, - 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, - 97, 100 }; + { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ + 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */ + 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */ + 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */ + 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */ + 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */ + 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */ + 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */ + 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */ + 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */ + 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */ + 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */ + 106, 87, 91, 104, 97, 100 }; /* [96:101] */ static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = - { 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, - 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, - 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, - 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, - 52, 53, 59, 40 }; + { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */ + 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */ + 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */ + 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */ + 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */ + 52, 53, 59, 40 }; /* [40:43] */ /* GPIO bank descriptions */ static const struct gpio_bank gpncore_bank = { - .gpio_count = GPNCORE_COUNT, - .gpio_to_pad = gpncore_gpio_to_pad, - .legacy_base = GP_LEGACY_BASE_NONE, - .pad_base = GPNCORE_PAD_BASE, - .has_wake_en = 0, + .gpio_count = GPNCORE_COUNT, + .gpio_to_pad = gpncore_gpio_to_pad, + .legacy_base = GP_LEGACY_BASE_NONE, + .pad_base = GPNCORE_PAD_BASE, + .has_wake_en = 0, }; static const struct gpio_bank gpscore_bank = { - .gpio_count = GPSCORE_COUNT, - .gpio_to_pad = gpscore_gpio_to_pad, - .legacy_base = GPSCORE_LEGACY_BASE, - .pad_base = GPSCORE_PAD_BASE, - .has_wake_en = 0, + .gpio_count = GPSCORE_COUNT, + .gpio_to_pad = gpscore_gpio_to_pad, + .legacy_base = GPSCORE_LEGACY_BASE, + .pad_base = GPSCORE_PAD_BASE, + .has_wake_en = 0, }; static const struct gpio_bank gpssus_bank = { - .gpio_count = GPSSUS_COUNT, - .gpio_to_pad = gpssus_gpio_to_pad, - .legacy_base = GPSSUS_LEGACY_BASE, - .pad_base = GPSSUS_PAD_BASE, - .has_wake_en = 1, + .gpio_count = GPSSUS_COUNT, + .gpio_to_pad = gpssus_gpio_to_pad, + .legacy_base = GPSSUS_LEGACY_BASE, + .pad_base = GPSSUS_PAD_BASE, + .has_wake_en = 1, }; static void setup_gpios(const struct soc_gpio_map *gpios,

1 0

Patch set updated for coreboot: 0601302 rambi: Add platform GPIO configuration tables
by Aaron Durbin 05 Feb '14

05 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4875 -gerrit commit 0601302b021ce4b5ae802ceb685e38db0e0d735f Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Thu Oct 10 13:41:19 2013 -0700 rambi: Add platform GPIO configuration tables Configure GPIOs according to function on board. TEST=compile only. BUG=chrome-os-partner:22863 Change-Id: Ic38eeb64149606f2d7a19cc7a0144cc7e24807b8 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172657 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 347 +++++++++++++++++++------------------- 1 file changed, 174 insertions(+), 173 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 3f91366..d7082be 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -20,191 +20,192 @@ #include <stdlib.h> #include <baytrail/gpio.h> +/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */ /* NCORE GPIOs */ static const struct soc_gpio_map gpncore_gpio_map[] = { - GPIO_DEFAULT, /* GPIO 0 */ - GPIO_DEFAULT, /* GPIO 1 */ - GPIO_DEFAULT, /* GPIO 2 */ - GPIO_DEFAULT, /* GPIO 3 */ - GPIO_DEFAULT, /* GPIO 4 */ - GPIO_DEFAULT, /* GPIO 5 */ - GPIO_DEFAULT, /* GPIO 6 */ - GPIO_DEFAULT, /* GPIO 7 */ - GPIO_DEFAULT, /* GPIO 8 */ - GPIO_DEFAULT, /* GPIO 9 */ - GPIO_DEFAULT, /* GPIO 10 */ - GPIO_DEFAULT, /* GPIO 11 */ - GPIO_DEFAULT, /* GPIO 12 */ - GPIO_DEFAULT, /* GPIO 13 */ - GPIO_DEFAULT, /* GPIO 14 */ - GPIO_DEFAULT, /* GPIO 15 */ - GPIO_DEFAULT, /* GPIO 16 */ - GPIO_DEFAULT, /* GPIO 17 */ - GPIO_DEFAULT, /* GPIO 18 */ - GPIO_DEFAULT, /* GPIO 19 */ - GPIO_DEFAULT, /* GPIO 20 */ - GPIO_DEFAULT, /* GPIO 21 */ - GPIO_DEFAULT, /* GPIO 22 */ - GPIO_DEFAULT, /* GPIO 23 */ - GPIO_DEFAULT, /* GPIO 24 */ - GPIO_DEFAULT, /* GPIO 25 */ - GPIO_DEFAULT, /* GPIO 26 */ + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_FUNC2, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_NC, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_NC, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_NC, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_NC, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_NC, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_NC, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_NC, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_NC, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_NC, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ GPIO_END }; /* SCORE GPIOs */ static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_DEFAULT, /* GPIO 0 */ - GPIO_DEFAULT, /* GPIO 1 */ - GPIO_DEFAULT, /* GPIO 2 */ - GPIO_DEFAULT, /* GPIO 3 */ - GPIO_DEFAULT, /* GPIO 4 */ - GPIO_DEFAULT, /* GPIO 5 */ - GPIO_DEFAULT, /* GPIO 6 */ - GPIO_DEFAULT, /* GPIO 7 */ - GPIO_DEFAULT, /* GPIO 8 */ - GPIO_DEFAULT, /* GPIO 9 */ - GPIO_DEFAULT, /* GPIO 10 */ - GPIO_DEFAULT, /* GPIO 11 */ - GPIO_DEFAULT, /* GPIO 12 */ - GPIO_DEFAULT, /* GPIO 13 */ - GPIO_DEFAULT, /* GPIO 14 */ - GPIO_DEFAULT, /* GPIO 15 */ - GPIO_DEFAULT, /* GPIO 16 */ - GPIO_DEFAULT, /* GPIO 17 */ - GPIO_DEFAULT, /* GPIO 18 */ - GPIO_DEFAULT, /* GPIO 19 */ - GPIO_DEFAULT, /* GPIO 20 */ - GPIO_DEFAULT, /* GPIO 21 */ - GPIO_DEFAULT, /* GPIO 22 */ - GPIO_DEFAULT, /* GPIO 23 */ - GPIO_DEFAULT, /* GPIO 24 */ - GPIO_DEFAULT, /* GPIO 25 */ - GPIO_DEFAULT, /* GPIO 26 */ - GPIO_DEFAULT, /* GPIO 27 */ - GPIO_DEFAULT, /* GPIO 28 */ - GPIO_DEFAULT, /* GPIO 29 */ - GPIO_DEFAULT, /* GPIO 30 */ - GPIO_DEFAULT, /* GPIO 31 */ - GPIO_DEFAULT, /* GPIO 32 */ - GPIO_DEFAULT, /* GPIO 33 */ - GPIO_DEFAULT, /* GPIO 34 */ - GPIO_DEFAULT, /* GPIO 35 */ - GPIO_DEFAULT, /* GPIO 36 */ - GPIO_DEFAULT, /* GPIO 37 */ - GPIO_DEFAULT, /* GPIO 38 */ - GPIO_DEFAULT, /* GPIO 39 */ - GPIO_DEFAULT, /* GPIO 40 */ - GPIO_DEFAULT, /* GPIO 41 */ - GPIO_DEFAULT, /* GPIO 42 */ - GPIO_DEFAULT, /* GPIO 43 */ - GPIO_DEFAULT, /* GPIO 44 */ - GPIO_DEFAULT, /* GPIO 45 */ - GPIO_DEFAULT, /* GPIO 46 */ - GPIO_DEFAULT, /* GPIO 47 */ - GPIO_DEFAULT, /* GPIO 48 */ - GPIO_DEFAULT, /* GPIO 49 */ - GPIO_DEFAULT, /* GPIO 50 */ - GPIO_FUNC1, /* GPIO 51 - SMBus DATA */ - GPIO_FUNC1, /* GPIO 52 - SMBus CLK */ - GPIO_DEFAULT, /* GPIO 53 */ - GPIO_DEFAULT, /* GPIO 54 */ - GPIO_DEFAULT, /* GPIO 55 */ - GPIO_DEFAULT, /* GPIO 56 */ - GPIO_FUNC1, /* GPIO 57 - COM1 TXD */ - GPIO_DEFAULT, /* GPIO 58 */ - GPIO_DEFAULT, /* GPIO 59 */ - GPIO_DEFAULT, /* GPIO 60 */ - GPIO_FUNC1, /* GPIO 61 - COM1 RXD */ - GPIO_DEFAULT, /* GPIO 62 */ - GPIO_DEFAULT, /* GPIO 63 */ - GPIO_DEFAULT, /* GPIO 64 */ - GPIO_DEFAULT, /* GPIO 65 */ - GPIO_DEFAULT, /* GPIO 66 */ - GPIO_DEFAULT, /* GPIO 67 */ - GPIO_DEFAULT, /* GPIO 68 */ - GPIO_DEFAULT, /* GPIO 69 */ - GPIO_DEFAULT, /* GPIO 70 */ - GPIO_DEFAULT, /* GPIO 71 */ - GPIO_DEFAULT, /* GPIO 72 */ - GPIO_DEFAULT, /* GPIO 73 */ - GPIO_DEFAULT, /* GPIO 74 */ - GPIO_DEFAULT, /* GPIO 75 */ - GPIO_DEFAULT, /* GPIO 76 */ - GPIO_DEFAULT, /* GPIO 77 */ - GPIO_DEFAULT, /* GPIO 78 */ - GPIO_DEFAULT, /* GPIO 79 */ - GPIO_DEFAULT, /* GPIO 80 */ - GPIO_DEFAULT, /* GPIO 81 */ - GPIO_DEFAULT, /* GPIO 82 */ - GPIO_DEFAULT, /* GPIO 83 */ - GPIO_DEFAULT, /* GPIO 84 */ - GPIO_DEFAULT, /* GPIO 85 */ - GPIO_DEFAULT, /* GPIO 86 */ - GPIO_DEFAULT, /* GPIO 87 */ - GPIO_DEFAULT, /* GPIO 88 */ - GPIO_DEFAULT, /* GPIO 89 */ - GPIO_DEFAULT, /* GPIO 90 */ - GPIO_DEFAULT, /* GPIO 91 */ - GPIO_DEFAULT, /* GPIO 92 */ - GPIO_DEFAULT, /* GPIO 93 */ - GPIO_DEFAULT, /* GPIO 94 */ - GPIO_DEFAULT, /* GPIO 95 */ - GPIO_DEFAULT, /* GPIO 96 */ - GPIO_DEFAULT, /* GPIO 97 */ - GPIO_DEFAULT, /* GPIO 98 */ - GPIO_DEFAULT, /* GPIO 99 */ - GPIO_DEFAULT, /* GPIO 100 */ - GPIO_DEFAULT, /* GPIO 101 */ + GPIO_INPUT, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_NC, /* S0-SC007 - SD3_WP (NC) */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC3, /* S0-SC016 - MMC1_CLK */ + GPIO_FUNC3, /* S0-SC017 - MMC1_D[0] */ + GPIO_FUNC3, /* S0-SC018 - MMC1_D[1] */ + GPIO_FUNC3, /* S0-SC019 - MMC1_D[2] */ + GPIO_FUNC3, /* S0-SC020 - MMC1_D[3] */ + GPIO_FUNC3, /* S0-SC021 - MMC1_D[4] */ + GPIO_FUNC3, /* S0-SC022 - MMC1_D[5] */ + GPIO_FUNC3, /* S0-SC023 - MMC1_D[6] */ + GPIO_FUNC3, /* S0-SC024 - MMC1_D[7] */ + GPIO_FUNC3, /* S0-SC025 - MMC1_CMD */ + GPIO_FUNC3, /* S0-SC026 - MMC1_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_NC, /* S0-SC033 - SD3_CLK (NC) */ + GPIO_NC, /* S0-SC034 - SD3_D0 (NC) */ + GPIO_NC, /* S0-SC035 - SD3_D1 (NC) */ + GPIO_NC, /* S0-SC036 - SD3_D2 (NC) */ + GPIO_NC, /* S0-SC037 - SD3_D3 (NC) */ + GPIO_NC, /* S0-SC038 - SD3_CD# (NC) */ + GPIO_NC, /* S0-SC039 - SD3_CMD (NC) */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN (NC) */ + GPIO_NC, /* S0-SC041 - SDIO3_PWR_EN# (NC)*/ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_FUNC1, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_INPUT, /* S0-SC055 - TRACKPAD_INT_DX - INT */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_INPUT, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_INPUT, /* S0-SC072 - TOUCH_INT_L_DX - INT */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_NC, /* S0-SC101 - NC*/ GPIO_END }; /* SSUS GPIOs */ static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_DEFAULT, /* GPIO 0 */ - GPIO_DEFAULT, /* GPIO 1 */ - GPIO_DEFAULT, /* GPIO 2 */ - GPIO_DEFAULT, /* GPIO 3 */ - GPIO_DEFAULT, /* GPIO 4 */ - GPIO_DEFAULT, /* GPIO 5 */ - GPIO_DEFAULT, /* GPIO 6 */ - GPIO_DEFAULT, /* GPIO 7 */ - GPIO_DEFAULT, /* GPIO 8 */ - GPIO_DEFAULT, /* GPIO 9 */ - GPIO_DEFAULT, /* GPIO 10 */ - GPIO_DEFAULT, /* GPIO 11 */ - GPIO_DEFAULT, /* GPIO 12 */ - GPIO_DEFAULT, /* GPIO 13 */ - GPIO_DEFAULT, /* GPIO 14 */ - GPIO_DEFAULT, /* GPIO 15 */ - GPIO_DEFAULT, /* GPIO 16 */ - GPIO_DEFAULT, /* GPIO 17 */ - GPIO_DEFAULT, /* GPIO 18 */ - GPIO_DEFAULT, /* GPIO 19 */ - GPIO_DEFAULT, /* GPIO 20 */ - GPIO_DEFAULT, /* GPIO 21 */ - GPIO_DEFAULT, /* GPIO 22 */ - GPIO_DEFAULT, /* GPIO 23 */ - GPIO_DEFAULT, /* GPIO 24 */ - GPIO_DEFAULT, /* GPIO 25 */ - GPIO_DEFAULT, /* GPIO 26 */ - GPIO_DEFAULT, /* GPIO 27 */ - GPIO_DEFAULT, /* GPIO 28 */ - GPIO_DEFAULT, /* GPIO 29 */ - GPIO_DEFAULT, /* GPIO 30 */ - GPIO_DEFAULT, /* GPIO 31 */ - GPIO_DEFAULT, /* GPIO 32 */ - GPIO_DEFAULT, /* GPIO 33 */ - GPIO_DEFAULT, /* GPIO 34 */ - GPIO_DEFAULT, /* GPIO 35 */ - GPIO_DEFAULT, /* GPIO 36 */ - GPIO_DEFAULT, /* GPIO 37 */ - GPIO_DEFAULT, /* GPIO 38 */ - GPIO_DEFAULT, /* GPIO 39 */ - GPIO_DEFAULT, /* GPIO 40 */ - GPIO_DEFAULT, /* GPIO 41 */ - GPIO_DEFAULT, /* GPIO 42 */ - GPIO_DEFAULT, /* GPIO 43 */ + GPIO_NC, /* S500 - PCH_WAKE# (NC) */ + GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */ + GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_INPUT, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_NC, /* S509 - MUX_AUD_INT1# (NC) */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ GPIO_END };

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Patch set updated for coreboot: 9e4d424 baytrail: add reset support
by Aaron Durbin 05 Feb '14

05 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4878 -gerrit commit 9e4d424d6147cc466625ca4ad37f14790945bff5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 20:54:57 2013 -0500 baytrail: add reset support Bay Trail has the following types of resets it supports: - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but with ETR[20] set. While these are documented this support currently provides support for 2nd soft reset as well as cold and warm reset. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted. Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172710 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/Makefile.inc | 2 ++ src/soc/intel/baytrail/baytrail/pmc.h | 12 +++++++++ src/soc/intel/baytrail/baytrail/reset.h | 36 +++++++++++++++++++++++++ src/soc/intel/baytrail/reset.c | 47 +++++++++++++++++++++++++++++++++ 5 files changed, 98 insertions(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 4cd2133..293ed21 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_MICROCODE_IN_CBFS select DYNAMIC_CBMEM select HAVE_SMI_HANDLER + select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index b4474c0..9695a70 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -20,6 +20,8 @@ romstage-y += iosf.c ramstage-y += northcluster.c ramstage-y += ramstage.c ramstage-y += gpio.c +romstage-y += reset.c +ramstage-y += reset.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index 2cf1f00..b85800a 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -26,6 +26,12 @@ /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ #define GEN_PMCONF1 0x20 # define UART_EN (1 << 24) +#define ETR 0x48 +# define CF9LOCK (1 << 31) +# define LTR_DEF (1 << 22) +# define IGNORE_HPET (1 << 21) +# define CF9GR (1 << 20) +# define CWORWRE (1 << 18) /* IO Mapped registers behind ACPI_BASE_ADDRESS */ #define TCO_RLD 0x60 @@ -37,4 +43,10 @@ # define TCO_TMR_HALT (1 << 11) #define TCO_TMR 0x70 +/* I/O ports */ +#define RST_CNT 0xcf9 +# define FULL_RST (1 << 3) +# define RST_CPU (1 << 2) +# define SYS_RST (1 << 1) + #endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/reset.h b/src/soc/intel/baytrail/baytrail/reset.h new file mode 100644 index 0000000..dbf0fd2 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/reset.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_RESET_H_ +#define _BAYTRAIL_RESET_H_ +#include <reset.h> + +/* Bay Trail has the following types of resets: + * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 + * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 + * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 + * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 + * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but + * with ETR[20] set. + */ + +void cold_reset(void); +void warm_reset(void); + +#endif /* _BAYTRAIL_RESET_H_ */ diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c new file mode 100644 index 0000000..a421ec9 --- /dev/null +++ b/src/soc/intel/baytrail/reset.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <baytrail/pmc.h> +#include <baytrail/reset.h> + +void cold_reset(void) +{ + /* S0->S5->S0 trip. */ + outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); +} + +void warm_reset(void) +{ + /* PMC_PLTRST# asserted. */ + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void soft_reset(void) +{ + /* Sends INIT# to CPU */ + outb(RST_CPU, RST_CNT); +} + +void hard_reset(void) +{ + /* Don't power cycle on hard_reset(). It's not really clear what the + * semantics should be for the meaning of hard_reset(). */ + warm_reset(); +}

1 0

Patch set updated for coreboot: 01357a9 baytrail: make default GPIO configs closer to power-on defaults
by Aaron Durbin 05 Feb '14

05 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4866 -gerrit commit 01357a934d42fca900122ce5ea6f6eb06655d6bf Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Oct 4 11:47:21 2013 -0700 baytrail: make default GPIO configs closer to power-on defaults - Set config0 defaults for hysteresis disable, pad bypass, etc. - Set config1 power-on defaults. - Set pad_val for input as default. BUG=chrome-os-partner:22863 TEST=Manual. Enable GPIO_DEBUG and verify pad registers are set according to expectation. Also verify bayleybay still boots to payload loading. Change-Id: I0f1c9e4d4f39c5c56d7e14a82eb4825612e19420 Reviewed-on: https://chromium-review.googlesource.com/171903 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/gpio.h | 113 +++++++++++++++++++++++++-------- 1 file changed, 86 insertions(+), 27 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index 32b991e..aae41a4 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -27,9 +27,9 @@ /* #define GPIO_DEBUG */ /* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ -#define GPSCORE_PAD_BASE IO_BASE_ADDRESS + 0x0000 -#define GPNCORE_PAD_BASE IO_BASE_ADDRESS + 0x1000 -#define GPSSUS_PAD_BASE IO_BASE_ADDRESS + 0x2000 +#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + 0x0000) +#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + 0x1000) +#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + 0x2000) /* Pad register offset */ #define PAD_CONF0_REG 0x0 @@ -37,8 +37,8 @@ #define PAD_VAL_REG 0x8 /* Legacy IO register base */ -#define GPSCORE_LEGACY_BASE GPIO_BASE_ADDRESS + 0x00 -#define GPSSUS_LEGACY_BASE GPIO_BASE_ADDRESS + 0x80 +#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) +#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) /* Some banks have no legacy GPIO interface */ #define GP_LEGACY_BASE_NONE 0xFFFF @@ -71,19 +71,45 @@ #define GPIO_NEDGE_DISABLE 0 #define GPIO_NEDGE_ENABLE 1 -/* PAD_CONF0 settings */ +/* config0[29] - Disable second mask */ +#define PAD_MASK2_DISABLE (1 << 29) + +/* config0[27] - Direct Irq En */ #define PAD_IRQ_EN (1 << 27) + +/* config0[24] - Gd Level */ #define PAD_LEVEL_IRQ (1 << 24) +#define PAD_EDGE_IRQ (0 << 24) + +/* config0[17] - Slow clkgate / glitch filter */ +#define PAD_SLOWGF_ENABLE (1 << 17) + +/* config0[16] - Fast clkgate / glitch filter */ +#define PAD_FASTGF_ENABLE (1 << 16) +/* config0[15] - Hysteresis enable (inverted) */ +#define PAD_HYST_DISABLE (1 << 15) +#define PAD_HYST_ENABLE (0 << 15) + +/* config0[14:13] - Hysteresis control */ +#define PAD_HYST_CTRL_DEFAULT (2 << 13) + +/* config0[11] - Bypass Flop */ +#define PAD_FLOP_BYPASS (1 << 11) +#define PAD_FLOP_ENABLE (0 << 11) + +/* config0[10:9] - Pull str */ #define PAD_PU_2K (0 << 9) #define PAD_PU_10K (1 << 9) #define PAD_PU_20K (2 << 9) #define PAD_PU_40K (3 << 9) +/* config0[8:7] - Pull assign */ #define PAD_PU_DISABLE (0 << 7) #define PAD_PU_UP (1 << 7) #define PAD_PU_DOWN (2 << 7) +/* config0[2:0] - Func. pin mux */ #define PAD_FUNC0 0x0 #define PAD_FUNC1 0x1 #define PAD_FUNC2 0x2 @@ -92,68 +118,101 @@ #define PAD_FUNC5 0x5 #define PAD_FUNC6 0x6 -/* PAD_VAL settings */ -#define PAD_INPUT_ENABLE (1 << 2) -#define PAD_OUTPUT_ENABLE (1 << 1) +/* pad config0 power-on values - We will not often want to change these */ +#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \ + PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \ + PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS) -/* End marker */ -#define GPIO_LIST_END 0xffffffff +/* pad config1 reg power-on values - Shouldn't need to change this */ +#define PAD_CONFIG1_DEFAULT 0x8000 + +/* pad_val[2] - Iinenb - active low */ +#define PAD_VAL_INPUT_DISABLE (1 << 2) +#define PAD_VAL_INPUT_ENABLE (0 << 2) + +/* pad_val[1] - Ioutenb - active low */ +#define PAD_VAL_OUTPUT_DISABLE (1 << 1) +#define PAD_VAL_OUTPUT_ENABLE (0 << 1) + +/* pad_val reg power-on default varies by pad, and apparently can cause issues + * if not set correctly, even if the pin isn't configured as GPIO. */ +#define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) #define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PU_UP, \ - .pad_val = PAD_INPUT_ENABLE, \ + { .pad_conf0 = PAD_PU_10K | PAD_PU_UP | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT_ENABLE, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT } #define GPIO_OUT_LOW \ - { .pad_conf0 = PAD_PU_DISABLE, \ - .pad_val = PAD_OUTPUT_ENABLE, \ + { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT_ENABLE, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_LOW } #define GPIO_OUT_HIGH \ - { .pad_conf0 = PAD_PU_DISABLE, \ - .pad_val = PAD_OUTPUT_ENABLE, \ + { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT_ENABLE, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_HIGH } #define GPIO_FUNC0 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC0 } + .pad_conf0 = PAD_FUNC0 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC1 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC1 } + .pad_conf0 = PAD_FUNC1 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC2 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC2 } + .pad_conf0 = PAD_FUNC2 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC3 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC3 } + .pad_conf0 = PAD_FUNC3 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC4 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC4 } + .pad_conf0 = PAD_FUNC4 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC5 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC5 } + .pad_conf0 = PAD_FUNC5 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC6 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC6 } + .pad_conf0 = PAD_FUNC6 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } + +/* End marker */ +#define GPIO_LIST_END 0xffffffff #define GPIO_END \ { .pad_conf0 = GPIO_LIST_END } /* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_PU_10K -#define GPIO_UNUSED GPIO_INPUT_PU_10K -#define GPIO_DEFAULT GPIO_FUNC0 +#define GPIO_INPUT GPIO_INPUT_PU_10K +#define GPIO_UNUSED GPIO_INPUT_PU_10K +#define GPIO_DEFAULT GPIO_FUNC0 struct soc_gpio_map { u32 pad_conf0;

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coreboot-gerrit February 2014