coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 2290d33 Remove CACHE_ROM.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146 -gerrit commit 2290d3324d66a75fb2cce5f543d5e94d2b0586d2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs on all systems I tried it on, hence screwing up I/O access and cache coherency in worst cases. Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/haswell_init.c | 3 - src/cpu/intel/haswell/mp_init.c | 15 ----- src/cpu/x86/Kconfig | 7 --- src/cpu/x86/mtrr/mtrr.c | 76 ------------------------- src/include/cpu/x86/mtrr.h | 20 +------ src/lib/coreboot_table.c | 20 ------- src/mainboard/google/Kconfig | 5 -- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 4 -- src/northbridge/intel/nehalem/northbridge.c | 2 - src/northbridge/intel/sandybridge/northbridge.c | 2 - src/soc/intel/baytrail/Kconfig | 1 - 16 files changed, 2 insertions(+), 158 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index f8d295e..6e6428b 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -782,9 +782,6 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); - - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index 51130a5..0398360 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -143,14 +143,6 @@ void release_aps_for_smm_relocation(int do_parallel) printk(BIOS_DEBUG, "Timed out waiting for AP SMM relocation\n"); } -/* The mtrr code sets up ROM caching on the BSP, but not the others. However, - * the boot loader payload disables this. In order for Linux not to complain - * ensure the caching is disabled for the APs before going to sleep. */ -static void cleanup_rom_caching(void) -{ - x86_mtrr_disable_rom_caching(); -} - /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) @@ -184,13 +176,6 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_ptr); - /* The MTRR resources are core scoped. Therefore, there is no need - * to do the same work twice. Additionally, this check keeps the - * ROM cache enabled on the BSP since its hyperthread sibling won't - * call cleanup_rom_caching(). */ - if ((lapicid() & 1) == 0) - cleanup_rom_caching(); - /* FIXME(adurbin): park CPUs properly -- preferably somewhere in a * reserved part of memory that the OS cannot get to. */ stop_this_cpu(); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 21282c3..4425ed3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -76,13 +76,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool "Allow for caching system ROM." - default n - help - When selected a variable range MTRR is allocated for coreboot and - the bootloader enables caching of the system ROM for faster access. - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dfb9c94..fc18603 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -184,16 +184,6 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); -#if CONFIG_CACHE_ROM - /* Add a write-protect region covering the ROM size - * when CONFIG_CACHE_ROM is enabled. The ROM is assumed - * to be located at 4GiB - rom size. */ - resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); -#endif - /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -365,61 +355,6 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } -/* Keep track of the MTRR that covers the ROM for caching purposes. */ -#if CONFIG_CACHE_ROM -static long rom_cache_mtrr = -1; - -long x86_mtrr_rom_cache_var_index(void) -{ - return rom_cache_mtrr; -} - -void x86_mtrr_enable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - msr_val.lo |= MTRR_TYPE_WRPROT; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -void x86_mtrr_disable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -static void disable_cache_rom(void *unused) -{ - x86_mtrr_disable_rom_caching(); -} - -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), -}; -#endif - struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -467,17 +402,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; -#if CONFIG_CACHE_ROM - /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing - * one to turn on caching for faster ROM access. However, it is - * left to the MTRR callers to enable it. */ - if (mtrr_type == MTRR_TYPE_WRPROT) { - mtrr_type = MTRR_TYPE_UNCACHEABLE; - if (rom_cache_mtrr < 0) - rom_cache_mtrr = var_state->mtrr_index; - } -#endif - printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9414687..d6cf039 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,10 +52,6 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. - * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling - * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsibility of the caller to enable it by calling - * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -71,24 +67,12 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); -/* ROM caching can be used after variable MTRRs are set up. Beware that - * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on - * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that +/* ROM caching can be used after variable MTRRs are set up. + * Be sure to check the console log when adding WRCOMB resources. Beware that * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the * rom caching will be disabled if all threads run the MTRR code. Therefore, * one needs to call x86_mtrr_enable_rom_caching() after all threads of the * same core have run the MTRR code. */ -#if CONFIG_CACHE_ROM -void x86_mtrr_enable_rom_caching(void); -void x86_mtrr_disable_rom_caching(void); -/* Return the variable range MTRR index of the ROM cache. */ -long x86_mtrr_rom_cache_var_index(void); -#else -static inline void x86_mtrr_enable_rom_caching(void) {} -static inline void x86_mtrr_disable_rom_caching(void) {} -static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } -#endif /* CONFIG_CACHE_ROM */ #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14c..904185a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -235,24 +235,6 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ -static void lb_x86_rom_cache(struct lb_header *header) -{ -#if CONFIG_ARCH_X86 - long mtrr_index; - struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; - - mtrr_index = x86_mtrr_rom_cache_var_index(); - - if (mtrr_index < 0) - return; - - lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); - lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; - lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); - lb_x86_rom_mtrr->index = mtrr_index; -#endif -} - static void add_cbmem_pointers(struct lb_header *header) { /* @@ -529,8 +511,6 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - /* Communicate x86 variable MTRR ROM cache information. */ - lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index b86b0ad..85c8592 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -18,11 +18,6 @@ ## if VENDOR_GOOGLE -# Auto select common options -config VENDOR_SPECIFIC_OPTIONS - def_bool y - select CACHE_ROM - choice prompt "Mainboard model" diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 5247070..47d41ed 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index d800206..5d19ffc 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 6cac476..f401feb 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 6980234..ba6a6fe 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 8e13108..00ea604 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select CACHE_ROM select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5..ce366ef 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index f9386de..d94bc09 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -340,8 +340,6 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7db9301..5440140 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 613593e..d3311ef 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS - select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_MICROCODE_IN_CBFS

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Patch merged into coreboot/master: 2303c2c MTRR: Mark all prefetchable resources as WRCOMB.
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 2303c2ccad560215d0390f3d36be62d61741d76e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 23:25:28 2014 +0100 MTRR: Mark all prefetchable resources as WRCOMB. Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5149 for details. -gerrit

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Patch merged into coreboot/master: e49af7a lib/memrange: Skip 0-sized resources.
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit e49af7aeec87bb5ec836a06f822b4224f4e8e72f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 23:38:29 2014 +0100 lib/memrange: Skip 0-sized resources. Change-Id: I44194153817b8e6b641e407fc4a9e0fd5bc3f318 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5152 for details. -gerrit

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Patch set updated for coreboot: 348026b hp/dl145_g1: Adding ACPI support
by Oskar Enoksson 05 Feb '14

05 Feb '14

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5097 -gerrit commit 348026b909ffc0b289d2d5aa690a329e6a231e51 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Sun Feb 2 15:26:37 2014 +0100 hp/dl145_g1: Adding ACPI support Basic ACPI support for this old platform. Created by copying and tweaking similar motherboard ACPI implementations in coreboot. Works reasonably well under Linux, providing PowerNow, HPET-timers and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44). Not tested under Windows. Change-Id: Ic4d2f9382b6770654eea8842a37ad38cf12de459 Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> --- src/mainboard/hp/dl145_g1/Kconfig | 5 + src/mainboard/hp/dl145_g1/acpi/amd8111.asl | 617 +++++++++++++++++++++++++ src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl | 155 +++++++ src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl | 231 +++++++++ src/mainboard/hp/dl145_g1/acpi/amd8131.asl | 101 ++++ src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl | 6 + src/mainboard/hp/dl145_g1/acpi_tables.c | 341 ++++++++++++++ src/mainboard/hp/dl145_g1/dsdt.asl | 314 +++++++++++++ src/mainboard/hp/dl145_g1/fadt.c | 183 ++++++++ src/mainboard/hp/dl145_g1/mptable.c | 20 +- src/mainboard/hp/dl145_g1/romstage.c | 81 +++- 11 files changed, 2021 insertions(+), 33 deletions(-) diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 7e63077..23a0a20 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -8,14 +8,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF + select HAVE_BUS_CONFIG + select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select SET_FIDVID + select SET_FIDVID_DEBUG select RAMINIT_SYSINFO # select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT select DRIVERS_I2C_I2CMUX + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl new file mode 100644 index 0000000..42381b4 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl @@ -0,0 +1,617 @@ +/* + * Copyright 2005 AMD + * Copyright (C) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + */ +//AMD8111 +// APIC version of the interrupt routing table +Name (APIC, Package (0x04) { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} +}) +// PIC version of the interrupt routing table +Name (PICM, Package (0x04) { + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} +}) +Name (DNCG, Ones) +Method (_PRT, 0, NotSerialized) { + If (LEqual (^DNCG, Ones)) { + Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0) + // Update the Device Number according to SBDN + Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0)) + + Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) + + Store (0x00, ^DNCG) + } + + If (LNot (PICF)) { + Return (PICM) + } Else { + Return (APIC) + } +} + +// AMD8111 System Management I/O Mapped Registers (PMxx) +OperationRegion (PMIO, SystemIO, PMBS, 0xDF) +Field (PMIO, ByteAcc, NoLock, Preserve) { + Offset (0x1E), + SWSM, 8, // Software SMI Trigger (sets GSTS) + Offset (0x28), + GSTS, 16, // Global STatuS + GNBL, 16, // Global SMI enable + Offset (0x30), + STMC, 5, // Miscellaneous SMI Status + Offset (0x32), + ENMC, 5, // Miscellaneous SMI Enable + Offset (0x44), + STC0, 9, // TCO Status 1 + Offset (0x46), + STC1, 4, // TCO Status 2 + Offset (0xA8), + STHW, 20 // Device monitor SMI Interrupt Enable +} +Device (HPET) { + Name (HPT, 0x00) + Name (_HID, EisaId ("PNP0103")) + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) + }) + Return (BUF0) + } +} +#include "amd8111_pic.asl" +#include "amd8111_isa.asl" + +Device (TP2P) { + // 8111 P2P and it should 0x00030000 when 8131 present + Method (_ADR, 0, NotSerialized) { + Return (DADD(\_SB.PCI0.SBDN, 0x00000000)) + } + Method (_PRW, 0, NotSerialized) { // Power Resource for Wake + // result : + // [0] Bit index into GPEx_EN in the GPE block described by FADT. + // [1] The lowest power state from which the system can be awakened. + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x08, 0x03 }) + //} Else { + Return (Package (0x02) { 0x08, 0x01 }) + //} + } + Device (ETHR) { + Name (_ADR, 0x00010000) + Method (_PRW, 0, NotSerialized) { // Power Resource for Wake + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x08, 0x03 }) + //} Else { + Return (Package (0x02) { 0x08, 0x01 }) + //} + } + } + Device (USB0) { + Name (_ADR, 0x00000000) + Method (_PSW, 1, NotSerialized) { // Power State Wake + And (GNBL, 0x7FFF, GNBL) + } + Method (_PRW, 0, NotSerialized) { // Power Resource for Wake + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x0F, 0x03 }) + //} Else { + Return (Package (0x02) { 0x0F, 0x01 }) + //} + } + } + Device (USB1) { + Name (_ADR, 0x00000001) + Method (_PSW, 1, NotSerialized) { // Power State Wake + And (GNBL, 0x7FFF, GNBL) + } + Method (_PRW, 0, NotSerialized) { // Power Resource for Wake + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x0F, 0x03 }) + //} Else { + Return (Package (0x02) { 0x0F, 0x01 }) + //} + } + } + Name (APIC, Package (0x0C) { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6 + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5 + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } + }) + Name (PICM, Package (0x0C) { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6 + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5 + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } + }) + Method (_PRT, 0, NotSerialized) { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } +} +Device (IDE0) { + Method (_ADR, 0, NotSerialized) { + Return (DADD(\_SB.PCI0.SBDN, 0x00010001)) + } + Name (REGF, 0x01) + Method (_REG, 2, NotSerialized) { + If (LEqual (Arg0, 0x02)) { + Store (Arg1, REGF) + } + } + OperationRegion (BAR0, PCI_Config, 0x00, 0x60) + Field (BAR0, ByteAcc, NoLock, Preserve) { + Offset (0x40), // EIDE Controller Configuration Register + SCEN, 1, // Secondary Channel Enable + PCEN, 1, // Primary Channel Enable + , 10, + SPWB, 1, // Secondary Port posted-write buffer for PIO modes enable + SRPB, 1, // RW (controls nothing) + PPWB, 1, // Primary Port posted-write buffer for PIO modes enable + PRPB, 1, // RW (controls nothing) + PM80, 1, // High-speed 80-pin cable enable Primary Master + PS80, 1, // High-speed 80-pin cable enable Primary Slave + SM80, 1, // High-speed 80-pin cable enable Secondary Master + SS80, 1, // High-speed 80-pin cable enable Secondary Slave + , 4, // RW (controls nothing) + Offset (0x48), + SSRT, 4, // + SSPW, 4, // + SMRT, 4, // + SMPW, 4, + PSRT, 4, + PSPW, 4, + PMRT, 4, + PMPW, 4, + SSAD, 2, + SMAD, 2, + PSAD, 2, + PMAD, 2, + Offset (0x4E), + SXRT, 4, + SXPW, 4, + PXRT, 4, + PXPW, 4, + SSUD, 8, + SMUD, 8, + PSUD, 8, + PMUD, 8, + PPDN, 1, + PPDS, 1, + , 2, + SPDN, 1, + SPDS, 1 + } + Name (TIM0, Package (0x06) { + Package (0x05) { + 0x78, + 0xB4, + 0xF0, + 0x0186, + 0x0258 + }, + Package (0x07) { + 0x78, + 0x5A, + 0x3C, + 0x2D, + 0x1E, + 0x14, + 0x0F + }, + Package (0x08) { + 0x04, + 0x03, + 0x02, + 0x01, + 0x00, + 0x00, + 0x00, + 0x00 + }, + Package (0x03) { + 0x02, + 0x01, + 0x00 + }, + Package (0x05) { + 0x20, + 0x22, + 0x42, + 0x65, + 0xA8 + }, + Package (0x07) { + 0xC2, + 0xC1, + 0xC0, + 0xC4, + 0xC5, + 0xC6, + 0xC7 + } + }) + Name (TMD0, Buffer (0x14) {}) + CreateDWordField (TMD0, 0x00, PIO0) + CreateDWordField (TMD0, 0x04, DMA0) + CreateDWordField (TMD0, 0x08, PIO1) + CreateDWordField (TMD0, 0x0C, DMA1) + CreateDWordField (TMD0, 0x10, CHNF) + Device (CHN0) { + Name (_ADR, 0x00) + Method (_STA, 0, NotSerialized) { + If (PCEN) { Return (0x0F) } + Else { Return (0x09) } + } + Method (_GTM, 0, NotSerialized) { + Return (GTM (PMPW, PMRT, PSPW, PSRT, PMUD, PSUD)) + } + Method (_STM, 3, NotSerialized) { + Store (Arg0, TMD0) + Store (STM (), Local0) + And (Local0, 0xFF, PSUD) + ShiftRight (Local0, 0x08, Local0) + And (Local0, 0xFF, PMUD) + ShiftRight (Local0, 0x08, Local0) + And (Local0, 0x0F, PSRT) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, PSPW) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, PMRT) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, PMPW) + Store (GTF (0x00, Arg1), ATA0) + Store (GTF (0x01, Arg2), ATA1) + } + Device (DRV0) { + Name (_ADR, 0x00) + Method (_GTF, 0, NotSerialized) { + Return (RATA (ATA0)) + } + } + Device (DRV1) { + Name (_ADR, 0x01) + Method (_GTF, 0, NotSerialized) { + Return (RATA (ATA1)) + } + } + } + Device (CHN1) { + Name (_ADR, 0x01) + Method (_STA, 0, NotSerialized) { + If (SCEN) { Return (0x0F) } + Else { Return (0x09) } + } + Method (_GTM, 0, NotSerialized) { + Return (GTM (SMPW, SMRT, SSPW, SSRT, SMUD, SSUD)) + } + Method (_STM, 3, NotSerialized) { + Store (Arg0, TMD0) + Store (STM (), Local0) + And (Local0, 0xFF, SSUD) + ShiftRight (Local0, 0x08, Local0) + And (Local0, 0xFF, SMUD) + ShiftRight (Local0, 0x08, Local0) + And (Local0, 0x0F, SSRT) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, SSPW) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, SMRT) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, SMPW) + Store (GTF (0x00, Arg1), ATA2) + Store (GTF (0x01, Arg2), ATA3) + } + Device (DRV0) { + Name (_ADR, 0x00) + Method (_GTF, 0, NotSerialized) { + Return (RATA (ATA2)) + } + } + Device (DRV1) { + Name (_ADR, 0x01) + Method (_GTF, 0, NotSerialized) { + Return (RATA (ATA3)) + } + } + } + Method (GTM, 6, Serialized) { + Store (Ones, PIO0) + Store (Ones, PIO1) + Store (Ones, DMA0) + Store (Ones, DMA1) + Store (0x1A, CHNF) + If (REGF) {} + Else { Return (TMD0) } + Add (Arg0, Arg1, Local0) + Add (Local0, 0x02, Local0) + Multiply (Local0, 0x1E, PIO0) + Add (Arg2, Arg3, Local0) + Add (Local0, 0x02, Local0) + Multiply (Local0, 0x1E, PIO1) + If (And (Arg4, 0x40)) { + Or (CHNF, 0x01, CHNF) + And (Arg4, 0x07, Local0) + If (LLess (Local0, 0x04)) { + Add (Local0, 0x02, Local0) + Multiply (Local0, 0x1E, DMA0) + } Else { + If (LEqual (Local0, 0x04)) { + Store (0x2D, DMA0) + } Else { + If (LEqual (Local0, 0x05)) { + Store (0x1E, DMA0) + } Else { + If (LEqual (Local0, 0x06)) { + Store (0x14, DMA0) + } Else { + If (LEqual (Local0, 0x07)) { + Store (0x0F, DMA0) + } Else { + Store (PIO0, DMA0) + } + } + } + } + } + } Else { + Store (PIO0, DMA0) + } + If (And (Arg5, 0x40)) { + Or (CHNF, 0x04, CHNF) + And (Arg5, 0x07, Local0) + If (LLess (Local0, 0x04)) { + Add (Local0, 0x02, Local0) + Multiply (Local0, 0x1E, DMA1) + } Else { + If (LEqual (Local0, 0x04)) { + Store (0x2D, DMA1) + } Else { + If (LEqual (Local0, 0x05)) { + Store (0x1E, DMA1) + } Else { + If (LEqual (Local0, 0x06)) { + Store (0x14, DMA1) + } Else { + If (LEqual (Local0, 0x07)) { + Store (0x0F, DMA0) + } Else { + Store (PIO1, DMA1) + } + } + } + } + } + } Else { + Store (PIO1, DMA1) + } + Return (TMD0) + } + Method (STM, 0, Serialized) { + If (REGF) {} + Else { Return (0xFFFFFFFF) } + If (LEqual (PIO0, 0xFFFFFFFF)) { + Store (0xA8, Local1) + } Else { + And (Match (DerefOf (Index (TIM0, 0x00)), + MGE, PIO0, MTR, + 0x00, 0x00), + 0x07, Local0) + Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)), + Local1) + } + ShiftLeft (Local1, 0x08, Local1) + If (LEqual (PIO1, 0xFFFFFFFF)) { + Or (Local1, 0xA8, Local1) + } Else { + And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO1, MTR, + 0x00, 0x00), 0x07, Local0) + Or (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)), + Local1, Local1) + } + ShiftLeft (Local1, 0x08, Local1) + If (LEqual (DMA0, 0xFFFFFFFF)) { + Or (Local1, 0x03, Local1) + } Else { + If (And (CHNF, 0x01)) { + And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA0, MTR, + 0x00, 0x00), 0x07, Local0) + Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)), + Local1, Local1) + } Else { + Or (Local1, 0x03, Local1) + } + } + ShiftLeft (Local1, 0x08, Local1) + If (LEqual (DMA1, 0xFFFFFFFF)) { + Or (Local1, 0x03, Local1) + } Else { + If (And (CHNF, 0x04)) { + And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA1, MTR, + 0x00, 0x00), 0x07, Local0) + Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)), + Local1, Local1) + } Else { + Or (Local1, 0x03, Local1) + } + } + Return (Local1) + } + Name (AT01, Buffer (0x07) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF + }) + Name (AT02, Buffer (0x07) { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90 + }) + Name (AT03, Buffer (0x07) { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6 + }) + Name (AT04, Buffer (0x07) { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91 + }) + Name (ATA0, Buffer (0x1D) {}) + Name (ATA1, Buffer (0x1D) {}) + Name (ATA2, Buffer (0x1D) {}) + Name (ATA3, Buffer (0x1D) {}) + Name (ATAB, Buffer (0x1D) {}) + CreateByteField (ATAB, 0x00, CMDC) + Method (GTFB, 3, Serialized) { + Multiply (CMDC, 0x38, Local0) + Add (Local0, 0x08, Local1) + CreateField (ATAB, Local1, 0x38, CMDX) + Multiply (CMDC, 0x07, Local0) + CreateByteField (ATAB, Add (Local0, 0x02), A001) + CreateByteField (ATAB, Add (Local0, 0x06), A005) + Store (Arg0, CMDX) + Store (Arg1, A001) + Store (Arg2, A005) + Increment (CMDC) + } + Method (GTF, 2, Serialized) { + Store (Arg1, Debug) + Store (0x00, CMDC) + Name (ID49, 0x0C00) + Name (ID59, 0x00) + Name (ID53, 0x04) + Name (ID63, 0x0F00) + Name (ID88, 0x0F00) + Name (IRDY, 0x01) + Name (PIOT, 0x00) + Name (DMAT, 0x00) + If (LEqual (SizeOf (Arg1), 0x0200)) { + CreateWordField (Arg1, 0x62, IW49) + Store (IW49, ID49) + CreateWordField (Arg1, 0x6A, IW53) + Store (IW53, ID53) + CreateWordField (Arg1, 0x7E, IW63) + Store (IW63, ID63) + CreateWordField (Arg1, 0x76, IW59) + Store (IW59, ID59) + CreateWordField (Arg1, 0xB0, IW88) + Store (IW88, ID88) + } + Store (0xA0, Local7) + If (Arg0) { + Store (0xB0, Local7) + And (CHNF, 0x08, IRDY) + If (And (CHNF, 0x10)) { + Store (PIO1, PIOT) + } Else { + Store (PIO0, PIOT) + } + If (And (CHNF, 0x04)) { + If (And (CHNF, 0x10)) { + Store (DMA1, DMAT) + } Else { + Store (DMA0, DMAT) + } + } Else { + Store (PIO1, DMAT) + } + } Else { + And (CHNF, 0x02, IRDY) + Store (PIO0, PIOT) + If (And (CHNF, 0x01)) { + Store (DMA0, DMAT) + } + } + If (LAnd (LAnd (And (ID53, 0x04), And (ID88, 0xFF00)), DMAT)) { + Store (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMAT, MTR, + 0x00, 0x00), Local1) + If (LGreater (Local1, 0x06)) { + Store (0x06, Local1) + } + GTFB (AT01, Or (0x40, Local1), Local7) + } Else { + If (LAnd (And (ID63, 0xFF00), PIOT)) { + And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR, + 0x00, 0x00), 0x07, Local0) + If (Local0) { + If (And (Local0, 0x04)) { + Store (0x02, Local0) + } Else { + Store (0x01, Local0) + } + } + Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0 + )), Local1) + GTFB (AT01, Local1, Local7) + } + } + If (IRDY) { + And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR, + 0x00, 0x00), 0x07, Local0) + Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0 + )), Local1) + GTFB (AT01, Local1, Local7) + } Else { + If (And (ID49, 0x0400)) { + GTFB (AT01, 0x01, Local7) + } + } + If (LAnd (And (ID59, 0x0100), And (ID59, 0xFF))) { + GTFB (AT03, And (ID59, 0xFF), Local7) + } + Store (ATAB, Debug) + Return (ATAB) + } + Method (RATA, 1, NotSerialized) { + CreateByteField (Arg0, 0x00, CMDN) + Multiply (CMDN, 0x38, Local0) + CreateField (Arg0, 0x08, Local0, RETB) + Store (RETB, Debug) + Return (RETB) + } +} +Device (PMF) { + // acpi smbus it should be 0x00040003 if 8131 present + Method (_ADR, 0, NotSerialized) + { + Return (DADD(\_SB.PCI0.SBDN, 0x00010003)) + } + OperationRegion (BAR0, PCI_Config, 0x00, 0xff) + Field (BAR0, ByteAcc, NoLock, Preserve) { + Offset (0x56), + PIRA, 4, + PIRB, 4, + PIRC, 4, + PIRD, 4 + } + //OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) + //Field (TS3_, DWordAcc, NoLock, Preserve) { + // PTS3, 16 + //} +} diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl new file mode 100644 index 0000000..be2a1ff --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl @@ -0,0 +1,155 @@ +/* + * Copyright 2005 AMD + * Copyright (C) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + */ +//AMD8111 isa + +Device (ISA) { + // lpc 0x00040000 + Method (_ADR, 0, NotSerialized) { + Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) + } + /* + OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers + Field (PIRY, ByteAcc, NoLock, Preserve) { + Z000, 2, // Parallel Port Range + , 1, + ECP , 1, // ECP Enable + FDC1, 1, // Floppy Drive Controller 1 + FDC2, 1, // Floppy Drive Controller 2 + Offset (0x01), + Z001, 3, // Serial Port A Range + SAEN, 1, // Serial Post A Enabled + Z002, 3, // Serial Port B Range + SBEN, 1 // Serial Post B Enabled + } + */ + Device (PIC) { + Name (_HID, EisaId ("PNP0000")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) // Master Interrupt controller + IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) // Slave Interrupt controller + IRQ (Edge, ActiveHigh, Exclusive) {2} + }) + } + Device (DMA1) { + Name (_HID, EisaId ("PNP0200")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) // Slave DMA controller + IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) // DMA page registers + IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) // Master DMA controller + DMA (Compatibility, NotBusMaster, Transfer16) {4} + }) + } + Device (TMR) { + Name (_HID, EisaId ("PNP0100")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) // Programmable Interval timer + IRQ (Edge, ActiveHigh, Exclusive) {0} + }) + } + Device (RTC) { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0070, 0x0070, 0x01, 0x04) // Realtime Clock and CMOS ram + IRQ (Edge, ActiveHigh, Exclusive) {8} + }) + } + Device (SPKR) { + Name (_HID, EisaId ("PNP0800")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) // PC speaker + }) + } + Device (COPR) { // Co-processor + Name (_HID, EisaId ("PNP0C04")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) // Floating point Error control + IRQ (Edge, ActiveHigh, Exclusive) {13} + }) + } + Device (SYSR) { // System control registers (?) + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x00) + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) + IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) + IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) + IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C) + IO (Decode16, 0x0080, 0x0080, 0x01, 0x01) + IO (Decode16, 0x0084, 0x0084, 0x01, 0x03) + IO (Decode16, 0x0088, 0x0088, 0x01, 0x01) + IO (Decode16, 0x008C, 0x008C, 0x01, 0x03) + IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) + // IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + // EISA defined level triggered interrupt control registers + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) + // IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + // IO (Decode16, 0xDE00, 0xDE00, 0x00, 0x80) + // IO (Decode16, 0xDE80, 0xDE80, 0x00, 0x80) + IO (Decode16,0xDE00,0xDE00,0x00,0x80) + IO (Decode16,0xDE80,0xDE80,0x00,0x80) + // IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM + // IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) + IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0D) // PMBS block + IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0E) // SMBS block + IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0F) // GPBS block + }) + Method (_CRS, 0, NotSerialized) { + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MIN, GP00) + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MAX, GP01) + CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._LEN, GP0L) + Store (PMBS, GP00) + Store (PMBS, GP01) + Store (PMLN, GP0L) + If (SMBS) { + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MIN, GP10) + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MAX, GP11) + CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._LEN, GP1L) + Store (SMBS, GP10) + Store (SMBS, GP11) + Store (SMBL, GP1L) + } + If (GPBS) { + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MIN, GP20) + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MAX, GP21) + CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._LEN, GP2L) + Store (GPBS, GP20) + Store (GPBS, GP21) + Store (GPLN, GP2L) + } + Return (CRS) + } + } + Device (MEM) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF + Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 + Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC + Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM + Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + }) +// Read the Video Memory length + CreateDWordField (BUF0, 0x14, CLEN) + CreateDWordField (BUF0, 0x10, CBAS) + + ShiftLeft (VGA1, 0x09, Local0) + Store (Local0, CLEN) + + Return (BUF0) + } + } +#include "superio/winbond/w83627hf/acpi/superio.asl" +} diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl new file mode 100644 index 0000000..a09c576 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl @@ -0,0 +1,231 @@ +/* + * Copyright 2005 AMD + * Copyright (C) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + */ +//AMD8111 pic LNKA B C D + +Device (LNKA) { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x01) + Method (_STA, 0, NotSerialized) { + If (LEqual (\_SB.PCI0.PMF.PIRA, 0x00) ) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + Method (_PRS, 0, Serialized) { + Name (BUFA, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + Method (_DIS, 0, NotSerialized) { + Store (0x00, \_SB.PCI0.PMF.PIRA ) + } + + Method (_CRS, 0, Serialized) { + Name (BUFA, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local2) + Store (0x00, Local3) + Store (\_SB.PCI0.PMF.PIRA, Local1) + If (LNot (LEqual (Local1, 0x00))) { // Routing enable + If (LGreater (Local1, 0x07)) { + Subtract (Local1, 0x08, Local1) + ShiftLeft (One, Local1, Local3) + } Else { + If (LGreater (Local1, 0x00)) { + ShiftLeft (One, Local1, Local2) + } + } + Store (Local2, IRA1) + Store (Local3, IRA2) + } + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + Store(Local1,\_SB.PCI0.PMF.PIRA) + } +} + +Device (LNKB) { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) { + If (LEqual (\_SB.PCI0.PMF.PIRB, 0x00) ) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + + Method (_PRS, 0, Serialized) { + Name (BUFB, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + + Method (_DIS, 0, NotSerialized) { + Store (0x00, \_SB.PCI0.PMF.PIRB ) + } + + Method (_CRS, 0, Serialized) { + Name (BUFB, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRA1) + CreateByteField (BUFB, 0x02, IRA2) + Store (0x00, Local2) + Store (0x00, Local3) + Store (\_SB.PCI0.PMF.PIRB, Local1) + If (LNot (LEqual (Local1, 0x00))) { // Routing enable + If (LGreater (Local1, 0x07)) { + Subtract (Local1, 0x08, Local1) + ShiftLeft (One, Local1, Local3) + } Else { + If (LGreater (Local1, 0x00)) { + ShiftLeft (One, Local1, Local2) + } + } + Store (Local2, IRA1) + Store (Local3, IRA2) + } + Return (BUFB) + } + + Method (_SRS, 1, NotSerialized) { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + Store(Local1,\_SB.PCI0.PMF.PIRB) + } +} + +Device (LNKC) { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x03) + Method (_STA, 0, NotSerialized) { + If (LEqual (\_SB.PCI0.PMF.PIRC, 0x00) ) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + + Method (_PRS, 0, Serialized) { + Name (BUFA, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + + Method (_DIS, 0, NotSerialized) { + Store (0x00, \_SB.PCI0.PMF.PIRC ) + } + + Method (_CRS, 0, Serialized) { + Name (BUFA, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local2) + Store (0x00, Local3) + Store (\_SB.PCI0.PMF.PIRC, Local1) + If (LNot (LEqual (Local1, 0x00))) { // Routing enable + If (LGreater (Local1, 0x07)) { + Subtract (Local1, 0x08, Local1) + ShiftLeft (One, Local1, Local3) + } Else { + If (LGreater (Local1, 0x00)) { + ShiftLeft (One, Local1, Local2) + } + } + Store (Local2, IRA1) + Store (Local3, IRA2) + } + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + Store(Local1,\_SB.PCI0.PMF.PIRC) + } +} + +Device (LNKD) { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x04) + Method (_STA, 0, NotSerialized) { + If (LEqual (\_SB.PCI0.PMF.PIRD, 0x00) ) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + Method (_PRS, 0, Serialized) { + Name (BUFB, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + Method (_DIS, 0, NotSerialized) { + Store (0x00, \_SB.PCI0.PMF.PIRD ) + } + Method (_CRS, 0, Serialized) { + Name (BUFB, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRA1) + CreateByteField (BUFB, 0x02, IRA2) + Store (0x00, Local2) + Store (0x00, Local3) + Store (\_SB.PCI0.PMF.PIRD, Local1) + If (LNot (LEqual (Local1, 0x00))) { // Routing enable + If (LGreater (Local1, 0x07)) { + Subtract (Local1, 0x08, Local1) + ShiftLeft (One, Local1, Local3) + } Else { + If (LGreater (Local1, 0x00)) { + ShiftLeft (One, Local1, Local2) + } + } + Store (Local2, IRA1) + Store (Local3, IRA2) + } + Return (BUFB) + } + Method (_SRS, 1, NotSerialized) { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + Store(Local1,\_SB.PCI0.PMF.PIRD) + } +} diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8131.asl b/src/mainboard/hp/dl145_g1/acpi/amd8131.asl new file mode 100644 index 0000000..54aae73 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi/amd8131.asl @@ -0,0 +1,101 @@ +/* + * Copyright 2005 AMD + * Copyright (C) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + */ + +Device (PG0A) { +/* 8131 pcix bridge 1 */ + Method (_ADR, 0, NotSerialized) { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + } + Method (_PRW, 0, NotSerialized) { + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x29, 0x03 }) + //} Else { + Return (Package (0x02) { 0x29, 0x01 }) + //} + } + Name (APIC, Package (0x0c) { + // Slot 3 - PIRQ BCDA ---- verified + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, + // Slot 4 - PIRQ CDAB ---- verified + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //? + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, + // Onboard NIC 1 - PIRQ DABC + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //? + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A }, + // NIC 2 - PIRQ ABCD -- verified + // Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //? + // Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, + // Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + // Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + // SERIAL ATA - PIRQ BCDA + // Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //? + // Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A }, + // Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B }, + // Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 } + }) + Name (PICM, Package (0x0c) { + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, + // Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + // Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + // Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + // Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + // Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + // Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + // Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + // Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } + }) + Method (_PRT, 0, NotSerialized) { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } +} +Device (PG0B) { +/* 8131 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + } + Method (_PRW, 0, NotSerialized) { + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x22, 0x03 }) + //} Else { + Return (Package (0x02) { 0x22, 0x01 }) + //} + } + Name (APIC, Package (0x04) { + // Slot A - PIRQ CDAB -- verfied + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },// Slot 2 + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1C }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1D }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1E } + }) + Name (PICM, Package (0x04) { + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2 + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 } + }) + Method (_PRT, 0, NotSerialized) { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } +} diff --git a/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl b/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl new file mode 100644 index 0000000..271d269 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2011,2014, Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ +#include "amd8111.asl" //real SB at first +#include "amd8131.asl" diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c new file mode 100644 index 0000000..35ec179 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi_tables.c @@ -0,0 +1,341 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer <stepan(a)openbios.org> + * (C) 2005 Stefan Reinauer + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + * + * Copyright (C) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdk8_sysconf.h> +#include "northbridge/amd/amdk8/acpi.h" +#include "mb_sysconf.h" +#include <cpu/amd/model_fxx_powernow.h> + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(unsigned start, unsigned end) +{ + + unsigned i; + print_debug("dump_mem:"); + for(i=start;i<end;i++) { + if((i & 0xf)==0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); + } + print_debug("\n"); +} +#endif + +extern unsigned pm_base; + +extern const unsigned char AmlCode[]; + +#if CONFIG_ACPI_SSDTX_NUM >= 1 +extern const unsigned char AmlCode_ssdt2[]; +extern const unsigned char AmlCode_ssdt3[]; +extern const unsigned char AmlCode_ssdt4[]; +extern const unsigned char AmlCode_ssdt5[]; +#endif + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base=0x18; + + struct mb_sysconf_t *m; + + m = sysconf.mb; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write 8111 IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, + IO_APIC_ADDR, 0); + + /* Write all 8131 IOAPICs */ + { + device_t dev; + struct resource *res; + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_1, + res->base, gsi_base ); + gsi_base+=4; + + } + } + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_2, + res->base, gsi_base ); + gsi_base+=4; + } + } + + /* + int i; + int j = 0; + + for(i=1; i< sysconf.hc_possible_num; i++) { + unsigned d = 0; + if(!(sysconf.pci1234[i] & 0x1) ) continue; + // 8131 need to use +4 + + switch (sysconf.hcid[i]) { + case 1: + d = 7; + break; + case 3: + d = 4; + break; + } + switch (sysconf.hcid[i]) { + case 1: + case 3: + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], + res->base, gsi_base ); + gsi_base+=d; + } + } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], + res->base, gsi_base ); + gsi_base+=d; + + } + } + break; + } + + j++; + } + */ + + } + + current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) + current, 0, 0, 2, 5 ); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high*/ + + + /* create all subtables for processors */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + /* 1: LINT1 connect to NMI */ + + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + k8acpi_write_vars(); +#if CONFIG_SET_FIDVID + amd_model_fxx_generate_powernow(pm_base+0x10, 6, 1); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); +#endif + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn + + /* Align ACPI tables to 16byte */ + start = ( start + 0x0f ) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp,hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current+=madt->header.length; + acpi_add_table(rsdp,madt); + + + /* SRAT */ + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current+=srat->header.length; + acpi_add_table(rsdp,srat); + + /* SLIT */ + printk(BIOS_DEBUG, "ACPI: * SLIT\n"); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdp,slit); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + +#if CONFIG_ACPI_SSDTX_NUM >= 1 + int i; + void *p; + acpi_header_t *ssdtx; + //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table + + for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + if((sysconf.pci1234[i] & 1) != 1 ) continue; + uint8_t c; + if(i<7) { + c = (uint8_t) ('4' + i - 1); + } + else { + c = (uint8_t) ('A' + i - 1 - 6); + } + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt + current = ( current + 0x07) & -0x08; + ssdtx = (acpi_header_t *)current; + switch(sysconf.hcid[i]) { + case 1: //8132 + p = &AmlCode_ssdt2; + break; + case 2: //8151 + p = &AmlCode_ssdt3; + break; + case 3: //8131 + p = &AmlCode_ssdt4; + break; + default: + //HTX no io apic + p = &AmlCode_ssdt5; + break; + } + memcpy(ssdtx, p, sizeof(acpi_header_t)); + current += ssdtx->length; + memcpy(ssdtx, p, ssdtx->length); + update_ssdtx((void *)ssdtx, i); + ssdtx->checksum = 0; + ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length); + acpi_add_table(rsdp,ssdtx); + } +#endif + + /* FACS */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FADT */ + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + acpi_fadt_t *fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt,facs,dsdt); + acpi_add_table(rsdp,fadt); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "xsdt\n"); + dump_mem(rsdt, ((void *)xsdt) + sizeof(acpi_xsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/hp/dl145_g1/dsdt.asl b/src/mainboard/hp/dl145_g1/dsdt.asl new file mode 100644 index 0000000..e8d2a14 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/dsdt.asl @@ -0,0 +1,314 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +{ + // Name (SPIO, 0x2E) // SuperIO (w83627hf) + Name (SPI2, 0x4E) // Unknown National Semiconductors (EPM3128A?) + Name (IO1B, 0x0680) // GPIO Base (?) + Name (IO1L, 0x80) + //Name (IO2B, 0x0295) // Hardware monitor + //Name (IO2L, 0x02) + Name (PMBS, 0x2000) // Power Management Base + Name (PMLN, 0xC0) // Power Management Length + Name (GPBS, 0x20C0) + Name (GPLN, 0x20) + Name (SMBS, 0x20E0) + Name (SMBL, 0x20) + +#define NO_W83627HF_FDC // don't expose the floppy disk controller +#define NO_W83627HF_FDC_ENUM // don't try to enumerate the connected floppy drives +#define NO_W83627HF_PPORT // don't expose the parallel port +//#define NO_W83627HF_UARTA // don't expose the first serial port +#define NO_W83627HF_UARTB // don't expose the second serial port (already hidden + // if UARTB is configured as IRDA port by firmware) +#define NO_W83627HF_IRDA // don't expose the IRDA port (already hidden if UARTB is + // configured as serial port by firmware) +#define NO_W83627HF_CIR // don't expose the Consumer Infrared functionality +//#define NO_W83627HF_KBC // don't expose the keyboard controller +//#define NO_W83627HF_PS2M // don't expose the PS/2 mouse functionality of the + // keyboard controller +#define NO_W83627HF_GAME // don't expose the game port +#define NO_W83627HF_MIDI // don't expose the MIDI port +// #define NO_W83627HF_HWMON // don't expose the hardware monitor as + // PnP "Motherboard Resource" +// Scope (\_PR) and relevant CPU? objects are auto-generated in SSDT + + Scope (\_SB) { // Root of the bus hierarchy + Device (PCI0) { // Top PCI device (AMD K8 Northbridge 1) + + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + // The following symbols are assumed to be created by coreboot + External (BUSN) + External (PCIO) + External (MMIO) + External (SBLK) + External (CBST) + External (SBDN) + External (TOM1) // Top Of Memory 1 (low 4GB ?) + External (HCLK) // Hypertransport possible CLocK frequencies + External (HCDN) // Hypertransport Controller Device Numbers + + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180000) + //Name (_UID, 0x00) + Name (_UID, 0x01) + + Name (HCIN, 0x00) // HC1 + Method (_BBN, 0, NotSerialized) { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate () { + // PCI Configuration address space address/data + IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) + IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h + IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x8100, // Address Range Minimum + 0xFFFF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x7F00,,, + , TypeStatic) //8100h-FFFFh + DWordMemory (ResourceProducer, PosDecode, + MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x000C0000, // Address Range Minimum + 0x000CFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00010000,,, + , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh + Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x03AF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x03B0,,, + , TypeStatic) //0-CF7h + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x03E0, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0918,,, + , TypeStatic) //0-CF7h + }) + \_SB.OSTP () + CreateDWordField (BUF0, 0x3E, VLEN) + CreateDWordField (BUF0, 0x36, VMAX) + CreateDWordField (BUF0, 0x32, VMIN) + ShiftLeft (VGA1, 0x09, Local0) + Add (VMIN, Local0, VMAX) + Decrement (VMAX) + Store (Local0, VLEN) + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + #include "acpi/pci0_hc.asl" + } + Device (PCI1) { + Name (_HID, "PNP0A03") + Name (_ADR, 0x00190000) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) { + Return (\_SB.PCI0.CBST) + } + //Name (HCIN, 0x01) // HC2 + //Method (_BBN, 0, NotSerialized) { + // Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + //} + Name (_BBN, 0x00) + } + Device (PWRB) { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 0xAA) + Name (_STA, 0x0B) + } + } + Scope (_GPE) { + Method (_L08, 0, NotSerialized) { + Notify (\_SB.PCI0, 0x02) //PME# Wakeup + Notify (\_SB.PCI0.TP2P.ETHR, 0x02) + Notify (\_SB.PWRB, 0x02) + } + Method (_L0F, 0, NotSerialized) { + Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup + Notify (\_SB.PCI0.TP2P.USB1, 0x02) + Notify (\_SB.PWRB, 0x02) + } + Method (_L22, 0, NotSerialized) { // GPIO18 (LID) - Pogo 0 Bridge B + Notify (\_SB.PCI0.PG0B, 0x02) + Notify (\_SB.PWRB, 0x02) + } + Method (_L29, 0, NotSerialized) { // GPIO25 (Suspend) - Pogo 0 Bridge A + Notify (\_SB.PCI0.PG0A, 0x02) + Notify (\_SB.PWRB, 0x02) + } + } + OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?) + Field (KSB0, ByteAcc, NoLock, Preserve) { + KSBI, 8, // Index + KSBD, 8 // Data + } +/* + OperationRegion (IHHM, SystemIO, IO2B, IO2L) // Hardware monitor + Field (IHHM, ByteAcc, NoLock, Preserve) { + HHMI, 8, // Index + HHMD, 8 // Data + } +*/ + // Method (_BFS, 1, NotSerialized) { + // Control method executed immediately following a wake event. + // Arg0 => Value of the sleeping state from which woken (1=S1, 2=S2 ...) + // Optional + //} + + Method (_PTS, 1, NotSerialized) { + // Control method used to Prepare To Sleep. + // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...) + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG8) + } + + // Method (_GTS, 1, NotSerialized) { + // Control method executed just prior to setting the sleep enable (SLP_EN) bit. + // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...) + // Optional + //} + + // System \_Sx states + // Four bytes must be stored for each supported power state: + // 0:7 Value for PM1a_CNT.SLP_TYP register to enter this system state. + // 8:f Value for PM1b_CNT.SLP_TYP register to enter this system state. + // To enter any given state, OSPM must write the PM1a_CNT.SLP_TYP + // register before the PM1b_CNT.SLP_TYP register. + // 10:1f Reserved + // The states are: + // S0 : Working + // S1 : Sleeping with Processor Context maintained + // S2 : Sleeping with Processor Context not maintained + // S3 : Same as S2, but more power saving (e.g. suspend to RAM) + // S4 : DRAM context not maintained (e.g. suspend to disk) + // S5 : Soft Off + // If only S0 and S5 are declared then no wake-up methods are needed + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + // S1 support should work, but never wakes up, so it's commented out + //Name (\_S1, Package () { 0x01, 0x01, 0x01, 0x01 }) + //Name (\_S3, Package () { 0x05, 0x05, 0x05, 0x05 }) + Name (\_S5, Package () { 0x07, 0x07, 0x07, 0x07 }) + //Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + Method (WAK, 1, NotSerialized) {} + + Name (WAKP, Package (0x02) { 0x00, 0x00 }) + // Status + // 0: 0 Wake was signaled but failed due to lack of power. + // 1: 1 Wake was signaled but failed due to thermal condition + // 2:31 Reserved + // PSS + // 0:1f If non-zero, the effective S-state the power supply really entered. + + Method (_WAK, 1, NotSerialized) { + // System Wake + // Arg0: The value of the sleeping state from which woken (1=S1, ...) + // Result: (2 DWORD package) + ShiftLeft (Arg0, 0x04, DBG8) + WAK (Arg0) + Store (0xFF, KSBI) // Clear 0xFF in CMOS RAM + Store (0x00, KSBD) + If (LEqual (Arg0, 0x01)) { // Wake from S1 state + And (\_SB.PCI0.GSTS, 0x10, Local0) + And (Local0, \_SB.PCI0.GNBL, Local0) + If (Local0) { + Notify (\_SB.PWRB, 0x02) + } + } + Store (\_SB.PCI0.GSTS, \_SB.PCI0.GSTS) + Store (\_SB.PCI0.STMC, \_SB.PCI0.STMC) + Store (\_SB.PCI0.STC0, \_SB.PCI0.STC0) + Store (\_SB.PCI0.STC1, \_SB.PCI0.STC1) + Store (\_SB.PCI0.STHW, \_SB.PCI0.STHW) + If (LEqual (Arg0, 0x03)) { // Wake from S3 state + Notify (\_SB.PCI0.TP2P.USB0, 0x01) + } + Store (0xC0, \_SB.PCI0.SWSM) + If (DerefOf (Index (WAKP, 0x00))) { + Store (0x00, Index (WAKP, 0x01)) + } Else { + Store (Arg0, Index (WAKP, 0x01)) + } + Return (WAKP) + } + + Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode + Method (_PIC, 1, NotSerialized) { //PIC Flag and Interface Method + // Control method that conveys interrupt model in use to the system + // firmware. OS reports interrupt model in use. + // 0 => PIC Mode + // 1 => APIC Mode + // 2 => SAPIC Mode + // 3.. => Reserved + Store (Arg0, PICF) + } + OperationRegion (DEB8, SystemIO, 0x80, 0x01) + Field (DEB8, ByteAcc, Lock, Preserve) { + DBG8, 8 + } + OperationRegion (DEB9, SystemIO, 0x90, 0x01) + Field (DEB9, ByteAcc, Lock, Preserve) { + DBG9, 8 + } + OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) + Field (EXTM, WordAcc, Lock, Preserve) { + AMEM, 32 + } + OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) + Field (VGAM, ByteAcc, Lock, Preserve) { + VGA1, 8 // Video memory length (in 2k units?) + } + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) { + Offset (0x10), + FLG0, 8 + } + OperationRegion (Z007, SystemIO, 0x21, 0x01) + Field (Z007, ByteAcc, NoLock, Preserve) { + Z008, 8 + } + OperationRegion (Z009, SystemIO, 0xA1, 0x01) + Field (Z009, ByteAcc, NoLock, Preserve) { + Z00A, 8 + } + #include "northbridge/amd/amdk8/util.asl" +} diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c new file mode 100644 index 0000000..b81caee --- /dev/null +++ b/src/mainboard/hp/dl145_g1/fadt.c @@ -0,0 +1,183 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * (C) Copyright 2005 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> + +extern unsigned pm_base; /* pm_base should be set in sb acpi */ + +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ + + acpi_header_t *header=&(fadt->header); + + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt,0,sizeof(acpi_fadt_t)); + memcpy(header->signature,"FACP",4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id,OEM_ID,6); + memcpy(header->oem_table_id,"COREBOOT",8); + memcpy(header->asl_compiler_id,ASLC,4); + header->asl_compiler_revision=0; + + fadt->firmware_ctrl=(u32)facs; + fadt->dsdt= (u32)dsdt; + // 3=Workstation,4=Enterprise Server, 7=Performance Server + fadt->preferred_pm_profile=0x04; + fadt->sci_int=9; + + // disable system management mode by setting to 0: + fadt->smi_cmd = 0;//pm_base+0x2f; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + fadt->pm1a_evt_blk = pm_base; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = pm_base+0x04; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = 0x0000; + fadt->pm_tmr_blk = pm_base+0x08; + fadt->gpe0_blk = pm_base+0x20; + fadt->gpe1_blk = pm_base+0xb0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + fadt->gpe1_blk_len = 8; + fadt->gpe1_base = 16; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state + fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state + fadt->flush_size = 0; // ignored if wbindv=1 in flags + fadt->flush_stride = 0; // ignored if wbindv=1 in flags + fadt->duty_offset = 1; + fadt->duty_width = 3; // 0 means duty cycle not supported + // _alrm value 0 means RTC alarm feature not supported + fadt->day_alrm = 0; // 0x7d these have to be + fadt->mon_alrm = 0; // 0x7e added to cmos.layout + fadt->century = 0; // 0x7f to make rtc alrm work + fadt->iapc_boot_arch = + ACPI_FADT_LEGACY_DEVICES | + ACPI_FADT_8042 | + // ACPI_FADT_VGA_NOT_PRESENT | + // ACPI_FADT_MSI_NOT_SUPPORTED| + // ACPI_FADT_NO_PCIE_ASPM_CONTROL| + 0; + + fadt->res2 = 0; + + fadt->flags = + ACPI_FADT_WBINVD | + // ACPI_FADT_WBINVD_FLUSH | + ACPI_FADT_C1_SUPPORTED | + // ACPI_FADT_C2_MP_SUPPORTED | + // ACPI_FADT_POWER_BUTTON | + ACPI_FADT_SLEEP_BUTTON | + // ACPI_FADT_FIXED_RTC | + // ACPI_FADT_S4_RTC_WAKE | + // ACPI_FADT_32BIT_TIMER | + // ACPI_FADT_DOCKING_SUPPORTED| + // ACPI_FADT_RESET_REGISTER | + // ACPI_FADT_SEALED_CASE | + // ACPI_FADT_HEADLESS | + // ACPI_FADT_SLEEP_TYPE | + // ACPI_FADT_PCI_EXPRESS_WAKE | + // ACPI_FADT_PLATFORM_CLOCK | + // ACPI_FADT_S4_RTC_VALID | + // ACPI_FADT_REMOTE_POWER_ON | + // ACPI_FADT_APIC_CLUSTER | + // ACPI_FADT_APIC_PHYSICAL | + 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + + fadt->res3 = 0; + fadt->res4 = 0; + fadt->res5 = 0; + + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pm_base; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pm_base+4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pm_base+0x08; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pm_base+0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 64; + fadt->x_gpe1_blk.bit_offset = 16; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = pm_base+0xb0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index 35dedde..ac3d814 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -1,3 +1,7 @@ +/* + * Copyright (c) 2011,2014, Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ #include <console/console.h> #include <arch/smp/mpspec.h> #include <arch/ioapic.h> @@ -53,26 +57,26 @@ static void *smp_write_config_table(void *v) // /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ // Integrated SMBus 2.0 - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); // Integrated AMD AC97 Audio - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); // Integrated AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13); // On board ATI Rage XL - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); // On board Broadcom nics smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00); // On board LSI SCSI - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); // PCIX-133 Slot smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 67ce9c1..4f5e3fe 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -1,3 +1,7 @@ +/* + * Copyright (c) 2011,2014, Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -44,18 +48,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); - smbus_write_byte(SMBUS_HUB, 0x03, 0); -} - static inline void change_i2c_mux(unsigned device) { int ret, i; @@ -69,6 +61,11 @@ static inline void change_i2c_mux(unsigned device) print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + change_i2c_mux(ctrl->channel0[0]>>8); +} + static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -82,22 +79,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" - -#define RC0 ((1<<1)<<8) -#define RC1 ((1<<2)<<8) +#if CONFIG_SET_FIDVID +#include "cpu/amd/model_fxx/fidvid.c" +#endif void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { - //first node - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC1|DIMM0, RC1|DIMM2, 0, 0, - RC1|DIMM1, RC1|DIMM3, 0, 0, -#endif - }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; @@ -126,6 +113,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif ht_setup_chains_x(sysinfo); +#if CONFIG_SET_FIDVID + /* Check to see if processor is capable of changing FIDVID */ + /* otherwise it will throw a GP# when reading FIDVID_STATUS */ + struct cpuid_result cpuid1 = cpuid(0x80000007); + if ((cpuid1.edx & 0x6) == 0x6) { + { + /* Read FIDVID_STATUS */ + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + + } else { + print_debug("Changing FIDVID not supported\n"); + } +#endif needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); @@ -138,6 +152,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); int i; + +#define RC0 ((1 << 1) << 8) +#define RC1 ((1 << 2) << 8) + for(i=0;i<2;i++) { activate_spd_rom(&sysinfo->ctrl[i]); } @@ -152,9 +170,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl now; + static const uint16_t spd_addr [] = { + //first node + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC1|DIMM0, RC1|DIMM2, 0, 0, + RC1|DIMM1, RC1|DIMM3, 0, 0, +#endif + }; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); +#if CONFIG_SET_FIDVID + init_timer(); // Need to use TMICT to synchronize FID/VID +#endif sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); //dump_pci_devices();

1 0

Patch merged into coreboot/master: d936785 mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit d936785ca9514470335cd2e0bae69319d228ae5c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 5 16:00:43 2014 -0600 mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation If the MTRR usage exceeds the BIOS allocation for MTRR usage re-try without the WRCOMB type. Change-Id: Ie70ce84994428ff6700c36310264c3c44d9ed128 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/5151 for details. -gerrit

1 0

Patch merged into coreboot/master: c85ba6c memranges: add memranges_update_tag() functionality
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit c85ba6cf7a4074630b184d910a1a0980ef98f7ea Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 5 15:44:30 2014 -0600 memranges: add memranges_update_tag() functionality The memranges_update_tag() function replaces all instances that are tagged with old_tag and update to new_tag. This can be helpful in the MTRR code by adjusting the address space if certain memory types cause the MTRR usage to become too large. Change-Id: Ie5c405204de2fdd9fd1dd5d6190b223925d6d318 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/5150 for details. -gerrit

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New patch to review for coreboot: e49af7a lib/memrange: Skip 0-sized resources.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5152 -gerrit commit e49af7aeec87bb5ec836a06f822b4224f4e8e72f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 23:38:29 2014 +0100 lib/memrange: Skip 0-sized resources. Change-Id: I44194153817b8e6b641e407fc4a9e0fd5bc3f318 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/lib/memrange.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 0ebac05..7fb6ef7 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -258,6 +258,9 @@ static void collect_ranges(void *gp, struct device *dev, struct resource *res) { struct collect_context *ctx = gp; + if (res->size == 0) + return; + memranges_insert(ctx->ranges, res->base, res->size, ctx->tag); }

1 0

Patch set updated for coreboot: d936785 mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5151 -gerrit commit d936785ca9514470335cd2e0bae69319d228ae5c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 5 16:00:43 2014 -0600 mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation If the MTRR usage exceeds the BIOS allocation for MTRR usage re-try without the WRCOMB type. Change-Id: Ie70ce84994428ff6700c36310264c3c44d9ed128 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dbedf0f..cdaa791 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -661,8 +661,9 @@ static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, calc_var_mtrr_range(var_state, c1, c2 - c1, mtrr_type); } -static int calc_var_mtrrs(struct memranges *addr_space, - int above4gb, int address_bits) +static void __calc_var_mtrrs(struct memranges *addr_space, + int above4gb, int address_bits, + int *num_def_wb_mtrrs, int *num_def_uc_mtrrs) { int wb_deftype_count; int uc_deftype_count; @@ -738,6 +739,28 @@ static int calc_var_mtrrs(struct memranges *addr_space, wb_deftype_count += var_state.mtrr_index; } } + *num_def_wb_mtrrs = wb_deftype_count; + *num_def_uc_mtrrs = uc_deftype_count; +} + +static int calc_var_mtrrs(struct memranges *addr_space, + int above4gb, int address_bits) +{ + int wb_deftype_count = 0; + int uc_deftype_count = 0; + + __calc_var_mtrrs(addr_space, above4gb, address_bits, &wb_deftype_count, + &uc_deftype_count); + + if (wb_deftype_count > bios_mtrrs && uc_deftype_count > bios_mtrrs) { + printk(BIOS_DEBUG, "MTRR: Removing WRCOMB type. " + "WB/UC MTRR counts: %d/%d > %d.\n", + wb_deftype_count, uc_deftype_count, bios_mtrrs); + memranges_update_tag(addr_space, MTRR_TYPE_WRCOMB, + MTRR_TYPE_UNCACHEABLE); + __calc_var_mtrrs(addr_space, above4gb, address_bits, + &wb_deftype_count, &uc_deftype_count); + } printk(BIOS_DEBUG, "MTRR: default type WB/UC MTRR counts: %d/%d.\n", wb_deftype_count, uc_deftype_count);

1 0

Patch set updated for coreboot: c85ba6c memranges: add memranges_update_tag() functionality
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5150 -gerrit commit c85ba6cf7a4074630b184d910a1a0980ef98f7ea Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 5 15:44:30 2014 -0600 memranges: add memranges_update_tag() functionality The memranges_update_tag() function replaces all instances that are tagged with old_tag and update to new_tag. This can be helpful in the MTRR code by adjusting the address space if certain memory types cause the MTRR usage to become too large. Change-Id: Ie5c405204de2fdd9fd1dd5d6190b223925d6d318 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/memrange.h | 4 ++++ src/lib/memrange.c | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/src/include/memrange.h b/src/include/memrange.h index 0e69b2f..4f094f5 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -110,6 +110,10 @@ void memranges_create_hole(struct memranges *ranges, void memranges_insert(struct memranges *ranges, resource_t base, resource_t size, unsigned long tag); +/* Update all entries with old_tag to new_tag. */ +void memranges_update_tag(struct memranges *ranges, unsigned long old_tag, + unsigned long new_tag); + /* Returns next entry after the provided entry. NULL if r is last. */ struct range_entry *memranges_next_entry(struct memranges *ranges, const struct range_entry *r); diff --git a/src/lib/memrange.c b/src/lib/memrange.c index af56e72..0ebac05 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -204,6 +204,19 @@ static void merge_add_memranges(struct memranges *ranges, merge_neighbor_entries(ranges); } +void memranges_update_tag(struct memranges *ranges, unsigned long old_tag, + unsigned long new_tag) +{ + struct range_entry *r; + + memranges_each_entry(r, ranges) { + if (range_entry_tag(r) == old_tag) + range_entry_update_tag(r, new_tag); + } + + merge_neighbor_entries(ranges); +} + typedef void (*range_action_t)(struct memranges *ranges, resource_t begin, resource_t end, unsigned long tag);

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Patch set updated for coreboot: 2303c2c MTRR: Mark all prefetchable resources as WRCOMB.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5149 -gerrit commit 2303c2ccad560215d0390f3d36be62d61741d76e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 23:25:28 2014 +0100 MTRR: Mark all prefetchable resources as WRCOMB. Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/Kconfig | 8 -------- src/cpu/x86/mtrr/mtrr.c | 5 ++--- src/include/device/resource.h | 1 - src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/link/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/rambi/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/haswell/gma.c | 19 +------------------ src/northbridge/intel/nehalem/gma.c | 3 --- src/northbridge/intel/sandybridge/gma.c | 19 +------------------ 13 files changed, 4 insertions(+), 58 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 0a21fcc..8854e6b 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -7,14 +7,6 @@ config X86_ARCH_OPTIONS select HAVE_ARCH_MEMCPY select HAVE_ARCH_MEMMOVE -config MARK_GRAPHICS_MEM_WRCOMB - bool "Mark graphics memory as write-combining." - default n - help - The graphics performance may increase if the graphics - memory is set as write-combining cache type. This option - enables marking the graphics memory as write-combining. - # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index cdaa791..dfb9c94 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -178,9 +178,8 @@ static struct memranges *get_physical_address_space(void) MTRR_TYPE_UNCACHEABLE); /* Handle any write combining resources. Only prefetchable - * resources with the IORESOURCE_WRCOMB flag are appropriate - * for this MTRR type. */ - match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; + * resources are appropriate for this MTRR type. */ + match = IORESOURCE_PREFETCH; mask |= match; memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 4bd9698..2d64c80 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,7 +21,6 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ -#define IORESOURCE_WRCOMB 0x00100000 /* Write combining resource. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */ diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 1d2b259..5247070 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM - select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index b372c47..d800206 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM - select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index d1e809e..efe9519 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT - select MARK_GRAPHICS_MEM_WRCOMB config MAINBOARD_DIR string diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 7a406e1..6cac476 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM - select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 4d149c9..292d321 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select CHROMEOS - select MARK_GRAPHICS_MEM_WRCOMB config MAINBOARD_DIR string diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 065830a..6980234 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM - select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 99ed53c..8e13108 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select CACHE_ROM - select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 00d7583..2ceffe4 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -429,29 +429,12 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void gma_read_resources(struct device *dev) -{ - pci_dev_read_resources(dev); - -#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB - struct resource *res; - - /* Set the graphics memory to write combining. */ - res = find_resource(dev, PCI_BASE_ADDRESS_2); - if (res == NULL) { - printk(BIOS_DEBUG, "gma: memory resource not found.\n"); - return; - } - res->flags |= IORESOURCE_WRCOMB; -#endif -} - static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = gma_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index c7a0e9b..2f13a6b 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -703,9 +703,6 @@ static void gma_read_resources(struct device *dev) 0xd0000001); pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); -#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB - res->flags |= IORESOURCE_WRCOMB; -#endif res->base = (resource_t) 0xd0000000; res->size = (resource_t) 0x10000000; } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 853139e..b9a07a2 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -664,29 +664,12 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void gma_read_resources(struct device *dev) -{ - pci_dev_read_resources(dev); - -#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB - struct resource *res; - - /* Set the graphics memory to write combining. */ - res = find_resource(dev, PCI_BASE_ADDRESS_2); - if (res == NULL) { - printk(BIOS_DEBUG, "gma: memory resource not found.\n"); - return; - } - res->flags |= IORESOURCE_WRCOMB; -#endif -} - static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = gma_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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coreboot-gerrit February 2014