coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 238c1d1 mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation
by Aaron Durbin 05 Feb '14

05 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5151 -gerrit commit 238c1d1d3b2dfadbe405fb9d2017893561cbd004 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 5 16:00:43 2014 -0600 mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation If the MTRR usage exceeds the BIOS allocation for MTRR usage re-try without the WRCOMB type. Change-Id: Ie70ce84994428ff6700c36310264c3c44d9ed128 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dbedf0f..cdaa791 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -661,8 +661,9 @@ static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, calc_var_mtrr_range(var_state, c1, c2 - c1, mtrr_type); } -static int calc_var_mtrrs(struct memranges *addr_space, - int above4gb, int address_bits) +static void __calc_var_mtrrs(struct memranges *addr_space, + int above4gb, int address_bits, + int *num_def_wb_mtrrs, int *num_def_uc_mtrrs) { int wb_deftype_count; int uc_deftype_count; @@ -738,6 +739,28 @@ static int calc_var_mtrrs(struct memranges *addr_space, wb_deftype_count += var_state.mtrr_index; } } + *num_def_wb_mtrrs = wb_deftype_count; + *num_def_uc_mtrrs = uc_deftype_count; +} + +static int calc_var_mtrrs(struct memranges *addr_space, + int above4gb, int address_bits) +{ + int wb_deftype_count = 0; + int uc_deftype_count = 0; + + __calc_var_mtrrs(addr_space, above4gb, address_bits, &wb_deftype_count, + &uc_deftype_count); + + if (wb_deftype_count > bios_mtrrs && uc_deftype_count > bios_mtrrs) { + printk(BIOS_DEBUG, "MTRR: Removing WRCOMB type. " + "WB/UC MTRR counts: %d/%d > %d.\n", + wb_deftype_count, uc_deftype_count, bios_mtrrs); + memranges_update_tag(addr_space, MTRR_TYPE_WRCOMB, + MTRR_TYPE_UNCACHEABLE); + __calc_var_mtrrs(addr_space, above4gb, address_bits, + &wb_deftype_count, &uc_deftype_count); + } printk(BIOS_DEBUG, "MTRR: default type WB/UC MTRR counts: %d/%d.\n", wb_deftype_count, uc_deftype_count);

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Patch merged into coreboot/master: 972091a load_payload: Use 32-bit accesses to speed up decompression.
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 972091a6a62387669739608d751c74306c26865e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 17:00:40 2014 +0100 load_payload: Use 32-bit accesses to speed up decompression. Flash prefers 32-bit sequential access. On some platforms ROM is not cached due to i.a. MTRR shortage. Moreover ROM caching is not currently enabled by default. With this patch payload decompression is sped up by theoretical factor of 4. Test on X201, with caching disabled: Before: 90:load payload 4,470,841 (24,505) 99:selfboot jump 6,073,812 (1,602,971) After: 90:load payload 4,530,979 (17,728) 99:selfboot jump 5,103,408 (572,429) Change-Id: Id17e61316dbbf73f4a837bf173f88bf26c01c62b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5144 for details. -gerrit

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New patch to review for coreboot: 66bf5a2 mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation
by Aaron Durbin 05 Feb '14

05 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5151 -gerrit commit 66bf5a20633489f138927a56fc4dc8de6f9a77ea Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 5 16:00:43 2014 -0600 mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation If the MTRR usage exceeds the BIOS allocation for MTRR usage re-try without the WRCOMB type. Change-Id: Ie70ce84994428ff6700c36310264c3c44d9ed128 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dbedf0f..af45f01 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -661,8 +661,9 @@ static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, calc_var_mtrr_range(var_state, c1, c2 - c1, mtrr_type); } -static int calc_var_mtrrs(struct memranges *addr_space, - int above4gb, int address_bits) +static void __calc_var_mtrrs(struct memranges *addr_space, + int above4gb, int address_bits, + int *num_def_wb_mtrrs, int *num_def_uc_mtrrs) { int wb_deftype_count; int uc_deftype_count; @@ -738,6 +739,27 @@ static int calc_var_mtrrs(struct memranges *addr_space, wb_deftype_count += var_state.mtrr_index; } } +} + +static int calc_var_mtrrs(struct memranges *addr_space, + int above4gb, int address_bits) +{ + int wb_deftype_count; + int uc_deftype_count; + + + __calc_var_mtrrs(addr_space, above4gb, address_bits, &wb_deftype_count, + &uc_deftype_count); + + if (wb_deftype_count > bios_mtrrs && uc_deftype_count > bios_mtrrs) { + printk(BIOS_DEBUG, "MTRR: Removing WRCOMB type. " + "WB/UC MTRR counts: %d/%d > %d.\n", + wb_deftype_count, uc_deftype_count, bios_mtrrs); + memranges_update_tag(addr_space, MTRR_TYPE_WRCOMB, + MTRR_TYPE_UNCACHEABLE); + __calc_var_mtrrs(addr_space, above4gb, address_bits, + &wb_deftype_count, &uc_deftype_count); + } printk(BIOS_DEBUG, "MTRR: default type WB/UC MTRR counts: %d/%d.\n", wb_deftype_count, uc_deftype_count);

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New patch to review for coreboot: cdf9c9b memranges: add memranges_update_tag() functionality
by Aaron Durbin 05 Feb '14

05 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5150 -gerrit commit cdf9c9b4c84f27207b10f6778e6df688b8deb9fe Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 5 15:44:30 2014 -0600 memranges: add memranges_update_tag() functionality The memranges_update_tag() function replaces all instances that are tagged with old_tag and update to new_tag. This can be helpful in the MTRR code by adjusting the address space if certain memory types cause the MTRR usage to become too large. Change-Id: Ie5c405204de2fdd9fd1dd5d6190b223925d6d318 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/memrange.h | 4 ++++ src/lib/memrange.c | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/src/include/memrange.h b/src/include/memrange.h index 0e69b2f..4f094f5 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -110,6 +110,10 @@ void memranges_create_hole(struct memranges *ranges, void memranges_insert(struct memranges *ranges, resource_t base, resource_t size, unsigned long tag); +/* Update all entries with old_tag to new_tag. */ +void memranges_update_tag(struct memranges *ranges, unsigned long old_tag, + unsigned long new_tag); + /* Returns next entry after the provided entry. NULL if r is last. */ struct range_entry *memranges_next_entry(struct memranges *ranges, const struct range_entry *r); diff --git a/src/lib/memrange.c b/src/lib/memrange.c index af56e72..0ebac05 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -204,6 +204,19 @@ static void merge_add_memranges(struct memranges *ranges, merge_neighbor_entries(ranges); } +void memranges_update_tag(struct memranges *ranges, unsigned long old_tag, + unsigned long new_tag) +{ + struct range_entry *r; + + memranges_each_entry(r, ranges) { + if (range_entry_tag(r) == old_tag) + range_entry_update_tag(r, new_tag); + } + + merge_neighbor_entries(ranges); +} + typedef void (*range_action_t)(struct memranges *ranges, resource_t begin, resource_t end, unsigned long tag);

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Patch set updated for coreboot: 6b8d1c0 NOTFORMERGE: MTRR: Mark all prefetchable resources as WRCOMB.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5149 -gerrit commit 6b8d1c0f9d6c44648f528fef584a0eb82dc61e76 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 22:21:26 2014 +0100 NOTFORMERGE: MTRR: Mark all prefetchable resources as WRCOMB. Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/x86/mtrr/mtrr.c | 7 +++---- src/include/device/resource.h | 1 - src/northbridge/intel/haswell/gma.c | 17 +---------------- src/northbridge/intel/nehalem/gma.c | 1 - src/northbridge/intel/sandybridge/gma.c | 17 +---------------- 5 files changed, 5 insertions(+), 38 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index ae49053..3b29150 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -181,10 +181,9 @@ static struct memranges *get_physical_address_space(int skip_wrcomb) MTRR_TYPE_UNCACHEABLE); /* Handle any write combining resources. Only prefetchable - * resources with the IORESOURCE_WRCOMB flag are appropriate - * for this MTRR type. */ + * resources are appropriate for this MTRR type. */ if (!skip_wrcomb) { - match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; + match = IORESOURCE_PREFETCH; mask |= match; memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); @@ -736,7 +735,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) mtrr_default_type = calc_var_mtrrs(addr_space, !!above4gb, address_bits, &need_mtrr); - } + } } disable_cache(); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 4bd9698..2d64c80 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,7 +21,6 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ -#define IORESOURCE_WRCOMB 0x00100000 /* Write combining resource. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f9387d5..2ceffe4 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -429,27 +429,12 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void gma_read_resources(struct device *dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - /* Set the graphics memory to write combining. */ - res = find_resource(dev, PCI_BASE_ADDRESS_2); - if (res == NULL) { - printk(BIOS_DEBUG, "gma: memory resource not found.\n"); - return; - } - res->flags |= IORESOURCE_WRCOMB; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = gma_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index f06e83f..2f13a6b 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -703,7 +703,6 @@ static void gma_read_resources(struct device *dev) 0xd0000001); pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); - res->flags |= IORESOURCE_WRCOMB; res->base = (resource_t) 0xd0000000; res->size = (resource_t) 0x10000000; } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 0d4eb11..b9a07a2 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -664,27 +664,12 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void gma_read_resources(struct device *dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - /* Set the graphics memory to write combining. */ - res = find_resource(dev, PCI_BASE_ADDRESS_2); - if (res == NULL) { - printk(BIOS_DEBUG, "gma: memory resource not found.\n"); - return; - } - res->flags |= IORESOURCE_WRCOMB; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = gma_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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New patch to review for coreboot: 22f1642 MTRR: Mark all prefetchable resources as WRCOMB.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5149 -gerrit commit 22f164214f37f8b2ad9f72ff98d134e049b03de2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 22:21:26 2014 +0100 MTRR: Mark all prefetchable resources as WRCOMB. Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/x86/mtrr/mtrr.c | 7 +++---- src/include/device/resource.h | 1 - src/northbridge/intel/haswell/gma.c | 17 +---------------- src/northbridge/intel/nehalem/gma.c | 1 - src/northbridge/intel/sandybridge/gma.c | 17 +---------------- 5 files changed, 5 insertions(+), 38 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index ae49053..3b29150 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -181,10 +181,9 @@ static struct memranges *get_physical_address_space(int skip_wrcomb) MTRR_TYPE_UNCACHEABLE); /* Handle any write combining resources. Only prefetchable - * resources with the IORESOURCE_WRCOMB flag are appropriate - * for this MTRR type. */ + * resources are appropriate for this MTRR type. */ if (!skip_wrcomb) { - match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; + match = IORESOURCE_PREFETCH; mask |= match; memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); @@ -736,7 +735,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) mtrr_default_type = calc_var_mtrrs(addr_space, !!above4gb, address_bits, &need_mtrr); - } + } } disable_cache(); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 4bd9698..2d64c80 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,7 +21,6 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ -#define IORESOURCE_WRCOMB 0x00100000 /* Write combining resource. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f9387d5..2ceffe4 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -429,27 +429,12 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void gma_read_resources(struct device *dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - /* Set the graphics memory to write combining. */ - res = find_resource(dev, PCI_BASE_ADDRESS_2); - if (res == NULL) { - printk(BIOS_DEBUG, "gma: memory resource not found.\n"); - return; - } - res->flags |= IORESOURCE_WRCOMB; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = gma_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index f06e83f..2f13a6b 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -703,7 +703,6 @@ static void gma_read_resources(struct device *dev) 0xd0000001); pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); - res->flags |= IORESOURCE_WRCOMB; res->base = (resource_t) 0xd0000000; res->size = (resource_t) 0x10000000; } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 0d4eb11..b9a07a2 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -664,27 +664,12 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void gma_read_resources(struct device *dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - /* Set the graphics memory to write combining. */ - res = find_resource(dev, PCI_BASE_ADDRESS_2); - if (res == NULL) { - printk(BIOS_DEBUG, "gma: memory resource not found.\n"); - return; - } - res->flags |= IORESOURCE_WRCOMB; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = gma_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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New patch to review for coreboot: 7e66ae0 NOTFORMERGE: MTRR: Automatically transform WRCOMB to UC if needed.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5148 -gerrit commit 7e66ae0ac9edb535b7d46be76c60074fcace4da8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 22:09:25 2014 +0100 NOTFORMERGE: MTRR: Automatically transform WRCOMB to UC if needed. Change-Id: Ic2a25c4ed91abbe062e755147d007d5b97c30571 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/x86/mtrr/mtrr.c | 40 ++++++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 54fdfd8..ae49053 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -154,19 +154,22 @@ static inline int range_entry_mtrr_type(struct range_entry *r) return range_entry_tag(r) & MTRR_TAG_MASK; } -static struct memranges *get_physical_address_space(void) +static struct memranges *get_physical_address_space(int skip_wrcomb) { static struct memranges *addr_space; static struct memranges addr_space_storage; + static int saved_skip_wrcomb = 0; /* In order to handle some chipsets not being able to pre-determine * uncacheable ranges, such as graphics memory, at resource insertion * time remove uncacheable regions from the cacheable ones. */ - if (addr_space == NULL) { + if (addr_space == NULL || skip_wrcomb != saved_skip_wrcomb) { struct range_entry *r; unsigned long mask; unsigned long match; + saved_skip_wrcomb = skip_wrcomb; + addr_space = &addr_space_storage; mask = IORESOURCE_CACHEABLE; @@ -180,10 +183,12 @@ static struct memranges *get_physical_address_space(void) /* Handle any write combining resources. Only prefetchable * resources with the IORESOURCE_WRCOMB flag are appropriate * for this MTRR type. */ - match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; - mask |= match; - memranges_add_resources(addr_space, mask, match, - MTRR_TYPE_WRCOMB); + if (!skip_wrcomb) { + match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; + mask |= match; + memranges_add_resources(addr_space, mask, match, + MTRR_TYPE_WRCOMB); + } /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations @@ -244,7 +249,7 @@ static void calc_fixed_mtrrs(void) if (fixed_mtrr_types_initialized) return; - phys_addr_space = get_physical_address_space(); + phys_addr_space = get_physical_address_space(0); /* Set all fixed ranges to uncacheable first. */ memset(&fixed_mtrr_types[0], MTRR_TYPE_UNCACHEABLE, NUM_FIXED_RANGES); @@ -586,7 +591,7 @@ static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, } static int calc_var_mtrrs(struct memranges *addr_space, - int above4gb, int address_bits) + int above4gb, int address_bits, int *need_mtrr) { int wb_deftype_count; int uc_deftype_count; @@ -668,9 +673,11 @@ static int calc_var_mtrrs(struct memranges *addr_space, if (wb_deftype_count < uc_deftype_count) { printk(BIOS_DEBUG, "MTRR: WB selected as default type.\n"); + *need_mtrr = wb_deftype_count; return MTRR_TYPE_WRBACK; } printk(BIOS_DEBUG, "MTRR: UC selected as default type.\n"); + *need_mtrr = uc_deftype_count; return MTRR_TYPE_UNCACHEABLE; } @@ -708,15 +715,28 @@ static void commit_var_mtrrs(struct memranges *addr_space, int def_type, void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) { static int mtrr_default_type = -1; + static int skip_wrcomb = 0; struct memranges *addr_space; - addr_space = get_physical_address_space(); + addr_space = get_physical_address_space(skip_wrcomb); if (mtrr_default_type == -1) { + int need_mtrr = 0; if (above4gb == 2) detect_var_mtrrs(); mtrr_default_type = - calc_var_mtrrs(addr_space, !!above4gb, address_bits); + calc_var_mtrrs(addr_space, !!above4gb, address_bits, + &need_mtrr); + /* Not enough MTRRs, make WRCOMB into UC. */ + if (need_mtrr > bios_mtrrs) { + printk(BIOS_ERR, "not enough MTRRs, degrading WRCOMB" + " to UC\n"); + skip_wrcomb = 1; + addr_space = get_physical_address_space(1); + mtrr_default_type = + calc_var_mtrrs(addr_space, !!above4gb, + address_bits, &need_mtrr); + } } disable_cache();

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New patch to review for coreboot: 252f844 nehalem, sandy, ivy, haswell: Hardwire MARK_GRAPHICS_MEM_WRCOMB to 1.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5147 -gerrit commit 252f844bcdf6d2aedb5872dffd646032d6f81788 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 21:35:17 2014 +0100 nehalem,sandy,ivy,haswell: Hardwire MARK_GRAPHICS_MEM_WRCOMB to 1. This config has effect only on mentioned northbridges. It should be enabled on all systems that work with it. board-status and tests on x201 and x230 indicate that this config works on all systems from the list (not tested on stout and ktqm77 but no reason for it not to work. Change-Id: I6ddff746b50b51a1fee0a1923c18b016861ab013 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/Kconfig | 8 -------- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/link/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/rambi/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/haswell/gma.c | 6 ++---- src/northbridge/intel/nehalem/gma.c | 2 -- src/northbridge/intel/sandybridge/gma.c | 6 ++---- 11 files changed, 4 insertions(+), 25 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 0a21fcc..8854e6b 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -7,14 +7,6 @@ config X86_ARCH_OPTIONS select HAVE_ARCH_MEMCPY select HAVE_ARCH_MEMMOVE -config MARK_GRAPHICS_MEM_WRCOMB - bool "Mark graphics memory as write-combining." - default n - help - The graphics performance may increase if the graphics - memory is set as write-combining cache type. This option - enables marking the graphics memory as write-combining. - # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 3004443..47d41ed 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 893c4e5..5d19ffc 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index d1e809e..efe9519 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT - select MARK_GRAPHICS_MEM_WRCOMB config MAINBOARD_DIR string diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 59fb8c0..f401feb 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 4d149c9..292d321 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select CHROMEOS - select MARK_GRAPHICS_MEM_WRCOMB config MAINBOARD_DIR string diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 3ffacde..ba6a6fe 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 7ff66ed..00ea604 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 00d7583..f9387d5 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -431,11 +431,10 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void gma_read_resources(struct device *dev) { - pci_dev_read_resources(dev); - -#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB struct resource *res; + pci_dev_read_resources(dev); + /* Set the graphics memory to write combining. */ res = find_resource(dev, PCI_BASE_ADDRESS_2); if (res == NULL) { @@ -443,7 +442,6 @@ static void gma_read_resources(struct device *dev) return; } res->flags |= IORESOURCE_WRCOMB; -#endif } static struct pci_operations gma_pci_ops = { diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index c7a0e9b..f06e83f 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -703,9 +703,7 @@ static void gma_read_resources(struct device *dev) 0xd0000001); pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); -#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB res->flags |= IORESOURCE_WRCOMB; -#endif res->base = (resource_t) 0xd0000000; res->size = (resource_t) 0x10000000; } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 853139e..0d4eb11 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -666,11 +666,10 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void gma_read_resources(struct device *dev) { - pci_dev_read_resources(dev); - -#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB struct resource *res; + pci_dev_read_resources(dev); + /* Set the graphics memory to write combining. */ res = find_resource(dev, PCI_BASE_ADDRESS_2); if (res == NULL) { @@ -678,7 +677,6 @@ static void gma_read_resources(struct device *dev) return; } res->flags |= IORESOURCE_WRCOMB; -#endif } static struct pci_operations gma_pci_ops = {

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Patch merged into coreboot/master: 9127a78 lenovo/x201: Enable flash prefetching.
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 9127a780c425f0cf42ef3ebc7ce575e5d3a666b7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:10:03 2014 +0100 lenovo/x201: Enable flash prefetching. Speeds up coreboot and especially payload load. Before: 90:load payload 4,530,979 (17,728) 99:selfboot jump 5,103,408 (572,429) After: 90:load payload 4,390,051 (14,849) 99:selfboot jump 4,505,966 (115,915) Change-Id: I45c3042594cda16ab3adde6472e00ec1b2d2a688 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5145 for details. -gerrit

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Patch set updated for coreboot: 3884a3e Remove CACHE_ROM.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146 -gerrit commit 3884a3ee7651bebe553dd66b3c146918b84c36b5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the improvements down in this patch stack, speed up by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs on all systems I tried it on, hence screwing up I/O access and cahce coherency in worst cases. Remove this as a buggy feature until we figure out how todo it properly if necessarry. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/haswell_init.c | 3 - src/cpu/intel/haswell/mp_init.c | 15 ----- src/cpu/x86/Kconfig | 7 --- src/cpu/x86/mtrr/mtrr.c | 76 ------------------------- src/include/cpu/x86/mtrr.h | 20 +------ src/lib/coreboot_table.c | 20 ------- src/mainboard/google/Kconfig | 5 -- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 4 -- src/northbridge/intel/nehalem/northbridge.c | 2 - src/northbridge/intel/sandybridge/northbridge.c | 2 - src/soc/intel/baytrail/Kconfig | 1 - 16 files changed, 2 insertions(+), 158 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index f8d295e..6e6428b 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -782,9 +782,6 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); - - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index 51130a5..0398360 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -143,14 +143,6 @@ void release_aps_for_smm_relocation(int do_parallel) printk(BIOS_DEBUG, "Timed out waiting for AP SMM relocation\n"); } -/* The mtrr code sets up ROM caching on the BSP, but not the others. However, - * the boot loader payload disables this. In order for Linux not to complain - * ensure the caching is disabled for the APs before going to sleep. */ -static void cleanup_rom_caching(void) -{ - x86_mtrr_disable_rom_caching(); -} - /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) @@ -184,13 +176,6 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_ptr); - /* The MTRR resources are core scoped. Therefore, there is no need - * to do the same work twice. Additionally, this check keeps the - * ROM cache enabled on the BSP since its hyperthread sibling won't - * call cleanup_rom_caching(). */ - if ((lapicid() & 1) == 0) - cleanup_rom_caching(); - /* FIXME(adurbin): park CPUs properly -- preferably somewhere in a * reserved part of memory that the OS cannot get to. */ stop_this_cpu(); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 21282c3..4425ed3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -76,13 +76,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool "Allow for caching system ROM." - default n - help - When selected a variable range MTRR is allocated for coreboot and - the bootloader enables caching of the system ROM for faster access. - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dbedf0f..54fdfd8 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -185,16 +185,6 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); -#if CONFIG_CACHE_ROM - /* Add a write-protect region covering the ROM size - * when CONFIG_CACHE_ROM is enabled. The ROM is assumed - * to be located at 4GiB - rom size. */ - resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); -#endif - /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -366,61 +356,6 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } -/* Keep track of the MTRR that covers the ROM for caching purposes. */ -#if CONFIG_CACHE_ROM -static long rom_cache_mtrr = -1; - -long x86_mtrr_rom_cache_var_index(void) -{ - return rom_cache_mtrr; -} - -void x86_mtrr_enable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - msr_val.lo |= MTRR_TYPE_WRPROT; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -void x86_mtrr_disable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -static void disable_cache_rom(void *unused) -{ - x86_mtrr_disable_rom_caching(); -} - -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), -}; -#endif - struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -468,17 +403,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; -#if CONFIG_CACHE_ROM - /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing - * one to turn on caching for faster ROM access. However, it is - * left to the MTRR callers to enable it. */ - if (mtrr_type == MTRR_TYPE_WRPROT) { - mtrr_type = MTRR_TYPE_UNCACHEABLE; - if (rom_cache_mtrr < 0) - rom_cache_mtrr = var_state->mtrr_index; - } -#endif - printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9414687..d6cf039 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,10 +52,6 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. - * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling - * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsibility of the caller to enable it by calling - * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -71,24 +67,12 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); -/* ROM caching can be used after variable MTRRs are set up. Beware that - * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on - * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that +/* ROM caching can be used after variable MTRRs are set up. + * Be sure to check the console log when adding WRCOMB resources. Beware that * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the * rom caching will be disabled if all threads run the MTRR code. Therefore, * one needs to call x86_mtrr_enable_rom_caching() after all threads of the * same core have run the MTRR code. */ -#if CONFIG_CACHE_ROM -void x86_mtrr_enable_rom_caching(void); -void x86_mtrr_disable_rom_caching(void); -/* Return the variable range MTRR index of the ROM cache. */ -long x86_mtrr_rom_cache_var_index(void); -#else -static inline void x86_mtrr_enable_rom_caching(void) {} -static inline void x86_mtrr_disable_rom_caching(void) {} -static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } -#endif /* CONFIG_CACHE_ROM */ #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14c..904185a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -235,24 +235,6 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ -static void lb_x86_rom_cache(struct lb_header *header) -{ -#if CONFIG_ARCH_X86 - long mtrr_index; - struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; - - mtrr_index = x86_mtrr_rom_cache_var_index(); - - if (mtrr_index < 0) - return; - - lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); - lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; - lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); - lb_x86_rom_mtrr->index = mtrr_index; -#endif -} - static void add_cbmem_pointers(struct lb_header *header) { /* @@ -529,8 +511,6 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - /* Communicate x86 variable MTRR ROM cache information. */ - lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index b86b0ad..85c8592 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -18,11 +18,6 @@ ## if VENDOR_GOOGLE -# Auto select common options -config VENDOR_SPECIFIC_OPTIONS - def_bool y - select CACHE_ROM - choice prompt "Mainboard model" diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 1d2b259..3004443 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index b372c47..893c4e5 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 7a406e1..59fb8c0 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 065830a..3ffacde 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 99ed53c..7ff66ed 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select CACHE_ROM select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5..ce366ef 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index f9386de..d94bc09 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -340,8 +340,6 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7db9301..5440140 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 613593e..d3311ef 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS - select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_MICROCODE_IN_CBFS

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coreboot-gerrit February 2014