coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: bd6fc05 asus/m2v-mx_se/romstage.c: Add time stamps for start and end of romstage
by Paul Menzel 06 Feb '14

06 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5154 -gerrit commit bd6fc056677de84f4674e5153af0affce7228486 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Feb 6 09:04:32 2014 +0100 asus/m2v-mx_se/romstage.c: Add time stamps for start and end of romstage Change-Id: I76ba6390f5fd3159ba6269e148941f0e4fc18e90 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/m2v-mx_se/romstage.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index ef0ce87..bd607b5 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -43,6 +43,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> +#include <timestamp.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) @@ -135,6 +136,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_INFO, "now booting... \n"); + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -187,4 +191,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); + + timestamp_add_now(TS_END_ROMSTAGE); }

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Patch set updated for coreboot: 1ceb56a cbfstool: Deserialize CBFS master header when reading image
by Alexandru Gagniuc 06 Feb '14

06 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5121 -gerrit commit 1ceb56af55fcc55187bffd62d2bd33b4f44601be Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Feb 5 01:10:08 2014 -0600 cbfstool: Deserialize CBFS master header when reading image Rather than using [hn]to[nh] whenever accessing a member of the CBFS header, deserialize the header when opening the CBFS image. The header is no longer a pointer inside the CBFS buffer, but a separate struct, a copy of the original header in a host-friendly format. This kills more of the ntohl usage. Change-Id: I5f8a5818b9d5a2d1152b1906249c4a5847d02bac Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/cbfs_image.c | 85 ++++++++++++++++++++++++++++++---------------- util/cbfstool/cbfs_image.h | 2 ++ util/cbfstool/cbfstool.c | 2 +- 3 files changed, 58 insertions(+), 31 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index dddd480..6ecffd1 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -113,7 +113,7 @@ static int cbfs_calculate_file_header_size(const char *name) align_up(strlen(name) + 1, CBFS_FILENAME_ALIGN)); } -static int cbfs_fix_legacy_size(struct cbfs_image *image) +static int cbfs_fix_legacy_size(struct cbfs_image *image, char *hdr_loc) { // A bug in old cbfstool may produce extra few bytes (by alignment) and // cause cbfstool to overwrite things after free space -- which is @@ -125,12 +125,11 @@ static int cbfs_fix_legacy_size(struct cbfs_image *image) entry = cbfs_find_next_entry(image, entry)) { last = entry; } - if ((char *)first < (char *)image->header && - (char *)entry > (char *)image->header) { + if ((char *)first < (char *)hdr_loc && + (char *)entry > (char *)hdr_loc) { WARN("CBFS image was created with old cbfstool with size bug. " "Fixing size in last entry...\n"); - last->len = htonl(ntohl(last->len) - - ntohl(image->header->align)); + last->len = htonl(ntohl(last->len) - image->header->align); DEBUG("Last entry has been changed from 0x%x to 0x%x.\n", cbfs_get_entry_addr(image, entry), cbfs_get_entry_addr(image, @@ -154,6 +153,23 @@ void cbfs_put_header(void *dest, const struct cbfs_header *header) xdr_be.put32(&outheader, header->offset); xdr_be.put32(&outheader, header->architecture); } + +void cbfs_get_header(struct cbfs_header *header, const void *src) +{ + struct buffer outheader; + + outheader.data = (void *)src; /* We're not modifying the data */ + outheader.size = 0; + + header->magic = xdr_be.get32(&outheader); + header->version = xdr_be.get32(&outheader); + header->romsize = xdr_be.get32(&outheader); + header->bootblocksize = xdr_be.get32(&outheader); + header->align = xdr_be.get32(&outheader); + header->offset = xdr_be.get32(&outheader); + header->architecture = xdr_be.get32(&outheader); +} + int cbfs_image_create(struct cbfs_image *image, uint32_t myarch, size_t size, @@ -167,6 +183,7 @@ int cbfs_image_create(struct cbfs_image *image, struct cbfs_file *entry; uint32_t cbfs_len; size_t entry_header_len; + void *header_loc; DEBUG("cbfs_image_create: bootblock=0x%x+0x%zx, " "header=0x%x+0x%zx, entries_offset=0x%x\n", @@ -175,7 +192,8 @@ int cbfs_image_create(struct cbfs_image *image, if (buffer_create(&image->buffer, size, "(new)") != 0) return -1; - image->header = NULL; + if ((image->header = malloc(sizeof(*image->header))) == NULL) + return -1; memset(image->buffer.data, CBFS_CONTENT_DEFAULT_VALUE, size); // Adjust legcay top-aligned address to ROM offset. @@ -214,15 +232,16 @@ int cbfs_image_create(struct cbfs_image *image, header_offset, sizeof(header), size); return -1; } - image->header = (struct cbfs_header *)(image->buffer.data + header_offset); - header.magic = CBFS_HEADER_MAGIC; - header.version = CBFS_HEADER_VERSION; - header.romsize = size; - header.bootblocksize = bootblock->size; - header.align = align; - header.offset = entries_offset; - header.architecture = myarch; - cbfs_put_header(image->header, &header); + image->header->magic = CBFS_HEADER_MAGIC; + image->header->version = CBFS_HEADER_VERSION; + image->header->romsize = size; + image->header->bootblocksize = bootblock->size; + image->header->align = align; + image->header->offset = entries_offset; + image->header->architecture = myarch; + + header_loc = (image->buffer.data + header_offset); + cbfs_put_header(header_loc, image->header); // Prepare entries if (align_up(entries_offset, align) != entries_offset) { @@ -252,18 +271,24 @@ int cbfs_image_create(struct cbfs_image *image, int cbfs_image_from_file(struct cbfs_image *image, const char *filename) { + void *header_loc; + if (buffer_from_file(&image->buffer, filename) != 0) return -1; DEBUG("read_cbfs_image: %s (%zd bytes)\n", image->buffer.name, image->buffer.size); - image->header = cbfs_find_header(image->buffer.data, - image->buffer.size); - if (!image->header) { + header_loc = cbfs_find_header(image->buffer.data, image->buffer.size); + if (!header_loc) { ERROR("%s does not have CBFS master header.\n", filename); cbfs_image_delete(image); return -1; } - cbfs_fix_legacy_size(image); + + if ((image->header = malloc(sizeof(*image->header))) == NULL) + return -1; + + cbfs_get_header(image->header, header_loc); + cbfs_fix_legacy_size(image, header_loc); return 0; } @@ -296,7 +321,7 @@ static int cbfs_add_entry_at(struct cbfs_image *image, uint32_t header_size = cbfs_calculate_file_header_size(name), min_entry_size = cbfs_calculate_file_header_size(""); uint32_t len, target; - uint32_t align = ntohl(image->header->align); + uint32_t align = image->header->align; target = content_offset - header_size; if (target % align) @@ -372,7 +397,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, if (IS_TOP_ALIGNED_ADDRESS(content_offset)) { // legacy cbfstool takes top-aligned address. - uint32_t theromsize = ntohl(image->header->romsize); + uint32_t theromsize = image->header->romsize; INFO("Converting top-aligned address 0x%x to offset: 0x%x\n", content_offset, content_offset + theromsize); content_offset += theromsize; @@ -546,10 +571,10 @@ int cbfs_print_header_info(struct cbfs_image *image) "alignment: %d bytes\n\n", basename(name), image->buffer.size / 1024, - ntohl(image->header->bootblocksize), - ntohl(image->header->romsize), - ntohl(image->header->offset), - ntohl(image->header->align)); + image->header->bootblocksize, + image->header->romsize, + image->header->offset, + image->header->align); free(name); return 0; } @@ -779,14 +804,14 @@ struct cbfs_file *cbfs_find_first_entry(struct cbfs_image *image) { assert(image && image->header); return (struct cbfs_file *)(image->buffer.data + - ntohl(image->header->offset)); + image->header->offset); } struct cbfs_file *cbfs_find_next_entry(struct cbfs_image *image, struct cbfs_file *entry) { uint32_t addr = cbfs_get_entry_addr(image, entry); - int align = ntohl(image->header->align); + int align = image->header->align; assert(entry && cbfs_is_valid_entry(image, entry)); addr += ntohl(entry->offset) + ntohl(entry->len); addr = align_up(addr, align); @@ -850,7 +875,7 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, /* Default values: allow fitting anywhere in ROM. */ if (!page_size) - page_size = ntohl(image->header->romsize); + page_size = image->header->romsize; if (!align) align = 1; @@ -858,9 +883,9 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, const char *name, ERROR("Input file size (%d) greater than page size (%d).\n", size, page_size); - if (page_size % ntohl(image->header->align)) + if (page_size % image->header->align) WARN("%s: Page size (%#x) not aligned with CBFS image (%#x).\n", - __func__, page_size, ntohl(image->header->align)); + __func__, page_size, image->header->align); /* TODO Old cbfstool always assume input is a stage file (and adding * sizeof(cbfs_stage) for header. We should fix that by adding "-t" diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 8ea4e47..0a05eb2 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -34,6 +34,8 @@ struct cbfs_image { /* Given a pointer, serialize the header from host-native byte format * to cbfs format, i.e. big-endian. */ void cbfs_put_header(void *dest, const struct cbfs_header *header); +/* Or deserialize into host-native format */ +void cbfs_get_header(struct cbfs_header *header, const void *src); /* Creates an empty CBFS image by given size, and description to its content * (bootblock, align, header location, starting offset of CBFS entries. diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 1d93981..792dd91 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -436,7 +436,7 @@ static int cbfs_locate(void) } if (param.top_aligned) - address = address - ntohl(image.header->romsize); + address = address - image.header->romsize; cbfs_image_delete(&image); printf("0x%x\n", address);

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Patch set updated for coreboot: feb7bd3 intel/bd82x6x: Allow limiting of SATA speed in CMOS config
by Alexandru Gagniuc 06 Feb '14

06 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4823 -gerrit commit feb7bd3fffa3e1ec3ab29640478696c0f71984dc Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Jan 26 11:36:07 2014 -0600 intel/bd82x6x: Allow limiting of SATA speed in CMOS config Up until now, the only way to limit SATA speed was via devicetree.cb, which required recompiling coreboot in order to lift this limit. However, there are cases where limiting is still desirable with the option to lift the limit later. To accommodate this, still check devicetree first, but if no hard limit is specified, then use CMOS to check if the user desires to limit the speed. google buterfly and stout are limited by default to Gen2 speeds due to issues with buggy SSD firmware. Change-Id: I0d6ac67416edcb28eb2a9091c86dc0a22d7b1d3f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/google/butterfly/cmos.default | 1 + src/mainboard/google/butterfly/cmos.layout | 7 ++++++- src/mainboard/google/link/cmos.layout | 7 ++++++- src/mainboard/google/parrot/cmos.layout | 7 ++++++- src/mainboard/google/stout/cmos.default | 1 + src/mainboard/google/stout/cmos.layout | 7 ++++++- src/mainboard/intel/emeraldlake2/cmos.layout | 7 ++++++- src/mainboard/kontron/ktqm77/cmos.layout | 7 ++++++- src/mainboard/lenovo/x230/cmos.default | 3 ++- src/mainboard/lenovo/x230/cmos.layout | 7 ++++++- src/mainboard/samsung/lumpy/cmos.layout | 7 ++++++- src/mainboard/samsung/stumpy/cmos.layout | 7 ++++++- src/southbridge/intel/bd82x6x/sata.c | 22 ++++++++++++++++++---- 13 files changed, 76 insertions(+), 14 deletions(-) diff --git a/src/mainboard/google/butterfly/cmos.default b/src/mainboard/google/butterfly/cmos.default index 77c7100..bc08ed9 100644 --- a/src/mainboard/google/butterfly/cmos.default +++ b/src/mainboard/google/butterfly/cmos.default @@ -4,3 +4,4 @@ debug_level = Spew nmi = Enable power_on_after_fail = Enable sata_mode = AHCI +sata_speed_limit = Gen2 diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index f0163f1..222d41b 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -88,7 +88,8 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused +412 2 e 9 sata_speed_limit +#414 2 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -137,6 +138,10 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +9 0 None +9 1 Gen1 +9 2 Gen2 +9 3 Gen3 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index b7320b5..b9a1178 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -86,7 +86,8 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused +412 2 e 9 sata_speed_limit +#414 2 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -134,6 +135,10 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +9 0 None +9 1 Gen1 +9 2 Gen2 +9 3 Gen3 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index b7320b5..b9a1178 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -86,7 +86,8 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused +412 2 e 9 sata_speed_limit +#414 2 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -134,6 +135,10 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +9 0 None +9 1 Gen1 +9 2 Gen2 +9 3 Gen3 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/cmos.default b/src/mainboard/google/stout/cmos.default index 77c7100..bc08ed9 100644 --- a/src/mainboard/google/stout/cmos.default +++ b/src/mainboard/google/stout/cmos.default @@ -4,3 +4,4 @@ debug_level = Spew nmi = Enable power_on_after_fail = Enable sata_mode = AHCI +sata_speed_limit = Gen2 diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index f0163f1..222d41b 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -88,7 +88,8 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused +412 2 e 9 sata_speed_limit +#414 2 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -137,6 +138,10 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +9 0 None +9 1 Gen1 +9 2 Gen2 +9 3 Gen3 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index b7320b5..b9a1178 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -86,7 +86,8 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused +412 2 e 9 sata_speed_limit +#414 2 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -134,6 +135,10 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +9 0 None +9 1 Gen1 +9 2 Gen2 +9 3 Gen3 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index dc6a44b..410b464 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -86,7 +86,8 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 11 sata_mode -#412 4 r 0 unused +412 2 e 12 sata_speed_limit +#414 2 r 0 unused # coreboot config options: additional mainboard options 416 4 e 10 systemp_type @@ -165,6 +166,10 @@ enumerations 10 4 LM75@9e 11 0 AHCI 11 1 Compatible +12 0 None +12 1 Gen1 +12 2 Gen2 +12 3 Gen3 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index 137f482..f8c5105 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -11,8 +11,9 @@ wwan=Enable wlan=Enable touchpad=Enable sata_mode=AHCI +sata_speed_limit=None fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable -backlight=Both \ No newline at end of file +backlight=Both diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 6f8822f..ad4bfb9 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -94,10 +94,11 @@ entries 416 1 e 1 trackpoint 417 1 e 1 fn_ctrl_swap 418 1 e 1 sticky_fn -#419 2 r 0 unused +419 2 e 11 sata_speed_limit 421 1 e 9 sata_mode 422 2 e 10 backlight + # coreboot config options: cpu 424 1 e 2 hyper_threading @@ -150,6 +151,10 @@ enumerations 10 1 Keyboard only 10 2 Thinklight only 10 3 None +11 0 None +11 1 Gen1 +11 2 Gen2 +11 3 Gen3 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 208e8ee..feff985 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -86,7 +86,8 @@ entries 408 1 e 1 nmi #409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused +412 2 e 9 sata_speed_limit +#414 2 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -134,6 +135,10 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +9 0 None +9 1 Gen1 +9 2 Gen2 +9 3 Gen3 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index ec393a5..27a35f4 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -85,7 +85,8 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused +412 2 e 9 sata_speed_limit +#414 2 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -134,6 +135,10 @@ enumerations 7 2 Keep 8 0 AHCI 8 1 Compatible +9 0 None +9 1 Gen1 +9 2 Gen2 +9 3 Gen3 # ----------------------------------------------------------------- checksums diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 8d12202..29be69e 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -46,7 +46,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; - u8 sata_mode; + u8 sata_mode, sata_limit; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -106,12 +106,26 @@ static void sata_init(struct device *dev) reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS - /* Set ISS, if available */ + /* Set ISS, if available + * Try devicetree.cb first, for hard limit, otherwise look in + * CMOS for user-selectable limit + */ if (config->sata_interface_speed_limit) { + printk(BIOS_INFO, "Applying hard limit on SATA speed"); + sata_limit = config->sata_interface_speed_limit; + } else { + /* Default to no limit if not configured in CMOS */ + if (get_option(&sata_limit, "sata_speed_limit") + != CB_SUCCESS) + sata_limit = 0; + } + sata_limit &= 0x03; + if (sata_limit) { + printk(BIOS_INFO, "Limiting SATA speed to Gen%d\n", + sata_limit); reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_limit & 0x03) - << 20; + reg32 |= sata_limit << 20; } write32(abar + 0x00, reg32); /* PI (Ports implemented) */

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Patch set updated for coreboot: 5422ffb google/stout: Sanitize cmos.layout
by Alexandru Gagniuc 06 Feb '14

06 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4821 -gerrit commit 5422ffb037c6654398babb26d617c907258239da Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Jan 26 11:18:27 2014 -0600 google/stout: Sanitize cmos.layout Remove 'baud_rate' and 'hyper_threading' for the same reason described in: * 74230c3 google/butterfly: Remove unused cmos.layout options Also add mrc_scrambler_seed_chk, for the same reason as in: * 655ac24 google/butterfly: Declare mrc_scrambler_seed_chk in cmos.layout Change-Id: I857d7a52917c6bbb62b53179f2b69d78bc297ea8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/google/stout/cmos.layout | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index b7320b5..f0163f1 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -74,12 +74,14 @@ entries # ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate +# No serial port on this motherboard +#392 3 e 5 baud_rate 395 4 e 6 debug_level #399 1 r 0 unused # coreboot config options: cpu -400 1 e 2 hyper_threading +# hyper_threading not supported by the Celeron 847 on this board +#400 1 e 2 hyper_threading #401 7 r 0 unused # coreboot config options: southbridge @@ -96,6 +98,7 @@ entries # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums 984 16 h 0 check_sum

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Patch set updated for coreboot: 664d9cb intel/bd82x6x: Rename SATA speed "support" register to "limit"
by Alexandru Gagniuc 06 Feb '14

06 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4777 -gerrit commit 664d9cbb39bc1fd1637ec3567f1665c371c3e80b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Jan 21 18:31:35 2014 -0600 intel/bd82x6x: Rename SATA speed "support" register to "limit" "sata_interface_speed_support" implies that we must tell coreboot, via devicetree.cb at what speed the SATA ports can operate. However, that is not necessary, and the actual use of this register is to limit the speed of all ports connected to the PCH. As such, use "sata_interface_speed_limit" as a better name. Change-Id: Icb07644d7bb044687b6b571bee6e2bde7f4cab85 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/google/butterfly/devicetree.cb | 2 +- src/mainboard/google/stout/devicetree.cb | 2 +- src/mainboard/kontron/ktqm77/devicetree.cb | 2 +- src/mainboard/lenovo/x230/devicetree.cb | 2 +- src/southbridge/intel/bd82x6x/chip.h | 16 +++++++++++----- src/southbridge/intel/bd82x6x/sata.c | 4 ++-- src/southbridge/intel/ibexpeak/sata.c | 4 ++-- 7 files changed, 19 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 9a7a1d5..36f3ba3 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -59,7 +59,7 @@ chip northbridge/intel/sandybridge # Enable SATA ports 0 & 1 register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s - register "sata_interface_speed_support" = "0x2" + register "sata_interface_speed_limit" = "0x2" # Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 653d3fe..e157035 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -59,7 +59,7 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s - register "sata_interface_speed_support" = "0x2" + register "sata_interface_speed_limit" = "0x2" # Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index f6390ac..c850609 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -39,7 +39,7 @@ chip northbridge/intel/sandybridge # Enable all SATA ports 0-5 register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s (should be the default, anyway) - register "sata_interface_speed_support" = "0x3" + register "sata_interface_speed_limit" = "0x3" # TODO: Enable generic LPC decodes... register "gen1_dec" = "0x001c02e1" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a76de5f..cd708a5 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) register "sata_port_map" = "0x7" # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" + register "sata_interface_speed_limit" = "0x3" register "gen1_dec" = "0x7c1601" register "gen2_dec" = "0x0c15e1" diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 0f2f0e9..c722da5 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -69,15 +69,21 @@ struct southbridge_intel_bd82x6x_config { uint32_t sata_port1_gen3_tx; /** - * SATA Interface Speed Support Configuration + * SATA Interface Speed Support Configuration (ISS) + * + * This option limits the maximum SATA link speed on all SATA ports. + * For systems with a mix of 6G and 3G ports, each port will operate up + * to its capability, but not any higher than the limit set here. This + * option should only be used if the SATA port cannot operate at its + * full speed due to hardware bugs, such as board mis-routing. * * Only the lower two bits have a meaning: * 00 - No effect (leave as chip default) - * 01 - 1.5 Gb/s maximum speed - * 10 - 3.0 Gb/s maximum speed - * 11 - 6.0 Gb/s maximum speed + * 01 - 1.5 Gb/s maximum speed (Gen 1) + * 10 - 3.0 Gb/s maximum speed (Gen 2) + * 11 - 6.0 Gb/s maximum speed (Gen 3) */ - uint8_t sata_interface_speed_support; + uint8_t sata_interface_speed_limit; uint32_t gen1_dec; uint32_t gen2_dec; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 133ebee..8d12202 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -107,10 +107,10 @@ static void sata_init(struct device *dev) reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS /* Set ISS, if available */ - if (config->sata_interface_speed_support) + if (config->sata_interface_speed_limit) { reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) + reg32 |= (config->sata_interface_speed_limit & 0x03) << 20; } write32(abar + 0x00, reg32); diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 078dc8e..2a6e454 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -110,9 +110,9 @@ static void sata_init(struct device *dev) reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS /* Set ISS, if available */ - if (config->sata_interface_speed_support) { + if (config->sata_interface_speed_limit) { reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) + reg32 |= (config->sata_interface_speed_limit & 0x03) << 20; } write32(abar + 0x00, reg32);

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Patch set updated for coreboot: e01bdb8 Revert "Butterfly, Stout: Force SATA link speed to 3 Gbps"
by Alexandru Gagniuc 06 Feb '14

06 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4762 -gerrit commit e01bdb85060d39651c56aa5e056de57d0201222d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Jan 20 22:26:05 2014 +0100 Revert "Butterfly, Stout: Force SATA link speed to 3 Gbps" This reverts commit 7b8952c19d8d809b7aeec629b31e1c3d66f19884. This commit was a hack to solve potential hangs caused by SSD bugs, but the workaround limited the SATA speed of all connected drives, despite the problem being localized to one specific model. As such, this solution is a layering violation, as it makes too many assumptions about the connected hardware. Since the SATA speed can now be limited by CMOS config, and is limited by default on butterfly and stout, the hard limit in devicetree.cb is of no further use. Change-Id: Ia35f7e8a24f9cb701ce0e357d9b3e929c4e0a4fb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/google/butterfly/devicetree.cb | 2 -- src/mainboard/google/stout/devicetree.cb | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 36f3ba3..c797fb0 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge # Enable SATA ports 0 & 1 register "sata_port_map" = "0x3" - # Set max SATA speed to 3.0 Gb/s - register "sata_interface_speed_limit" = "0x2" # Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index e157035..a9e499f 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge register "gpi6_routing" = "2" register "sata_port_map" = "0x3" - # Set max SATA speed to 3.0 Gb/s - register "sata_interface_speed_limit" = "0x2" # Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069"

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Patch set updated for coreboot: 1e4b87b util/xcompile/xcompile: improve userspace warnings
by Idwer Vollering 06 Feb '14

06 Feb '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5153 -gerrit commit 1e4b87b13d7f02222876e9f9462d1f0eb0588085 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Thu Feb 6 00:42:50 2014 +0000 util/xcompile/xcompile: improve userspace warnings Warn when the default installation directory for crossgcc (util/crossgcc/xgcc/bin/) is not found. Change-Id: I1f2a1d29f0d7117d1f80de4af1c24ecedcbea4da Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/xcompile/xcompile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index df7d558..d04f212 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -161,6 +161,10 @@ TCLIST_x86="i386 x86_64" TWIDTH_x86="32" XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} +if [ ! -d "$XGCCPATH" ]; then + printf "Warning: crossgcc seems to not have been built: can't find ${XGCCPATH}\n" >&2 +fi + # This loops over all supported architectures. for architecture in $SUPPORTED_ARCHITECTURE; do GCCPREFIX="invalid"

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New patch to review for coreboot: feb1a15 util/xcompile/xcompile: warn when crossgcc is not built
by Idwer Vollering 06 Feb '14

06 Feb '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5153 -gerrit commit feb1a150ad5b576cad4e76902f2f01ebd49db620 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Thu Feb 6 00:42:50 2014 +0000 util/xcompile/xcompile: warn when crossgcc is not built Warn when the default installation directory for crossgcc (util/crossgcc/xgcc/bin/) is not found. Change-Id: I1f2a1d29f0d7117d1f80de4af1c24ecedcbea4da Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/xcompile/xcompile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index df7d558..d04f212 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -161,6 +161,10 @@ TCLIST_x86="i386 x86_64" TWIDTH_x86="32" XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} +if [ ! -d "$XGCCPATH" ]; then + printf "Warning: crossgcc seems to not have been built: can't find ${XGCCPATH}\n" >&2 +fi + # This loops over all supported architectures. for architecture in $SUPPORTED_ARCHITECTURE; do GCCPREFIX="invalid"

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Patch set updated for coreboot: d59d1bd Kill ALT_CBFS_LOAD_PAYLOAD
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5132 -gerrit commit d59d1bd64417bd38a56667a1a71eeece23a9c3e3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:27:22 2014 +0100 Kill ALT_CBFS_LOAD_PAYLOAD Not used anymore. Change-Id: Icf3a4a7f932776981048b805478582ad2b784182 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 9 --------- src/lib/cbfs.c | 2 -- 2 files changed, 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 31a41ab..e6b237a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -47,15 +47,6 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. -config ALT_CBFS_LOAD_PAYLOAD - bool "Use alternative cbfs_load_payload() implementation." - default n - help - Either board or southbridge provide an alternative cbfs_load_payload() - implementation. This may be used, for example, if accessing the ROM - through memory-mapped I/O is slow and a faster alternative can be - provided. - choice prompt "Compiler to use" default COMPILER_GCC diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..30e7949 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -213,7 +213,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) } #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ -#if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) { struct cbfs_payload *payload; @@ -226,7 +225,6 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) media, name, CBFS_TYPE_PAYLOAD, NULL); return payload; } -#endif /* Simple buffer */

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Patch set updated for coreboot: b66e855 lynxpoint: Kill alternative cbfs_load_payload.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5131 -gerrit commit b66e8554bbad22be3e7257a43915d69184fe4ab7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:23:56 2014 +0100 lynxpoint: Kill alternative cbfs_load_payload. With generic load using 32-bit accesses this is no longer necessarry Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/lynxpoint/Kconfig | 1 - src/southbridge/intel/lynxpoint/Makefile.inc | 1 - src/southbridge/intel/lynxpoint/spi_loading.c | 90 --------------------------- 3 files changed, 92 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5ff00db..970a11d 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -32,7 +32,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH - select ALT_CBFS_LOAD_PAYLOAD config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 7be2d03..b691e6f 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -41,7 +41,6 @@ ramstage-y += me_status.c ramstage-y += reset.c ramstage-y += watchdog.c ramstage-y += acpi.c -ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += spi.c diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c deleted file mode 100644 index 57e3af8..0000000 --- a/src/southbridge/intel/lynxpoint/spi_loading.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 ChromeOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#if CONFIG_VBOOT_VERIFY_FIRMWARE -#include <vendorcode/google/chromeos/chromeos.h> -#else -static inline void *vboot_get_payload(size_t *len) { return NULL; } -#endif - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -} - -void *cbfs_load_payload(struct cbfs_media *media, const char *name) -{ - size_t file_len; - void *file_start; - - file_start = vboot_get_payload(&file_len); - - if (file_start != NULL) - return spi_mirror(file_start, file_len); - - file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len); - - if (file_start == NULL) - return NULL; - - return spi_mirror(file_start, file_len); -}

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coreboot-gerrit February 2014