coreboot-gerrit February 2014

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New patch to review for coreboot: 24a130d QEMU debugcon: Move under drivers/emulation/qemu
by Kyösti Mälkki 05 Feb '14

05 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5136 -gerrit commit 24a130d84250ff5b61d90bb486b0e7df57d00a80 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 2 19:12:14 2014 +0200 QEMU debugcon: Move under drivers/emulation/qemu Also prepare this console for use in romstage. Change-Id: I26a4d4b5db1e44a261396a21bb0f0574d72aa86d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/emulation/qemu/Makefile.inc | 3 +++ src/drivers/emulation/qemu/qemu_debugcon.c | 41 ++++++++++++++++++++++++++++++ src/include/console/qemu_debugcon.h | 7 +++++ 3 files changed, 51 insertions(+) diff --git a/src/drivers/emulation/qemu/Makefile.inc b/src/drivers/emulation/qemu/Makefile.inc index e7dc5ed..3351627 100644 --- a/src/drivers/emulation/qemu/Makefile.inc +++ b/src/drivers/emulation/qemu/Makefile.inc @@ -1,3 +1,6 @@ +romstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon.c +ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon.c + ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += bochs.c ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += cirrus.c ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += ../../pc80/vga/vga_io.c diff --git a/src/drivers/emulation/qemu/qemu_debugcon.c b/src/drivers/emulation/qemu/qemu_debugcon.c new file mode 100644 index 0000000..9c00585 --- /dev/null +++ b/src/drivers/emulation/qemu/qemu_debugcon.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Red Hat Inc. + * Written by Gerd Hoffmann <kraxel(a)redhat.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/qemu_debugcon.h> +#include <arch/io.h> +#include <arch/early_variables.h> + +static int qemu_debugcon_detected CAR_GLOBAL; + +void qemu_debugcon_init(void) +{ + int detected = (inb(CONFIG_CONSOLE_QEMU_DEBUGCON_PORT) == 0xe9); + car_set_var(qemu_debugcon_detected, detected); + printk(BIOS_INFO, "QEMU debugcon %s [port 0x%x]\n", + detected ? "detected" : "not found", + CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); +} + +void qemu_debugcon_tx_byte(unsigned char data) +{ + if (car_get_var(qemu_debugcon_detected) != 0) + outb(data, CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); +} diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h new file mode 100644 index 0000000..63b1455 --- /dev/null +++ b/src/include/console/qemu_debugcon.h @@ -0,0 +1,7 @@ +#ifndef _QEMU_DEBUGCON_H_ +#define _QEMU_DEBUGCON_H_ + +void qemu_debugcon_init(void); +void qemu_debugcon_tx_byte(unsigned char data); + +#endif

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New patch to review for coreboot: 56e9caf ne2k: Move under drivers/net
by Kyösti Mälkki 05 Feb '14

05 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5135 -gerrit commit 56e9caf5f1b4a6a469ac396e45bf1d2c1c3fe85f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 31 07:38:21 2014 +0200 ne2k: Move under drivers/net Change-Id: I978b6009c09c31be4429f57be40ef82f438f7574 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 2 +- src/drivers/Makefile.inc | 1 + src/drivers/net/Makefile.inc | 2 + src/drivers/net/ne2k.c | 458 +++++++++++++++++++++++++++++++++++++++ src/drivers/net/ns8390.h | 110 ++++++++++ src/lib/Makefile.inc | 3 - src/lib/ne2k.c | 458 --------------------------------------- src/lib/ns8390.h | 110 ---------- 8 files changed, 572 insertions(+), 572 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 13ee1f0..db84f9e 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -35,7 +35,7 @@ #include "lib/uart8250.c" #endif #if CONFIG_CONSOLE_NE2K -#include "lib/ne2k.c" +#include "drivers/net/ne2k.c" #endif static void __console_tx_byte(unsigned char byte) diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 4b63a8f..eb86a4c 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -24,6 +24,7 @@ subdirs-y += generic subdirs-y += i2c subdirs-y += intel subdirs-y += maxim +subdirs-y += net subdirs-y += oxford subdirs-y += parade subdirs-y += realtek diff --git a/src/drivers/net/Makefile.inc b/src/drivers/net/Makefile.inc new file mode 100644 index 0000000..9b3008d --- /dev/null +++ b/src/drivers/net/Makefile.inc @@ -0,0 +1,2 @@ +romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c +ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c new file mode 100644 index 0000000..b678d79 --- /dev/null +++ b/src/drivers/net/ne2k.c @@ -0,0 +1,458 @@ +/* +ETHERBOOT - BOOTP/TFTP Bootstrap Program + +Author: Martin Renters + Date: May/94 + + This code is based heavily on David Greenman's if_ed.c driver + + Copyright (C) 1993-1994, David Greenman, Martin Renters. + This software may be used, modified, copied, distributed, and sold, in + both source and binary form provided that the above copyright and these + terms are retained. Under no circumstances are the authors responsible for + the proper functioning of this software, nor do the authors assume any + responsibility for damages incurred with its use. + +Multicast support added by Timothy Legge (timlegge(a)users.sourceforge.net) 09/28/2003 +Relocation support added by Ken Yap (ken_yap(a)users.sourceforge.net) 28/12/02 +3c503 support added by Bill Paul (wpaul(a)ctr.columbia.edu) on 11/15/94 +SMC8416 support added by Bill Paul (wpaul(a)ctr.columbia.edu) on 12/25/94 +3c503 PIO support added by Jim Hague (jim.hague(a)acm.org) on 2/17/98 +RX overrun by Klaus Espenlaub (espenlaub(a)informatik.uni-ulm.de) on 3/10/99 + parts taken from the Linux 8390 driver (by Donald Becker and Paul Gortmaker) +SMC8416 PIO support added by Andrew Bettison (andrewb(a)zip.com.au) on 4/3/02 + based on the Linux 8390 driver (by Donald Becker and Paul Gortmaker) + +(C) Rudolf Marek <r.marek(a)assembler.cz> Simplify for RTL8029, Add coreboot glue logic + +*/ + +#define ETH_ALEN 6 /* Size of Ethernet address */ +#define ETH_HLEN 14 /* Size of ethernet header */ +#define ETH_ZLEN 60 /* Minimum packet */ +#define ETH_FRAME_LEN 1514 /* Maximum packet */ +#define ETH_DATA_ALIGN 2 /* Amount needed to align the data after an ethernet header */ +#define ETH_MAX_MTU (ETH_FRAME_LEN-ETH_HLEN) + +#include "ns8390.h" +#include <ip_checksum.h> +#include <console/ne2k.h> +#include <arch/io.h> + +#define MEM_SIZE MEM_32768 +#define TX_START 64 +#define RX_START (64 + D8390_TXBUF_SIZE) + +static unsigned int get_count(unsigned int eth_nic_base) +{ + unsigned int ret; + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, + eth_nic_base + D8390_P0_COMMAND); + + ret = inb(eth_nic_base + 8 + 0) | (inb(eth_nic_base + 8 + 1) << 8); + + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, + eth_nic_base + D8390_P0_COMMAND); + return ret; +} + +static void set_count(unsigned int eth_nic_base, unsigned int what) +{ + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, + eth_nic_base + D8390_P0_COMMAND); + + outb(what & 0xff,eth_nic_base + 8); + outb((what >> 8) & 0xff,eth_nic_base + 8 + 1); + + outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, + eth_nic_base + D8390_P0_COMMAND); +} + +static void eth_pio_write(unsigned char *src, unsigned int dst, unsigned int cnt, + unsigned int eth_nic_base) +{ + outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR); + outb(cnt, eth_nic_base + D8390_P0_RBCR0); + outb(cnt >> 8, eth_nic_base + D8390_P0_RBCR1); + outb(dst, eth_nic_base + D8390_P0_RSAR0); + outb(dst >> 8, eth_nic_base + D8390_P0_RSAR1); + outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + + while (cnt--) { + outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA); + } + /* + #warning "Add timeout" + */ + /* wait for operation finish */ + while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) != D8390_ISR_RDC) + ; +} + +void ne2k_append_data(unsigned char *d, int len, unsigned int base) +{ + eth_pio_write(d, (TX_START << 8) + 42 + get_count(base), len, base); + set_count(base, get_count(base)+len); +} + +#ifdef __ROMCC__ + +void eth_pio_write_byte(int data, unsigned short dst, unsigned int eth_nic_base) +{ + outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR); + outb(1, eth_nic_base + D8390_P0_RBCR0); + outb(0, eth_nic_base + D8390_P0_RBCR1); + outb(dst, eth_nic_base + D8390_P0_RSAR0); + outb(dst >> 8, eth_nic_base + D8390_P0_RSAR1); + outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(data, eth_nic_base + NE_ASIC_OFFSET + NE_DATA); + + while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) != D8390_ISR_RDC) + ; +} + +void ne2k_append_data_byte(int d, unsigned int base) +{ + eth_pio_write_byte(d, (TX_START << 8) + 42 + get_count(base), base); + set_count(base, get_count(base)+1); +} + +static unsigned char eth_pio_read_byte(unsigned int src, + unsigned int eth_nic_base) +{ + outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + outb(0, eth_nic_base + D8390_P0_RBCR0); + outb(1, eth_nic_base + D8390_P0_RBCR1); + outb(src, eth_nic_base + D8390_P0_RSAR0); + outb(src >> 8, eth_nic_base + D8390_P0_RSAR1); + outb(D8390_COMMAND_RD0 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + return inb(eth_nic_base + NE_ASIC_OFFSET + NE_DATA); +} + + +/* Variation of compute_ip_checksum which works on SRAM */ +unsigned long compute_ip_checksum_from_sram(unsigned short offset, unsigned short length, + unsigned int eth_nic_base) +{ + unsigned long sum; + unsigned long i; + /* In the most straight forward way possible, + * compute an ip style checksum. + */ + sum = 0; + for(i = 0; i < length; i++) { + unsigned long v; + v = eth_pio_read_byte((TX_START << 8)+i+offset, eth_nic_base); + if (i & 1) { + v <<= 8; + } + /* Add the new value */ + sum += v; + /* Wrap around the carry */ + if (sum > 0xFFFF) { + sum = (sum + (sum >> 16)) & 0xFFFF; + } + } + return (~((sum & 0xff) | (((sum >> 8) & 0xff) << 8) )) & 0xffff; +} + + +static void str2ip_load(const char *str, unsigned short offset, unsigned int eth_nic_base) +#else +static void str2ip(const char *str, unsigned char *ip) +#endif +{ + unsigned char c, i = 0; + int acc = 0; + + do { + c = str[i]; + if ((c >= '0') && (c <= '9')) { + acc *= 10; + acc += (c - '0'); + } else { +#ifdef __ROMCC__ + eth_pio_write_byte(acc, (TX_START << 8)+offset, eth_nic_base); + offset++; +#else + *ip++ = acc; +#endif + acc = 0; + } + i++; + } while (c != '\0'); +} + +#ifdef __ROMCC__ +static void str2mac_load(const char *str, unsigned short offset, unsigned int eth_nic_base) +#else +static void str2mac(const char *str, unsigned char *mac) +#endif +{ + unsigned char c, i = 0; + int acc = 0; + + do { + + c = str[i]; + if ((c >= '0') && (c <= '9')) { + acc *= 16; + acc += (c - '0'); + } else if ((c >= 'a') && (c <= 'f')) { + acc *= 16; + acc += ((c - 'a') + 10) ; + } else if ((c >= 'A') && (c <= 'F')) { + acc *= 16; + acc += ((c - 'A') + 10) ; + } else { +#ifdef __ROMCC__ + eth_pio_write_byte(acc, ((TX_START << 8)+offset), eth_nic_base); + offset++; +#else + *mac++ = acc; +#endif + acc = 0; + } + + i++; + } while (c != '\0'); +} + + +#ifndef __ROMCC__ +static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen) { + unsigned short chksum; + unsigned char hdr[] = { +#else +static const unsigned char hdr[] = { +#endif + /* + * ETHERNET HDR + */ + + // destination macaddr + 0x02, 0x00, 0x00, 0x00, 0x00, 0x01, + /* source mac */ + 0x02, 0x00, 0x00, 0xC0, 0xFF, 0xEE, + /* ethtype (IP) */ + 0x08, 0x00, + /* + * IP HDR + */ + 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, + /* TTL, proto (UDP), chksum_hi, chksum_lo, IP0, IP1, IP2, IP3, */ + 0x40, 0x11, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x1, + /* IP0, IP1, IP2, IP3 */ + 0xff, 0xff, 0xff, 0xff, + /* + * UDP HDR + */ + /* SRC PORT DST PORT (2bytes each), ulen, uchksum (must be zero or correct */ + 0x1a, 0x0b, 0x1a, 0x0a, 0x00, 0x9, 0x00, 0x00, + }; + +#ifndef __ROMCC__ + str2mac(CONFIG_CONSOLE_NE2K_DST_MAC, &hdr[0]); + str2ip(CONFIG_CONSOLE_NE2K_DST_IP, &hdr[30]); + str2ip(CONFIG_CONSOLE_NE2K_SRC_IP, &hdr[26]); + + /* zero checksum */ + hdr[24] = 0; + hdr[25] = 0; + + /* update IP packet len */ + hdr[16] = ((28 + pktlen) >> 8) & 0xff; + hdr[17] = (28 + pktlen) & 0xff; + + /* update UDP len */ + hdr[38] = (8 + pktlen) >> 8; + hdr[39] = 8 + pktlen; + + chksum = compute_ip_checksum(&hdr[14], 20); + + hdr[25] = chksum >> 8; + hdr[24] = chksum; + eth_pio_write(hdr, (TX_START << 8), sizeof(hdr), eth_nic_base); +} + + +#else + +/* ROMCC madness */ +static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen) +{ + unsigned short chksum; + + eth_pio_write(hdr, (TX_START << 8), sizeof(hdr), eth_nic_base); + + str2mac_load(CONFIG_CONSOLE_NE2K_DST_MAC, 0, eth_nic_base); + + str2ip_load(CONFIG_CONSOLE_NE2K_DST_IP, 30, eth_nic_base); + str2ip_load(CONFIG_CONSOLE_NE2K_SRC_IP, 26, eth_nic_base); + /* zero checksum */ + eth_pio_write_byte(0, (TX_START << 8)+24, eth_nic_base); + eth_pio_write_byte(0, (TX_START << 8)+25, eth_nic_base); + + /* update IP packet len */ + eth_pio_write_byte(((28 + pktlen) >> 8) & 0xff, (TX_START << 8)+16, eth_nic_base); + eth_pio_write_byte( (28 + pktlen) & 0xff, (TX_START << 8)+17, eth_nic_base); + + /* update UDP len */ + eth_pio_write_byte((8 + pktlen) >> 8, (TX_START << 8)+38, eth_nic_base); + eth_pio_write_byte( 8 + pktlen, (TX_START << 8)+39, eth_nic_base); + + chksum = compute_ip_checksum_from_sram(14, 20, eth_nic_base); + + eth_pio_write_byte(chksum, (TX_START << 8)+24, eth_nic_base); + eth_pio_write_byte(chksum >> 8, (TX_START << 8)+25, eth_nic_base); +} + +#endif + +void ne2k_transmit(unsigned int eth_nic_base) { + unsigned int pktsize; + unsigned int len = get_count(eth_nic_base); + + // so place whole header inside chip buffer + ns8390_tx_header(eth_nic_base, len); + + // commit sending now + outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + + outb(TX_START, eth_nic_base + D8390_P0_TPSR); + + pktsize = 42 + len; + if (pktsize < 64) + pktsize = 64; + + outb(pktsize, eth_nic_base + D8390_P0_TBCR0); + outb(pktsize >> 8, eth_nic_base + D8390_P0_TBCR1); + + outb(D8390_ISR_PTX, eth_nic_base + D8390_P0_ISR); + + outb(D8390_COMMAND_PS0 | D8390_COMMAND_TXP | D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); + + /* wait for operation finish */ + while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_PTX) != D8390_ISR_PTX) ; + + set_count(eth_nic_base, 0); +} + +#ifdef __PRE_RAM__ + +static void ns8390_reset(unsigned int eth_nic_base) +{ + int i; + + outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | + D8390_COMMAND_STP, eth_nic_base + D8390_P0_COMMAND); + + outb(0x48, eth_nic_base + D8390_P0_DCR); + outb(0, eth_nic_base + D8390_P0_RBCR0); + outb(0, eth_nic_base + D8390_P0_RBCR1); + outb(0x20, eth_nic_base + D8390_P0_RCR); + outb(2, eth_nic_base + D8390_P0_TCR); + outb(TX_START, eth_nic_base + D8390_P0_TPSR); + outb(RX_START, eth_nic_base + D8390_P0_PSTART); + outb(MEM_SIZE, eth_nic_base + D8390_P0_PSTOP); + outb(MEM_SIZE - 1, eth_nic_base + D8390_P0_BOUND); + outb(0xFF, eth_nic_base + D8390_P0_ISR); + outb(0, eth_nic_base + D8390_P0_IMR); + + outb(D8390_COMMAND_PS1 | + D8390_COMMAND_RD2 | D8390_COMMAND_STP, + eth_nic_base + D8390_P0_COMMAND); + + for (i = 0; i < ETH_ALEN; i++) + outb(0x0C, eth_nic_base + D8390_P1_PAR0 + i); + + for (i = 0; i < ETH_ALEN; i++) + outb(0xFF, eth_nic_base + D8390_P1_MAR0 + i); + + outb(RX_START, eth_nic_base + D8390_P1_CURR); + outb(D8390_COMMAND_PS0 | + D8390_COMMAND_RD2 | D8390_COMMAND_STA, + eth_nic_base + D8390_P0_COMMAND); + outb(0xFF, eth_nic_base + D8390_P0_ISR); + outb(0, eth_nic_base + D8390_P0_TCR); + outb(4, eth_nic_base + D8390_P0_RCR); + set_count(eth_nic_base, 0); +} + + +int ne2k_init(unsigned int eth_nic_base) { + + device_t dev; + unsigned char c; + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(0x10ec, + 0x8029), 0); + + if (dev == PCI_DEV_INVALID) + return 0; + + pci_write_config32(dev, 0x10, eth_nic_base | 1 ); + pci_write_config8(dev, 0x4, 0x1); + + c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET); + outb(c, eth_nic_base + NE_ASIC_OFFSET + NE_RESET); + + (void) inb(0x84); + + outb(D8390_COMMAND_STP | D8390_COMMAND_RD2, eth_nic_base + D8390_P0_COMMAND); + outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR); + + outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR); + outb(MEM_8192, eth_nic_base + D8390_P0_PSTART); + outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP); + + ns8390_reset(eth_nic_base); + return 1; +} + +#else + +#include <delay.h> +#include <stdlib.h> +#include <string.h> +#include <arch/io.h> + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + +static void read_resources(struct device *dev) +{ + struct resource *res; + + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = CONFIG_CONSOLE_NE2K_IO_PORT; + res->size = 32; + res->align = 5; + res->gran = 5; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; + return; +} + +static struct device_operations ne2k_ops = { + .read_resources = read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, +}; + +static const struct pci_driver ne2k_driver __pci_driver = { + .ops = &ne2k_ops, + .vendor = 0x10ec, + .device = 0x8029, +}; + +#endif diff --git a/src/drivers/net/ns8390.h b/src/drivers/net/ns8390.h new file mode 100644 index 0000000..eeffe45 --- /dev/null +++ b/src/drivers/net/ns8390.h @@ -0,0 +1,110 @@ +/************************************************************************** +ETHERBOOT - BOOTP/TFTP Bootstrap Program + +Author: Martin Renters + Date: Jun/94 + +**************************************************************************/ + +//FILE_LICENCE ( BSD2 ); + +#define VENDOR_NONE 0 +#define VENDOR_WD 1 +#define VENDOR_NOVELL 2 +#define VENDOR_3COM 3 + +#define FLAG_PIO 0x01 +#define FLAG_16BIT 0x02 +#define FLAG_790 0x04 + +#define MEM_8192 32 +#define MEM_16384 64 +#define MEM_32768 128 + +#define ISA_MAX_ADDR 0x400 + +/************************************************************************** +NE1000/2000 definitions +**************************************************************************/ +#define NE_ASIC_OFFSET 0x10 +#define NE_RESET 0x0F /* Used to reset card */ +#define NE_DATA 0x00 /* Used to read/write NIC mem */ + +#define COMPEX_RL2000_TRIES 200 + +/************************************************************************** +8390 Register Definitions +**************************************************************************/ +#define D8390_P0_COMMAND 0x00 +#define D8390_P0_PSTART 0x01 +#define D8390_P0_PSTOP 0x02 +#define D8390_P0_BOUND 0x03 +#define D8390_P0_TSR 0x04 +#define D8390_P0_TPSR 0x04 +#define D8390_P0_TBCR0 0x05 +#define D8390_P0_TBCR1 0x06 +#define D8390_P0_ISR 0x07 +#define D8390_P0_RSAR0 0x08 +#define D8390_P0_RSAR1 0x09 +#define D8390_P0_RBCR0 0x0A +#define D8390_P0_RBCR1 0x0B +#define D8390_P0_RSR 0x0C +#define D8390_P0_RCR 0x0C +#define D8390_P0_TCR 0x0D +#define D8390_P0_DCR 0x0E +#define D8390_P0_IMR 0x0F +#define D8390_P1_COMMAND 0x00 +#define D8390_P1_PAR0 0x01 +#define D8390_P1_PAR1 0x02 +#define D8390_P1_PAR2 0x03 +#define D8390_P1_PAR3 0x04 +#define D8390_P1_PAR4 0x05 +#define D8390_P1_PAR5 0x06 +#define D8390_P1_CURR 0x07 +#define D8390_P1_MAR0 0x08 + +#define D8390_COMMAND_PS0 0x0 /* Page 0 select */ +#define D8390_COMMAND_PS1 0x40 /* Page 1 select */ +#define D8390_COMMAND_PS2 0x80 /* Page 2 select */ +#define D8390_COMMAND_RD2 0x20 /* Remote DMA control */ +#define D8390_COMMAND_RD1 0x10 +#define D8390_COMMAND_RD0 0x08 +#define D8390_COMMAND_TXP 0x04 /* transmit packet */ +#define D8390_COMMAND_STA 0x02 /* start */ +#define D8390_COMMAND_STP 0x01 /* stop */ + +#define D8390_RCR_MON 0x20 /* monitor mode */ + +#define D8390_DCR_FT1 0x40 +#define D8390_DCR_LS 0x08 /* Loopback select */ +#define D8390_DCR_WTS 0x01 /* Word transfer select */ + +#define D8390_ISR_PRX 0x01 /* successful recv */ +#define D8390_ISR_PTX 0x02 /* successful xmit */ +#define D8390_ISR_RXE 0x04 /* receive error */ +#define D8390_ISR_TXE 0x08 /* transmit error */ +#define D8390_ISR_OVW 0x10 /* Overflow */ +#define D8390_ISR_CNT 0x20 /* Counter overflow */ +#define D8390_ISR_RDC 0x40 /* Remote DMA complete */ +#define D8390_ISR_RST 0x80 /* reset */ + +#define D8390_RSTAT_PRX 0x01 /* successful recv */ +#define D8390_RSTAT_CRC 0x02 /* CRC error */ +#define D8390_RSTAT_FAE 0x04 /* Frame alignment error */ +#define D8390_RSTAT_OVER 0x08 /* FIFO overrun */ + +#define D8390_TXBUF_SIZE 6 +#define D8390_RXBUF_END 32 +#define D8390_PAGE_SIZE 256 + +struct ringbuffer { + unsigned char status; + unsigned char next; + unsigned short len; +}; +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ + diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 3bad3fd..79ceebf 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -47,7 +47,6 @@ romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c -romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -113,8 +112,6 @@ ramstage-y += cbmem_info.c ramstage-y += hexdump.c romstage-y += hexdump.c -ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c - romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) diff --git a/src/lib/ne2k.c b/src/lib/ne2k.c deleted file mode 100644 index b678d79..0000000 --- a/src/lib/ne2k.c +++ /dev/null @@ -1,458 +0,0 @@ -/* -ETHERBOOT - BOOTP/TFTP Bootstrap Program - -Author: Martin Renters - Date: May/94 - - This code is based heavily on David Greenman's if_ed.c driver - - Copyright (C) 1993-1994, David Greenman, Martin Renters. - This software may be used, modified, copied, distributed, and sold, in - both source and binary form provided that the above copyright and these - terms are retained. Under no circumstances are the authors responsible for - the proper functioning of this software, nor do the authors assume any - responsibility for damages incurred with its use. - -Multicast support added by Timothy Legge (timlegge(a)users.sourceforge.net) 09/28/2003 -Relocation support added by Ken Yap (ken_yap(a)users.sourceforge.net) 28/12/02 -3c503 support added by Bill Paul (wpaul(a)ctr.columbia.edu) on 11/15/94 -SMC8416 support added by Bill Paul (wpaul(a)ctr.columbia.edu) on 12/25/94 -3c503 PIO support added by Jim Hague (jim.hague(a)acm.org) on 2/17/98 -RX overrun by Klaus Espenlaub (espenlaub(a)informatik.uni-ulm.de) on 3/10/99 - parts taken from the Linux 8390 driver (by Donald Becker and Paul Gortmaker) -SMC8416 PIO support added by Andrew Bettison (andrewb(a)zip.com.au) on 4/3/02 - based on the Linux 8390 driver (by Donald Becker and Paul Gortmaker) - -(C) Rudolf Marek <r.marek(a)assembler.cz> Simplify for RTL8029, Add coreboot glue logic - -*/ - -#define ETH_ALEN 6 /* Size of Ethernet address */ -#define ETH_HLEN 14 /* Size of ethernet header */ -#define ETH_ZLEN 60 /* Minimum packet */ -#define ETH_FRAME_LEN 1514 /* Maximum packet */ -#define ETH_DATA_ALIGN 2 /* Amount needed to align the data after an ethernet header */ -#define ETH_MAX_MTU (ETH_FRAME_LEN-ETH_HLEN) - -#include "ns8390.h" -#include <ip_checksum.h> -#include <console/ne2k.h> -#include <arch/io.h> - -#define MEM_SIZE MEM_32768 -#define TX_START 64 -#define RX_START (64 + D8390_TXBUF_SIZE) - -static unsigned int get_count(unsigned int eth_nic_base) -{ - unsigned int ret; - outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, - eth_nic_base + D8390_P0_COMMAND); - - ret = inb(eth_nic_base + 8 + 0) | (inb(eth_nic_base + 8 + 1) << 8); - - outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, - eth_nic_base + D8390_P0_COMMAND); - return ret; -} - -static void set_count(unsigned int eth_nic_base, unsigned int what) -{ - outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, - eth_nic_base + D8390_P0_COMMAND); - - outb(what & 0xff,eth_nic_base + 8); - outb((what >> 8) & 0xff,eth_nic_base + 8 + 1); - - outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, - eth_nic_base + D8390_P0_COMMAND); -} - -static void eth_pio_write(unsigned char *src, unsigned int dst, unsigned int cnt, - unsigned int eth_nic_base) -{ - outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); - outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR); - outb(cnt, eth_nic_base + D8390_P0_RBCR0); - outb(cnt >> 8, eth_nic_base + D8390_P0_RBCR1); - outb(dst, eth_nic_base + D8390_P0_RSAR0); - outb(dst >> 8, eth_nic_base + D8390_P0_RSAR1); - outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); - - while (cnt--) { - outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA); - } - /* - #warning "Add timeout" - */ - /* wait for operation finish */ - while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) != D8390_ISR_RDC) - ; -} - -void ne2k_append_data(unsigned char *d, int len, unsigned int base) -{ - eth_pio_write(d, (TX_START << 8) + 42 + get_count(base), len, base); - set_count(base, get_count(base)+len); -} - -#ifdef __ROMCC__ - -void eth_pio_write_byte(int data, unsigned short dst, unsigned int eth_nic_base) -{ - outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); - outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR); - outb(1, eth_nic_base + D8390_P0_RBCR0); - outb(0, eth_nic_base + D8390_P0_RBCR1); - outb(dst, eth_nic_base + D8390_P0_RSAR0); - outb(dst >> 8, eth_nic_base + D8390_P0_RSAR1); - outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); - outb(data, eth_nic_base + NE_ASIC_OFFSET + NE_DATA); - - while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) != D8390_ISR_RDC) - ; -} - -void ne2k_append_data_byte(int d, unsigned int base) -{ - eth_pio_write_byte(d, (TX_START << 8) + 42 + get_count(base), base); - set_count(base, get_count(base)+1); -} - -static unsigned char eth_pio_read_byte(unsigned int src, - unsigned int eth_nic_base) -{ - outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); - outb(0, eth_nic_base + D8390_P0_RBCR0); - outb(1, eth_nic_base + D8390_P0_RBCR1); - outb(src, eth_nic_base + D8390_P0_RSAR0); - outb(src >> 8, eth_nic_base + D8390_P0_RSAR1); - outb(D8390_COMMAND_RD0 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); - return inb(eth_nic_base + NE_ASIC_OFFSET + NE_DATA); -} - - -/* Variation of compute_ip_checksum which works on SRAM */ -unsigned long compute_ip_checksum_from_sram(unsigned short offset, unsigned short length, - unsigned int eth_nic_base) -{ - unsigned long sum; - unsigned long i; - /* In the most straight forward way possible, - * compute an ip style checksum. - */ - sum = 0; - for(i = 0; i < length; i++) { - unsigned long v; - v = eth_pio_read_byte((TX_START << 8)+i+offset, eth_nic_base); - if (i & 1) { - v <<= 8; - } - /* Add the new value */ - sum += v; - /* Wrap around the carry */ - if (sum > 0xFFFF) { - sum = (sum + (sum >> 16)) & 0xFFFF; - } - } - return (~((sum & 0xff) | (((sum >> 8) & 0xff) << 8) )) & 0xffff; -} - - -static void str2ip_load(const char *str, unsigned short offset, unsigned int eth_nic_base) -#else -static void str2ip(const char *str, unsigned char *ip) -#endif -{ - unsigned char c, i = 0; - int acc = 0; - - do { - c = str[i]; - if ((c >= '0') && (c <= '9')) { - acc *= 10; - acc += (c - '0'); - } else { -#ifdef __ROMCC__ - eth_pio_write_byte(acc, (TX_START << 8)+offset, eth_nic_base); - offset++; -#else - *ip++ = acc; -#endif - acc = 0; - } - i++; - } while (c != '\0'); -} - -#ifdef __ROMCC__ -static void str2mac_load(const char *str, unsigned short offset, unsigned int eth_nic_base) -#else -static void str2mac(const char *str, unsigned char *mac) -#endif -{ - unsigned char c, i = 0; - int acc = 0; - - do { - - c = str[i]; - if ((c >= '0') && (c <= '9')) { - acc *= 16; - acc += (c - '0'); - } else if ((c >= 'a') && (c <= 'f')) { - acc *= 16; - acc += ((c - 'a') + 10) ; - } else if ((c >= 'A') && (c <= 'F')) { - acc *= 16; - acc += ((c - 'A') + 10) ; - } else { -#ifdef __ROMCC__ - eth_pio_write_byte(acc, ((TX_START << 8)+offset), eth_nic_base); - offset++; -#else - *mac++ = acc; -#endif - acc = 0; - } - - i++; - } while (c != '\0'); -} - - -#ifndef __ROMCC__ -static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen) { - unsigned short chksum; - unsigned char hdr[] = { -#else -static const unsigned char hdr[] = { -#endif - /* - * ETHERNET HDR - */ - - // destination macaddr - 0x02, 0x00, 0x00, 0x00, 0x00, 0x01, - /* source mac */ - 0x02, 0x00, 0x00, 0xC0, 0xFF, 0xEE, - /* ethtype (IP) */ - 0x08, 0x00, - /* - * IP HDR - */ - 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, - /* TTL, proto (UDP), chksum_hi, chksum_lo, IP0, IP1, IP2, IP3, */ - 0x40, 0x11, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x1, - /* IP0, IP1, IP2, IP3 */ - 0xff, 0xff, 0xff, 0xff, - /* - * UDP HDR - */ - /* SRC PORT DST PORT (2bytes each), ulen, uchksum (must be zero or correct */ - 0x1a, 0x0b, 0x1a, 0x0a, 0x00, 0x9, 0x00, 0x00, - }; - -#ifndef __ROMCC__ - str2mac(CONFIG_CONSOLE_NE2K_DST_MAC, &hdr[0]); - str2ip(CONFIG_CONSOLE_NE2K_DST_IP, &hdr[30]); - str2ip(CONFIG_CONSOLE_NE2K_SRC_IP, &hdr[26]); - - /* zero checksum */ - hdr[24] = 0; - hdr[25] = 0; - - /* update IP packet len */ - hdr[16] = ((28 + pktlen) >> 8) & 0xff; - hdr[17] = (28 + pktlen) & 0xff; - - /* update UDP len */ - hdr[38] = (8 + pktlen) >> 8; - hdr[39] = 8 + pktlen; - - chksum = compute_ip_checksum(&hdr[14], 20); - - hdr[25] = chksum >> 8; - hdr[24] = chksum; - eth_pio_write(hdr, (TX_START << 8), sizeof(hdr), eth_nic_base); -} - - -#else - -/* ROMCC madness */ -static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen) -{ - unsigned short chksum; - - eth_pio_write(hdr, (TX_START << 8), sizeof(hdr), eth_nic_base); - - str2mac_load(CONFIG_CONSOLE_NE2K_DST_MAC, 0, eth_nic_base); - - str2ip_load(CONFIG_CONSOLE_NE2K_DST_IP, 30, eth_nic_base); - str2ip_load(CONFIG_CONSOLE_NE2K_SRC_IP, 26, eth_nic_base); - /* zero checksum */ - eth_pio_write_byte(0, (TX_START << 8)+24, eth_nic_base); - eth_pio_write_byte(0, (TX_START << 8)+25, eth_nic_base); - - /* update IP packet len */ - eth_pio_write_byte(((28 + pktlen) >> 8) & 0xff, (TX_START << 8)+16, eth_nic_base); - eth_pio_write_byte( (28 + pktlen) & 0xff, (TX_START << 8)+17, eth_nic_base); - - /* update UDP len */ - eth_pio_write_byte((8 + pktlen) >> 8, (TX_START << 8)+38, eth_nic_base); - eth_pio_write_byte( 8 + pktlen, (TX_START << 8)+39, eth_nic_base); - - chksum = compute_ip_checksum_from_sram(14, 20, eth_nic_base); - - eth_pio_write_byte(chksum, (TX_START << 8)+24, eth_nic_base); - eth_pio_write_byte(chksum >> 8, (TX_START << 8)+25, eth_nic_base); -} - -#endif - -void ne2k_transmit(unsigned int eth_nic_base) { - unsigned int pktsize; - unsigned int len = get_count(eth_nic_base); - - // so place whole header inside chip buffer - ns8390_tx_header(eth_nic_base, len); - - // commit sending now - outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); - - outb(TX_START, eth_nic_base + D8390_P0_TPSR); - - pktsize = 42 + len; - if (pktsize < 64) - pktsize = 64; - - outb(pktsize, eth_nic_base + D8390_P0_TBCR0); - outb(pktsize >> 8, eth_nic_base + D8390_P0_TBCR1); - - outb(D8390_ISR_PTX, eth_nic_base + D8390_P0_ISR); - - outb(D8390_COMMAND_PS0 | D8390_COMMAND_TXP | D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND); - - /* wait for operation finish */ - while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_PTX) != D8390_ISR_PTX) ; - - set_count(eth_nic_base, 0); -} - -#ifdef __PRE_RAM__ - -static void ns8390_reset(unsigned int eth_nic_base) -{ - int i; - - outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | - D8390_COMMAND_STP, eth_nic_base + D8390_P0_COMMAND); - - outb(0x48, eth_nic_base + D8390_P0_DCR); - outb(0, eth_nic_base + D8390_P0_RBCR0); - outb(0, eth_nic_base + D8390_P0_RBCR1); - outb(0x20, eth_nic_base + D8390_P0_RCR); - outb(2, eth_nic_base + D8390_P0_TCR); - outb(TX_START, eth_nic_base + D8390_P0_TPSR); - outb(RX_START, eth_nic_base + D8390_P0_PSTART); - outb(MEM_SIZE, eth_nic_base + D8390_P0_PSTOP); - outb(MEM_SIZE - 1, eth_nic_base + D8390_P0_BOUND); - outb(0xFF, eth_nic_base + D8390_P0_ISR); - outb(0, eth_nic_base + D8390_P0_IMR); - - outb(D8390_COMMAND_PS1 | - D8390_COMMAND_RD2 | D8390_COMMAND_STP, - eth_nic_base + D8390_P0_COMMAND); - - for (i = 0; i < ETH_ALEN; i++) - outb(0x0C, eth_nic_base + D8390_P1_PAR0 + i); - - for (i = 0; i < ETH_ALEN; i++) - outb(0xFF, eth_nic_base + D8390_P1_MAR0 + i); - - outb(RX_START, eth_nic_base + D8390_P1_CURR); - outb(D8390_COMMAND_PS0 | - D8390_COMMAND_RD2 | D8390_COMMAND_STA, - eth_nic_base + D8390_P0_COMMAND); - outb(0xFF, eth_nic_base + D8390_P0_ISR); - outb(0, eth_nic_base + D8390_P0_TCR); - outb(4, eth_nic_base + D8390_P0_RCR); - set_count(eth_nic_base, 0); -} - - -int ne2k_init(unsigned int eth_nic_base) { - - device_t dev; - unsigned char c; - - /* Power management controller */ - dev = pci_locate_device(PCI_ID(0x10ec, - 0x8029), 0); - - if (dev == PCI_DEV_INVALID) - return 0; - - pci_write_config32(dev, 0x10, eth_nic_base | 1 ); - pci_write_config8(dev, 0x4, 0x1); - - c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET); - outb(c, eth_nic_base + NE_ASIC_OFFSET + NE_RESET); - - (void) inb(0x84); - - outb(D8390_COMMAND_STP | D8390_COMMAND_RD2, eth_nic_base + D8390_P0_COMMAND); - outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR); - - outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR); - outb(MEM_8192, eth_nic_base + D8390_P0_PSTART); - outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP); - - ns8390_reset(eth_nic_base); - return 1; -} - -#else - -#include <delay.h> -#include <stdlib.h> -#include <string.h> -#include <arch/io.h> - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - -static void read_resources(struct device *dev) -{ - struct resource *res; - - res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = CONFIG_CONSOLE_NE2K_IO_PORT; - res->size = 32; - res->align = 5; - res->gran = 5; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - return; -} - -static struct device_operations ne2k_ops = { - .read_resources = read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, -}; - -static const struct pci_driver ne2k_driver __pci_driver = { - .ops = &ne2k_ops, - .vendor = 0x10ec, - .device = 0x8029, -}; - -#endif diff --git a/src/lib/ns8390.h b/src/lib/ns8390.h deleted file mode 100644 index eeffe45..0000000 --- a/src/lib/ns8390.h +++ /dev/null @@ -1,110 +0,0 @@ -/************************************************************************** -ETHERBOOT - BOOTP/TFTP Bootstrap Program - -Author: Martin Renters - Date: Jun/94 - -**************************************************************************/ - -//FILE_LICENCE ( BSD2 ); - -#define VENDOR_NONE 0 -#define VENDOR_WD 1 -#define VENDOR_NOVELL 2 -#define VENDOR_3COM 3 - -#define FLAG_PIO 0x01 -#define FLAG_16BIT 0x02 -#define FLAG_790 0x04 - -#define MEM_8192 32 -#define MEM_16384 64 -#define MEM_32768 128 - -#define ISA_MAX_ADDR 0x400 - -/************************************************************************** -NE1000/2000 definitions -**************************************************************************/ -#define NE_ASIC_OFFSET 0x10 -#define NE_RESET 0x0F /* Used to reset card */ -#define NE_DATA 0x00 /* Used to read/write NIC mem */ - -#define COMPEX_RL2000_TRIES 200 - -/************************************************************************** -8390 Register Definitions -**************************************************************************/ -#define D8390_P0_COMMAND 0x00 -#define D8390_P0_PSTART 0x01 -#define D8390_P0_PSTOP 0x02 -#define D8390_P0_BOUND 0x03 -#define D8390_P0_TSR 0x04 -#define D8390_P0_TPSR 0x04 -#define D8390_P0_TBCR0 0x05 -#define D8390_P0_TBCR1 0x06 -#define D8390_P0_ISR 0x07 -#define D8390_P0_RSAR0 0x08 -#define D8390_P0_RSAR1 0x09 -#define D8390_P0_RBCR0 0x0A -#define D8390_P0_RBCR1 0x0B -#define D8390_P0_RSR 0x0C -#define D8390_P0_RCR 0x0C -#define D8390_P0_TCR 0x0D -#define D8390_P0_DCR 0x0E -#define D8390_P0_IMR 0x0F -#define D8390_P1_COMMAND 0x00 -#define D8390_P1_PAR0 0x01 -#define D8390_P1_PAR1 0x02 -#define D8390_P1_PAR2 0x03 -#define D8390_P1_PAR3 0x04 -#define D8390_P1_PAR4 0x05 -#define D8390_P1_PAR5 0x06 -#define D8390_P1_CURR 0x07 -#define D8390_P1_MAR0 0x08 - -#define D8390_COMMAND_PS0 0x0 /* Page 0 select */ -#define D8390_COMMAND_PS1 0x40 /* Page 1 select */ -#define D8390_COMMAND_PS2 0x80 /* Page 2 select */ -#define D8390_COMMAND_RD2 0x20 /* Remote DMA control */ -#define D8390_COMMAND_RD1 0x10 -#define D8390_COMMAND_RD0 0x08 -#define D8390_COMMAND_TXP 0x04 /* transmit packet */ -#define D8390_COMMAND_STA 0x02 /* start */ -#define D8390_COMMAND_STP 0x01 /* stop */ - -#define D8390_RCR_MON 0x20 /* monitor mode */ - -#define D8390_DCR_FT1 0x40 -#define D8390_DCR_LS 0x08 /* Loopback select */ -#define D8390_DCR_WTS 0x01 /* Word transfer select */ - -#define D8390_ISR_PRX 0x01 /* successful recv */ -#define D8390_ISR_PTX 0x02 /* successful xmit */ -#define D8390_ISR_RXE 0x04 /* receive error */ -#define D8390_ISR_TXE 0x08 /* transmit error */ -#define D8390_ISR_OVW 0x10 /* Overflow */ -#define D8390_ISR_CNT 0x20 /* Counter overflow */ -#define D8390_ISR_RDC 0x40 /* Remote DMA complete */ -#define D8390_ISR_RST 0x80 /* reset */ - -#define D8390_RSTAT_PRX 0x01 /* successful recv */ -#define D8390_RSTAT_CRC 0x02 /* CRC error */ -#define D8390_RSTAT_FAE 0x04 /* Frame alignment error */ -#define D8390_RSTAT_OVER 0x08 /* FIFO overrun */ - -#define D8390_TXBUF_SIZE 6 -#define D8390_RXBUF_END 32 -#define D8390_PAGE_SIZE 256 - -struct ringbuffer { - unsigned char status; - unsigned char next; - unsigned short len; -}; -/* - * Local variables: - * c-basic-offset: 8 - * End: - */ -

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New patch to review for coreboot: 7207305 spkmodem: Move under drivers/pc80
by Kyösti Mälkki 05 Feb '14

05 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5134 -gerrit commit 720730520bf512fd302b1a0f71c8be915d0d9880 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 31 07:38:21 2014 +0200 spkmodem: Move under drivers/pc80 Change-Id: I46eb17ab19cea8759b3e4822019285cbe907e83a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/pc80/Makefile.inc | 5 +- src/drivers/pc80/spkmodem.c | 128 ++++++++++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 2 - src/lib/spkmodem.c | 128 ------------------------------------------ 4 files changed, 132 insertions(+), 131 deletions(-) diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index 23e986a..4d0a280 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -4,9 +4,12 @@ ramstage-y += i8254.c ramstage-y += i8259.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c -romstage-$(CONFIG_TPM) += tpm.c +ramstage-$(CONFIG_SPKMODEM) += spkmodem.c romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c +romstage-$(CONFIG_TPM) += tpm.c +romstage-$(CONFIG_SPKMODEM) += spkmodem.c + subdirs-y += vga cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default diff --git a/src/drivers/pc80/spkmodem.c b/src/drivers/pc80/spkmodem.c new file mode 100644 index 0000000..89773b1 --- /dev/null +++ b/src/drivers/pc80/spkmodem.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <console/spkmodem.h> +#include <cpu/x86/tsc.h> + +#define SPEAKER_PIT_FREQUENCY 0x1234dd + + +enum { + PIT_COUNTER_0 = 0x40, + PIT_COUNTER_1 = 0x41, + PIT_COUNTER_2 = 0x42, + PIT_CTRL = 0x43, + PIT_SPEAKER_PORT = 0x61, +}; + + +enum { + PIT_SPK_TMR2 = 0x01, + PIT_SPK_DATA = 0x02, + PIT_SPK_TMR2_LATCH = 0x20 +}; + +enum { + PIT_CTRL_SELECT_MASK = 0xc0, + PIT_CTRL_SELECT_0 = 0x00, + PIT_CTRL_SELECT_1 = 0x40, + PIT_CTRL_SELECT_2 = 0x80, + + PIT_CTRL_READLOAD_MASK= 0x30, + PIT_CTRL_COUNTER_LATCH = 0x00, + PIT_CTRL_READLOAD_LSB = 0x10, + PIT_CTRL_READLOAD_MSB = 0x20, + PIT_CTRL_READLOAD_WORD = 0x30, + + PIT_CTRL_MODE_MASK = 0x0e, + PIT_CTRL_INTR_ON_TERM = 0x00, + PIT_CTRL_PROGR_ONE_SHOT = 0x02, + + PIT_CTRL_RATE_GEN = 0x04, + + PIT_CTRL_SQUAREWAVE_GEN = 0x06, + PIT_CTRL_SOFTSTROBE = 0x08, + + PIT_CTRL_HARDSTROBE = 0x0a, + + + PIT_CTRL_COUNT_MASK = 0x01, + PIT_CTRL_COUNT_BINARY = 0x00, + PIT_CTRL_COUNT_BCD = 0x01 +}; + + +static void +make_tone (uint16_t freq_count, unsigned int duration) +{ + outb (PIT_CTRL_SELECT_2 + | PIT_CTRL_READLOAD_WORD + | PIT_CTRL_SQUAREWAVE_GEN + | PIT_CTRL_COUNT_BINARY, PIT_CTRL); + + outb (freq_count & 0xff, PIT_COUNTER_2); + + outb ((freq_count >> 8) & 0xff, PIT_COUNTER_2); + + outb (inb (PIT_SPEAKER_PORT) + | PIT_SPK_TMR2 | PIT_SPK_DATA, + PIT_SPEAKER_PORT); + + for (; duration; duration--) { + unsigned short counter, previous_counter = 0xffff; + while (1) { + counter = inb (PIT_COUNTER_2); + counter |= ((uint16_t) inb (PIT_COUNTER_2)) << 8; + if (counter > previous_counter) + { + previous_counter = counter; + break; + } + previous_counter = counter; + } + } +} + +void spkmodem_tx_byte(unsigned char c) +{ + int i; + + make_tone (SPEAKER_PIT_FREQUENCY / 200, 4); + for (i = 7; i >= 0; i--) { + if ((c >> i) & 1) + make_tone (SPEAKER_PIT_FREQUENCY / 2000, 20); + else + make_tone (SPEAKER_PIT_FREQUENCY / 4000, 40); + make_tone (SPEAKER_PIT_FREQUENCY / 1000, 10); + } + make_tone (SPEAKER_PIT_FREQUENCY / 200, 0); +} + +void spkmodem_init(void) +{ + /* Some cards need time to come online. Output some message to get it started. */ + spkmodem_tx_byte('S'); + spkmodem_tx_byte('P'); + spkmodem_tx_byte('K'); + spkmodem_tx_byte('\r'); + spkmodem_tx_byte('\n'); +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b1b4748..3bad3fd 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -48,7 +48,6 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c -romstage-$(CONFIG_SPKMODEM) += spkmodem.c ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -91,7 +90,6 @@ romstage-y += clog2.c ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c -ramstage-$(CONFIG_SPKMODEM) += spkmodem.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c diff --git a/src/lib/spkmodem.c b/src/lib/spkmodem.c deleted file mode 100644 index 89773b1..0000000 --- a/src/lib/spkmodem.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <arch/io.h> -#include <console/spkmodem.h> -#include <cpu/x86/tsc.h> - -#define SPEAKER_PIT_FREQUENCY 0x1234dd - - -enum { - PIT_COUNTER_0 = 0x40, - PIT_COUNTER_1 = 0x41, - PIT_COUNTER_2 = 0x42, - PIT_CTRL = 0x43, - PIT_SPEAKER_PORT = 0x61, -}; - - -enum { - PIT_SPK_TMR2 = 0x01, - PIT_SPK_DATA = 0x02, - PIT_SPK_TMR2_LATCH = 0x20 -}; - -enum { - PIT_CTRL_SELECT_MASK = 0xc0, - PIT_CTRL_SELECT_0 = 0x00, - PIT_CTRL_SELECT_1 = 0x40, - PIT_CTRL_SELECT_2 = 0x80, - - PIT_CTRL_READLOAD_MASK= 0x30, - PIT_CTRL_COUNTER_LATCH = 0x00, - PIT_CTRL_READLOAD_LSB = 0x10, - PIT_CTRL_READLOAD_MSB = 0x20, - PIT_CTRL_READLOAD_WORD = 0x30, - - PIT_CTRL_MODE_MASK = 0x0e, - PIT_CTRL_INTR_ON_TERM = 0x00, - PIT_CTRL_PROGR_ONE_SHOT = 0x02, - - PIT_CTRL_RATE_GEN = 0x04, - - PIT_CTRL_SQUAREWAVE_GEN = 0x06, - PIT_CTRL_SOFTSTROBE = 0x08, - - PIT_CTRL_HARDSTROBE = 0x0a, - - - PIT_CTRL_COUNT_MASK = 0x01, - PIT_CTRL_COUNT_BINARY = 0x00, - PIT_CTRL_COUNT_BCD = 0x01 -}; - - -static void -make_tone (uint16_t freq_count, unsigned int duration) -{ - outb (PIT_CTRL_SELECT_2 - | PIT_CTRL_READLOAD_WORD - | PIT_CTRL_SQUAREWAVE_GEN - | PIT_CTRL_COUNT_BINARY, PIT_CTRL); - - outb (freq_count & 0xff, PIT_COUNTER_2); - - outb ((freq_count >> 8) & 0xff, PIT_COUNTER_2); - - outb (inb (PIT_SPEAKER_PORT) - | PIT_SPK_TMR2 | PIT_SPK_DATA, - PIT_SPEAKER_PORT); - - for (; duration; duration--) { - unsigned short counter, previous_counter = 0xffff; - while (1) { - counter = inb (PIT_COUNTER_2); - counter |= ((uint16_t) inb (PIT_COUNTER_2)) << 8; - if (counter > previous_counter) - { - previous_counter = counter; - break; - } - previous_counter = counter; - } - } -} - -void spkmodem_tx_byte(unsigned char c) -{ - int i; - - make_tone (SPEAKER_PIT_FREQUENCY / 200, 4); - for (i = 7; i >= 0; i--) { - if ((c >> i) & 1) - make_tone (SPEAKER_PIT_FREQUENCY / 2000, 20); - else - make_tone (SPEAKER_PIT_FREQUENCY / 4000, 40); - make_tone (SPEAKER_PIT_FREQUENCY / 1000, 10); - } - make_tone (SPEAKER_PIT_FREQUENCY / 200, 0); -} - -void spkmodem_init(void) -{ - /* Some cards need time to come online. Output some message to get it started. */ - spkmodem_tx_byte('S'); - spkmodem_tx_byte('P'); - spkmodem_tx_byte('K'); - spkmodem_tx_byte('\r'); - spkmodem_tx_byte('\n'); -}

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Patch set updated for coreboot: ce1ee04 util/xcompile/xcompile: Remove `-Wno-unused-but-set-variable` from `CFLAGS`
by Paul Menzel 05 Feb '14

05 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3981 -gerrit commit ce1ee045b3b01e726e10adc5b521f9827b3a9f90 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Oct 20 00:11:34 2013 +0200 util/xcompile/xcompile: Remove `-Wno-unused-but-set-variable` from `CFLAGS` Do not disable warnings about unused but set variables to further improve the code quality. Change-Id: I25fa29ac42c9d09596d03f11fb01f31635a62a11 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/xcompile/xcompile | 5 ----- 1 file changed, 5 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index df7d558..bfb6da1 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -89,11 +89,6 @@ testas() { detect_special_flags() { local architecture="$1" - # GCC 4.6 is much more picky about unused variables. - # Turn off it's warnings for now: - testcc "$CC" "$CFLAGS -Wno-unused-but-set-variable " && - CFLAGS="$CFLAGS -Wno-unused-but-set-variable " - # Use bfd linker instead of gold if available: testcc "$CC" "$CFLAGS -fuse-ld=bfd" && CFLAGS="$CFLAGS -fuse-ld=bfd" && LINKER_SUFFIX='.bfd'

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Patch set updated for coreboot: 276f46f Asus F2A85-M: show POST codes
by Idwer Vollering 05 Feb '14

05 Feb '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4561 -gerrit commit 276f46f1d221c48f7e05255d0b39ef56f9767548 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:01:51 2013 +0000 Asus F2A85-M: show POST codes Add conditional POST code output, tunable with CONFIG_IO_POST. Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/mainboard/asus/f2a85-m/romstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index fe66dde..b0111eb 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -64,7 +64,9 @@ static void sbxxx_enable_48mhzout(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { +#if CONFIG_IO_POST hudson_pci_port80(); +#endif u32 val; u8 byte;

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Patch set updated for coreboot: 1e12f92 Asus F2A85-M: show POST codes
by Idwer Vollering 05 Feb '14

05 Feb '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4561 -gerrit commit 1e12f9212285b4e931930207cc1c3691c8a3f542 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Dec 22 21:01:51 2013 +0000 Asus F2A85-M: show POST codes Add conditional POST code output, tunable with CONFIG_IO_POST. Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/mainboard/asus/f2a85-m/romstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index fe66dde..df21ede 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -64,7 +64,9 @@ static void sbxxx_enable_48mhzout(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { +#if CONFIG_IO_POST_PORT hudson_pci_port80(); +#endif u32 val; u8 byte;

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New patch to review for coreboot: 4760ab9 southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5133 -gerrit commit 4760ab93695e5c9ceadabbdda22fe1793efcaea3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 15:03:50 2014 +0100 southbridge/bd82x6x: Reserve 16 MiB for flash and not 8. X230 has 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash but address map limits this to 16MiB. Change-Id: Icc39c3c8d45d2d14e437bdfce920f8b4b039789d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/bd82x6x/lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e052150..5e6a7e0 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -593,8 +593,8 @@ static void pch_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ + res->base = 0xff000000; + res->size = 0x01000000; /* 16 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

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Patch set updated for coreboot: f15b070 ibexpeak/azalia: Remove C4-register extended init.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5074 -gerrit commit f15b070e892a327a47311866a88c302e84830deb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jan 28 14:28:49 2014 +0100 ibexpeak/azalia: Remove C4-register extended init. This sequence was derived from BD82X6X and on ibexpeak it inadvertently disables interrupts. In older kernels it wasn't a problem but in new kernel it makes codec probe fail. Change-Id: I40184ae8c4cfe758869af1a1565b88f0a238150e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/ibexpeak/azalia.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 0e3d365..395832b 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -278,26 +278,10 @@ static void azalia_init(struct device *dev) reg8 |= (1 << 6); pci_write_config8(dev, 0x43, reg8); - /* Additional programming steps */ - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 13); - pci_write_config32(dev, 0xc4, reg32); - - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 10); - pci_write_config32(dev, 0xc4, reg32); - reg32 = pci_read_config32(dev, 0xd0); reg32 &= ~(1 << 31); pci_write_config32(dev, 0xd0, reg32); - if (dev->device == 0x1e20) { - /* Additional step on Panther Point */ - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 17); - pci_write_config32(dev, 0xc4, reg32); - } - /* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);

1 0

Patch set updated for coreboot: 5959bc4 intel/model_2065x: Add 20652 microcode.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5117 -gerrit commit 5959bc43fa876fd48bf6bdf6099dc48b9718e1d4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Feb 4 21:19:51 2014 +0100 intel/model_2065x: Add 20652 microcode. Change-Id: I2a46806a3f0a57497edebd49e69b97f90948adb9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- .../model_2065x/microcode-m1220652_0000000d.h | 483 +++++++++++++++++++++ src/cpu/intel/model_2065x/microcode_blob.h | 1 + 2 files changed, 484 insertions(+) diff --git a/src/cpu/intel/model_2065x/microcode-m1220652_0000000d.h b/src/cpu/intel/model_2065x/microcode-m1220652_0000000d.h new file mode 100644 index 0000000..fc6664c --- /dev/null +++ b/src/cpu/intel/model_2065x/microcode-m1220652_0000000d.h @@ -0,0 +1,483 @@ +//+++ +// Copyright (c) <1995-2013>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//--- +/* Fri Feb 22 16:02:34 CST 2013 */ +/* m1220652_0000000d.inc */ +0x00000001, 0x0000000d, 0x09012011, 0x00020652, +0xaa7e2951, 0x00000001, 0x00000012, 0x00001bd0, +0x00001c00, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x000000a1, 0x00020001, 0x0000000d, +0x00000000, 0x00000000, 0x20110831, 0x00000661, +0x00000001, 0x00020652, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 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0xe18d0040, 0x5106f6eb, +0x0aee7c68, 0xca971603, 0x0eb55c92, 0x6dea930e, +0x75a64c09, 0x035155da, 0xde1b28f0, 0xbf46380e, +0x0598ffd6, 0x4750ab9c, 0x2bb893f3, 0x5e98717f, +0x3505eb3a, 0xb631b55d, 0x6a0f4b37, 0x21101012, +0x798fd260, 0xf576d38a, 0x9acbc6e4, 0xbe69064e, +0x9b015a9f, 0xe50ad106, 0x04b1f1dd, 0x9c4c0bd7, +0xdd71823c, 0xdf2e91b3, 0x159ad675, 0x9341041b, +0x50090592, 0x0c457f5d, 0x2ea03609, 0x032a2d6a, +0x95367a13, 0x283db93e, 0x0faab7ee, 0x76b0edd6, +0xa41cd1b9, 0x54859e7f, 0x36ecaa7c, 0xe63bab70, +0x567debce, 0x36dd287c, 0xd031273b, 0x644f7da7, +0x1177d229, 0xb263ada7, 0xbedfc96d, 0x9e5eade4, +0x7ace4447, 0xfda81252, 0xe51a0c7b, 0x267cedb1, +0xf7a73bdf, 0xb5c420be, 0x097fd60c, 0xeb7de107, +0xa4d128d5, 0xd396be30, 0xa442a5b8, 0x9e621b82, +0x9422bca9, 0x15c2f6f2, 0x6bc462ac, 0x0528f7a1, +0x5d733fcb, 0x870e6781, 0xafe0c5b8, 0x645abf56, +0x7d429570, 0x46275d48, 0x727dec85, 0x39fa7581, +0x8e0844ce, 0x990a25aa, 0xb32eb8ff, 0x7d9c301d, +0x24c418e2, 0xa37a663e, 0x92ef3e2a, 0x7ad55b41, +0xfc592a17, 0xcd540582, 0xcc3da1ee, 0x24466d39, +0x26ac6f86, 0x02a71f64, 0x7b248995, 0x6ef68c4e, +0x2dab4794, 0x7cd5bd5a, 0x57fd5d04, 0xdeb86710, +0x69aac22f, 0xb1368e05, 0x56f16ae3, 0xedd70836, +0x55b8d8f0, 0x56f2a47c, 0x15803e4a, 0x6341bf59, +0x55e82bd7, 0x33135bca, 0x9eaa44a6, 0xfbe95037, +0x369c4b7d, 0x7f03d739, 0xd56638dc, 0x05237a2c, +0xa75913da, 0x4af23c6b, 0x4493a6ed, 0xa7219216, +0x16b71d06, 0x32e0b074, 0x2a8b419c, 0xa7ea58da, +0xa06ad198, 0x1a425559, 0x5600b1dd, 0x60597133, +0x31804c7f, 0x677e01b7, 0xd0dafe04, 0x7616d789, +0xa23dba7b, 0x65b53075, 0x6526a4fe, 0xae8486ed, +0x48529d9c, 0x089db2c3, 0xbf61101c, 0xd81c0690, +0x6f41fb5e, 0x4b5902c6, 0x50a60c1f, 0x58b7f339, +0x3827304f, 0xc892b1b0, 0x1a8e909c, 0x68b5b89b, diff --git a/src/cpu/intel/model_2065x/microcode_blob.h b/src/cpu/intel/model_2065x/microcode_blob.h index 7aa6fdf..61b5f81 100644 --- a/src/cpu/intel/model_2065x/microcode_blob.h +++ b/src/cpu/intel/model_2065x/microcode_blob.h @@ -17,4 +17,5 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + #include "microcode-m1220652_0000000d.h" #include "microcode-m9220655_00000003.h"

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New patch to review for coreboot: ab88b5b Kill ALT_CBFS_LOAD_PAYLOAD
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5132 -gerrit commit ab88b5b382d5aa22a4fa5d0dc18a4419d757beef Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:27:22 2014 +0100 Kill ALT_CBFS_LOAD_PAYLOAD Not used anymore. Change-Id: Icf3a4a7f932776981048b805478582ad2b784182 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 9 --------- src/lib/cbfs.c | 2 -- 2 files changed, 11 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 31a41ab..e6b237a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -47,15 +47,6 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. -config ALT_CBFS_LOAD_PAYLOAD - bool "Use alternative cbfs_load_payload() implementation." - default n - help - Either board or southbridge provide an alternative cbfs_load_payload() - implementation. This may be used, for example, if accessing the ROM - through memory-mapped I/O is slow and a faster alternative can be - provided. - choice prompt "Compiler to use" default COMPILER_GCC diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..30e7949 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -213,7 +213,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) } #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ -#if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) { struct cbfs_payload *payload; @@ -226,7 +225,6 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) media, name, CBFS_TYPE_PAYLOAD, NULL); return payload; } -#endif /* Simple buffer */

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coreboot-gerrit February 2014