Patch set updated for coreboot: b778fa3 lynxpoint: Kill alternative cbfs_load_payload.
by Vladimir Serbinenko 05 Feb '14
by Vladimir Serbinenko 05 Feb '14
05 Feb '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5131
-gerrit
commit b778fa3c18a7ec0bc3d59ab91caeb38a7aad01eb
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Feb 5 14:23:56 2014 +0100
lynxpoint: Kill alternative cbfs_load_payload.
The only thing which this file does differently to increase the speed is
usage of cache but since MTRR is covering ROM already anyway, this makes
no difference and only increases maintenance efforts and cache usage.
Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/southbridge/intel/lynxpoint/Kconfig | 1 -
src/southbridge/intel/lynxpoint/Makefile.inc | 1 -
src/southbridge/intel/lynxpoint/spi_loading.c | 90 ---------------------------
3 files changed, 92 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 5ff00db..970a11d 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -32,7 +32,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
- select ALT_CBFS_LOAD_PAYLOAD
config INTEL_LYNXPOINT_LP
bool
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 7be2d03..b691e6f 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -41,7 +41,6 @@ ramstage-y += me_status.c
ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-y += acpi.c
-ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += spi.c
diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c
deleted file mode 100644
index 57e3af8..0000000
--- a/src/southbridge/intel/lynxpoint/spi_loading.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 ChromeOS Authors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <stdlib.h>
-#include <string.h>
-#include <arch/byteorder.h>
-#include <cbmem.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#if CONFIG_VBOOT_VERIFY_FIRMWARE
-#include <vendorcode/google/chromeos/chromeos.h>
-#else
-static inline void *vboot_get_payload(size_t *len) { return NULL; }
-#endif
-
-#define CACHELINE_SIZE 64
-#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1)
-#define CACHELINE_MASK (~INTRA_CACHELINE_MASK)
-
-/* Mirror the payload file to the default SMM location if it is small enough.
- * The default SMM region can be used since no one is using the memory at this
- * location at this stage in the boot. */
-static inline void *spi_mirror(void *file_start, int file_len)
-{
- int alignment_diff;
- char *src;
- char *dest = (void *)SMM_DEFAULT_BASE;
-
- alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start);
-
- /* Adjust file length so that the start and end points are aligned to a
- * cacheline. Coupled with the ROM caching in the CPU the SPI hardware
- * will read and cache full length cachelines. It will also prefetch
- * data as well. Once things are mirrored in memory all accesses should
- * hit the CPUs cache. */
- file_len += alignment_diff;
- file_len = ALIGN(file_len, CACHELINE_SIZE);
-
- printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len);
-
- /* Just pass back the pointer to ROM space if the file is larger
- * than the RAM mirror region. */
- if (file_len > SMM_DEFAULT_SIZE)
- return file_start;
-
- src = (void *)(CACHELINE_MASK & (long)file_start);
- /* Note that if mempcy is not using 32-bit moves the performance will
- * degrade because the SPI hardware prefetchers look for
- * cacheline-aligned 32-bit accesses to kick in. */
- memcpy(dest, src, file_len);
-
- /* Provide pointer into mirrored space. */
- return &dest[alignment_diff];
-}
-
-void *cbfs_load_payload(struct cbfs_media *media, const char *name)
-{
- size_t file_len;
- void *file_start;
-
- file_start = vboot_get_payload(&file_len);
-
- if (file_start != NULL)
- return spi_mirror(file_start, file_len);
-
- file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len);
-
- if (file_start == NULL)
- return NULL;
-
- return spi_mirror(file_start, file_len);
-}
1
0
New patch to review for coreboot: 3f0f513 lynxpoint: Kill alternative cbfs_load_payload.
by Vladimir Serbinenko 05 Feb '14
by Vladimir Serbinenko 05 Feb '14
05 Feb '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5131
-gerrit
commit 3f0f51370bfee7e358d715eda9340ad652760ac0
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Feb 5 14:23:56 2014 +0100
lynxpoint: Kill alternative cbfs_load_payload.
The only thing which this file does differently to increase the speed is
usage of cache but since MTRR is covering ROM already anyway, this makes
no difference and only increases maintenance efforts and cache usage.
Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/southbridge/intel/lynxpoint/Makefile.inc | 1 -
src/southbridge/intel/lynxpoint/spi_loading.c | 90 ---------------------------
2 files changed, 91 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 7be2d03..b691e6f 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -41,7 +41,6 @@ ramstage-y += me_status.c
ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-y += acpi.c
-ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += spi.c
diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c
deleted file mode 100644
index 57e3af8..0000000
--- a/src/southbridge/intel/lynxpoint/spi_loading.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 ChromeOS Authors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <stdlib.h>
-#include <string.h>
-#include <arch/byteorder.h>
-#include <cbmem.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#if CONFIG_VBOOT_VERIFY_FIRMWARE
-#include <vendorcode/google/chromeos/chromeos.h>
-#else
-static inline void *vboot_get_payload(size_t *len) { return NULL; }
-#endif
-
-#define CACHELINE_SIZE 64
-#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1)
-#define CACHELINE_MASK (~INTRA_CACHELINE_MASK)
-
-/* Mirror the payload file to the default SMM location if it is small enough.
- * The default SMM region can be used since no one is using the memory at this
- * location at this stage in the boot. */
-static inline void *spi_mirror(void *file_start, int file_len)
-{
- int alignment_diff;
- char *src;
- char *dest = (void *)SMM_DEFAULT_BASE;
-
- alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start);
-
- /* Adjust file length so that the start and end points are aligned to a
- * cacheline. Coupled with the ROM caching in the CPU the SPI hardware
- * will read and cache full length cachelines. It will also prefetch
- * data as well. Once things are mirrored in memory all accesses should
- * hit the CPUs cache. */
- file_len += alignment_diff;
- file_len = ALIGN(file_len, CACHELINE_SIZE);
-
- printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len);
-
- /* Just pass back the pointer to ROM space if the file is larger
- * than the RAM mirror region. */
- if (file_len > SMM_DEFAULT_SIZE)
- return file_start;
-
- src = (void *)(CACHELINE_MASK & (long)file_start);
- /* Note that if mempcy is not using 32-bit moves the performance will
- * degrade because the SPI hardware prefetchers look for
- * cacheline-aligned 32-bit accesses to kick in. */
- memcpy(dest, src, file_len);
-
- /* Provide pointer into mirrored space. */
- return &dest[alignment_diff];
-}
-
-void *cbfs_load_payload(struct cbfs_media *media, const char *name)
-{
- size_t file_len;
- void *file_start;
-
- file_start = vboot_get_payload(&file_len);
-
- if (file_start != NULL)
- return spi_mirror(file_start, file_len);
-
- file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len);
-
- if (file_start == NULL)
- return NULL;
-
- return spi_mirror(file_start, file_len);
-}
1
0
05 Feb '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4700
-gerrit
commit 023dbabc458b13441a54bcea7f3bc433c1dd7de2
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Jan 15 22:26:03 2014 +0200
usbdebug: Improve receive speed
Read from USB endpoint_in 8 bytes at a time, the maximum what
EHCI debug port capability has to offer.
Change-Id: I3d012d758a24b24f894e587b301f620933331407
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/console/usbdebug_console.c | 7 +------
src/drivers/usb/ehci_debug.c | 18 ++++++++++++++++++
src/include/console/usb.h | 1 +
3 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c
index 99726be..cb627bb 100644
--- a/src/console/usbdebug_console.c
+++ b/src/console/usbdebug_console.c
@@ -34,12 +34,7 @@ static void dbgp_tx_byte(unsigned char data)
static unsigned char dbgp_rx_byte(void)
{
- unsigned char data = 0xff;
-
- if (dbgp_ep_is_active(dbgp_console_input()))
- dbgp_bulk_read_x(dbgp_console_input(), &data, 1);
-
- return data;
+ return usbdebug_rx_byte(dbgp_console_input());
}
static void dbgp_tx_flush(void)
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
index 94625c0..b28208d 100644
--- a/src/drivers/usb/ehci_debug.c
+++ b/src/drivers/usb/ehci_debug.c
@@ -48,6 +48,7 @@ struct dbgp_pipe
int timeout;
u8 bufidx;
+ u8 buflen;
char buf[8];
};
@@ -912,6 +913,23 @@ void usbdebug_tx_flush(struct dbgp_pipe *pipe)
dbgp_put(pipe);
}
+unsigned char usbdebug_rx_byte(struct dbgp_pipe *pipe)
+{
+ unsigned char data = 0xff;
+ if (!dbgp_try_get(pipe))
+ return 0xff;
+ while (pipe->bufidx >= pipe->buflen) {
+ pipe->buflen = 0;
+ pipe->bufidx = 0;
+ int count = dbgp_bulk_read_x(pipe, pipe->buf, 8);
+ if (count>0)
+ pipe->buflen = count;
+ }
+ data = pipe->buf[pipe->bufidx++];
+ dbgp_put(pipe);
+ return data;
+}
+
#if !defined(__PRE_RAM__) && !defined(__SMM__)
static void usbdebug_re_enable(unsigned ehci_base)
{
diff --git a/src/include/console/usb.h b/src/include/console/usb.h
index 47f3d74..430557f 100644
--- a/src/include/console/usb.h
+++ b/src/include/console/usb.h
@@ -32,5 +32,6 @@ int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size);
int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size);
void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data);
void usbdebug_tx_flush(struct dbgp_pipe *pipe);
+unsigned char usbdebug_rx_byte(struct dbgp_pipe *pipe);
#endif /* _CONSOLE_USB_H_ */
1
0
Patch set updated for coreboot: 97ae5bd usbdebug: Fix data toggle on receive
by Kyösti Mälkki 05 Feb '14
by Kyösti Mälkki 05 Feb '14
05 Feb '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4775
-gerrit
commit 97ae5bd0e871cb5af7957336973144f9b73b0de3
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jan 21 10:44:08 2014 +0200
usbdebug: Fix data toggle on receive
USB device end toggles data PID when we ACK'd the zero-length data
packet. As USB host we need to toggle data PID too or the next data
received would get discarded.
Change-Id: I3203bc874c7ded9244c7548a666d7041a0fbb379
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/drivers/usb/ehci_debug.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
index b28208d..7413a8a 100644
--- a/src/drivers/usb/ehci_debug.c
+++ b/src/drivers/usb/ehci_debug.c
@@ -204,8 +204,7 @@ host_retry:
/* If I get an ACK or in-sync DATA PID, we are done. */
if ((lpid == USB_PID_ACK) || (lpid == pipe->pid)) {
- if (DBGP_LEN(rd_ctrl))
- pipe->pid ^= USB_PID_DATA_TOGGLE;
+ pipe->pid ^= USB_PID_DATA_TOGGLE;
}
/* If the port is getting full or it has dropped data
1
0
Patch set updated for coreboot: 42bf709 usbdebug: Remove duplicate port claim
by Kyösti Mälkki 05 Feb '14
by Kyösti Mälkki 05 Feb '14
05 Feb '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4709
-gerrit
commit 42bf709756f132b654bab64700606cca0aa2678d
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sat Jan 18 12:26:13 2014 +0200
usbdebug: Remove duplicate port claim
This claim is useless when done before EHCI controller reset. Code in
usbdebug_init_() already sets this properly after reset, see use of
DBGP_OWNER.
Change-Id: Ic17493fe4edbbbed6ebcbef35a264fbf188f1fba
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/southbridge/intel/common/usb_debug.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index fecd716..d18cb0f 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -64,8 +64,6 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- u32 dbgctl;
-
/* Bail out. No console to complain in. */
if (!dev)
return;
@@ -75,9 +73,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
- /* Force ownership of the Debug Port to the EHCI controller. */
- dbgctl = read32(base + CONFIG_EHCI_DEBUG_OFFSET);
- dbgctl |= (1 << 30);
- write32(base + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
}
1
0
05 Feb '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5130
-gerrit
commit 6bf5292444aa79ec4def55b20cdda26629f4644c
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Feb 4 19:18:59 2014 +0200
usbdebug: Drop obsolete code
Change-Id: I918ca1d0d0d7bcb7e16d41a12830a0357f15b8ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 16 ----------------
src/southbridge/intel/ibexpeak/thermal.c | 1 -
2 files changed, 17 deletions(-)
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
index 6eb4787..c362ae3 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
@@ -34,7 +34,6 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <pc80/mc146818rtc.h>
-#include <usbdebug.h>
#include "model_206ax.h"
#include "chip.h"
@@ -289,10 +288,6 @@ static void configure_mca(void)
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
}
-#if CONFIG_USBDEBUG
-static unsigned ehci_debug_addr;
-#endif
-
/*
* Initialize any extra cores/threads in this package.
*/
@@ -365,13 +360,6 @@ static void model_206ax_init(device_t cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
-#if CONFIG_USBDEBUG
- // Is this caution really needed?
- if(!ehci_debug_addr)
- ehci_debug_addr = get_ehci_debug();
- set_ehci_debug(0);
-#endif
-
/* Setup MTRRs based on physical address size */
cpuid_regs = cpuid(0x80000008);
x86_setup_fixed_mtrrs();
@@ -381,10 +369,6 @@ static void model_206ax_init(device_t cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
-#if CONFIG_USBDEBUG
- set_ehci_debug(ehci_debug_addr);
-#endif
-
/* Enable the local cpu apics */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
index 11b6555..e01a6db 100644
--- a/src/southbridge/intel/ibexpeak/thermal.c
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -23,7 +23,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
-#include <usbdebug.h>
#include <arch/io.h>
static void thermal_init(struct device *dev)
1
0
Patch set updated for coreboot: b821c90 usbdebug: Move under drivers/usb
by Kyösti Mälkki 05 Feb '14
by Kyösti Mälkki 05 Feb '14
05 Feb '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5129
-gerrit
commit b821c9068f8ad2942be5ec72fa8de1bb23437bcc
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Feb 5 13:02:55 2014 +0200
usbdebug: Move under drivers/usb
Also relocate and split header files, there is some interest
for EHCI debug support without PCI.
Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/arch/x86/lib/romstage_console.c | 2 +-
src/console/usbdebug_console.c | 2 +-
src/drivers/Makefile.inc | 1 +
src/drivers/usb/Makefile.inc | 3 +
src/drivers/usb/ehci.h | 200 ++++
src/drivers/usb/ehci_debug.c | 1044 ++++++++++++++++++++
src/drivers/usb/usb_ch9.h | 102 ++
src/include/console/console.h | 2 +-
src/include/console/usb.h | 36 +
src/include/device/pci_ehci.h | 52 +
src/include/ehci.h | 200 ----
src/include/usb_ch9.h | 102 --
src/include/usbdebug.h | 61 --
src/lib/Makefile.inc | 2 -
src/lib/usbdebug.c | 1043 -------------------
src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 2 +-
src/southbridge/amd/agesa/hudson/usb.c | 2 +-
src/southbridge/amd/cimx/sb700/late.c | 2 +-
src/southbridge/amd/cimx/sb800/late.c | 2 +-
src/southbridge/amd/cimx/sb900/late.c | 2 +-
src/southbridge/amd/sb600/enable_usbdebug.c | 2 +-
src/southbridge/amd/sb600/usb.c | 2 +-
src/southbridge/amd/sb700/enable_usbdebug.c | 2 +-
src/southbridge/amd/sb700/usb.c | 2 +-
src/southbridge/amd/sb800/enable_usbdebug.c | 2 +-
src/southbridge/amd/sb800/usb.c | 2 +-
src/southbridge/intel/bd82x6x/usb_ehci.c | 2 +-
src/southbridge/intel/bd82x6x/usb_xhci.c | 2 +-
src/southbridge/intel/common/usb_debug.c | 2 +-
src/southbridge/intel/i82801dx/usb2.c | 2 +-
src/southbridge/intel/i82801ex/ehci.c | 2 +-
src/southbridge/intel/i82801gx/usb_ehci.c | 2 +-
src/southbridge/intel/i82801ix/usb_ehci.c | 2 +-
src/southbridge/intel/ibexpeak/usb_ehci.c | 2 +-
src/southbridge/intel/lynxpoint/usb_ehci.c | 2 +-
src/southbridge/nvidia/ck804/enable_usbdebug.c | 2 +-
src/southbridge/nvidia/mcp55/enable_usbdebug.c | 2 +-
src/southbridge/nvidia/mcp55/usb2.c | 2 +-
src/southbridge/sis/sis966/enable_usbdebug.c | 2 +-
src/southbridge/sis/sis966/usb2.c | 2 +-
40 files changed, 1466 insertions(+), 1436 deletions(-)
diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index 278ef1a..0eb3dc2 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -23,7 +23,7 @@
#include <uart8250.h>
#endif
#if CONFIG_USBDEBUG
-#include <usbdebug.h>
+#include <console/usb.h>
#endif
#if CONFIG_CONSOLE_NE2K
#include <console/ne2k.h>
diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c
index 8df6417..99726be 100644
--- a/src/console/usbdebug_console.c
+++ b/src/console/usbdebug_console.c
@@ -20,7 +20,7 @@
#include <string.h>
#include <console/console.h>
-#include <usbdebug.h>
+#include <console/usb.h>
static void dbgp_init(void)
{
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index 34ae62e..4b63a8f 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -29,6 +29,7 @@ subdirs-y += parade
subdirs-y += realtek
subdirs-y += sil
subdirs-y += trident
+subdirs-y += usb
subdirs-y += ics
subdirs-y += spi
subdirs-y += ti
diff --git a/src/drivers/usb/Makefile.inc b/src/drivers/usb/Makefile.inc
new file mode 100644
index 0000000..43931a9
--- /dev/null
+++ b/src/drivers/usb/Makefile.inc
@@ -0,0 +1,3 @@
+romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ehci_debug.c
+
+ramstage-$(CONFIG_USBDEBUG) += ehci_debug.c
diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h
new file mode 100644
index 0000000..f920352
--- /dev/null
+++ b/src/drivers/usb/ehci.h
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * It was taken from the Linux kernel (include/linux/usb/ehci_def.h).
+ *
+ * Copyright (C) 2001-2002 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef EHCI_H
+#define EHCI_H
+
+/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
+
+/* Section 2.2 Host Controller Capability Registers */
+struct ehci_caps {
+ /* these fields are specified as 8 and 16 bit registers,
+ * but some hosts can't perform 8 or 16 bit PCI accesses.
+ */
+ u32 hc_capbase;
+#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
+#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
+ u32 hcs_params; /* HCSPARAMS - offset 0x4 */
+#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
+#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
+#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
+#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
+#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
+#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
+#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
+
+ u32 hcc_params; /* HCCPARAMS - offset 0x8 */
+/* EHCI 1.1 addendum */
+#define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19))
+#define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18))
+#define HCC_LPM(p) ((p)&(1 << 17))
+#define HCC_HW_PREFETCH(p) ((p)&(1 << 16))
+
+#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
+#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
+#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
+#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
+#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
+#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
+ u8 portroute[8]; /* nibbles for routing - offset 0xC */
+} __attribute__ ((packed));
+
+
+/* Section 2.3 Host Controller Operational Registers */
+struct ehci_regs {
+
+ /* USBCMD: offset 0x00 */
+ u32 command;
+
+/* EHCI 1.1 addendum */
+#define CMD_HIRD (0xf<<24) /* host initiated resume duration */
+#define CMD_PPCEE (1<<15) /* per port change event enable */
+#define CMD_FSP (1<<14) /* fully synchronized prefetch */
+#define CMD_ASPE (1<<13) /* async schedule prefetch enable */
+#define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */
+/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
+#define CMD_PARK (1<<11) /* enable "park" on async qh */
+#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
+#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
+#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
+#define CMD_ASE (1<<5) /* async schedule enable */
+#define CMD_PSE (1<<4) /* periodic schedule enable */
+/* 3:2 is periodic frame list size */
+#define CMD_RESET (1<<1) /* reset HC not bus */
+#define CMD_RUN (1<<0) /* start/stop HC */
+
+ /* USBSTS: offset 0x04 */
+ u32 status;
+#define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */
+#define STS_ASS (1<<15) /* Async Schedule Status */
+#define STS_PSS (1<<14) /* Periodic Schedule Status */
+#define STS_RECL (1<<13) /* Reclamation */
+#define STS_HALT (1<<12) /* Not running (any reason) */
+/* some bits reserved */
+ /* these STS_* flags are also intr_enable bits (USBINTR) */
+#define STS_IAA (1<<5) /* Interrupted on async advance */
+#define STS_FATAL (1<<4) /* such as some PCI access errors */
+#define STS_FLR (1<<3) /* frame list rolled over */
+#define STS_PCD (1<<2) /* port change detect */
+#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
+#define STS_INT (1<<0) /* "normal" completion (short, ...) */
+
+ /* USBINTR: offset 0x08 */
+ u32 intr_enable;
+
+ /* FRINDEX: offset 0x0C */
+ u32 frame_index; /* current microframe number */
+ /* CTRLDSSEGMENT: offset 0x10 */
+ u32 segment; /* address bits 63:32 if needed */
+ /* PERIODICLISTBASE: offset 0x14 */
+ u32 frame_list; /* points to periodic list */
+ /* ASYNCLISTADDR: offset 0x18 */
+ u32 async_next; /* address of next async queue head */
+
+ u32 reserved[9];
+
+ /* CONFIGFLAG: offset 0x40 */
+ u32 configured_flag;
+#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
+
+ /* PORTSC: offset 0x44 */
+ u32 port_status[0]; /* up to N_PORTS */
+/* EHCI 1.1 addendum */
+#define PORTSC_SUSPEND_STS_ACK 0
+#define PORTSC_SUSPEND_STS_NYET 1
+#define PORTSC_SUSPEND_STS_STALL 2
+#define PORTSC_SUSPEND_STS_ERR 3
+
+#define PORT_DEV_ADDR (0x7f<<25) /* device address */
+#define PORT_SSTS (0x3<<23) /* suspend status */
+/* 31:23 reserved */
+#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
+#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
+#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
+/* 19:16 for port testing */
+#define PORT_TEST_PKT (0x4<<16) /* Port Test Control - packet test */
+#define PORT_LED_OFF (0<<14)
+#define PORT_LED_AMBER (1<<14)
+#define PORT_LED_GREEN (2<<14)
+#define PORT_LED_MASK (3<<14)
+#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
+#define PORT_POWER (1<<12) /* true: has power (see PPC) */
+#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
+/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
+/* 9 reserved */
+#define PORT_LPM (1<<9) /* LPM transaction */
+#define PORT_RESET (1<<8) /* reset port */
+#define PORT_SUSPEND (1<<7) /* suspend port */
+#define PORT_RESUME (1<<6) /* resume it */
+#define PORT_OCC (1<<5) /* over current change */
+#define PORT_OC (1<<4) /* over current active */
+#define PORT_PEC (1<<3) /* port enable change */
+#define PORT_PE (1<<2) /* port enable */
+#define PORT_CSC (1<<1) /* connect status change */
+#define PORT_CONNECT (1<<0) /* device connected */
+#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
+} __attribute__ ((packed));
+
+#define USBMODE 0x68 /* USB Device mode */
+#define USBMODE_SDIS (1<<3) /* Stream disable */
+#define USBMODE_BE (1<<2) /* BE/LE endianness select */
+#define USBMODE_CM_HC (3<<0) /* host controller mode */
+#define USBMODE_CM_IDLE (0<<0) /* idle state */
+
+/* Moorestown has some non-standard registers, partially due to the fact that
+ * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
+ * PORTSCx
+ */
+#define HOSTPC0 0x84 /* HOSTPC extension */
+#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
+#define HOSTPC_PSPD (3<<25) /* Port speed detection */
+#define USBMODE_EX 0xc8 /* USB Device mode extension */
+#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */
+#define USBMODE_EX_HC (3<<0) /* host controller mode */
+#define TXFILLTUNING 0x24 /* TX FIFO Tuning register */
+#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
+
+/* Appendix C, Debug port ... intended for use with special "debug devices"
+ * that can help if there's no serial console. (nonstandard enumeration.)
+ */
+struct ehci_dbg_port {
+ u32 control;
+#define DBGP_OWNER (1<<30)
+#define DBGP_ENABLED (1<<28)
+#define DBGP_DONE (1<<16)
+#define DBGP_INUSE (1<<10)
+#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
+# define DBGP_ERR_BAD 1
+# define DBGP_ERR_SIGNAL 2
+#define DBGP_ERROR (1<<6)
+#define DBGP_GO (1<<5)
+#define DBGP_OUT (1<<4)
+#define DBGP_LEN(x) (((x)>>0)&0x0f)
+ u32 pids;
+#define DBGP_PID_GET(x) (((x)>>16)&0xff)
+#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
+ u32 data03;
+ u32 data47;
+ u32 address;
+#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
+} __attribute__ ((packed));
+#endif
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
new file mode 100644
index 0000000..94625c0
--- /dev/null
+++ b/src/drivers/usb/ehci_debug.c
@@ -0,0 +1,1044 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Eric Biederman (ebiederm(a)xmission.com)
+ * Copyright (C) 2007 AMD
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <console/console.h>
+#include <console/usb.h>
+#include <device/pci_ehci.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <arch/byteorder.h>
+#include <arch/early_variables.h>
+#include <string.h>
+#include <cbmem.h>
+
+#include "usb_ch9.h"
+#include "ehci.h"
+
+
+#define DBGP_EP_VALID (1<<0)
+#define DBGP_EP_ENABLED (1<<1)
+#define DBGP_EP_BUSY (1<<2)
+#define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED)
+
+struct dbgp_pipe
+{
+ u8 devnum;
+ u8 endpoint;
+ u8 pid;
+ u8 status;
+ int timeout;
+
+ u8 bufidx;
+ char buf[8];
+};
+
+#define DBGP_MAX_ENDPOINTS 4
+#define DBGP_SETUP_EP0 0 /* Compulsory endpoint 0. */
+#define DBGP_CONSOLE_EPOUT 1
+#define DBGP_CONSOLE_EPIN 2
+
+struct ehci_debug_info {
+ void *ehci_caps;
+ void *ehci_regs;
+ void *ehci_debug;
+
+ struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS];
+};
+
+#if CONFIG_DEBUG_USBDEBUG
+static void dbgp_print_data(struct ehci_dbg_port *ehci_debug);
+static int dbgp_enabled(void);
+# define dprintk(LEVEL, args...) \
+ do { if (!dbgp_enabled()) printk(LEVEL, ##args); } while (0)
+#else
+# define dbgp_print_data(x) do {} while(0)
+# define dprintk(LEVEL, args...) do {} while(0)
+#endif
+
+#define USB_DEBUG_DEVNUM 127
+
+#define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f))
+/*
+ * USB Packet IDs (PIDs)
+ */
+
+/* token */
+#define USB_PID_OUT 0xe1
+#define USB_PID_IN 0x69
+#define USB_PID_SOF 0xa5
+#define USB_PID_SETUP 0x2d
+/* handshake */
+#define USB_PID_ACK 0xd2
+#define USB_PID_NAK 0x5a
+#define USB_PID_STALL 0x1e
+#define USB_PID_NYET 0x96
+/* data */
+#define USB_PID_DATA0 0xc3
+#define USB_PID_DATA1 0x4b
+#define USB_PID_DATA2 0x87
+#define USB_PID_MDATA 0x0f
+/* Special */
+#define USB_PID_PREAMBLE 0x3c
+#define USB_PID_ERR 0x3c
+#define USB_PID_SPLIT 0x78
+#define USB_PID_PING 0xb4
+#define USB_PID_UNDEF_0 0xf0
+
+#define USB_PID_DATA_TOGGLE 0x88
+#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
+
+#define PCI_CAP_ID_EHCI_DEBUG 0xa
+
+#define HUB_ROOT_RESET_TIME 50 /* times are in msec */
+#define HUB_SHORT_RESET_TIME 10
+#define HUB_LONG_RESET_TIME 200
+#define HUB_RESET_TIMEOUT 500
+
+#define DBGP_MICROFRAME_TIMEOUT_LOOPS 1000
+#define DBGP_MICROFRAME_RETRIES 10
+#define DBGP_MAX_PACKET 8
+
+static struct ehci_debug_info glob_dbg_info CAR_GLOBAL;
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
+static struct device_operations *ehci_drv_ops;
+static struct device_operations ehci_dbg_ops;
+#endif
+
+static inline struct ehci_debug_info *dbgp_ehci_info(void)
+{
+ return car_get_var_ptr(&glob_dbg_info);
+}
+
+static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
+{
+ u32 ctrl;
+ int loop = 0;
+
+ do {
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ /* Stop when the transaction is finished */
+ if (ctrl & DBGP_DONE)
+ break;
+ } while (++loop < DBGP_MICROFRAME_TIMEOUT_LOOPS);
+
+ if (! (ctrl & DBGP_DONE)) {
+ dprintk(BIOS_ERR, "dbgp_wait_until_complete: retry timeout.\n");
+ return -DBGP_ERR_SIGNAL;
+ }
+
+ /* Now that we have observed the completed transaction,
+ * clear the done bit.
+ */
+ write32((unsigned long)&ehci_debug->control, ctrl | DBGP_DONE);
+ return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
+}
+
+static void dbgp_breath(void)
+{
+ /* Sleep to give the debug port a chance to breathe */
+}
+
+static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
+ unsigned ctrl, const int timeout)
+{
+ u32 rd_ctrl, rd_pids;
+ u32 ctrl_prev = 0, pids_prev = 0;
+ u8 lpid;
+ int ret, host_retries;
+ int loop;
+
+ loop = 0;
+device_retry:
+ host_retries = 0;
+ if (loop++ >= timeout)
+ return -DBGP_ERR_BAD;
+
+host_retry:
+ if (host_retries++ >= DBGP_MICROFRAME_RETRIES)
+ return -DBGP_ERR_BAD;
+ if (loop == 1 || host_retries > 1)
+ dprintk(BIOS_SPEW, "dbgp: start (@ %3d,%d) ctrl=%08x\n",
+ loop, host_retries, ctrl | DBGP_GO);
+ write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO);
+ ret = dbgp_wait_until_complete(ehci_debug);
+ rd_ctrl = read32((unsigned long)&ehci_debug->control);
+ rd_pids = read32((unsigned long)&ehci_debug->pids);
+
+ if (rd_ctrl != ctrl_prev || rd_pids != pids_prev || (ret<0)) {
+ ctrl_prev = rd_ctrl;
+ pids_prev = rd_pids;
+ dprintk(BIOS_SPEW, "dbgp: status (@ %3d,%d) ctrl=%08x pids=%08x ret=%d\n",
+ loop, host_retries, rd_ctrl, rd_pids, ret);
+ }
+
+ /* Controller hardware failure. */
+ if (ret == -DBGP_ERR_SIGNAL) {
+ return ret;
+
+ /* Bus failure (corrupted microframe). */
+ } else if (ret == -DBGP_ERR_BAD) {
+ goto host_retry;
+ }
+
+ lpid = DBGP_PID_GET(rd_pids);
+
+ /* If I get an ACK or in-sync DATA PID, we are done. */
+ if ((lpid == USB_PID_ACK) || (lpid == pipe->pid)) {
+ if (DBGP_LEN(rd_ctrl))
+ pipe->pid ^= USB_PID_DATA_TOGGLE;
+ }
+
+ /* If the port is getting full or it has dropped data
+ * start pacing ourselves, not necessary but it's friendly.
+ */
+ else if (lpid == USB_PID_NYET) {
+ dbgp_breath();
+ goto device_retry;
+ }
+
+ /* If I get a NACK or out-of-sync DATA PID, reissue the transmission. */
+ else if ((lpid == USB_PID_NAK) || (lpid == (pipe->pid ^ USB_PID_DATA_TOGGLE))) {
+ goto device_retry;
+ }
+
+ /* Abort on STALL handshake for endpoint 0.*/
+ else if ((lpid == USB_PID_STALL) && (pipe->endpoint == 0x0)) {
+ ret = -DBGP_ERR_BAD;
+ }
+
+ dbgp_print_data(ehci_debug);
+
+ return ret;
+}
+
+static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int size)
+{
+ const unsigned char *bytes = buf;
+ u32 lo, hi;
+ int i;
+
+ lo = hi = 0;
+ for (i = 0; i < 4 && i < size; i++)
+ lo |= bytes[i] << (8*i);
+ for (; i < 8 && i < size; i++)
+ hi |= bytes[i] << (8*(i - 4));
+ write32((unsigned long)&ehci_debug->data03, lo);
+ write32((unsigned long)&ehci_debug->data47, hi);
+}
+
+static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
+{
+ unsigned char *bytes = buf;
+ u32 lo, hi;
+ int i;
+
+ lo = read32((unsigned long)&ehci_debug->data03);
+ hi = read32((unsigned long)&ehci_debug->data47);
+ for (i = 0; i < 4 && i < size; i++)
+ bytes[i] = (lo >> (8*i)) & 0xff;
+ for (; i < 8 && i < size; i++)
+ bytes[i] = (hi >> (8*(i - 4))) & 0xff;
+}
+
+#if CONFIG_DEBUG_USBDEBUG
+static void dbgp_print_data(struct ehci_dbg_port *ehci_debug)
+{
+ u32 ctrl = read32((unsigned long)&ehci_debug->control);
+ u32 lo = read32((unsigned long)&ehci_debug->data03);
+ u32 hi = read32((unsigned long)&ehci_debug->data47);
+ int len = DBGP_LEN(ctrl);
+ if (len) {
+ int i;
+ dprintk(BIOS_SPEW, "dbgp: buf:");
+ for (i = 0; i < 4 && i < len; i++)
+ dprintk(BIOS_SPEW, " %02x", (lo >> (8*i)) & 0xff);
+ for (; i < 8 && i < len; i++)
+ dprintk(BIOS_SPEW, " %02x", (hi >> (8*(i - 4))) & 0xff);
+ dprintk(BIOS_SPEW, "\n");
+ }
+}
+#endif
+
+static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
+ const char *bytes, int size)
+{
+ u32 pids, addr, ctrl;
+ int ret;
+
+ if (size > DBGP_MAX_PACKET)
+ return -1;
+
+ addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
+ pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
+
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = DBGP_LEN_UPDATE(ctrl, size);
+ ctrl |= DBGP_OUT;
+
+ dbgp_set_data(ehci_debug, bytes, size);
+ write32((unsigned long)&ehci_debug->address, addr);
+ write32((unsigned long)&ehci_debug->pids, pids);
+
+ ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
+
+ return ret;
+}
+
+int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+ return dbgp_bulk_write(dbg_info->ehci_debug, pipe, bytes, size);
+}
+
+static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
+ void *data, int size)
+{
+ u32 pids, addr, ctrl;
+ int ret;
+
+ if (size > DBGP_MAX_PACKET)
+ return -1;
+
+ addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
+ pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
+
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = DBGP_LEN_UPDATE(ctrl, size);
+ ctrl &= ~DBGP_OUT;
+
+ write32((unsigned long)&ehci_debug->address, addr);
+ write32((unsigned long)&ehci_debug->pids, pids);
+ ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
+ if (ret < 0)
+ return ret;
+
+ if (size > ret)
+ size = ret;
+ dbgp_get_data(ehci_debug, data, size);
+ return ret;
+}
+
+int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+ return dbgp_bulk_read(dbg_info->ehci_debug, pipe, data, size);
+}
+
+static void dbgp_mdelay(int ms)
+{
+ int i;
+
+ while (ms--) {
+ for (i = 0; i < 1000; i++)
+ inb(0x80);
+ }
+}
+
+static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype,
+ int request, int value, int index, void *data, int size)
+{
+ struct ehci_debug_info *info = dbgp_ehci_info();
+ struct dbgp_pipe *pipe = &info->ep_pipe[DBGP_SETUP_EP0];
+ u32 pids, addr, ctrl;
+ struct usb_ctrlrequest req;
+ int read;
+ int ret, ret2;
+
+ read = (requesttype & USB_DIR_IN) != 0;
+ if (size > DBGP_MAX_PACKET)
+ return -1;
+
+ /* Compute the control message */
+ req.bRequestType = requesttype;
+ req.bRequest = request;
+ req.wValue = cpu_to_le16(value);
+ req.wIndex = cpu_to_le16(index);
+ req.wLength = cpu_to_le16(size);
+
+ pipe->devnum = devnum;
+ pipe->endpoint = 0;
+ pipe->pid = USB_PID_DATA0;
+ pipe->timeout = 1000;
+ addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
+ pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP);
+
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
+ ctrl |= DBGP_OUT;
+
+ /* Setup stage */
+ dbgp_set_data(ehci_debug, &req, sizeof(req));
+ write32((unsigned long)&ehci_debug->address, addr);
+ write32((unsigned long)&ehci_debug->pids, pids);
+ ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, 1);
+ if (ret < 0)
+ return ret;
+
+ /* Data stage (optional) */
+ if (read && size)
+ ret = dbgp_bulk_read(ehci_debug, pipe, data, size);
+ else if (!read && size)
+ ret = dbgp_bulk_write(ehci_debug, pipe, data, size);
+
+ /* Status stage in opposite direction */
+ pipe->pid = USB_PID_DATA1;
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = DBGP_LEN_UPDATE(ctrl, 0);
+ if (read) {
+ pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
+ ctrl |= DBGP_OUT;
+ } else {
+ pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
+ ctrl &= ~DBGP_OUT;
+ }
+
+ write32((unsigned long)&ehci_debug->pids, pids);
+ ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
+ if (ret2 < 0)
+ return ret2;
+
+ return ret;
+}
+
+static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
+{
+ u32 portsc;
+ u32 delay_time, delay_ms;
+ int loop;
+
+ /* Reset the usb debug port */
+ portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ portsc &= ~PORT_PE;
+ portsc |= PORT_RESET;
+ write32((unsigned long)&ehci_regs->port_status[port - 1], portsc);
+
+ delay_ms = HUB_ROOT_RESET_TIME;
+ for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
+ delay_time += delay_ms) {
+ dbgp_mdelay(delay_ms);
+
+ portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ if (portsc & PORT_RESET) {
+ /* force reset to complete */
+ loop = 2;
+ write32((unsigned long)&ehci_regs->port_status[port - 1],
+ portsc & ~(PORT_RWC_BITS | PORT_RESET));
+ do {
+ dbgp_mdelay(delay_ms);
+ portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ delay_time += delay_ms;
+ } while ((portsc & PORT_RESET) && (--loop > 0));
+ if (!loop) {
+ printk(BIOS_DEBUG, "ehci_reset_port forced done");
+ }
+ }
+
+ /* Device went away? */
+ if (!(portsc & PORT_CONNECT))
+ return -1; //-ENOTCONN;
+
+ /* bomb out completely if something weird happened */
+ if ((portsc & PORT_CSC))
+ return -2; //-EINVAL;
+
+ /* If we've finished resetting, then break out of the loop */
+ if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
+ return 0;
+ }
+ return -3; //-EBUSY;
+}
+
+static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
+{
+ u32 status;
+ int ret, reps;
+
+ for (reps = 0; reps < 3; reps++) {
+ dbgp_mdelay(100);
+ status = read32((unsigned long)&ehci_regs->status);
+ if (status & STS_PCD) {
+ ret = ehci_reset_port(ehci_regs, port);
+ if (ret == 0)
+ return 0;
+ }
+ }
+ return -1; //-ENOTCONN;
+}
+
+#define USB_HUB_PORT_CONNECTION 0
+#define USB_HUB_PORT_ENABLED 1
+#define USB_HUB_PORT_RESET 4
+#define USB_HUB_PORT_POWER 8
+#define USB_HUB_C_PORT_CONNECTION 16
+#define USB_HUB_C_PORT_RESET 20
+
+#if CONFIG_USBDEBUG_OPTIONAL_HUB_PORT
+
+static int hub_port_status(const char * buf, int feature)
+{
+ return !!(buf[feature>>3] & (1<<(feature&0x7)));
+}
+
+static int dbgp_hub_enable(struct ehci_dbg_port *ehci_debug, unsigned int port)
+{
+ const u8 hub_addr = USB_DEBUG_DEVNUM-1;
+ char status[8];
+ int ret, loop;
+
+ /* Move hub to address 126. */
+ ret = dbgp_control_msg(ehci_debug, 0,
+ USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_SET_ADDRESS, hub_addr, 0, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+ /* Enter configured state on hub. */
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+ /* Set PORT_POWER, poll for PORT_CONNECTION. */
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_SET_FEATURE, USB_HUB_PORT_POWER, port, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+ loop = 100;
+ do {
+ dbgp_mdelay(10);
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_GET_STATUS, 0, port, status, 4);
+ if (ret < 0)
+ goto err;
+ if (hub_port_status(status, USB_HUB_PORT_CONNECTION))
+ break;
+ } while (--loop);
+ if (! loop)
+ goto err;
+
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_CLEAR_FEATURE, USB_HUB_C_PORT_CONNECTION, port, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+
+ /* Set PORT_RESET, poll for C_PORT_RESET. */
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_SET_FEATURE, USB_HUB_PORT_RESET, port, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+ loop = 100;
+ do {
+ dbgp_mdelay(10);
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_GET_STATUS, 0, port, status, 4);
+ if (ret < 0)
+ goto err;
+ if (hub_port_status(status, USB_HUB_C_PORT_RESET))
+ break;
+ } while (--loop);
+ if (! loop)
+ goto err;
+
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_CLEAR_FEATURE, USB_HUB_C_PORT_RESET, port, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+ if (hub_port_status(status, USB_HUB_PORT_ENABLED))
+ return 0;
+err:
+ return -1;
+}
+#endif /* CONFIG_USBDEBUG_OPTIONAL_HUB_PORT */
+
+static void enable_usbdebug(void)
+{
+#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE
+ pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
+ pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR);
+#endif
+}
+
+static void set_debug_port(unsigned int port)
+{
+ pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
+ pci_ehci_dbg_set_port(dbg_dev, port);
+}
+
+static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info)
+{
+ struct ehci_caps *ehci_caps;
+ struct ehci_regs *ehci_regs;
+ struct ehci_dbg_port *ehci_debug;
+
+ struct usb_debug_descriptor dbgp_desc;
+ u32 cmd, ctrl, status, portsc, hcs_params;
+ u32 debug_port, new_debug_port = 0, n_ports;
+ u32 devnum;
+ int ret, i, configured;
+ int loop;
+ int port_map_tried;
+ int playtimes = 3;
+
+ ehci_caps = (struct ehci_caps *)ehci_bar;
+ ehci_regs = (struct ehci_regs *)(ehci_bar +
+ HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
+ ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
+ info->ehci_debug = (void *)0;
+ memset(&info->ep_pipe, 0, sizeof (info->ep_pipe));
+
+ if (CONFIG_USBDEBUG_DEFAULT_PORT > 0)
+ set_debug_port(CONFIG_USBDEBUG_DEFAULT_PORT);
+ else
+ set_debug_port(1);
+
+try_next_time:
+ port_map_tried = 0;
+
+try_next_port:
+ hcs_params = read32((unsigned long)&ehci_caps->hcs_params);
+ debug_port = HCS_DEBUG_PORT(hcs_params);
+ n_ports = HCS_N_PORTS(hcs_params);
+
+ dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar);
+ dprintk(BIOS_INFO, "debug_port: %d\n", debug_port);
+ dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
+
+ for (i = 1; i <= n_ports; i++) {
+ portsc = read32((unsigned long)&ehci_regs->port_status[i-1]);
+ dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
+ }
+
+ if(port_map_tried && (new_debug_port != debug_port)) {
+ if(--playtimes) {
+ set_debug_port(debug_port);
+ goto try_next_time;
+ }
+ return -1;
+ }
+
+ /* Wait until the controller is halted */
+ status = read32((unsigned long)&ehci_regs->status);
+ if (!(status & STS_HALT)) {
+ cmd = read32((unsigned long)&ehci_regs->command);
+ cmd &= ~CMD_RUN;
+ write32((unsigned long)&ehci_regs->command, cmd);
+ loop = 100;
+ do {
+ dbgp_mdelay(10);
+ status = read32((unsigned long)&ehci_regs->status);
+ } while (!(status & STS_HALT) && (--loop > 0));
+ if (status & STS_HALT)
+ dprintk(BIOS_INFO, "EHCI controller halted successfully.\n");
+ else
+ dprintk(BIOS_INFO, "EHCI controller is not halted. Reset may fail.\n");
+ }
+
+ loop = 100;
+ /* Reset the EHCI controller */
+ cmd = read32((unsigned long)&ehci_regs->command);
+ cmd |= CMD_RESET;
+ write32((unsigned long)&ehci_regs->command, cmd);
+ do {
+ dbgp_mdelay(10);
+ cmd = read32((unsigned long)&ehci_regs->command);
+ } while ((cmd & CMD_RESET) && (--loop > 0));
+
+ if(!loop) {
+ dprintk(BIOS_INFO, "Could not reset EHCI controller.\n");
+ // on some systems it works without succeeding here.
+ // return -2;
+ } else {
+ dprintk(BIOS_INFO, "EHCI controller reset successfully.\n");
+ }
+
+ /* Claim ownership, but do not enable yet */
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl |= DBGP_OWNER;
+ ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
+ write32((unsigned long)&ehci_debug->control, ctrl);
+
+ /* Start EHCI controller */
+ cmd = read32((unsigned long)&ehci_regs->command);
+ cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
+ cmd |= CMD_RUN;
+ write32((unsigned long)&ehci_regs->command, cmd);
+
+ /* Ensure everything is routed to the EHCI */
+ write32((unsigned long)&ehci_regs->configured_flag, FLAG_CF);
+
+ /* Wait until the controller is no longer halted */
+ loop = 10;
+ do {
+ dbgp_mdelay(10);
+ status = read32((unsigned long)&ehci_regs->status);
+ } while ((status & STS_HALT) && (--loop > 0));
+
+ if(!loop) {
+ dprintk(BIOS_INFO, "EHCI could not be started.\n");
+ return -3;
+ }
+ dprintk(BIOS_INFO, "EHCI started.\n");
+
+ /* Wait for a device to show up in the debug port */
+ ret = ehci_wait_for_port(ehci_regs, debug_port);
+ if (ret < 0) {
+ dprintk(BIOS_INFO, "No device found in debug port %d\n", debug_port);
+ goto next_debug_port;
+ }
+ dprintk(BIOS_INFO, "EHCI done waiting for port.\n");
+
+ /* Enable the debug port */
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl |= DBGP_CLAIM;
+ write32((unsigned long)&ehci_debug->control, ctrl);
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
+ dprintk(BIOS_INFO, "No device in EHCI debug port.\n");
+ write32((unsigned long)&ehci_debug->control, ctrl & ~DBGP_CLAIM);
+ ret = -4;
+ goto err;
+ }
+ dprintk(BIOS_INFO, "EHCI debug port enabled.\n");
+
+ /* Completely transfer the debug device to the debug controller */
+ portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]);
+ portsc &= ~PORT_PE;
+ write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc);
+
+ dbgp_mdelay(100);
+
+#if CONFIG_USBDEBUG_OPTIONAL_HUB_PORT
+ ret = dbgp_hub_enable(ehci_debug, CONFIG_USBDEBUG_OPTIONAL_HUB_PORT);
+ if (ret < 0) {
+ dprintk(BIOS_INFO, "Could not enable USB hub on debug port.\n");
+ ret = -6;
+ goto err;
+ }
+#endif
+
+ /* Find the debug device and make it device number 127 */
+ devnum = 0;
+debug_dev_retry:
+ memset(&dbgp_desc, 0, sizeof(dbgp_desc));
+ ret = dbgp_control_msg(ehci_debug, devnum,
+ USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
+ &dbgp_desc, sizeof(dbgp_desc));
+ if (ret == sizeof(dbgp_desc)) {
+ if (dbgp_desc.bLength == sizeof(dbgp_desc) && dbgp_desc.bDescriptorType==USB_DT_DEBUG)
+ goto debug_dev_found;
+ else
+ dprintk(BIOS_INFO, "Invalid debug device descriptor.\n");
+ }
+ if (devnum == 0) {
+ devnum = USB_DEBUG_DEVNUM;
+ goto debug_dev_retry;
+ } else {
+ dprintk(BIOS_INFO, "Could not find attached debug device.\n");
+ ret = -5;
+ goto err;
+ }
+debug_dev_found:
+
+ /* Move the device to 127 if it isn't already there */
+ if (devnum != USB_DEBUG_DEVNUM) {
+ ret = dbgp_control_msg(ehci_debug, devnum,
+ USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
+ if (ret < 0) {
+ dprintk(BIOS_INFO, "Could not move attached device to %d.\n",
+ USB_DEBUG_DEVNUM);
+ ret = -7;
+ goto err;
+ }
+ devnum = USB_DEBUG_DEVNUM;
+ dprintk(BIOS_INFO, "EHCI debug device renamed to 127.\n");
+ }
+
+ /* Enable the debug interface */
+ ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
+ USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
+ if (ret < 0) {
+ dprintk(BIOS_INFO, "Could not enable EHCI debug device.\n");
+ ret = -8;
+ goto err;
+ }
+ dprintk(BIOS_INFO, "EHCI debug interface enabled.\n");
+
+ /* Prepare endpoint pipes. */
+ for (i=1; i<DBGP_MAX_ENDPOINTS; i++) {
+ info->ep_pipe[i].devnum = USB_DEBUG_DEVNUM;
+ info->ep_pipe[i].pid = USB_PID_DATA0;
+ info->ep_pipe[i].timeout = 1000;
+ }
+ info->ep_pipe[DBGP_CONSOLE_EPOUT].endpoint = dbgp_desc.bDebugOutEndpoint;
+ info->ep_pipe[DBGP_CONSOLE_EPIN].endpoint = dbgp_desc.bDebugInEndpoint;
+
+ /* Perform a small write. */
+ configured = 0;
+small_write:
+ ret = dbgp_bulk_write(ehci_debug, &info->ep_pipe[DBGP_CONSOLE_EPOUT], "USB\r\n",5);
+ if (ret < 0) {
+ dprintk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret);
+ if (!configured) {
+ /* Send Set Configure request to device. This is required for FX2
+ (CY7C68013) to transfer from USB state Addressed to Configured,
+ only then endpoints other than 0 are enabled. */
+ if (dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
+ USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0) >= 0) {
+ configured = 1;
+ goto small_write;
+ }
+ }
+ ret = -9;
+ goto err;
+ }
+ dprintk(BIOS_INFO, "Test write done\n");
+
+ info->ehci_caps = ehci_caps;
+ info->ehci_regs = ehci_regs;
+ info->ehci_debug = ehci_debug;
+
+ info->ep_pipe[DBGP_SETUP_EP0].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
+ info->ep_pipe[DBGP_CONSOLE_EPOUT].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
+ info->ep_pipe[DBGP_CONSOLE_EPIN].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
+ return 0;
+err:
+ /* Things didn't work so remove my claim */
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
+ write32((unsigned long)(unsigned long)&ehci_debug->control, ctrl);
+ //return ret;
+
+next_debug_port:
+#if CONFIG_USBDEBUG_DEFAULT_PORT==0
+ port_map_tried |= (1 << (debug_port - 1));
+ new_debug_port = ((debug_port-1 + 1) % n_ports) + 1;
+ if (port_map_tried != ((1 << n_ports) - 1)) {
+ set_debug_port(new_debug_port);
+ goto try_next_port;
+ }
+ if (--playtimes) {
+ set_debug_port(new_debug_port);
+ goto try_next_time;
+ }
+#else
+ if (0)
+ goto try_next_port;
+ if (--playtimes)
+ goto try_next_time;
+#endif
+
+ return -10;
+}
+
+#if CONFIG_DEBUG_USBDEBUG
+static int dbgp_enabled(void)
+{
+ struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
+ return (globals->status & DBGP_EP_ENABLED);
+}
+#endif
+
+static int dbgp_try_get(struct dbgp_pipe *pipe)
+{
+ struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
+ if (!dbgp_ep_is_active(pipe) || (globals->status & DBGP_EP_BUSY))
+ return 0;
+ globals->status |= DBGP_EP_BUSY;
+ pipe->status |= DBGP_EP_BUSY;
+ return 1;
+}
+
+static void dbgp_put(struct dbgp_pipe *pipe)
+{
+ struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
+ globals->status &= ~DBGP_EP_BUSY;
+ pipe->status &= ~DBGP_EP_BUSY;
+}
+
+void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data)
+{
+ if (!dbgp_try_get(pipe))
+ return;
+ pipe->buf[pipe->bufidx++] = data;
+ if (pipe->bufidx >= 8) {
+ dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx);
+ pipe->bufidx = 0;
+ }
+ dbgp_put(pipe);
+}
+
+void usbdebug_tx_flush(struct dbgp_pipe *pipe)
+{
+ if (!dbgp_try_get(pipe))
+ return;
+ if (pipe->bufidx > 0) {
+ dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx);
+ pipe->bufidx = 0;
+ }
+ dbgp_put(pipe);
+}
+
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
+static void usbdebug_re_enable(unsigned ehci_base)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+ unsigned diff;
+ int i;
+
+ if (!dbg_info->ehci_debug)
+ return;
+
+ diff = (unsigned)dbg_info->ehci_caps - ehci_base;
+ dbg_info->ehci_regs -= diff;
+ dbg_info->ehci_debug -= diff;
+ dbg_info->ehci_caps = (void*)ehci_base;
+
+ for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
+ dbg_info->ep_pipe[i].status |= DBGP_EP_ENABLED;
+}
+
+static void usbdebug_disable(void)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+ int i;
+ for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
+ dbg_info->ep_pipe[i].status &= ~DBGP_EP_ENABLED;
+}
+
+static void pci_ehci_set_resources(struct device *dev)
+{
+ struct resource *res;
+
+ printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev));
+ usbdebug_disable();
+
+ if (ehci_drv_ops->set_resources)
+ ehci_drv_ops->set_resources(dev);
+ res = find_resource(dev, EHCI_BAR_INDEX);
+ if (!res)
+ return;
+
+ usbdebug_re_enable((u32)res->base);
+ report_resource_stored(dev, res, "");
+ printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev));
+}
+
+void pci_ehci_read_resources(struct device *dev)
+{
+ pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
+
+ if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) {
+ memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops));
+ ehci_drv_ops = dev->ops;
+ ehci_dbg_ops.set_resources = pci_ehci_set_resources;
+ dev->ops = &ehci_dbg_ops;
+ printk(BIOS_DEBUG, "%s EHCI BAR hook registered\n", dev_path(dev));
+ } else {
+ printk(BIOS_DEBUG, "More than one caller of %s from %s\n", __func__, dev_path(dev));
+ }
+
+ pci_dev_read_resources(dev);
+}
+#endif
+
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
+static int get_usbdebug_from_cbmem(struct ehci_debug_info *info)
+{
+ struct ehci_debug_info *dbg_info_cbmem;
+
+ dbg_info_cbmem = cbmem_find(CBMEM_ID_EHCI_DEBUG);
+ if (dbg_info_cbmem == NULL)
+ return -1;
+
+ memcpy(info, dbg_info_cbmem, sizeof (*info));
+ printk(BIOS_DEBUG, "EHCI debug port found in CBMEM.\n");
+
+ return 0;
+}
+
+#elif defined(__PRE_RAM__)
+static void migrate_ehci_debug(void)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+ struct ehci_debug_info *dbg_info_cbmem;
+
+ dbg_info_cbmem = cbmem_add(CBMEM_ID_EHCI_DEBUG, sizeof(*dbg_info));
+ if (dbg_info_cbmem == NULL)
+ return;
+
+ memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info));
+}
+CAR_MIGRATE(migrate_ehci_debug);
+#endif
+
+unsigned long pci_ehci_base_regs(pci_devfn_t sdev)
+{
+#ifdef __SIMPLE_DEVICE__
+ unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f;
+#else
+ device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
+ unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f;
+#endif
+ return base + HC_LENGTH(read32(base));
+}
+
+int dbgp_ep_is_active(struct dbgp_pipe *pipe)
+{
+ return (pipe->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED);
+}
+
+struct dbgp_pipe *dbgp_console_output(void)
+{
+ return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPOUT];
+}
+
+struct dbgp_pipe *dbgp_console_input(void)
+{
+ return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPIN];
+}
+
+int usbdebug_init(void)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
+ if (!get_usbdebug_from_cbmem(dbg_info))
+ return 0;
+#endif
+ enable_usbdebug();
+ return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
+}
diff --git a/src/drivers/usb/usb_ch9.h b/src/drivers/usb/usb_ch9.h
new file mode 100644
index 0000000..b0aa773
--- /dev/null
+++ b/src/drivers/usb/usb_ch9.h
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef USB_CH9_H
+#define USB_CH9_H
+
+#define USB_DIR_OUT 0 /* to device */
+#define USB_DIR_IN 0x80 /* to host */
+
+/*
+ * USB types, the second of three bRequestType fields
+ */
+#define USB_TYPE_MASK (0x03 << 5)
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS (0x01 << 5)
+#define USB_TYPE_VENDOR (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
+/*
+ * USB recipients, the third of three bRequestType fields
+ */
+#define USB_RECIP_MASK 0x1f
+#define USB_RECIP_DEVICE 0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT 0x02
+#define USB_RECIP_OTHER 0x03
+/* From Wireless USB 1.0 */
+#define USB_RECIP_PORT 0x04
+#define USB_RECIP_RPIPE 0x05
+
+/*
+ * Standard requests, for the bRequest field of a SETUP packet.
+ *
+ * These are qualified by the bRequestType field, so that for example
+ * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
+ * by a GET_STATUS request.
+ */
+#define USB_REQ_GET_STATUS 0x00
+#define USB_REQ_CLEAR_FEATURE 0x01
+#define USB_REQ_SET_FEATURE 0x03
+#define USB_REQ_SET_ADDRESS 0x05
+#define USB_REQ_GET_DESCRIPTOR 0x06
+#define USB_REQ_SET_DESCRIPTOR 0x07
+#define USB_REQ_GET_CONFIGURATION 0x08
+#define USB_REQ_SET_CONFIGURATION 0x09
+#define USB_REQ_GET_INTERFACE 0x0A
+#define USB_REQ_SET_INTERFACE 0x0B
+#define USB_REQ_SYNCH_FRAME 0x0C
+
+#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */
+#define USB_REQ_GET_ENCRYPTION 0x0E
+#define USB_REQ_RPIPE_ABORT 0x0E
+#define USB_REQ_SET_HANDSHAKE 0x0F
+#define USB_REQ_RPIPE_RESET 0x0F
+#define USB_REQ_GET_HANDSHAKE 0x10
+#define USB_REQ_SET_CONNECTION 0x11
+#define USB_REQ_SET_SECURITY_DATA 0x12
+#define USB_REQ_GET_SECURITY_DATA 0x13
+#define USB_REQ_SET_WUSB_DATA 0x14
+#define USB_REQ_LOOPBACK_DATA_WRITE 0x15
+#define USB_REQ_LOOPBACK_DATA_READ 0x16
+#define USB_REQ_SET_INTERFACE_DS 0x17
+
+#define USB_DT_DEBUG 0x0a
+
+#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
+
+struct usb_ctrlrequest {
+ u8 bRequestType;
+ u8 bRequest;
+ u16 wValue;
+ u16 wIndex;
+ u16 wLength;
+} __attribute__ ((packed));
+
+struct usb_debug_descriptor {
+ u8 bLength;
+ u8 bDescriptorType;
+
+ /* bulk endpoints with 8 byte maxpacket */
+ u8 bDebugInEndpoint;
+ u8 bDebugOutEndpoint;
+};
+
+#endif
+
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 5750b4a..c5f5297 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -28,7 +28,7 @@
#include <uart.h>
#endif
#if CONFIG_USBDEBUG && !defined(__ROMCC__)
-#include <usbdebug.h>
+#include <console/usb.h>
#endif
#if CONFIG_CONSOLE_NE2K
#include <console/ne2k.h>
diff --git a/src/include/console/usb.h b/src/include/console/usb.h
new file mode 100644
index 0000000..47f3d74
--- /dev/null
+++ b/src/include/console/usb.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef _CONSOLE_USB_H_
+#define _CONSOLE_USB_H_
+
+struct dbgp_pipe;
+
+int usbdebug_init(void);
+
+struct dbgp_pipe *dbgp_console_output(void);
+struct dbgp_pipe *dbgp_console_input(void);
+int dbgp_ep_is_active(struct dbgp_pipe *pipe);
+int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size);
+int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size);
+void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data);
+void usbdebug_tx_flush(struct dbgp_pipe *pipe);
+
+#endif /* _CONSOLE_USB_H_ */
diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h
new file mode 100644
index 0000000..4d3f746
--- /dev/null
+++ b/src/include/device/pci_ehci.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef _PCI_EHCI_H_
+#define _PCI_EHCI_H_
+
+#include <arch/io.h>
+#include <device/device.h>
+
+#define EHCI_BAR_INDEX 0x10
+#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
+
+pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx);
+unsigned long pci_ehci_base_regs(pci_devfn_t dev);
+void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
+void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
+
+#ifndef __PRE_RAM__
+#if !CONFIG_USBDEBUG
+#define pci_ehci_read_resources pci_dev_read_resources
+#else
+/* Relocation of EHCI Debug Port BAR
+ *
+ * PCI EHCI controller with Debug Port capability shall replace
+ * pci_dev_read_resources() with pci_ehci_read_resources() in its
+ * declaration of device_operations for .read_resources.
+ * This installs a hook to reconfigure usbdebug when resource allocator
+ * assigns a new BAR for the device.
+ */
+struct device;
+void pci_ehci_read_resources(struct device *dev);
+#endif
+#endif
+
+#endif /* _PCI_EHCI_H_ */
diff --git a/src/include/ehci.h b/src/include/ehci.h
deleted file mode 100644
index f920352..0000000
--- a/src/include/ehci.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * It was taken from the Linux kernel (include/linux/usb/ehci_def.h).
- *
- * Copyright (C) 2001-2002 David Brownell
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef EHCI_H
-#define EHCI_H
-
-/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
-
-/* Section 2.2 Host Controller Capability Registers */
-struct ehci_caps {
- /* these fields are specified as 8 and 16 bit registers,
- * but some hosts can't perform 8 or 16 bit PCI accesses.
- */
- u32 hc_capbase;
-#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
-#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
- u32 hcs_params; /* HCSPARAMS - offset 0x4 */
-#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
-#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
-#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
-#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
-#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
-#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
-#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
-
- u32 hcc_params; /* HCCPARAMS - offset 0x8 */
-/* EHCI 1.1 addendum */
-#define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19))
-#define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18))
-#define HCC_LPM(p) ((p)&(1 << 17))
-#define HCC_HW_PREFETCH(p) ((p)&(1 << 16))
-
-#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
-#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
-#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
-#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
-#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
-#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
- u8 portroute[8]; /* nibbles for routing - offset 0xC */
-} __attribute__ ((packed));
-
-
-/* Section 2.3 Host Controller Operational Registers */
-struct ehci_regs {
-
- /* USBCMD: offset 0x00 */
- u32 command;
-
-/* EHCI 1.1 addendum */
-#define CMD_HIRD (0xf<<24) /* host initiated resume duration */
-#define CMD_PPCEE (1<<15) /* per port change event enable */
-#define CMD_FSP (1<<14) /* fully synchronized prefetch */
-#define CMD_ASPE (1<<13) /* async schedule prefetch enable */
-#define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */
-/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
-#define CMD_PARK (1<<11) /* enable "park" on async qh */
-#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
-#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
-#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
-#define CMD_ASE (1<<5) /* async schedule enable */
-#define CMD_PSE (1<<4) /* periodic schedule enable */
-/* 3:2 is periodic frame list size */
-#define CMD_RESET (1<<1) /* reset HC not bus */
-#define CMD_RUN (1<<0) /* start/stop HC */
-
- /* USBSTS: offset 0x04 */
- u32 status;
-#define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */
-#define STS_ASS (1<<15) /* Async Schedule Status */
-#define STS_PSS (1<<14) /* Periodic Schedule Status */
-#define STS_RECL (1<<13) /* Reclamation */
-#define STS_HALT (1<<12) /* Not running (any reason) */
-/* some bits reserved */
- /* these STS_* flags are also intr_enable bits (USBINTR) */
-#define STS_IAA (1<<5) /* Interrupted on async advance */
-#define STS_FATAL (1<<4) /* such as some PCI access errors */
-#define STS_FLR (1<<3) /* frame list rolled over */
-#define STS_PCD (1<<2) /* port change detect */
-#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
-#define STS_INT (1<<0) /* "normal" completion (short, ...) */
-
- /* USBINTR: offset 0x08 */
- u32 intr_enable;
-
- /* FRINDEX: offset 0x0C */
- u32 frame_index; /* current microframe number */
- /* CTRLDSSEGMENT: offset 0x10 */
- u32 segment; /* address bits 63:32 if needed */
- /* PERIODICLISTBASE: offset 0x14 */
- u32 frame_list; /* points to periodic list */
- /* ASYNCLISTADDR: offset 0x18 */
- u32 async_next; /* address of next async queue head */
-
- u32 reserved[9];
-
- /* CONFIGFLAG: offset 0x40 */
- u32 configured_flag;
-#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
-
- /* PORTSC: offset 0x44 */
- u32 port_status[0]; /* up to N_PORTS */
-/* EHCI 1.1 addendum */
-#define PORTSC_SUSPEND_STS_ACK 0
-#define PORTSC_SUSPEND_STS_NYET 1
-#define PORTSC_SUSPEND_STS_STALL 2
-#define PORTSC_SUSPEND_STS_ERR 3
-
-#define PORT_DEV_ADDR (0x7f<<25) /* device address */
-#define PORT_SSTS (0x3<<23) /* suspend status */
-/* 31:23 reserved */
-#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
-#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
-#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
-/* 19:16 for port testing */
-#define PORT_TEST_PKT (0x4<<16) /* Port Test Control - packet test */
-#define PORT_LED_OFF (0<<14)
-#define PORT_LED_AMBER (1<<14)
-#define PORT_LED_GREEN (2<<14)
-#define PORT_LED_MASK (3<<14)
-#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
-#define PORT_POWER (1<<12) /* true: has power (see PPC) */
-#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
-/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
-/* 9 reserved */
-#define PORT_LPM (1<<9) /* LPM transaction */
-#define PORT_RESET (1<<8) /* reset port */
-#define PORT_SUSPEND (1<<7) /* suspend port */
-#define PORT_RESUME (1<<6) /* resume it */
-#define PORT_OCC (1<<5) /* over current change */
-#define PORT_OC (1<<4) /* over current active */
-#define PORT_PEC (1<<3) /* port enable change */
-#define PORT_PE (1<<2) /* port enable */
-#define PORT_CSC (1<<1) /* connect status change */
-#define PORT_CONNECT (1<<0) /* device connected */
-#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
-} __attribute__ ((packed));
-
-#define USBMODE 0x68 /* USB Device mode */
-#define USBMODE_SDIS (1<<3) /* Stream disable */
-#define USBMODE_BE (1<<2) /* BE/LE endianness select */
-#define USBMODE_CM_HC (3<<0) /* host controller mode */
-#define USBMODE_CM_IDLE (0<<0) /* idle state */
-
-/* Moorestown has some non-standard registers, partially due to the fact that
- * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
- * PORTSCx
- */
-#define HOSTPC0 0x84 /* HOSTPC extension */
-#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
-#define HOSTPC_PSPD (3<<25) /* Port speed detection */
-#define USBMODE_EX 0xc8 /* USB Device mode extension */
-#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */
-#define USBMODE_EX_HC (3<<0) /* host controller mode */
-#define TXFILLTUNING 0x24 /* TX FIFO Tuning register */
-#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
-
-/* Appendix C, Debug port ... intended for use with special "debug devices"
- * that can help if there's no serial console. (nonstandard enumeration.)
- */
-struct ehci_dbg_port {
- u32 control;
-#define DBGP_OWNER (1<<30)
-#define DBGP_ENABLED (1<<28)
-#define DBGP_DONE (1<<16)
-#define DBGP_INUSE (1<<10)
-#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
-# define DBGP_ERR_BAD 1
-# define DBGP_ERR_SIGNAL 2
-#define DBGP_ERROR (1<<6)
-#define DBGP_GO (1<<5)
-#define DBGP_OUT (1<<4)
-#define DBGP_LEN(x) (((x)>>0)&0x0f)
- u32 pids;
-#define DBGP_PID_GET(x) (((x)>>16)&0xff)
-#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
- u32 data03;
- u32 data47;
- u32 address;
-#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
-} __attribute__ ((packed));
-#endif
diff --git a/src/include/usb_ch9.h b/src/include/usb_ch9.h
deleted file mode 100644
index b0aa773..0000000
--- a/src/include/usb_ch9.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#ifndef USB_CH9_H
-#define USB_CH9_H
-
-#define USB_DIR_OUT 0 /* to device */
-#define USB_DIR_IN 0x80 /* to host */
-
-/*
- * USB types, the second of three bRequestType fields
- */
-#define USB_TYPE_MASK (0x03 << 5)
-#define USB_TYPE_STANDARD (0x00 << 5)
-#define USB_TYPE_CLASS (0x01 << 5)
-#define USB_TYPE_VENDOR (0x02 << 5)
-#define USB_TYPE_RESERVED (0x03 << 5)
-/*
- * USB recipients, the third of three bRequestType fields
- */
-#define USB_RECIP_MASK 0x1f
-#define USB_RECIP_DEVICE 0x00
-#define USB_RECIP_INTERFACE 0x01
-#define USB_RECIP_ENDPOINT 0x02
-#define USB_RECIP_OTHER 0x03
-/* From Wireless USB 1.0 */
-#define USB_RECIP_PORT 0x04
-#define USB_RECIP_RPIPE 0x05
-
-/*
- * Standard requests, for the bRequest field of a SETUP packet.
- *
- * These are qualified by the bRequestType field, so that for example
- * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
- * by a GET_STATUS request.
- */
-#define USB_REQ_GET_STATUS 0x00
-#define USB_REQ_CLEAR_FEATURE 0x01
-#define USB_REQ_SET_FEATURE 0x03
-#define USB_REQ_SET_ADDRESS 0x05
-#define USB_REQ_GET_DESCRIPTOR 0x06
-#define USB_REQ_SET_DESCRIPTOR 0x07
-#define USB_REQ_GET_CONFIGURATION 0x08
-#define USB_REQ_SET_CONFIGURATION 0x09
-#define USB_REQ_GET_INTERFACE 0x0A
-#define USB_REQ_SET_INTERFACE 0x0B
-#define USB_REQ_SYNCH_FRAME 0x0C
-
-#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */
-#define USB_REQ_GET_ENCRYPTION 0x0E
-#define USB_REQ_RPIPE_ABORT 0x0E
-#define USB_REQ_SET_HANDSHAKE 0x0F
-#define USB_REQ_RPIPE_RESET 0x0F
-#define USB_REQ_GET_HANDSHAKE 0x10
-#define USB_REQ_SET_CONNECTION 0x11
-#define USB_REQ_SET_SECURITY_DATA 0x12
-#define USB_REQ_GET_SECURITY_DATA 0x13
-#define USB_REQ_SET_WUSB_DATA 0x14
-#define USB_REQ_LOOPBACK_DATA_WRITE 0x15
-#define USB_REQ_LOOPBACK_DATA_READ 0x16
-#define USB_REQ_SET_INTERFACE_DS 0x17
-
-#define USB_DT_DEBUG 0x0a
-
-#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
-
-struct usb_ctrlrequest {
- u8 bRequestType;
- u8 bRequest;
- u16 wValue;
- u16 wIndex;
- u16 wLength;
-} __attribute__ ((packed));
-
-struct usb_debug_descriptor {
- u8 bLength;
- u8 bDescriptorType;
-
- /* bulk endpoints with 8 byte maxpacket */
- u8 bDebugInEndpoint;
- u8 bDebugOutEndpoint;
-};
-
-#endif
-
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
deleted file mode 100644
index 926d658..0000000
--- a/src/include/usbdebug.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#ifndef USBDEBUG_H
-#define USBDEBUG_H
-
-#define EHCI_BAR_INDEX 0x10
-#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
-
-typedef u32 pci_devfn_t;
-pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx);
-unsigned long pci_ehci_base_regs(pci_devfn_t dev);
-void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
-
-#ifndef __PRE_RAM__
-#if !CONFIG_USBDEBUG
-#define pci_ehci_read_resources pci_dev_read_resources
-#else
-/* Relocation of EHCI Debug Port BAR
- *
- * PCI EHCI controller with Debug Port capability shall replace
- * pci_dev_read_resources() with pci_ehci_read_resources() in its
- * declaration of device_operations for .read_resources.
- * This installs a hook to reconfigure usbdebug when resource allocator
- * assigns a new BAR for the device.
- */
-struct device;
-void pci_ehci_read_resources(struct device *dev);
-#endif
-#endif
-
-struct dbgp_pipe;
-
-int usbdebug_init(void);
-
-struct dbgp_pipe *dbgp_console_output(void);
-struct dbgp_pipe *dbgp_console_input(void);
-int dbgp_ep_is_active(struct dbgp_pipe *pipe);
-int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size);
-int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size);
-void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data);
-void usbdebug_tx_flush(struct dbgp_pipe *pipe);
-#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 18b30ef..b1b4748 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -49,7 +49,6 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
romstage-$(CONFIG_SPKMODEM) += spkmodem.c
-romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usbdebug.c
ifeq ($(CONFIG_EARLY_CBMEM_INIT),y)
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
@@ -92,7 +91,6 @@ romstage-y += clog2.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
-ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
ramstage-$(CONFIG_SPKMODEM) += spkmodem.c
ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
ramstage-$(CONFIG_TRACE) += trace.c
diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
deleted file mode 100644
index 885599b..0000000
--- a/src/lib/usbdebug.c
+++ /dev/null
@@ -1,1043 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Eric Biederman (ebiederm(a)xmission.com)
- * Copyright (C) 2007 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#include <stddef.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-#include <arch/byteorder.h>
-#include <arch/early_variables.h>
-#include <string.h>
-#include <cbmem.h>
-
-#include <usb_ch9.h>
-#include <ehci.h>
-#include <usbdebug.h>
-
-
-#define DBGP_EP_VALID (1<<0)
-#define DBGP_EP_ENABLED (1<<1)
-#define DBGP_EP_BUSY (1<<2)
-#define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED)
-
-struct dbgp_pipe
-{
- u8 devnum;
- u8 endpoint;
- u8 pid;
- u8 status;
- int timeout;
-
- u8 bufidx;
- char buf[8];
-};
-
-#define DBGP_MAX_ENDPOINTS 4
-#define DBGP_SETUP_EP0 0 /* Compulsory endpoint 0. */
-#define DBGP_CONSOLE_EPOUT 1
-#define DBGP_CONSOLE_EPIN 2
-
-struct ehci_debug_info {
- void *ehci_caps;
- void *ehci_regs;
- void *ehci_debug;
-
- struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS];
-};
-
-#if CONFIG_DEBUG_USBDEBUG
-static void dbgp_print_data(struct ehci_dbg_port *ehci_debug);
-static int dbgp_enabled(void);
-# define dprintk(LEVEL, args...) \
- do { if (!dbgp_enabled()) printk(LEVEL, ##args); } while (0)
-#else
-# define dbgp_print_data(x) do {} while(0)
-# define dprintk(LEVEL, args...) do {} while(0)
-#endif
-
-#define USB_DEBUG_DEVNUM 127
-
-#define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f))
-/*
- * USB Packet IDs (PIDs)
- */
-
-/* token */
-#define USB_PID_OUT 0xe1
-#define USB_PID_IN 0x69
-#define USB_PID_SOF 0xa5
-#define USB_PID_SETUP 0x2d
-/* handshake */
-#define USB_PID_ACK 0xd2
-#define USB_PID_NAK 0x5a
-#define USB_PID_STALL 0x1e
-#define USB_PID_NYET 0x96
-/* data */
-#define USB_PID_DATA0 0xc3
-#define USB_PID_DATA1 0x4b
-#define USB_PID_DATA2 0x87
-#define USB_PID_MDATA 0x0f
-/* Special */
-#define USB_PID_PREAMBLE 0x3c
-#define USB_PID_ERR 0x3c
-#define USB_PID_SPLIT 0x78
-#define USB_PID_PING 0xb4
-#define USB_PID_UNDEF_0 0xf0
-
-#define USB_PID_DATA_TOGGLE 0x88
-#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
-
-#define PCI_CAP_ID_EHCI_DEBUG 0xa
-
-#define HUB_ROOT_RESET_TIME 50 /* times are in msec */
-#define HUB_SHORT_RESET_TIME 10
-#define HUB_LONG_RESET_TIME 200
-#define HUB_RESET_TIMEOUT 500
-
-#define DBGP_MICROFRAME_TIMEOUT_LOOPS 1000
-#define DBGP_MICROFRAME_RETRIES 10
-#define DBGP_MAX_PACKET 8
-
-static struct ehci_debug_info glob_dbg_info CAR_GLOBAL;
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
-static struct device_operations *ehci_drv_ops;
-static struct device_operations ehci_dbg_ops;
-#endif
-
-static inline struct ehci_debug_info *dbgp_ehci_info(void)
-{
- return car_get_var_ptr(&glob_dbg_info);
-}
-
-static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
-{
- u32 ctrl;
- int loop = 0;
-
- do {
- ctrl = read32((unsigned long)&ehci_debug->control);
- /* Stop when the transaction is finished */
- if (ctrl & DBGP_DONE)
- break;
- } while (++loop < DBGP_MICROFRAME_TIMEOUT_LOOPS);
-
- if (! (ctrl & DBGP_DONE)) {
- dprintk(BIOS_ERR, "dbgp_wait_until_complete: retry timeout.\n");
- return -DBGP_ERR_SIGNAL;
- }
-
- /* Now that we have observed the completed transaction,
- * clear the done bit.
- */
- write32((unsigned long)&ehci_debug->control, ctrl | DBGP_DONE);
- return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
-}
-
-static void dbgp_breath(void)
-{
- /* Sleep to give the debug port a chance to breathe */
-}
-
-static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
- unsigned ctrl, const int timeout)
-{
- u32 rd_ctrl, rd_pids;
- u32 ctrl_prev = 0, pids_prev = 0;
- u8 lpid;
- int ret, host_retries;
- int loop;
-
- loop = 0;
-device_retry:
- host_retries = 0;
- if (loop++ >= timeout)
- return -DBGP_ERR_BAD;
-
-host_retry:
- if (host_retries++ >= DBGP_MICROFRAME_RETRIES)
- return -DBGP_ERR_BAD;
- if (loop == 1 || host_retries > 1)
- dprintk(BIOS_SPEW, "dbgp: start (@ %3d,%d) ctrl=%08x\n",
- loop, host_retries, ctrl | DBGP_GO);
- write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO);
- ret = dbgp_wait_until_complete(ehci_debug);
- rd_ctrl = read32((unsigned long)&ehci_debug->control);
- rd_pids = read32((unsigned long)&ehci_debug->pids);
-
- if (rd_ctrl != ctrl_prev || rd_pids != pids_prev || (ret<0)) {
- ctrl_prev = rd_ctrl;
- pids_prev = rd_pids;
- dprintk(BIOS_SPEW, "dbgp: status (@ %3d,%d) ctrl=%08x pids=%08x ret=%d\n",
- loop, host_retries, rd_ctrl, rd_pids, ret);
- }
-
- /* Controller hardware failure. */
- if (ret == -DBGP_ERR_SIGNAL) {
- return ret;
-
- /* Bus failure (corrupted microframe). */
- } else if (ret == -DBGP_ERR_BAD) {
- goto host_retry;
- }
-
- lpid = DBGP_PID_GET(rd_pids);
-
- /* If I get an ACK or in-sync DATA PID, we are done. */
- if ((lpid == USB_PID_ACK) || (lpid == pipe->pid)) {
- if (DBGP_LEN(rd_ctrl))
- pipe->pid ^= USB_PID_DATA_TOGGLE;
- }
-
- /* If the port is getting full or it has dropped data
- * start pacing ourselves, not necessary but it's friendly.
- */
- else if (lpid == USB_PID_NYET) {
- dbgp_breath();
- goto device_retry;
- }
-
- /* If I get a NACK or out-of-sync DATA PID, reissue the transmission. */
- else if ((lpid == USB_PID_NAK) || (lpid == (pipe->pid ^ USB_PID_DATA_TOGGLE))) {
- goto device_retry;
- }
-
- /* Abort on STALL handshake for endpoint 0.*/
- else if ((lpid == USB_PID_STALL) && (pipe->endpoint == 0x0)) {
- ret = -DBGP_ERR_BAD;
- }
-
- dbgp_print_data(ehci_debug);
-
- return ret;
-}
-
-static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int size)
-{
- const unsigned char *bytes = buf;
- u32 lo, hi;
- int i;
-
- lo = hi = 0;
- for (i = 0; i < 4 && i < size; i++)
- lo |= bytes[i] << (8*i);
- for (; i < 8 && i < size; i++)
- hi |= bytes[i] << (8*(i - 4));
- write32((unsigned long)&ehci_debug->data03, lo);
- write32((unsigned long)&ehci_debug->data47, hi);
-}
-
-static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
-{
- unsigned char *bytes = buf;
- u32 lo, hi;
- int i;
-
- lo = read32((unsigned long)&ehci_debug->data03);
- hi = read32((unsigned long)&ehci_debug->data47);
- for (i = 0; i < 4 && i < size; i++)
- bytes[i] = (lo >> (8*i)) & 0xff;
- for (; i < 8 && i < size; i++)
- bytes[i] = (hi >> (8*(i - 4))) & 0xff;
-}
-
-#if CONFIG_DEBUG_USBDEBUG
-static void dbgp_print_data(struct ehci_dbg_port *ehci_debug)
-{
- u32 ctrl = read32((unsigned long)&ehci_debug->control);
- u32 lo = read32((unsigned long)&ehci_debug->data03);
- u32 hi = read32((unsigned long)&ehci_debug->data47);
- int len = DBGP_LEN(ctrl);
- if (len) {
- int i;
- dprintk(BIOS_SPEW, "dbgp: buf:");
- for (i = 0; i < 4 && i < len; i++)
- dprintk(BIOS_SPEW, " %02x", (lo >> (8*i)) & 0xff);
- for (; i < 8 && i < len; i++)
- dprintk(BIOS_SPEW, " %02x", (hi >> (8*(i - 4))) & 0xff);
- dprintk(BIOS_SPEW, "\n");
- }
-}
-#endif
-
-static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
- const char *bytes, int size)
-{
- u32 pids, addr, ctrl;
- int ret;
-
- if (size > DBGP_MAX_PACKET)
- return -1;
-
- addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
- pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
-
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl = DBGP_LEN_UPDATE(ctrl, size);
- ctrl |= DBGP_OUT;
-
- dbgp_set_data(ehci_debug, bytes, size);
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
-
- ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
-
- return ret;
-}
-
-int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
- return dbgp_bulk_write(dbg_info->ehci_debug, pipe, bytes, size);
-}
-
-static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
- void *data, int size)
-{
- u32 pids, addr, ctrl;
- int ret;
-
- if (size > DBGP_MAX_PACKET)
- return -1;
-
- addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
- pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
-
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl = DBGP_LEN_UPDATE(ctrl, size);
- ctrl &= ~DBGP_OUT;
-
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
- ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
- if (ret < 0)
- return ret;
-
- if (size > ret)
- size = ret;
- dbgp_get_data(ehci_debug, data, size);
- return ret;
-}
-
-int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
- return dbgp_bulk_read(dbg_info->ehci_debug, pipe, data, size);
-}
-
-static void dbgp_mdelay(int ms)
-{
- int i;
-
- while (ms--) {
- for (i = 0; i < 1000; i++)
- inb(0x80);
- }
-}
-
-static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype,
- int request, int value, int index, void *data, int size)
-{
- struct ehci_debug_info *info = dbgp_ehci_info();
- struct dbgp_pipe *pipe = &info->ep_pipe[DBGP_SETUP_EP0];
- u32 pids, addr, ctrl;
- struct usb_ctrlrequest req;
- int read;
- int ret, ret2;
-
- read = (requesttype & USB_DIR_IN) != 0;
- if (size > DBGP_MAX_PACKET)
- return -1;
-
- /* Compute the control message */
- req.bRequestType = requesttype;
- req.bRequest = request;
- req.wValue = cpu_to_le16(value);
- req.wIndex = cpu_to_le16(index);
- req.wLength = cpu_to_le16(size);
-
- pipe->devnum = devnum;
- pipe->endpoint = 0;
- pipe->pid = USB_PID_DATA0;
- pipe->timeout = 1000;
- addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
- pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP);
-
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
- ctrl |= DBGP_OUT;
-
- /* Setup stage */
- dbgp_set_data(ehci_debug, &req, sizeof(req));
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
- ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, 1);
- if (ret < 0)
- return ret;
-
- /* Data stage (optional) */
- if (read && size)
- ret = dbgp_bulk_read(ehci_debug, pipe, data, size);
- else if (!read && size)
- ret = dbgp_bulk_write(ehci_debug, pipe, data, size);
-
- /* Status stage in opposite direction */
- pipe->pid = USB_PID_DATA1;
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl = DBGP_LEN_UPDATE(ctrl, 0);
- if (read) {
- pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
- ctrl |= DBGP_OUT;
- } else {
- pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
- ctrl &= ~DBGP_OUT;
- }
-
- write32((unsigned long)&ehci_debug->pids, pids);
- ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
- if (ret2 < 0)
- return ret2;
-
- return ret;
-}
-
-static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
-{
- u32 portsc;
- u32 delay_time, delay_ms;
- int loop;
-
- /* Reset the usb debug port */
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
- portsc &= ~PORT_PE;
- portsc |= PORT_RESET;
- write32((unsigned long)&ehci_regs->port_status[port - 1], portsc);
-
- delay_ms = HUB_ROOT_RESET_TIME;
- for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
- delay_time += delay_ms) {
- dbgp_mdelay(delay_ms);
-
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
- if (portsc & PORT_RESET) {
- /* force reset to complete */
- loop = 2;
- write32((unsigned long)&ehci_regs->port_status[port - 1],
- portsc & ~(PORT_RWC_BITS | PORT_RESET));
- do {
- dbgp_mdelay(delay_ms);
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
- delay_time += delay_ms;
- } while ((portsc & PORT_RESET) && (--loop > 0));
- if (!loop) {
- printk(BIOS_DEBUG, "ehci_reset_port forced done");
- }
- }
-
- /* Device went away? */
- if (!(portsc & PORT_CONNECT))
- return -1; //-ENOTCONN;
-
- /* bomb out completely if something weird happened */
- if ((portsc & PORT_CSC))
- return -2; //-EINVAL;
-
- /* If we've finished resetting, then break out of the loop */
- if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
- return 0;
- }
- return -3; //-EBUSY;
-}
-
-static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
-{
- u32 status;
- int ret, reps;
-
- for (reps = 0; reps < 3; reps++) {
- dbgp_mdelay(100);
- status = read32((unsigned long)&ehci_regs->status);
- if (status & STS_PCD) {
- ret = ehci_reset_port(ehci_regs, port);
- if (ret == 0)
- return 0;
- }
- }
- return -1; //-ENOTCONN;
-}
-
-#define USB_HUB_PORT_CONNECTION 0
-#define USB_HUB_PORT_ENABLED 1
-#define USB_HUB_PORT_RESET 4
-#define USB_HUB_PORT_POWER 8
-#define USB_HUB_C_PORT_CONNECTION 16
-#define USB_HUB_C_PORT_RESET 20
-
-#if CONFIG_USBDEBUG_OPTIONAL_HUB_PORT
-
-static int hub_port_status(const char * buf, int feature)
-{
- return !!(buf[feature>>3] & (1<<(feature&0x7)));
-}
-
-static int dbgp_hub_enable(struct ehci_dbg_port *ehci_debug, unsigned int port)
-{
- const u8 hub_addr = USB_DEBUG_DEVNUM-1;
- char status[8];
- int ret, loop;
-
- /* Move hub to address 126. */
- ret = dbgp_control_msg(ehci_debug, 0,
- USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_SET_ADDRESS, hub_addr, 0, NULL, 0);
- if (ret < 0)
- goto err;
-
- /* Enter configured state on hub. */
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0);
- if (ret < 0)
- goto err;
-
- /* Set PORT_POWER, poll for PORT_CONNECTION. */
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_SET_FEATURE, USB_HUB_PORT_POWER, port, NULL, 0);
- if (ret < 0)
- goto err;
-
- loop = 100;
- do {
- dbgp_mdelay(10);
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_GET_STATUS, 0, port, status, 4);
- if (ret < 0)
- goto err;
- if (hub_port_status(status, USB_HUB_PORT_CONNECTION))
- break;
- } while (--loop);
- if (! loop)
- goto err;
-
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_CLEAR_FEATURE, USB_HUB_C_PORT_CONNECTION, port, NULL, 0);
- if (ret < 0)
- goto err;
-
-
- /* Set PORT_RESET, poll for C_PORT_RESET. */
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_SET_FEATURE, USB_HUB_PORT_RESET, port, NULL, 0);
- if (ret < 0)
- goto err;
-
- loop = 100;
- do {
- dbgp_mdelay(10);
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_GET_STATUS, 0, port, status, 4);
- if (ret < 0)
- goto err;
- if (hub_port_status(status, USB_HUB_C_PORT_RESET))
- break;
- } while (--loop);
- if (! loop)
- goto err;
-
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_CLEAR_FEATURE, USB_HUB_C_PORT_RESET, port, NULL, 0);
- if (ret < 0)
- goto err;
-
- if (hub_port_status(status, USB_HUB_PORT_ENABLED))
- return 0;
-err:
- return -1;
-}
-#endif /* CONFIG_USBDEBUG_OPTIONAL_HUB_PORT */
-
-static void enable_usbdebug(void)
-{
-#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE
- pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
- pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR);
-#endif
-}
-
-static void set_debug_port(unsigned int port)
-{
- pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
- pci_ehci_dbg_set_port(dbg_dev, port);
-}
-
-static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info)
-{
- struct ehci_caps *ehci_caps;
- struct ehci_regs *ehci_regs;
- struct ehci_dbg_port *ehci_debug;
-
- struct usb_debug_descriptor dbgp_desc;
- u32 cmd, ctrl, status, portsc, hcs_params;
- u32 debug_port, new_debug_port = 0, n_ports;
- u32 devnum;
- int ret, i, configured;
- int loop;
- int port_map_tried;
- int playtimes = 3;
-
- ehci_caps = (struct ehci_caps *)ehci_bar;
- ehci_regs = (struct ehci_regs *)(ehci_bar +
- HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
- ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
- info->ehci_debug = (void *)0;
- memset(&info->ep_pipe, 0, sizeof (info->ep_pipe));
-
- if (CONFIG_USBDEBUG_DEFAULT_PORT > 0)
- set_debug_port(CONFIG_USBDEBUG_DEFAULT_PORT);
- else
- set_debug_port(1);
-
-try_next_time:
- port_map_tried = 0;
-
-try_next_port:
- hcs_params = read32((unsigned long)&ehci_caps->hcs_params);
- debug_port = HCS_DEBUG_PORT(hcs_params);
- n_ports = HCS_N_PORTS(hcs_params);
-
- dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar);
- dprintk(BIOS_INFO, "debug_port: %d\n", debug_port);
- dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
-
- for (i = 1; i <= n_ports; i++) {
- portsc = read32((unsigned long)&ehci_regs->port_status[i-1]);
- dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
- }
-
- if(port_map_tried && (new_debug_port != debug_port)) {
- if(--playtimes) {
- set_debug_port(debug_port);
- goto try_next_time;
- }
- return -1;
- }
-
- /* Wait until the controller is halted */
- status = read32((unsigned long)&ehci_regs->status);
- if (!(status & STS_HALT)) {
- cmd = read32((unsigned long)&ehci_regs->command);
- cmd &= ~CMD_RUN;
- write32((unsigned long)&ehci_regs->command, cmd);
- loop = 100;
- do {
- dbgp_mdelay(10);
- status = read32((unsigned long)&ehci_regs->status);
- } while (!(status & STS_HALT) && (--loop > 0));
- if (status & STS_HALT)
- dprintk(BIOS_INFO, "EHCI controller halted successfully.\n");
- else
- dprintk(BIOS_INFO, "EHCI controller is not halted. Reset may fail.\n");
- }
-
- loop = 100;
- /* Reset the EHCI controller */
- cmd = read32((unsigned long)&ehci_regs->command);
- cmd |= CMD_RESET;
- write32((unsigned long)&ehci_regs->command, cmd);
- do {
- dbgp_mdelay(10);
- cmd = read32((unsigned long)&ehci_regs->command);
- } while ((cmd & CMD_RESET) && (--loop > 0));
-
- if(!loop) {
- dprintk(BIOS_INFO, "Could not reset EHCI controller.\n");
- // on some systems it works without succeeding here.
- // return -2;
- } else {
- dprintk(BIOS_INFO, "EHCI controller reset successfully.\n");
- }
-
- /* Claim ownership, but do not enable yet */
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl |= DBGP_OWNER;
- ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
- write32((unsigned long)&ehci_debug->control, ctrl);
-
- /* Start EHCI controller */
- cmd = read32((unsigned long)&ehci_regs->command);
- cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
- cmd |= CMD_RUN;
- write32((unsigned long)&ehci_regs->command, cmd);
-
- /* Ensure everything is routed to the EHCI */
- write32((unsigned long)&ehci_regs->configured_flag, FLAG_CF);
-
- /* Wait until the controller is no longer halted */
- loop = 10;
- do {
- dbgp_mdelay(10);
- status = read32((unsigned long)&ehci_regs->status);
- } while ((status & STS_HALT) && (--loop > 0));
-
- if(!loop) {
- dprintk(BIOS_INFO, "EHCI could not be started.\n");
- return -3;
- }
- dprintk(BIOS_INFO, "EHCI started.\n");
-
- /* Wait for a device to show up in the debug port */
- ret = ehci_wait_for_port(ehci_regs, debug_port);
- if (ret < 0) {
- dprintk(BIOS_INFO, "No device found in debug port %d\n", debug_port);
- goto next_debug_port;
- }
- dprintk(BIOS_INFO, "EHCI done waiting for port.\n");
-
- /* Enable the debug port */
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl |= DBGP_CLAIM;
- write32((unsigned long)&ehci_debug->control, ctrl);
- ctrl = read32((unsigned long)&ehci_debug->control);
- if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
- dprintk(BIOS_INFO, "No device in EHCI debug port.\n");
- write32((unsigned long)&ehci_debug->control, ctrl & ~DBGP_CLAIM);
- ret = -4;
- goto err;
- }
- dprintk(BIOS_INFO, "EHCI debug port enabled.\n");
-
- /* Completely transfer the debug device to the debug controller */
- portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]);
- portsc &= ~PORT_PE;
- write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc);
-
- dbgp_mdelay(100);
-
-#if CONFIG_USBDEBUG_OPTIONAL_HUB_PORT
- ret = dbgp_hub_enable(ehci_debug, CONFIG_USBDEBUG_OPTIONAL_HUB_PORT);
- if (ret < 0) {
- dprintk(BIOS_INFO, "Could not enable USB hub on debug port.\n");
- ret = -6;
- goto err;
- }
-#endif
-
- /* Find the debug device and make it device number 127 */
- devnum = 0;
-debug_dev_retry:
- memset(&dbgp_desc, 0, sizeof(dbgp_desc));
- ret = dbgp_control_msg(ehci_debug, devnum,
- USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
- &dbgp_desc, sizeof(dbgp_desc));
- if (ret == sizeof(dbgp_desc)) {
- if (dbgp_desc.bLength == sizeof(dbgp_desc) && dbgp_desc.bDescriptorType==USB_DT_DEBUG)
- goto debug_dev_found;
- else
- dprintk(BIOS_INFO, "Invalid debug device descriptor.\n");
- }
- if (devnum == 0) {
- devnum = USB_DEBUG_DEVNUM;
- goto debug_dev_retry;
- } else {
- dprintk(BIOS_INFO, "Could not find attached debug device.\n");
- ret = -5;
- goto err;
- }
-debug_dev_found:
-
- /* Move the device to 127 if it isn't already there */
- if (devnum != USB_DEBUG_DEVNUM) {
- ret = dbgp_control_msg(ehci_debug, devnum,
- USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
- if (ret < 0) {
- dprintk(BIOS_INFO, "Could not move attached device to %d.\n",
- USB_DEBUG_DEVNUM);
- ret = -7;
- goto err;
- }
- devnum = USB_DEBUG_DEVNUM;
- dprintk(BIOS_INFO, "EHCI debug device renamed to 127.\n");
- }
-
- /* Enable the debug interface */
- ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
- USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
- if (ret < 0) {
- dprintk(BIOS_INFO, "Could not enable EHCI debug device.\n");
- ret = -8;
- goto err;
- }
- dprintk(BIOS_INFO, "EHCI debug interface enabled.\n");
-
- /* Prepare endpoint pipes. */
- for (i=1; i<DBGP_MAX_ENDPOINTS; i++) {
- info->ep_pipe[i].devnum = USB_DEBUG_DEVNUM;
- info->ep_pipe[i].pid = USB_PID_DATA0;
- info->ep_pipe[i].timeout = 1000;
- }
- info->ep_pipe[DBGP_CONSOLE_EPOUT].endpoint = dbgp_desc.bDebugOutEndpoint;
- info->ep_pipe[DBGP_CONSOLE_EPIN].endpoint = dbgp_desc.bDebugInEndpoint;
-
- /* Perform a small write. */
- configured = 0;
-small_write:
- ret = dbgp_bulk_write(ehci_debug, &info->ep_pipe[DBGP_CONSOLE_EPOUT], "USB\r\n",5);
- if (ret < 0) {
- dprintk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret);
- if (!configured) {
- /* Send Set Configure request to device. This is required for FX2
- (CY7C68013) to transfer from USB state Addressed to Configured,
- only then endpoints other than 0 are enabled. */
- if (dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
- USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0) >= 0) {
- configured = 1;
- goto small_write;
- }
- }
- ret = -9;
- goto err;
- }
- dprintk(BIOS_INFO, "Test write done\n");
-
- info->ehci_caps = ehci_caps;
- info->ehci_regs = ehci_regs;
- info->ehci_debug = ehci_debug;
-
- info->ep_pipe[DBGP_SETUP_EP0].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
- info->ep_pipe[DBGP_CONSOLE_EPOUT].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
- info->ep_pipe[DBGP_CONSOLE_EPIN].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
- return 0;
-err:
- /* Things didn't work so remove my claim */
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
- write32((unsigned long)(unsigned long)&ehci_debug->control, ctrl);
- //return ret;
-
-next_debug_port:
-#if CONFIG_USBDEBUG_DEFAULT_PORT==0
- port_map_tried |= (1 << (debug_port - 1));
- new_debug_port = ((debug_port-1 + 1) % n_ports) + 1;
- if (port_map_tried != ((1 << n_ports) - 1)) {
- set_debug_port(new_debug_port);
- goto try_next_port;
- }
- if (--playtimes) {
- set_debug_port(new_debug_port);
- goto try_next_time;
- }
-#else
- if (0)
- goto try_next_port;
- if (--playtimes)
- goto try_next_time;
-#endif
-
- return -10;
-}
-
-#if CONFIG_DEBUG_USBDEBUG
-static int dbgp_enabled(void)
-{
- struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
- return (globals->status & DBGP_EP_ENABLED);
-}
-#endif
-
-static int dbgp_try_get(struct dbgp_pipe *pipe)
-{
- struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
- if (!dbgp_ep_is_active(pipe) || (globals->status & DBGP_EP_BUSY))
- return 0;
- globals->status |= DBGP_EP_BUSY;
- pipe->status |= DBGP_EP_BUSY;
- return 1;
-}
-
-static void dbgp_put(struct dbgp_pipe *pipe)
-{
- struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
- globals->status &= ~DBGP_EP_BUSY;
- pipe->status &= ~DBGP_EP_BUSY;
-}
-
-void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data)
-{
- if (!dbgp_try_get(pipe))
- return;
- pipe->buf[pipe->bufidx++] = data;
- if (pipe->bufidx >= 8) {
- dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx);
- pipe->bufidx = 0;
- }
- dbgp_put(pipe);
-}
-
-void usbdebug_tx_flush(struct dbgp_pipe *pipe)
-{
- if (!dbgp_try_get(pipe))
- return;
- if (pipe->bufidx > 0) {
- dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx);
- pipe->bufidx = 0;
- }
- dbgp_put(pipe);
-}
-
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
-static void usbdebug_re_enable(unsigned ehci_base)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
- unsigned diff;
- int i;
-
- if (!dbg_info->ehci_debug)
- return;
-
- diff = (unsigned)dbg_info->ehci_caps - ehci_base;
- dbg_info->ehci_regs -= diff;
- dbg_info->ehci_debug -= diff;
- dbg_info->ehci_caps = (void*)ehci_base;
-
- for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
- dbg_info->ep_pipe[i].status |= DBGP_EP_ENABLED;
-}
-
-static void usbdebug_disable(void)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
- int i;
- for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
- dbg_info->ep_pipe[i].status &= ~DBGP_EP_ENABLED;
-}
-
-static void pci_ehci_set_resources(struct device *dev)
-{
- struct resource *res;
-
- printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev));
- usbdebug_disable();
-
- if (ehci_drv_ops->set_resources)
- ehci_drv_ops->set_resources(dev);
- res = find_resource(dev, EHCI_BAR_INDEX);
- if (!res)
- return;
-
- usbdebug_re_enable((u32)res->base);
- report_resource_stored(dev, res, "");
- printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev));
-}
-
-void pci_ehci_read_resources(struct device *dev)
-{
- pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
-
- if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) {
- memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops));
- ehci_drv_ops = dev->ops;
- ehci_dbg_ops.set_resources = pci_ehci_set_resources;
- dev->ops = &ehci_dbg_ops;
- printk(BIOS_DEBUG, "%s EHCI BAR hook registered\n", dev_path(dev));
- } else {
- printk(BIOS_DEBUG, "More than one caller of %s from %s\n", __func__, dev_path(dev));
- }
-
- pci_dev_read_resources(dev);
-}
-#endif
-
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
-static int get_usbdebug_from_cbmem(struct ehci_debug_info *info)
-{
- struct ehci_debug_info *dbg_info_cbmem;
-
- dbg_info_cbmem = cbmem_find(CBMEM_ID_EHCI_DEBUG);
- if (dbg_info_cbmem == NULL)
- return -1;
-
- memcpy(info, dbg_info_cbmem, sizeof (*info));
- printk(BIOS_DEBUG, "EHCI debug port found in CBMEM.\n");
-
- return 0;
-}
-
-#elif defined(__PRE_RAM__)
-static void migrate_ehci_debug(void)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
- struct ehci_debug_info *dbg_info_cbmem;
-
- dbg_info_cbmem = cbmem_add(CBMEM_ID_EHCI_DEBUG, sizeof(*dbg_info));
- if (dbg_info_cbmem == NULL)
- return;
-
- memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info));
-}
-CAR_MIGRATE(migrate_ehci_debug);
-#endif
-
-unsigned long pci_ehci_base_regs(pci_devfn_t sdev)
-{
-#ifdef __SIMPLE_DEVICE__
- unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f;
-#else
- device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
- unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f;
-#endif
- return base + HC_LENGTH(read32(base));
-}
-
-int dbgp_ep_is_active(struct dbgp_pipe *pipe)
-{
- return (pipe->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED);
-}
-
-struct dbgp_pipe *dbgp_console_output(void)
-{
- return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPOUT];
-}
-
-struct dbgp_pipe *dbgp_console_input(void)
-{
- return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPIN];
-}
-
-int usbdebug_init(void)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
-
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
- if (!get_usbdebug_from_cbmem(dbg_info))
- return 0;
-#endif
- enable_usbdebug();
- return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
-}
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index cce3925..258267e 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -22,7 +22,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "hudson.h"
diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c
index f5d0d4c..36eff6e 100644
--- a/src/southbridge/amd/agesa/hudson/usb.c
+++ b/src/southbridge/amd/agesa/hudson/usb.c
@@ -22,7 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
#include "hudson.h"
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index e2ecdc3..b03f13a 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -25,7 +25,7 @@
#include <device/smbus.h> /* smbus_bus_operations */
#include <pc80/mc146818rtc.h>
#include <console/console.h> /* printk */
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include "lpc.h" /* lpc_read_resources */
#include "Platform.h" /* Platfrom Specific Definitions */
#include "sb_cimx.h"
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 90b26ae..3a534cd 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -26,7 +26,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h> /* printk */
#include <arch/acpi.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include "lpc.h" /* lpc_read_resources */
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
#include "cfg.h" /* sb800 Cimx configuration */
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index d2ce72c..3cd603c 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -24,7 +24,7 @@
#include <device/smbus.h> /* smbus_bus_operations */
#include <pc80/mc146818rtc.h>
#include <console/console.h> /* printk */
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include "lpc.h" /* lpc_read_resources */
#include "SbPlatform.h" /* Platfrom Specific Definitions */
#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index 09fce2f..0f25ead 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -22,7 +22,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "sb600.h"
diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c
index d551661..d55f561 100644
--- a/src/southbridge/amd/sb600/usb.c
+++ b/src/southbridge/amd/sb600/usb.c
@@ -22,7 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
#include "sb600.h"
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 57798c1..3d23da0 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -23,7 +23,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "sb700.h"
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
index d3a9f3e..77dcf2e 100644
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -22,7 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
#include "sb700.h"
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index 34d7608..74e3d33 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -22,7 +22,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "sb800.h"
diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c
index 305a7e6..9304344 100644
--- a/src/southbridge/amd/sb800/usb.c
+++ b/src/southbridge/amd/sb800/usb.c
@@ -22,7 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
#include "sb800.h"
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index d2bf690..78f92d9 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
static void usb_ehci_init(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 2b8ae28..19c419f 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
static void usb_xhci_init(struct device *dev)
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index 9fe22cd..fecd716 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -23,7 +23,7 @@
#include <stdint.h>
#include <arch/io.h>
#include <console/console.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c
index 5dd5866..9e5c48e 100644
--- a/src/southbridge/intel/i82801dx/usb2.c
+++ b/src/southbridge/intel/i82801dx/usb2.c
@@ -24,7 +24,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include "i82801dx.h"
static void usb2_init(struct device *dev)
diff --git a/src/southbridge/intel/i82801ex/ehci.c b/src/southbridge/intel/i82801ex/ehci.c
index 045840a..28164c5 100644
--- a/src/southbridge/intel/i82801ex/ehci.c
+++ b/src/southbridge/intel/i82801ex/ehci.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include "i82801ex.h"
static void ehci_init(struct device *dev)
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index 8dcda39..bb176c7 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
static void usb_ehci_init(struct device *dev)
diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c
index b6c0edd..6276995 100644
--- a/src/southbridge/intel/i82801ix/usb_ehci.c
+++ b/src/southbridge/intel/i82801ix/usb_ehci.c
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801ix.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
static void usb_ehci_init(struct device *dev)
{
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index d941438..7dc7b03 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -24,7 +24,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
static void usb_ehci_init(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index 4382611..845129f 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -23,7 +23,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
#include "pch.h"
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index d98bc98..97e8ecb 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -26,7 +26,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "ck804.h"
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index b0afec2..23c2219 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -26,7 +26,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "mcp55.h"
diff --git a/src/southbridge/nvidia/mcp55/usb2.c b/src/southbridge/nvidia/mcp55/usb2.c
index 1f129ec..a9174f6 100644
--- a/src/southbridge/nvidia/mcp55/usb2.c
+++ b/src/southbridge/nvidia/mcp55/usb2.c
@@ -27,7 +27,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "mcp55.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
static void usb2_init(struct device *dev)
{
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index 0d7503d..274aeb7 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -28,7 +28,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "sis966.h"
diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c
index 195c982..e2112eb 100644
--- a/src/southbridge/sis/sis966/usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
@@ -30,7 +30,7 @@
#include <device/pci_ops.h>
#include <arch/io.h>
#include "sis966.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
static const u8 SiS_SiS7002_init[22][3]={
{0x04, 0x00, 0x06},
1
0
05 Feb '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5130
-gerrit
commit f78bb20fd010226702caa511f1dede15af44d5d8
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Feb 4 19:18:59 2014 +0200
usbdebug: Drop obsolete code
Change-Id: I918ca1d0d0d7bcb7e16d41a12830a0357f15b8ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 16 ----------------
src/southbridge/intel/ibexpeak/thermal.c | 1 -
2 files changed, 17 deletions(-)
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
index 6eb4787..c362ae3 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c
@@ -34,7 +34,6 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <pc80/mc146818rtc.h>
-#include <usbdebug.h>
#include "model_206ax.h"
#include "chip.h"
@@ -289,10 +288,6 @@ static void configure_mca(void)
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
}
-#if CONFIG_USBDEBUG
-static unsigned ehci_debug_addr;
-#endif
-
/*
* Initialize any extra cores/threads in this package.
*/
@@ -365,13 +360,6 @@ static void model_206ax_init(device_t cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
-#if CONFIG_USBDEBUG
- // Is this caution really needed?
- if(!ehci_debug_addr)
- ehci_debug_addr = get_ehci_debug();
- set_ehci_debug(0);
-#endif
-
/* Setup MTRRs based on physical address size */
cpuid_regs = cpuid(0x80000008);
x86_setup_fixed_mtrrs();
@@ -381,10 +369,6 @@ static void model_206ax_init(device_t cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
-#if CONFIG_USBDEBUG
- set_ehci_debug(ehci_debug_addr);
-#endif
-
/* Enable the local cpu apics */
enable_lapic_tpr();
setup_lapic();
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
index 11b6555..e01a6db 100644
--- a/src/southbridge/intel/ibexpeak/thermal.c
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -23,7 +23,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
-#include <usbdebug.h>
#include <arch/io.h>
static void thermal_init(struct device *dev)
1
0
New patch to review for coreboot: f4c0b0a usbdebug: Move under drivers/usb
by Kyösti Mälkki 05 Feb '14
by Kyösti Mälkki 05 Feb '14
05 Feb '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5129
-gerrit
commit f4c0b0ad1983f2fdf53fad2e0a654068ee2da646
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Feb 5 13:02:55 2014 +0200
usbdebug: Move under drivers/usb
Also relocate and split header files, there is some interest
for EHCI debug support without PCI.
Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/arch/x86/lib/romstage_console.c | 2 +-
src/console/usbdebug_console.c | 2 +-
src/drivers/Makefile.inc | 1 +
src/drivers/usb/Makefile.inc | 3 +
src/drivers/usb/ehci.h | 200 ++++
src/drivers/usb/ehci_debug.c | 1044 ++++++++++++++++++++
src/drivers/usb/usb_ch9.h | 102 ++
src/include/console/console.h | 2 +-
src/include/console/usb.h | 36 +
src/include/device/pci_ehci.h | 52 +
src/include/ehci.h | 200 ----
src/include/usb_ch9.h | 102 --
src/include/usbdebug.h | 61 --
src/lib/Makefile.inc | 2 -
src/lib/usbdebug.c | 1043 -------------------
src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 2 +-
src/southbridge/amd/agesa/hudson/usb.c | 2 +-
src/southbridge/amd/cimx/sb700/late.c | 2 +-
src/southbridge/amd/cimx/sb800/late.c | 2 +-
src/southbridge/amd/cimx/sb900/late.c | 2 +-
src/southbridge/amd/sb600/enable_usbdebug.c | 2 +-
src/southbridge/amd/sb600/usb.c | 2 +-
src/southbridge/amd/sb700/enable_usbdebug.c | 2 +-
src/southbridge/amd/sb700/usb.c | 2 +-
src/southbridge/amd/sb800/enable_usbdebug.c | 2 +-
src/southbridge/amd/sb800/usb.c | 2 +-
src/southbridge/intel/bd82x6x/usb_ehci.c | 2 +-
src/southbridge/intel/bd82x6x/usb_xhci.c | 2 +-
src/southbridge/intel/common/usb_debug.c | 2 +-
src/southbridge/intel/i82801dx/usb2.c | 2 +-
src/southbridge/intel/i82801ex/ehci.c | 2 +-
src/southbridge/intel/i82801gx/usb_ehci.c | 2 +-
src/southbridge/intel/i82801ix/usb_ehci.c | 2 +-
src/southbridge/intel/ibexpeak/usb_ehci.c | 2 +-
src/southbridge/intel/lynxpoint/usb_ehci.c | 2 +-
src/southbridge/nvidia/ck804/enable_usbdebug.c | 2 +-
src/southbridge/nvidia/mcp55/enable_usbdebug.c | 2 +-
src/southbridge/nvidia/mcp55/usb2.c | 2 +-
src/southbridge/sis/sis966/enable_usbdebug.c | 2 +-
src/southbridge/sis/sis966/usb2.c | 2 +-
40 files changed, 1466 insertions(+), 1436 deletions(-)
diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index 278ef1a..0eb3dc2 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -23,7 +23,7 @@
#include <uart8250.h>
#endif
#if CONFIG_USBDEBUG
-#include <usbdebug.h>
+#include <console/usb.h>
#endif
#if CONFIG_CONSOLE_NE2K
#include <console/ne2k.h>
diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c
index 8df6417..99726be 100644
--- a/src/console/usbdebug_console.c
+++ b/src/console/usbdebug_console.c
@@ -20,7 +20,7 @@
#include <string.h>
#include <console/console.h>
-#include <usbdebug.h>
+#include <console/usb.h>
static void dbgp_init(void)
{
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index 34ae62e..4b63a8f 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -29,6 +29,7 @@ subdirs-y += parade
subdirs-y += realtek
subdirs-y += sil
subdirs-y += trident
+subdirs-y += usb
subdirs-y += ics
subdirs-y += spi
subdirs-y += ti
diff --git a/src/drivers/usb/Makefile.inc b/src/drivers/usb/Makefile.inc
new file mode 100644
index 0000000..43931a9
--- /dev/null
+++ b/src/drivers/usb/Makefile.inc
@@ -0,0 +1,3 @@
+romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ehci_debug.c
+
+ramstage-$(CONFIG_USBDEBUG) += ehci_debug.c
diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h
new file mode 100644
index 0000000..f920352
--- /dev/null
+++ b/src/drivers/usb/ehci.h
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * It was taken from the Linux kernel (include/linux/usb/ehci_def.h).
+ *
+ * Copyright (C) 2001-2002 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef EHCI_H
+#define EHCI_H
+
+/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
+
+/* Section 2.2 Host Controller Capability Registers */
+struct ehci_caps {
+ /* these fields are specified as 8 and 16 bit registers,
+ * but some hosts can't perform 8 or 16 bit PCI accesses.
+ */
+ u32 hc_capbase;
+#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
+#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
+ u32 hcs_params; /* HCSPARAMS - offset 0x4 */
+#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
+#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
+#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
+#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
+#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
+#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
+#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
+
+ u32 hcc_params; /* HCCPARAMS - offset 0x8 */
+/* EHCI 1.1 addendum */
+#define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19))
+#define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18))
+#define HCC_LPM(p) ((p)&(1 << 17))
+#define HCC_HW_PREFETCH(p) ((p)&(1 << 16))
+
+#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
+#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
+#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
+#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
+#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
+#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
+ u8 portroute[8]; /* nibbles for routing - offset 0xC */
+} __attribute__ ((packed));
+
+
+/* Section 2.3 Host Controller Operational Registers */
+struct ehci_regs {
+
+ /* USBCMD: offset 0x00 */
+ u32 command;
+
+/* EHCI 1.1 addendum */
+#define CMD_HIRD (0xf<<24) /* host initiated resume duration */
+#define CMD_PPCEE (1<<15) /* per port change event enable */
+#define CMD_FSP (1<<14) /* fully synchronized prefetch */
+#define CMD_ASPE (1<<13) /* async schedule prefetch enable */
+#define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */
+/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
+#define CMD_PARK (1<<11) /* enable "park" on async qh */
+#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
+#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
+#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
+#define CMD_ASE (1<<5) /* async schedule enable */
+#define CMD_PSE (1<<4) /* periodic schedule enable */
+/* 3:2 is periodic frame list size */
+#define CMD_RESET (1<<1) /* reset HC not bus */
+#define CMD_RUN (1<<0) /* start/stop HC */
+
+ /* USBSTS: offset 0x04 */
+ u32 status;
+#define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */
+#define STS_ASS (1<<15) /* Async Schedule Status */
+#define STS_PSS (1<<14) /* Periodic Schedule Status */
+#define STS_RECL (1<<13) /* Reclamation */
+#define STS_HALT (1<<12) /* Not running (any reason) */
+/* some bits reserved */
+ /* these STS_* flags are also intr_enable bits (USBINTR) */
+#define STS_IAA (1<<5) /* Interrupted on async advance */
+#define STS_FATAL (1<<4) /* such as some PCI access errors */
+#define STS_FLR (1<<3) /* frame list rolled over */
+#define STS_PCD (1<<2) /* port change detect */
+#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
+#define STS_INT (1<<0) /* "normal" completion (short, ...) */
+
+ /* USBINTR: offset 0x08 */
+ u32 intr_enable;
+
+ /* FRINDEX: offset 0x0C */
+ u32 frame_index; /* current microframe number */
+ /* CTRLDSSEGMENT: offset 0x10 */
+ u32 segment; /* address bits 63:32 if needed */
+ /* PERIODICLISTBASE: offset 0x14 */
+ u32 frame_list; /* points to periodic list */
+ /* ASYNCLISTADDR: offset 0x18 */
+ u32 async_next; /* address of next async queue head */
+
+ u32 reserved[9];
+
+ /* CONFIGFLAG: offset 0x40 */
+ u32 configured_flag;
+#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
+
+ /* PORTSC: offset 0x44 */
+ u32 port_status[0]; /* up to N_PORTS */
+/* EHCI 1.1 addendum */
+#define PORTSC_SUSPEND_STS_ACK 0
+#define PORTSC_SUSPEND_STS_NYET 1
+#define PORTSC_SUSPEND_STS_STALL 2
+#define PORTSC_SUSPEND_STS_ERR 3
+
+#define PORT_DEV_ADDR (0x7f<<25) /* device address */
+#define PORT_SSTS (0x3<<23) /* suspend status */
+/* 31:23 reserved */
+#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
+#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
+#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
+/* 19:16 for port testing */
+#define PORT_TEST_PKT (0x4<<16) /* Port Test Control - packet test */
+#define PORT_LED_OFF (0<<14)
+#define PORT_LED_AMBER (1<<14)
+#define PORT_LED_GREEN (2<<14)
+#define PORT_LED_MASK (3<<14)
+#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
+#define PORT_POWER (1<<12) /* true: has power (see PPC) */
+#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
+/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
+/* 9 reserved */
+#define PORT_LPM (1<<9) /* LPM transaction */
+#define PORT_RESET (1<<8) /* reset port */
+#define PORT_SUSPEND (1<<7) /* suspend port */
+#define PORT_RESUME (1<<6) /* resume it */
+#define PORT_OCC (1<<5) /* over current change */
+#define PORT_OC (1<<4) /* over current active */
+#define PORT_PEC (1<<3) /* port enable change */
+#define PORT_PE (1<<2) /* port enable */
+#define PORT_CSC (1<<1) /* connect status change */
+#define PORT_CONNECT (1<<0) /* device connected */
+#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
+} __attribute__ ((packed));
+
+#define USBMODE 0x68 /* USB Device mode */
+#define USBMODE_SDIS (1<<3) /* Stream disable */
+#define USBMODE_BE (1<<2) /* BE/LE endianness select */
+#define USBMODE_CM_HC (3<<0) /* host controller mode */
+#define USBMODE_CM_IDLE (0<<0) /* idle state */
+
+/* Moorestown has some non-standard registers, partially due to the fact that
+ * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
+ * PORTSCx
+ */
+#define HOSTPC0 0x84 /* HOSTPC extension */
+#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
+#define HOSTPC_PSPD (3<<25) /* Port speed detection */
+#define USBMODE_EX 0xc8 /* USB Device mode extension */
+#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */
+#define USBMODE_EX_HC (3<<0) /* host controller mode */
+#define TXFILLTUNING 0x24 /* TX FIFO Tuning register */
+#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
+
+/* Appendix C, Debug port ... intended for use with special "debug devices"
+ * that can help if there's no serial console. (nonstandard enumeration.)
+ */
+struct ehci_dbg_port {
+ u32 control;
+#define DBGP_OWNER (1<<30)
+#define DBGP_ENABLED (1<<28)
+#define DBGP_DONE (1<<16)
+#define DBGP_INUSE (1<<10)
+#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
+# define DBGP_ERR_BAD 1
+# define DBGP_ERR_SIGNAL 2
+#define DBGP_ERROR (1<<6)
+#define DBGP_GO (1<<5)
+#define DBGP_OUT (1<<4)
+#define DBGP_LEN(x) (((x)>>0)&0x0f)
+ u32 pids;
+#define DBGP_PID_GET(x) (((x)>>16)&0xff)
+#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
+ u32 data03;
+ u32 data47;
+ u32 address;
+#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
+} __attribute__ ((packed));
+#endif
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
new file mode 100644
index 0000000..94625c0
--- /dev/null
+++ b/src/drivers/usb/ehci_debug.c
@@ -0,0 +1,1044 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Eric Biederman (ebiederm(a)xmission.com)
+ * Copyright (C) 2007 AMD
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <console/console.h>
+#include <console/usb.h>
+#include <device/pci_ehci.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <arch/byteorder.h>
+#include <arch/early_variables.h>
+#include <string.h>
+#include <cbmem.h>
+
+#include "usb_ch9.h"
+#include "ehci.h"
+
+
+#define DBGP_EP_VALID (1<<0)
+#define DBGP_EP_ENABLED (1<<1)
+#define DBGP_EP_BUSY (1<<2)
+#define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED)
+
+struct dbgp_pipe
+{
+ u8 devnum;
+ u8 endpoint;
+ u8 pid;
+ u8 status;
+ int timeout;
+
+ u8 bufidx;
+ char buf[8];
+};
+
+#define DBGP_MAX_ENDPOINTS 4
+#define DBGP_SETUP_EP0 0 /* Compulsory endpoint 0. */
+#define DBGP_CONSOLE_EPOUT 1
+#define DBGP_CONSOLE_EPIN 2
+
+struct ehci_debug_info {
+ void *ehci_caps;
+ void *ehci_regs;
+ void *ehci_debug;
+
+ struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS];
+};
+
+#if CONFIG_DEBUG_USBDEBUG
+static void dbgp_print_data(struct ehci_dbg_port *ehci_debug);
+static int dbgp_enabled(void);
+# define dprintk(LEVEL, args...) \
+ do { if (!dbgp_enabled()) printk(LEVEL, ##args); } while (0)
+#else
+# define dbgp_print_data(x) do {} while(0)
+# define dprintk(LEVEL, args...) do {} while(0)
+#endif
+
+#define USB_DEBUG_DEVNUM 127
+
+#define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f))
+/*
+ * USB Packet IDs (PIDs)
+ */
+
+/* token */
+#define USB_PID_OUT 0xe1
+#define USB_PID_IN 0x69
+#define USB_PID_SOF 0xa5
+#define USB_PID_SETUP 0x2d
+/* handshake */
+#define USB_PID_ACK 0xd2
+#define USB_PID_NAK 0x5a
+#define USB_PID_STALL 0x1e
+#define USB_PID_NYET 0x96
+/* data */
+#define USB_PID_DATA0 0xc3
+#define USB_PID_DATA1 0x4b
+#define USB_PID_DATA2 0x87
+#define USB_PID_MDATA 0x0f
+/* Special */
+#define USB_PID_PREAMBLE 0x3c
+#define USB_PID_ERR 0x3c
+#define USB_PID_SPLIT 0x78
+#define USB_PID_PING 0xb4
+#define USB_PID_UNDEF_0 0xf0
+
+#define USB_PID_DATA_TOGGLE 0x88
+#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
+
+#define PCI_CAP_ID_EHCI_DEBUG 0xa
+
+#define HUB_ROOT_RESET_TIME 50 /* times are in msec */
+#define HUB_SHORT_RESET_TIME 10
+#define HUB_LONG_RESET_TIME 200
+#define HUB_RESET_TIMEOUT 500
+
+#define DBGP_MICROFRAME_TIMEOUT_LOOPS 1000
+#define DBGP_MICROFRAME_RETRIES 10
+#define DBGP_MAX_PACKET 8
+
+static struct ehci_debug_info glob_dbg_info CAR_GLOBAL;
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
+static struct device_operations *ehci_drv_ops;
+static struct device_operations ehci_dbg_ops;
+#endif
+
+static inline struct ehci_debug_info *dbgp_ehci_info(void)
+{
+ return car_get_var_ptr(&glob_dbg_info);
+}
+
+static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
+{
+ u32 ctrl;
+ int loop = 0;
+
+ do {
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ /* Stop when the transaction is finished */
+ if (ctrl & DBGP_DONE)
+ break;
+ } while (++loop < DBGP_MICROFRAME_TIMEOUT_LOOPS);
+
+ if (! (ctrl & DBGP_DONE)) {
+ dprintk(BIOS_ERR, "dbgp_wait_until_complete: retry timeout.\n");
+ return -DBGP_ERR_SIGNAL;
+ }
+
+ /* Now that we have observed the completed transaction,
+ * clear the done bit.
+ */
+ write32((unsigned long)&ehci_debug->control, ctrl | DBGP_DONE);
+ return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
+}
+
+static void dbgp_breath(void)
+{
+ /* Sleep to give the debug port a chance to breathe */
+}
+
+static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
+ unsigned ctrl, const int timeout)
+{
+ u32 rd_ctrl, rd_pids;
+ u32 ctrl_prev = 0, pids_prev = 0;
+ u8 lpid;
+ int ret, host_retries;
+ int loop;
+
+ loop = 0;
+device_retry:
+ host_retries = 0;
+ if (loop++ >= timeout)
+ return -DBGP_ERR_BAD;
+
+host_retry:
+ if (host_retries++ >= DBGP_MICROFRAME_RETRIES)
+ return -DBGP_ERR_BAD;
+ if (loop == 1 || host_retries > 1)
+ dprintk(BIOS_SPEW, "dbgp: start (@ %3d,%d) ctrl=%08x\n",
+ loop, host_retries, ctrl | DBGP_GO);
+ write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO);
+ ret = dbgp_wait_until_complete(ehci_debug);
+ rd_ctrl = read32((unsigned long)&ehci_debug->control);
+ rd_pids = read32((unsigned long)&ehci_debug->pids);
+
+ if (rd_ctrl != ctrl_prev || rd_pids != pids_prev || (ret<0)) {
+ ctrl_prev = rd_ctrl;
+ pids_prev = rd_pids;
+ dprintk(BIOS_SPEW, "dbgp: status (@ %3d,%d) ctrl=%08x pids=%08x ret=%d\n",
+ loop, host_retries, rd_ctrl, rd_pids, ret);
+ }
+
+ /* Controller hardware failure. */
+ if (ret == -DBGP_ERR_SIGNAL) {
+ return ret;
+
+ /* Bus failure (corrupted microframe). */
+ } else if (ret == -DBGP_ERR_BAD) {
+ goto host_retry;
+ }
+
+ lpid = DBGP_PID_GET(rd_pids);
+
+ /* If I get an ACK or in-sync DATA PID, we are done. */
+ if ((lpid == USB_PID_ACK) || (lpid == pipe->pid)) {
+ if (DBGP_LEN(rd_ctrl))
+ pipe->pid ^= USB_PID_DATA_TOGGLE;
+ }
+
+ /* If the port is getting full or it has dropped data
+ * start pacing ourselves, not necessary but it's friendly.
+ */
+ else if (lpid == USB_PID_NYET) {
+ dbgp_breath();
+ goto device_retry;
+ }
+
+ /* If I get a NACK or out-of-sync DATA PID, reissue the transmission. */
+ else if ((lpid == USB_PID_NAK) || (lpid == (pipe->pid ^ USB_PID_DATA_TOGGLE))) {
+ goto device_retry;
+ }
+
+ /* Abort on STALL handshake for endpoint 0.*/
+ else if ((lpid == USB_PID_STALL) && (pipe->endpoint == 0x0)) {
+ ret = -DBGP_ERR_BAD;
+ }
+
+ dbgp_print_data(ehci_debug);
+
+ return ret;
+}
+
+static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int size)
+{
+ const unsigned char *bytes = buf;
+ u32 lo, hi;
+ int i;
+
+ lo = hi = 0;
+ for (i = 0; i < 4 && i < size; i++)
+ lo |= bytes[i] << (8*i);
+ for (; i < 8 && i < size; i++)
+ hi |= bytes[i] << (8*(i - 4));
+ write32((unsigned long)&ehci_debug->data03, lo);
+ write32((unsigned long)&ehci_debug->data47, hi);
+}
+
+static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
+{
+ unsigned char *bytes = buf;
+ u32 lo, hi;
+ int i;
+
+ lo = read32((unsigned long)&ehci_debug->data03);
+ hi = read32((unsigned long)&ehci_debug->data47);
+ for (i = 0; i < 4 && i < size; i++)
+ bytes[i] = (lo >> (8*i)) & 0xff;
+ for (; i < 8 && i < size; i++)
+ bytes[i] = (hi >> (8*(i - 4))) & 0xff;
+}
+
+#if CONFIG_DEBUG_USBDEBUG
+static void dbgp_print_data(struct ehci_dbg_port *ehci_debug)
+{
+ u32 ctrl = read32((unsigned long)&ehci_debug->control);
+ u32 lo = read32((unsigned long)&ehci_debug->data03);
+ u32 hi = read32((unsigned long)&ehci_debug->data47);
+ int len = DBGP_LEN(ctrl);
+ if (len) {
+ int i;
+ dprintk(BIOS_SPEW, "dbgp: buf:");
+ for (i = 0; i < 4 && i < len; i++)
+ dprintk(BIOS_SPEW, " %02x", (lo >> (8*i)) & 0xff);
+ for (; i < 8 && i < len; i++)
+ dprintk(BIOS_SPEW, " %02x", (hi >> (8*(i - 4))) & 0xff);
+ dprintk(BIOS_SPEW, "\n");
+ }
+}
+#endif
+
+static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
+ const char *bytes, int size)
+{
+ u32 pids, addr, ctrl;
+ int ret;
+
+ if (size > DBGP_MAX_PACKET)
+ return -1;
+
+ addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
+ pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
+
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = DBGP_LEN_UPDATE(ctrl, size);
+ ctrl |= DBGP_OUT;
+
+ dbgp_set_data(ehci_debug, bytes, size);
+ write32((unsigned long)&ehci_debug->address, addr);
+ write32((unsigned long)&ehci_debug->pids, pids);
+
+ ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
+
+ return ret;
+}
+
+int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+ return dbgp_bulk_write(dbg_info->ehci_debug, pipe, bytes, size);
+}
+
+static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
+ void *data, int size)
+{
+ u32 pids, addr, ctrl;
+ int ret;
+
+ if (size > DBGP_MAX_PACKET)
+ return -1;
+
+ addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
+ pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
+
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = DBGP_LEN_UPDATE(ctrl, size);
+ ctrl &= ~DBGP_OUT;
+
+ write32((unsigned long)&ehci_debug->address, addr);
+ write32((unsigned long)&ehci_debug->pids, pids);
+ ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
+ if (ret < 0)
+ return ret;
+
+ if (size > ret)
+ size = ret;
+ dbgp_get_data(ehci_debug, data, size);
+ return ret;
+}
+
+int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+ return dbgp_bulk_read(dbg_info->ehci_debug, pipe, data, size);
+}
+
+static void dbgp_mdelay(int ms)
+{
+ int i;
+
+ while (ms--) {
+ for (i = 0; i < 1000; i++)
+ inb(0x80);
+ }
+}
+
+static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype,
+ int request, int value, int index, void *data, int size)
+{
+ struct ehci_debug_info *info = dbgp_ehci_info();
+ struct dbgp_pipe *pipe = &info->ep_pipe[DBGP_SETUP_EP0];
+ u32 pids, addr, ctrl;
+ struct usb_ctrlrequest req;
+ int read;
+ int ret, ret2;
+
+ read = (requesttype & USB_DIR_IN) != 0;
+ if (size > DBGP_MAX_PACKET)
+ return -1;
+
+ /* Compute the control message */
+ req.bRequestType = requesttype;
+ req.bRequest = request;
+ req.wValue = cpu_to_le16(value);
+ req.wIndex = cpu_to_le16(index);
+ req.wLength = cpu_to_le16(size);
+
+ pipe->devnum = devnum;
+ pipe->endpoint = 0;
+ pipe->pid = USB_PID_DATA0;
+ pipe->timeout = 1000;
+ addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
+ pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP);
+
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
+ ctrl |= DBGP_OUT;
+
+ /* Setup stage */
+ dbgp_set_data(ehci_debug, &req, sizeof(req));
+ write32((unsigned long)&ehci_debug->address, addr);
+ write32((unsigned long)&ehci_debug->pids, pids);
+ ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, 1);
+ if (ret < 0)
+ return ret;
+
+ /* Data stage (optional) */
+ if (read && size)
+ ret = dbgp_bulk_read(ehci_debug, pipe, data, size);
+ else if (!read && size)
+ ret = dbgp_bulk_write(ehci_debug, pipe, data, size);
+
+ /* Status stage in opposite direction */
+ pipe->pid = USB_PID_DATA1;
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = DBGP_LEN_UPDATE(ctrl, 0);
+ if (read) {
+ pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
+ ctrl |= DBGP_OUT;
+ } else {
+ pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
+ ctrl &= ~DBGP_OUT;
+ }
+
+ write32((unsigned long)&ehci_debug->pids, pids);
+ ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
+ if (ret2 < 0)
+ return ret2;
+
+ return ret;
+}
+
+static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
+{
+ u32 portsc;
+ u32 delay_time, delay_ms;
+ int loop;
+
+ /* Reset the usb debug port */
+ portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ portsc &= ~PORT_PE;
+ portsc |= PORT_RESET;
+ write32((unsigned long)&ehci_regs->port_status[port - 1], portsc);
+
+ delay_ms = HUB_ROOT_RESET_TIME;
+ for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
+ delay_time += delay_ms) {
+ dbgp_mdelay(delay_ms);
+
+ portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ if (portsc & PORT_RESET) {
+ /* force reset to complete */
+ loop = 2;
+ write32((unsigned long)&ehci_regs->port_status[port - 1],
+ portsc & ~(PORT_RWC_BITS | PORT_RESET));
+ do {
+ dbgp_mdelay(delay_ms);
+ portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ delay_time += delay_ms;
+ } while ((portsc & PORT_RESET) && (--loop > 0));
+ if (!loop) {
+ printk(BIOS_DEBUG, "ehci_reset_port forced done");
+ }
+ }
+
+ /* Device went away? */
+ if (!(portsc & PORT_CONNECT))
+ return -1; //-ENOTCONN;
+
+ /* bomb out completely if something weird happened */
+ if ((portsc & PORT_CSC))
+ return -2; //-EINVAL;
+
+ /* If we've finished resetting, then break out of the loop */
+ if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
+ return 0;
+ }
+ return -3; //-EBUSY;
+}
+
+static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
+{
+ u32 status;
+ int ret, reps;
+
+ for (reps = 0; reps < 3; reps++) {
+ dbgp_mdelay(100);
+ status = read32((unsigned long)&ehci_regs->status);
+ if (status & STS_PCD) {
+ ret = ehci_reset_port(ehci_regs, port);
+ if (ret == 0)
+ return 0;
+ }
+ }
+ return -1; //-ENOTCONN;
+}
+
+#define USB_HUB_PORT_CONNECTION 0
+#define USB_HUB_PORT_ENABLED 1
+#define USB_HUB_PORT_RESET 4
+#define USB_HUB_PORT_POWER 8
+#define USB_HUB_C_PORT_CONNECTION 16
+#define USB_HUB_C_PORT_RESET 20
+
+#if CONFIG_USBDEBUG_OPTIONAL_HUB_PORT
+
+static int hub_port_status(const char * buf, int feature)
+{
+ return !!(buf[feature>>3] & (1<<(feature&0x7)));
+}
+
+static int dbgp_hub_enable(struct ehci_dbg_port *ehci_debug, unsigned int port)
+{
+ const u8 hub_addr = USB_DEBUG_DEVNUM-1;
+ char status[8];
+ int ret, loop;
+
+ /* Move hub to address 126. */
+ ret = dbgp_control_msg(ehci_debug, 0,
+ USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_SET_ADDRESS, hub_addr, 0, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+ /* Enter configured state on hub. */
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+ /* Set PORT_POWER, poll for PORT_CONNECTION. */
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_SET_FEATURE, USB_HUB_PORT_POWER, port, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+ loop = 100;
+ do {
+ dbgp_mdelay(10);
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_GET_STATUS, 0, port, status, 4);
+ if (ret < 0)
+ goto err;
+ if (hub_port_status(status, USB_HUB_PORT_CONNECTION))
+ break;
+ } while (--loop);
+ if (! loop)
+ goto err;
+
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_CLEAR_FEATURE, USB_HUB_C_PORT_CONNECTION, port, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+
+ /* Set PORT_RESET, poll for C_PORT_RESET. */
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_SET_FEATURE, USB_HUB_PORT_RESET, port, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+ loop = 100;
+ do {
+ dbgp_mdelay(10);
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_GET_STATUS, 0, port, status, 4);
+ if (ret < 0)
+ goto err;
+ if (hub_port_status(status, USB_HUB_C_PORT_RESET))
+ break;
+ } while (--loop);
+ if (! loop)
+ goto err;
+
+ ret = dbgp_control_msg(ehci_debug, hub_addr,
+ USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
+ USB_REQ_CLEAR_FEATURE, USB_HUB_C_PORT_RESET, port, NULL, 0);
+ if (ret < 0)
+ goto err;
+
+ if (hub_port_status(status, USB_HUB_PORT_ENABLED))
+ return 0;
+err:
+ return -1;
+}
+#endif /* CONFIG_USBDEBUG_OPTIONAL_HUB_PORT */
+
+static void enable_usbdebug(void)
+{
+#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE
+ pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
+ pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR);
+#endif
+}
+
+static void set_debug_port(unsigned int port)
+{
+ pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
+ pci_ehci_dbg_set_port(dbg_dev, port);
+}
+
+static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info)
+{
+ struct ehci_caps *ehci_caps;
+ struct ehci_regs *ehci_regs;
+ struct ehci_dbg_port *ehci_debug;
+
+ struct usb_debug_descriptor dbgp_desc;
+ u32 cmd, ctrl, status, portsc, hcs_params;
+ u32 debug_port, new_debug_port = 0, n_ports;
+ u32 devnum;
+ int ret, i, configured;
+ int loop;
+ int port_map_tried;
+ int playtimes = 3;
+
+ ehci_caps = (struct ehci_caps *)ehci_bar;
+ ehci_regs = (struct ehci_regs *)(ehci_bar +
+ HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
+ ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
+ info->ehci_debug = (void *)0;
+ memset(&info->ep_pipe, 0, sizeof (info->ep_pipe));
+
+ if (CONFIG_USBDEBUG_DEFAULT_PORT > 0)
+ set_debug_port(CONFIG_USBDEBUG_DEFAULT_PORT);
+ else
+ set_debug_port(1);
+
+try_next_time:
+ port_map_tried = 0;
+
+try_next_port:
+ hcs_params = read32((unsigned long)&ehci_caps->hcs_params);
+ debug_port = HCS_DEBUG_PORT(hcs_params);
+ n_ports = HCS_N_PORTS(hcs_params);
+
+ dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar);
+ dprintk(BIOS_INFO, "debug_port: %d\n", debug_port);
+ dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
+
+ for (i = 1; i <= n_ports; i++) {
+ portsc = read32((unsigned long)&ehci_regs->port_status[i-1]);
+ dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
+ }
+
+ if(port_map_tried && (new_debug_port != debug_port)) {
+ if(--playtimes) {
+ set_debug_port(debug_port);
+ goto try_next_time;
+ }
+ return -1;
+ }
+
+ /* Wait until the controller is halted */
+ status = read32((unsigned long)&ehci_regs->status);
+ if (!(status & STS_HALT)) {
+ cmd = read32((unsigned long)&ehci_regs->command);
+ cmd &= ~CMD_RUN;
+ write32((unsigned long)&ehci_regs->command, cmd);
+ loop = 100;
+ do {
+ dbgp_mdelay(10);
+ status = read32((unsigned long)&ehci_regs->status);
+ } while (!(status & STS_HALT) && (--loop > 0));
+ if (status & STS_HALT)
+ dprintk(BIOS_INFO, "EHCI controller halted successfully.\n");
+ else
+ dprintk(BIOS_INFO, "EHCI controller is not halted. Reset may fail.\n");
+ }
+
+ loop = 100;
+ /* Reset the EHCI controller */
+ cmd = read32((unsigned long)&ehci_regs->command);
+ cmd |= CMD_RESET;
+ write32((unsigned long)&ehci_regs->command, cmd);
+ do {
+ dbgp_mdelay(10);
+ cmd = read32((unsigned long)&ehci_regs->command);
+ } while ((cmd & CMD_RESET) && (--loop > 0));
+
+ if(!loop) {
+ dprintk(BIOS_INFO, "Could not reset EHCI controller.\n");
+ // on some systems it works without succeeding here.
+ // return -2;
+ } else {
+ dprintk(BIOS_INFO, "EHCI controller reset successfully.\n");
+ }
+
+ /* Claim ownership, but do not enable yet */
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl |= DBGP_OWNER;
+ ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
+ write32((unsigned long)&ehci_debug->control, ctrl);
+
+ /* Start EHCI controller */
+ cmd = read32((unsigned long)&ehci_regs->command);
+ cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
+ cmd |= CMD_RUN;
+ write32((unsigned long)&ehci_regs->command, cmd);
+
+ /* Ensure everything is routed to the EHCI */
+ write32((unsigned long)&ehci_regs->configured_flag, FLAG_CF);
+
+ /* Wait until the controller is no longer halted */
+ loop = 10;
+ do {
+ dbgp_mdelay(10);
+ status = read32((unsigned long)&ehci_regs->status);
+ } while ((status & STS_HALT) && (--loop > 0));
+
+ if(!loop) {
+ dprintk(BIOS_INFO, "EHCI could not be started.\n");
+ return -3;
+ }
+ dprintk(BIOS_INFO, "EHCI started.\n");
+
+ /* Wait for a device to show up in the debug port */
+ ret = ehci_wait_for_port(ehci_regs, debug_port);
+ if (ret < 0) {
+ dprintk(BIOS_INFO, "No device found in debug port %d\n", debug_port);
+ goto next_debug_port;
+ }
+ dprintk(BIOS_INFO, "EHCI done waiting for port.\n");
+
+ /* Enable the debug port */
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl |= DBGP_CLAIM;
+ write32((unsigned long)&ehci_debug->control, ctrl);
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
+ dprintk(BIOS_INFO, "No device in EHCI debug port.\n");
+ write32((unsigned long)&ehci_debug->control, ctrl & ~DBGP_CLAIM);
+ ret = -4;
+ goto err;
+ }
+ dprintk(BIOS_INFO, "EHCI debug port enabled.\n");
+
+ /* Completely transfer the debug device to the debug controller */
+ portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]);
+ portsc &= ~PORT_PE;
+ write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc);
+
+ dbgp_mdelay(100);
+
+#if CONFIG_USBDEBUG_OPTIONAL_HUB_PORT
+ ret = dbgp_hub_enable(ehci_debug, CONFIG_USBDEBUG_OPTIONAL_HUB_PORT);
+ if (ret < 0) {
+ dprintk(BIOS_INFO, "Could not enable USB hub on debug port.\n");
+ ret = -6;
+ goto err;
+ }
+#endif
+
+ /* Find the debug device and make it device number 127 */
+ devnum = 0;
+debug_dev_retry:
+ memset(&dbgp_desc, 0, sizeof(dbgp_desc));
+ ret = dbgp_control_msg(ehci_debug, devnum,
+ USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
+ &dbgp_desc, sizeof(dbgp_desc));
+ if (ret == sizeof(dbgp_desc)) {
+ if (dbgp_desc.bLength == sizeof(dbgp_desc) && dbgp_desc.bDescriptorType==USB_DT_DEBUG)
+ goto debug_dev_found;
+ else
+ dprintk(BIOS_INFO, "Invalid debug device descriptor.\n");
+ }
+ if (devnum == 0) {
+ devnum = USB_DEBUG_DEVNUM;
+ goto debug_dev_retry;
+ } else {
+ dprintk(BIOS_INFO, "Could not find attached debug device.\n");
+ ret = -5;
+ goto err;
+ }
+debug_dev_found:
+
+ /* Move the device to 127 if it isn't already there */
+ if (devnum != USB_DEBUG_DEVNUM) {
+ ret = dbgp_control_msg(ehci_debug, devnum,
+ USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
+ if (ret < 0) {
+ dprintk(BIOS_INFO, "Could not move attached device to %d.\n",
+ USB_DEBUG_DEVNUM);
+ ret = -7;
+ goto err;
+ }
+ devnum = USB_DEBUG_DEVNUM;
+ dprintk(BIOS_INFO, "EHCI debug device renamed to 127.\n");
+ }
+
+ /* Enable the debug interface */
+ ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
+ USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
+ if (ret < 0) {
+ dprintk(BIOS_INFO, "Could not enable EHCI debug device.\n");
+ ret = -8;
+ goto err;
+ }
+ dprintk(BIOS_INFO, "EHCI debug interface enabled.\n");
+
+ /* Prepare endpoint pipes. */
+ for (i=1; i<DBGP_MAX_ENDPOINTS; i++) {
+ info->ep_pipe[i].devnum = USB_DEBUG_DEVNUM;
+ info->ep_pipe[i].pid = USB_PID_DATA0;
+ info->ep_pipe[i].timeout = 1000;
+ }
+ info->ep_pipe[DBGP_CONSOLE_EPOUT].endpoint = dbgp_desc.bDebugOutEndpoint;
+ info->ep_pipe[DBGP_CONSOLE_EPIN].endpoint = dbgp_desc.bDebugInEndpoint;
+
+ /* Perform a small write. */
+ configured = 0;
+small_write:
+ ret = dbgp_bulk_write(ehci_debug, &info->ep_pipe[DBGP_CONSOLE_EPOUT], "USB\r\n",5);
+ if (ret < 0) {
+ dprintk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret);
+ if (!configured) {
+ /* Send Set Configure request to device. This is required for FX2
+ (CY7C68013) to transfer from USB state Addressed to Configured,
+ only then endpoints other than 0 are enabled. */
+ if (dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
+ USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+ USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0) >= 0) {
+ configured = 1;
+ goto small_write;
+ }
+ }
+ ret = -9;
+ goto err;
+ }
+ dprintk(BIOS_INFO, "Test write done\n");
+
+ info->ehci_caps = ehci_caps;
+ info->ehci_regs = ehci_regs;
+ info->ehci_debug = ehci_debug;
+
+ info->ep_pipe[DBGP_SETUP_EP0].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
+ info->ep_pipe[DBGP_CONSOLE_EPOUT].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
+ info->ep_pipe[DBGP_CONSOLE_EPIN].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
+ return 0;
+err:
+ /* Things didn't work so remove my claim */
+ ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
+ write32((unsigned long)(unsigned long)&ehci_debug->control, ctrl);
+ //return ret;
+
+next_debug_port:
+#if CONFIG_USBDEBUG_DEFAULT_PORT==0
+ port_map_tried |= (1 << (debug_port - 1));
+ new_debug_port = ((debug_port-1 + 1) % n_ports) + 1;
+ if (port_map_tried != ((1 << n_ports) - 1)) {
+ set_debug_port(new_debug_port);
+ goto try_next_port;
+ }
+ if (--playtimes) {
+ set_debug_port(new_debug_port);
+ goto try_next_time;
+ }
+#else
+ if (0)
+ goto try_next_port;
+ if (--playtimes)
+ goto try_next_time;
+#endif
+
+ return -10;
+}
+
+#if CONFIG_DEBUG_USBDEBUG
+static int dbgp_enabled(void)
+{
+ struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
+ return (globals->status & DBGP_EP_ENABLED);
+}
+#endif
+
+static int dbgp_try_get(struct dbgp_pipe *pipe)
+{
+ struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
+ if (!dbgp_ep_is_active(pipe) || (globals->status & DBGP_EP_BUSY))
+ return 0;
+ globals->status |= DBGP_EP_BUSY;
+ pipe->status |= DBGP_EP_BUSY;
+ return 1;
+}
+
+static void dbgp_put(struct dbgp_pipe *pipe)
+{
+ struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
+ globals->status &= ~DBGP_EP_BUSY;
+ pipe->status &= ~DBGP_EP_BUSY;
+}
+
+void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data)
+{
+ if (!dbgp_try_get(pipe))
+ return;
+ pipe->buf[pipe->bufidx++] = data;
+ if (pipe->bufidx >= 8) {
+ dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx);
+ pipe->bufidx = 0;
+ }
+ dbgp_put(pipe);
+}
+
+void usbdebug_tx_flush(struct dbgp_pipe *pipe)
+{
+ if (!dbgp_try_get(pipe))
+ return;
+ if (pipe->bufidx > 0) {
+ dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx);
+ pipe->bufidx = 0;
+ }
+ dbgp_put(pipe);
+}
+
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
+static void usbdebug_re_enable(unsigned ehci_base)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+ unsigned diff;
+ int i;
+
+ if (!dbg_info->ehci_debug)
+ return;
+
+ diff = (unsigned)dbg_info->ehci_caps - ehci_base;
+ dbg_info->ehci_regs -= diff;
+ dbg_info->ehci_debug -= diff;
+ dbg_info->ehci_caps = (void*)ehci_base;
+
+ for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
+ dbg_info->ep_pipe[i].status |= DBGP_EP_ENABLED;
+}
+
+static void usbdebug_disable(void)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+ int i;
+ for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
+ dbg_info->ep_pipe[i].status &= ~DBGP_EP_ENABLED;
+}
+
+static void pci_ehci_set_resources(struct device *dev)
+{
+ struct resource *res;
+
+ printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev));
+ usbdebug_disable();
+
+ if (ehci_drv_ops->set_resources)
+ ehci_drv_ops->set_resources(dev);
+ res = find_resource(dev, EHCI_BAR_INDEX);
+ if (!res)
+ return;
+
+ usbdebug_re_enable((u32)res->base);
+ report_resource_stored(dev, res, "");
+ printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev));
+}
+
+void pci_ehci_read_resources(struct device *dev)
+{
+ pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
+
+ if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) {
+ memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops));
+ ehci_drv_ops = dev->ops;
+ ehci_dbg_ops.set_resources = pci_ehci_set_resources;
+ dev->ops = &ehci_dbg_ops;
+ printk(BIOS_DEBUG, "%s EHCI BAR hook registered\n", dev_path(dev));
+ } else {
+ printk(BIOS_DEBUG, "More than one caller of %s from %s\n", __func__, dev_path(dev));
+ }
+
+ pci_dev_read_resources(dev);
+}
+#endif
+
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
+static int get_usbdebug_from_cbmem(struct ehci_debug_info *info)
+{
+ struct ehci_debug_info *dbg_info_cbmem;
+
+ dbg_info_cbmem = cbmem_find(CBMEM_ID_EHCI_DEBUG);
+ if (dbg_info_cbmem == NULL)
+ return -1;
+
+ memcpy(info, dbg_info_cbmem, sizeof (*info));
+ printk(BIOS_DEBUG, "EHCI debug port found in CBMEM.\n");
+
+ return 0;
+}
+
+#elif defined(__PRE_RAM__)
+static void migrate_ehci_debug(void)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+ struct ehci_debug_info *dbg_info_cbmem;
+
+ dbg_info_cbmem = cbmem_add(CBMEM_ID_EHCI_DEBUG, sizeof(*dbg_info));
+ if (dbg_info_cbmem == NULL)
+ return;
+
+ memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info));
+}
+CAR_MIGRATE(migrate_ehci_debug);
+#endif
+
+unsigned long pci_ehci_base_regs(pci_devfn_t sdev)
+{
+#ifdef __SIMPLE_DEVICE__
+ unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f;
+#else
+ device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
+ unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f;
+#endif
+ return base + HC_LENGTH(read32(base));
+}
+
+int dbgp_ep_is_active(struct dbgp_pipe *pipe)
+{
+ return (pipe->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED);
+}
+
+struct dbgp_pipe *dbgp_console_output(void)
+{
+ return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPOUT];
+}
+
+struct dbgp_pipe *dbgp_console_input(void)
+{
+ return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPIN];
+}
+
+int usbdebug_init(void)
+{
+ struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
+ if (!get_usbdebug_from_cbmem(dbg_info))
+ return 0;
+#endif
+ enable_usbdebug();
+ return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
+}
diff --git a/src/drivers/usb/usb_ch9.h b/src/drivers/usb/usb_ch9.h
new file mode 100644
index 0000000..b0aa773
--- /dev/null
+++ b/src/drivers/usb/usb_ch9.h
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef USB_CH9_H
+#define USB_CH9_H
+
+#define USB_DIR_OUT 0 /* to device */
+#define USB_DIR_IN 0x80 /* to host */
+
+/*
+ * USB types, the second of three bRequestType fields
+ */
+#define USB_TYPE_MASK (0x03 << 5)
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS (0x01 << 5)
+#define USB_TYPE_VENDOR (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
+/*
+ * USB recipients, the third of three bRequestType fields
+ */
+#define USB_RECIP_MASK 0x1f
+#define USB_RECIP_DEVICE 0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT 0x02
+#define USB_RECIP_OTHER 0x03
+/* From Wireless USB 1.0 */
+#define USB_RECIP_PORT 0x04
+#define USB_RECIP_RPIPE 0x05
+
+/*
+ * Standard requests, for the bRequest field of a SETUP packet.
+ *
+ * These are qualified by the bRequestType field, so that for example
+ * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
+ * by a GET_STATUS request.
+ */
+#define USB_REQ_GET_STATUS 0x00
+#define USB_REQ_CLEAR_FEATURE 0x01
+#define USB_REQ_SET_FEATURE 0x03
+#define USB_REQ_SET_ADDRESS 0x05
+#define USB_REQ_GET_DESCRIPTOR 0x06
+#define USB_REQ_SET_DESCRIPTOR 0x07
+#define USB_REQ_GET_CONFIGURATION 0x08
+#define USB_REQ_SET_CONFIGURATION 0x09
+#define USB_REQ_GET_INTERFACE 0x0A
+#define USB_REQ_SET_INTERFACE 0x0B
+#define USB_REQ_SYNCH_FRAME 0x0C
+
+#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */
+#define USB_REQ_GET_ENCRYPTION 0x0E
+#define USB_REQ_RPIPE_ABORT 0x0E
+#define USB_REQ_SET_HANDSHAKE 0x0F
+#define USB_REQ_RPIPE_RESET 0x0F
+#define USB_REQ_GET_HANDSHAKE 0x10
+#define USB_REQ_SET_CONNECTION 0x11
+#define USB_REQ_SET_SECURITY_DATA 0x12
+#define USB_REQ_GET_SECURITY_DATA 0x13
+#define USB_REQ_SET_WUSB_DATA 0x14
+#define USB_REQ_LOOPBACK_DATA_WRITE 0x15
+#define USB_REQ_LOOPBACK_DATA_READ 0x16
+#define USB_REQ_SET_INTERFACE_DS 0x17
+
+#define USB_DT_DEBUG 0x0a
+
+#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
+
+struct usb_ctrlrequest {
+ u8 bRequestType;
+ u8 bRequest;
+ u16 wValue;
+ u16 wIndex;
+ u16 wLength;
+} __attribute__ ((packed));
+
+struct usb_debug_descriptor {
+ u8 bLength;
+ u8 bDescriptorType;
+
+ /* bulk endpoints with 8 byte maxpacket */
+ u8 bDebugInEndpoint;
+ u8 bDebugOutEndpoint;
+};
+
+#endif
+
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 5750b4a..c5f5297 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -28,7 +28,7 @@
#include <uart.h>
#endif
#if CONFIG_USBDEBUG && !defined(__ROMCC__)
-#include <usbdebug.h>
+#include <console/usb.h>
#endif
#if CONFIG_CONSOLE_NE2K
#include <console/ne2k.h>
diff --git a/src/include/console/usb.h b/src/include/console/usb.h
new file mode 100644
index 0000000..47f3d74
--- /dev/null
+++ b/src/include/console/usb.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef _CONSOLE_USB_H_
+#define _CONSOLE_USB_H_
+
+struct dbgp_pipe;
+
+int usbdebug_init(void);
+
+struct dbgp_pipe *dbgp_console_output(void);
+struct dbgp_pipe *dbgp_console_input(void);
+int dbgp_ep_is_active(struct dbgp_pipe *pipe);
+int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size);
+int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size);
+void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data);
+void usbdebug_tx_flush(struct dbgp_pipe *pipe);
+
+#endif /* _CONSOLE_USB_H_ */
diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h
new file mode 100644
index 0000000..4d3f746
--- /dev/null
+++ b/src/include/device/pci_ehci.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef _PCI_EHCI_H_
+#define _PCI_EHCI_H_
+
+#include <arch/io.h>
+#include <device/device.h>
+
+#define EHCI_BAR_INDEX 0x10
+#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
+
+pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx);
+unsigned long pci_ehci_base_regs(pci_devfn_t dev);
+void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
+void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
+
+#ifndef __PRE_RAM__
+#if !CONFIG_USBDEBUG
+#define pci_ehci_read_resources pci_dev_read_resources
+#else
+/* Relocation of EHCI Debug Port BAR
+ *
+ * PCI EHCI controller with Debug Port capability shall replace
+ * pci_dev_read_resources() with pci_ehci_read_resources() in its
+ * declaration of device_operations for .read_resources.
+ * This installs a hook to reconfigure usbdebug when resource allocator
+ * assigns a new BAR for the device.
+ */
+struct device;
+void pci_ehci_read_resources(struct device *dev);
+#endif
+#endif
+
+#endif /* _PCI_EHCI_H_ */
diff --git a/src/include/ehci.h b/src/include/ehci.h
deleted file mode 100644
index f920352..0000000
--- a/src/include/ehci.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * It was taken from the Linux kernel (include/linux/usb/ehci_def.h).
- *
- * Copyright (C) 2001-2002 David Brownell
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef EHCI_H
-#define EHCI_H
-
-/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
-
-/* Section 2.2 Host Controller Capability Registers */
-struct ehci_caps {
- /* these fields are specified as 8 and 16 bit registers,
- * but some hosts can't perform 8 or 16 bit PCI accesses.
- */
- u32 hc_capbase;
-#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
-#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
- u32 hcs_params; /* HCSPARAMS - offset 0x4 */
-#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
-#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
-#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
-#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
-#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
-#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
-#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
-
- u32 hcc_params; /* HCCPARAMS - offset 0x8 */
-/* EHCI 1.1 addendum */
-#define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19))
-#define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18))
-#define HCC_LPM(p) ((p)&(1 << 17))
-#define HCC_HW_PREFETCH(p) ((p)&(1 << 16))
-
-#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
-#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
-#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
-#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
-#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
-#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
- u8 portroute[8]; /* nibbles for routing - offset 0xC */
-} __attribute__ ((packed));
-
-
-/* Section 2.3 Host Controller Operational Registers */
-struct ehci_regs {
-
- /* USBCMD: offset 0x00 */
- u32 command;
-
-/* EHCI 1.1 addendum */
-#define CMD_HIRD (0xf<<24) /* host initiated resume duration */
-#define CMD_PPCEE (1<<15) /* per port change event enable */
-#define CMD_FSP (1<<14) /* fully synchronized prefetch */
-#define CMD_ASPE (1<<13) /* async schedule prefetch enable */
-#define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */
-/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
-#define CMD_PARK (1<<11) /* enable "park" on async qh */
-#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
-#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
-#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
-#define CMD_ASE (1<<5) /* async schedule enable */
-#define CMD_PSE (1<<4) /* periodic schedule enable */
-/* 3:2 is periodic frame list size */
-#define CMD_RESET (1<<1) /* reset HC not bus */
-#define CMD_RUN (1<<0) /* start/stop HC */
-
- /* USBSTS: offset 0x04 */
- u32 status;
-#define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */
-#define STS_ASS (1<<15) /* Async Schedule Status */
-#define STS_PSS (1<<14) /* Periodic Schedule Status */
-#define STS_RECL (1<<13) /* Reclamation */
-#define STS_HALT (1<<12) /* Not running (any reason) */
-/* some bits reserved */
- /* these STS_* flags are also intr_enable bits (USBINTR) */
-#define STS_IAA (1<<5) /* Interrupted on async advance */
-#define STS_FATAL (1<<4) /* such as some PCI access errors */
-#define STS_FLR (1<<3) /* frame list rolled over */
-#define STS_PCD (1<<2) /* port change detect */
-#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
-#define STS_INT (1<<0) /* "normal" completion (short, ...) */
-
- /* USBINTR: offset 0x08 */
- u32 intr_enable;
-
- /* FRINDEX: offset 0x0C */
- u32 frame_index; /* current microframe number */
- /* CTRLDSSEGMENT: offset 0x10 */
- u32 segment; /* address bits 63:32 if needed */
- /* PERIODICLISTBASE: offset 0x14 */
- u32 frame_list; /* points to periodic list */
- /* ASYNCLISTADDR: offset 0x18 */
- u32 async_next; /* address of next async queue head */
-
- u32 reserved[9];
-
- /* CONFIGFLAG: offset 0x40 */
- u32 configured_flag;
-#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
-
- /* PORTSC: offset 0x44 */
- u32 port_status[0]; /* up to N_PORTS */
-/* EHCI 1.1 addendum */
-#define PORTSC_SUSPEND_STS_ACK 0
-#define PORTSC_SUSPEND_STS_NYET 1
-#define PORTSC_SUSPEND_STS_STALL 2
-#define PORTSC_SUSPEND_STS_ERR 3
-
-#define PORT_DEV_ADDR (0x7f<<25) /* device address */
-#define PORT_SSTS (0x3<<23) /* suspend status */
-/* 31:23 reserved */
-#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
-#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
-#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
-/* 19:16 for port testing */
-#define PORT_TEST_PKT (0x4<<16) /* Port Test Control - packet test */
-#define PORT_LED_OFF (0<<14)
-#define PORT_LED_AMBER (1<<14)
-#define PORT_LED_GREEN (2<<14)
-#define PORT_LED_MASK (3<<14)
-#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
-#define PORT_POWER (1<<12) /* true: has power (see PPC) */
-#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
-/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
-/* 9 reserved */
-#define PORT_LPM (1<<9) /* LPM transaction */
-#define PORT_RESET (1<<8) /* reset port */
-#define PORT_SUSPEND (1<<7) /* suspend port */
-#define PORT_RESUME (1<<6) /* resume it */
-#define PORT_OCC (1<<5) /* over current change */
-#define PORT_OC (1<<4) /* over current active */
-#define PORT_PEC (1<<3) /* port enable change */
-#define PORT_PE (1<<2) /* port enable */
-#define PORT_CSC (1<<1) /* connect status change */
-#define PORT_CONNECT (1<<0) /* device connected */
-#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
-} __attribute__ ((packed));
-
-#define USBMODE 0x68 /* USB Device mode */
-#define USBMODE_SDIS (1<<3) /* Stream disable */
-#define USBMODE_BE (1<<2) /* BE/LE endianness select */
-#define USBMODE_CM_HC (3<<0) /* host controller mode */
-#define USBMODE_CM_IDLE (0<<0) /* idle state */
-
-/* Moorestown has some non-standard registers, partially due to the fact that
- * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
- * PORTSCx
- */
-#define HOSTPC0 0x84 /* HOSTPC extension */
-#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
-#define HOSTPC_PSPD (3<<25) /* Port speed detection */
-#define USBMODE_EX 0xc8 /* USB Device mode extension */
-#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */
-#define USBMODE_EX_HC (3<<0) /* host controller mode */
-#define TXFILLTUNING 0x24 /* TX FIFO Tuning register */
-#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
-
-/* Appendix C, Debug port ... intended for use with special "debug devices"
- * that can help if there's no serial console. (nonstandard enumeration.)
- */
-struct ehci_dbg_port {
- u32 control;
-#define DBGP_OWNER (1<<30)
-#define DBGP_ENABLED (1<<28)
-#define DBGP_DONE (1<<16)
-#define DBGP_INUSE (1<<10)
-#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
-# define DBGP_ERR_BAD 1
-# define DBGP_ERR_SIGNAL 2
-#define DBGP_ERROR (1<<6)
-#define DBGP_GO (1<<5)
-#define DBGP_OUT (1<<4)
-#define DBGP_LEN(x) (((x)>>0)&0x0f)
- u32 pids;
-#define DBGP_PID_GET(x) (((x)>>16)&0xff)
-#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
- u32 data03;
- u32 data47;
- u32 address;
-#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
-} __attribute__ ((packed));
-#endif
diff --git a/src/include/usb_ch9.h b/src/include/usb_ch9.h
deleted file mode 100644
index b0aa773..0000000
--- a/src/include/usb_ch9.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#ifndef USB_CH9_H
-#define USB_CH9_H
-
-#define USB_DIR_OUT 0 /* to device */
-#define USB_DIR_IN 0x80 /* to host */
-
-/*
- * USB types, the second of three bRequestType fields
- */
-#define USB_TYPE_MASK (0x03 << 5)
-#define USB_TYPE_STANDARD (0x00 << 5)
-#define USB_TYPE_CLASS (0x01 << 5)
-#define USB_TYPE_VENDOR (0x02 << 5)
-#define USB_TYPE_RESERVED (0x03 << 5)
-/*
- * USB recipients, the third of three bRequestType fields
- */
-#define USB_RECIP_MASK 0x1f
-#define USB_RECIP_DEVICE 0x00
-#define USB_RECIP_INTERFACE 0x01
-#define USB_RECIP_ENDPOINT 0x02
-#define USB_RECIP_OTHER 0x03
-/* From Wireless USB 1.0 */
-#define USB_RECIP_PORT 0x04
-#define USB_RECIP_RPIPE 0x05
-
-/*
- * Standard requests, for the bRequest field of a SETUP packet.
- *
- * These are qualified by the bRequestType field, so that for example
- * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
- * by a GET_STATUS request.
- */
-#define USB_REQ_GET_STATUS 0x00
-#define USB_REQ_CLEAR_FEATURE 0x01
-#define USB_REQ_SET_FEATURE 0x03
-#define USB_REQ_SET_ADDRESS 0x05
-#define USB_REQ_GET_DESCRIPTOR 0x06
-#define USB_REQ_SET_DESCRIPTOR 0x07
-#define USB_REQ_GET_CONFIGURATION 0x08
-#define USB_REQ_SET_CONFIGURATION 0x09
-#define USB_REQ_GET_INTERFACE 0x0A
-#define USB_REQ_SET_INTERFACE 0x0B
-#define USB_REQ_SYNCH_FRAME 0x0C
-
-#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */
-#define USB_REQ_GET_ENCRYPTION 0x0E
-#define USB_REQ_RPIPE_ABORT 0x0E
-#define USB_REQ_SET_HANDSHAKE 0x0F
-#define USB_REQ_RPIPE_RESET 0x0F
-#define USB_REQ_GET_HANDSHAKE 0x10
-#define USB_REQ_SET_CONNECTION 0x11
-#define USB_REQ_SET_SECURITY_DATA 0x12
-#define USB_REQ_GET_SECURITY_DATA 0x13
-#define USB_REQ_SET_WUSB_DATA 0x14
-#define USB_REQ_LOOPBACK_DATA_WRITE 0x15
-#define USB_REQ_LOOPBACK_DATA_READ 0x16
-#define USB_REQ_SET_INTERFACE_DS 0x17
-
-#define USB_DT_DEBUG 0x0a
-
-#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
-
-struct usb_ctrlrequest {
- u8 bRequestType;
- u8 bRequest;
- u16 wValue;
- u16 wIndex;
- u16 wLength;
-} __attribute__ ((packed));
-
-struct usb_debug_descriptor {
- u8 bLength;
- u8 bDescriptorType;
-
- /* bulk endpoints with 8 byte maxpacket */
- u8 bDebugInEndpoint;
- u8 bDebugOutEndpoint;
-};
-
-#endif
-
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
deleted file mode 100644
index 926d658..0000000
--- a/src/include/usbdebug.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#ifndef USBDEBUG_H
-#define USBDEBUG_H
-
-#define EHCI_BAR_INDEX 0x10
-#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
-
-typedef u32 pci_devfn_t;
-pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx);
-unsigned long pci_ehci_base_regs(pci_devfn_t dev);
-void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port);
-void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base);
-
-#ifndef __PRE_RAM__
-#if !CONFIG_USBDEBUG
-#define pci_ehci_read_resources pci_dev_read_resources
-#else
-/* Relocation of EHCI Debug Port BAR
- *
- * PCI EHCI controller with Debug Port capability shall replace
- * pci_dev_read_resources() with pci_ehci_read_resources() in its
- * declaration of device_operations for .read_resources.
- * This installs a hook to reconfigure usbdebug when resource allocator
- * assigns a new BAR for the device.
- */
-struct device;
-void pci_ehci_read_resources(struct device *dev);
-#endif
-#endif
-
-struct dbgp_pipe;
-
-int usbdebug_init(void);
-
-struct dbgp_pipe *dbgp_console_output(void);
-struct dbgp_pipe *dbgp_console_input(void);
-int dbgp_ep_is_active(struct dbgp_pipe *pipe);
-int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size);
-int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size);
-void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data);
-void usbdebug_tx_flush(struct dbgp_pipe *pipe);
-#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 18b30ef..b1b4748 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -49,7 +49,6 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
romstage-$(CONFIG_SPKMODEM) += spkmodem.c
-romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usbdebug.c
ifeq ($(CONFIG_EARLY_CBMEM_INIT),y)
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
@@ -92,7 +91,6 @@ romstage-y += clog2.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
-ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
ramstage-$(CONFIG_SPKMODEM) += spkmodem.c
ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
ramstage-$(CONFIG_TRACE) += trace.c
diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
deleted file mode 100644
index 885599b..0000000
--- a/src/lib/usbdebug.c
+++ /dev/null
@@ -1,1043 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Eric Biederman (ebiederm(a)xmission.com)
- * Copyright (C) 2007 AMD
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#include <stddef.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-#include <arch/byteorder.h>
-#include <arch/early_variables.h>
-#include <string.h>
-#include <cbmem.h>
-
-#include <usb_ch9.h>
-#include <ehci.h>
-#include <usbdebug.h>
-
-
-#define DBGP_EP_VALID (1<<0)
-#define DBGP_EP_ENABLED (1<<1)
-#define DBGP_EP_BUSY (1<<2)
-#define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED)
-
-struct dbgp_pipe
-{
- u8 devnum;
- u8 endpoint;
- u8 pid;
- u8 status;
- int timeout;
-
- u8 bufidx;
- char buf[8];
-};
-
-#define DBGP_MAX_ENDPOINTS 4
-#define DBGP_SETUP_EP0 0 /* Compulsory endpoint 0. */
-#define DBGP_CONSOLE_EPOUT 1
-#define DBGP_CONSOLE_EPIN 2
-
-struct ehci_debug_info {
- void *ehci_caps;
- void *ehci_regs;
- void *ehci_debug;
-
- struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS];
-};
-
-#if CONFIG_DEBUG_USBDEBUG
-static void dbgp_print_data(struct ehci_dbg_port *ehci_debug);
-static int dbgp_enabled(void);
-# define dprintk(LEVEL, args...) \
- do { if (!dbgp_enabled()) printk(LEVEL, ##args); } while (0)
-#else
-# define dbgp_print_data(x) do {} while(0)
-# define dprintk(LEVEL, args...) do {} while(0)
-#endif
-
-#define USB_DEBUG_DEVNUM 127
-
-#define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f))
-/*
- * USB Packet IDs (PIDs)
- */
-
-/* token */
-#define USB_PID_OUT 0xe1
-#define USB_PID_IN 0x69
-#define USB_PID_SOF 0xa5
-#define USB_PID_SETUP 0x2d
-/* handshake */
-#define USB_PID_ACK 0xd2
-#define USB_PID_NAK 0x5a
-#define USB_PID_STALL 0x1e
-#define USB_PID_NYET 0x96
-/* data */
-#define USB_PID_DATA0 0xc3
-#define USB_PID_DATA1 0x4b
-#define USB_PID_DATA2 0x87
-#define USB_PID_MDATA 0x0f
-/* Special */
-#define USB_PID_PREAMBLE 0x3c
-#define USB_PID_ERR 0x3c
-#define USB_PID_SPLIT 0x78
-#define USB_PID_PING 0xb4
-#define USB_PID_UNDEF_0 0xf0
-
-#define USB_PID_DATA_TOGGLE 0x88
-#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
-
-#define PCI_CAP_ID_EHCI_DEBUG 0xa
-
-#define HUB_ROOT_RESET_TIME 50 /* times are in msec */
-#define HUB_SHORT_RESET_TIME 10
-#define HUB_LONG_RESET_TIME 200
-#define HUB_RESET_TIMEOUT 500
-
-#define DBGP_MICROFRAME_TIMEOUT_LOOPS 1000
-#define DBGP_MICROFRAME_RETRIES 10
-#define DBGP_MAX_PACKET 8
-
-static struct ehci_debug_info glob_dbg_info CAR_GLOBAL;
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
-static struct device_operations *ehci_drv_ops;
-static struct device_operations ehci_dbg_ops;
-#endif
-
-static inline struct ehci_debug_info *dbgp_ehci_info(void)
-{
- return car_get_var_ptr(&glob_dbg_info);
-}
-
-static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
-{
- u32 ctrl;
- int loop = 0;
-
- do {
- ctrl = read32((unsigned long)&ehci_debug->control);
- /* Stop when the transaction is finished */
- if (ctrl & DBGP_DONE)
- break;
- } while (++loop < DBGP_MICROFRAME_TIMEOUT_LOOPS);
-
- if (! (ctrl & DBGP_DONE)) {
- dprintk(BIOS_ERR, "dbgp_wait_until_complete: retry timeout.\n");
- return -DBGP_ERR_SIGNAL;
- }
-
- /* Now that we have observed the completed transaction,
- * clear the done bit.
- */
- write32((unsigned long)&ehci_debug->control, ctrl | DBGP_DONE);
- return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
-}
-
-static void dbgp_breath(void)
-{
- /* Sleep to give the debug port a chance to breathe */
-}
-
-static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
- unsigned ctrl, const int timeout)
-{
- u32 rd_ctrl, rd_pids;
- u32 ctrl_prev = 0, pids_prev = 0;
- u8 lpid;
- int ret, host_retries;
- int loop;
-
- loop = 0;
-device_retry:
- host_retries = 0;
- if (loop++ >= timeout)
- return -DBGP_ERR_BAD;
-
-host_retry:
- if (host_retries++ >= DBGP_MICROFRAME_RETRIES)
- return -DBGP_ERR_BAD;
- if (loop == 1 || host_retries > 1)
- dprintk(BIOS_SPEW, "dbgp: start (@ %3d,%d) ctrl=%08x\n",
- loop, host_retries, ctrl | DBGP_GO);
- write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO);
- ret = dbgp_wait_until_complete(ehci_debug);
- rd_ctrl = read32((unsigned long)&ehci_debug->control);
- rd_pids = read32((unsigned long)&ehci_debug->pids);
-
- if (rd_ctrl != ctrl_prev || rd_pids != pids_prev || (ret<0)) {
- ctrl_prev = rd_ctrl;
- pids_prev = rd_pids;
- dprintk(BIOS_SPEW, "dbgp: status (@ %3d,%d) ctrl=%08x pids=%08x ret=%d\n",
- loop, host_retries, rd_ctrl, rd_pids, ret);
- }
-
- /* Controller hardware failure. */
- if (ret == -DBGP_ERR_SIGNAL) {
- return ret;
-
- /* Bus failure (corrupted microframe). */
- } else if (ret == -DBGP_ERR_BAD) {
- goto host_retry;
- }
-
- lpid = DBGP_PID_GET(rd_pids);
-
- /* If I get an ACK or in-sync DATA PID, we are done. */
- if ((lpid == USB_PID_ACK) || (lpid == pipe->pid)) {
- if (DBGP_LEN(rd_ctrl))
- pipe->pid ^= USB_PID_DATA_TOGGLE;
- }
-
- /* If the port is getting full or it has dropped data
- * start pacing ourselves, not necessary but it's friendly.
- */
- else if (lpid == USB_PID_NYET) {
- dbgp_breath();
- goto device_retry;
- }
-
- /* If I get a NACK or out-of-sync DATA PID, reissue the transmission. */
- else if ((lpid == USB_PID_NAK) || (lpid == (pipe->pid ^ USB_PID_DATA_TOGGLE))) {
- goto device_retry;
- }
-
- /* Abort on STALL handshake for endpoint 0.*/
- else if ((lpid == USB_PID_STALL) && (pipe->endpoint == 0x0)) {
- ret = -DBGP_ERR_BAD;
- }
-
- dbgp_print_data(ehci_debug);
-
- return ret;
-}
-
-static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int size)
-{
- const unsigned char *bytes = buf;
- u32 lo, hi;
- int i;
-
- lo = hi = 0;
- for (i = 0; i < 4 && i < size; i++)
- lo |= bytes[i] << (8*i);
- for (; i < 8 && i < size; i++)
- hi |= bytes[i] << (8*(i - 4));
- write32((unsigned long)&ehci_debug->data03, lo);
- write32((unsigned long)&ehci_debug->data47, hi);
-}
-
-static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
-{
- unsigned char *bytes = buf;
- u32 lo, hi;
- int i;
-
- lo = read32((unsigned long)&ehci_debug->data03);
- hi = read32((unsigned long)&ehci_debug->data47);
- for (i = 0; i < 4 && i < size; i++)
- bytes[i] = (lo >> (8*i)) & 0xff;
- for (; i < 8 && i < size; i++)
- bytes[i] = (hi >> (8*(i - 4))) & 0xff;
-}
-
-#if CONFIG_DEBUG_USBDEBUG
-static void dbgp_print_data(struct ehci_dbg_port *ehci_debug)
-{
- u32 ctrl = read32((unsigned long)&ehci_debug->control);
- u32 lo = read32((unsigned long)&ehci_debug->data03);
- u32 hi = read32((unsigned long)&ehci_debug->data47);
- int len = DBGP_LEN(ctrl);
- if (len) {
- int i;
- dprintk(BIOS_SPEW, "dbgp: buf:");
- for (i = 0; i < 4 && i < len; i++)
- dprintk(BIOS_SPEW, " %02x", (lo >> (8*i)) & 0xff);
- for (; i < 8 && i < len; i++)
- dprintk(BIOS_SPEW, " %02x", (hi >> (8*(i - 4))) & 0xff);
- dprintk(BIOS_SPEW, "\n");
- }
-}
-#endif
-
-static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
- const char *bytes, int size)
-{
- u32 pids, addr, ctrl;
- int ret;
-
- if (size > DBGP_MAX_PACKET)
- return -1;
-
- addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
- pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
-
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl = DBGP_LEN_UPDATE(ctrl, size);
- ctrl |= DBGP_OUT;
-
- dbgp_set_data(ehci_debug, bytes, size);
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
-
- ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
-
- return ret;
-}
-
-int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
- return dbgp_bulk_write(dbg_info->ehci_debug, pipe, bytes, size);
-}
-
-static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe,
- void *data, int size)
-{
- u32 pids, addr, ctrl;
- int ret;
-
- if (size > DBGP_MAX_PACKET)
- return -1;
-
- addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
- pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
-
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl = DBGP_LEN_UPDATE(ctrl, size);
- ctrl &= ~DBGP_OUT;
-
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
- ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
- if (ret < 0)
- return ret;
-
- if (size > ret)
- size = ret;
- dbgp_get_data(ehci_debug, data, size);
- return ret;
-}
-
-int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
- return dbgp_bulk_read(dbg_info->ehci_debug, pipe, data, size);
-}
-
-static void dbgp_mdelay(int ms)
-{
- int i;
-
- while (ms--) {
- for (i = 0; i < 1000; i++)
- inb(0x80);
- }
-}
-
-static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype,
- int request, int value, int index, void *data, int size)
-{
- struct ehci_debug_info *info = dbgp_ehci_info();
- struct dbgp_pipe *pipe = &info->ep_pipe[DBGP_SETUP_EP0];
- u32 pids, addr, ctrl;
- struct usb_ctrlrequest req;
- int read;
- int ret, ret2;
-
- read = (requesttype & USB_DIR_IN) != 0;
- if (size > DBGP_MAX_PACKET)
- return -1;
-
- /* Compute the control message */
- req.bRequestType = requesttype;
- req.bRequest = request;
- req.wValue = cpu_to_le16(value);
- req.wIndex = cpu_to_le16(index);
- req.wLength = cpu_to_le16(size);
-
- pipe->devnum = devnum;
- pipe->endpoint = 0;
- pipe->pid = USB_PID_DATA0;
- pipe->timeout = 1000;
- addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
- pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP);
-
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
- ctrl |= DBGP_OUT;
-
- /* Setup stage */
- dbgp_set_data(ehci_debug, &req, sizeof(req));
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
- ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, 1);
- if (ret < 0)
- return ret;
-
- /* Data stage (optional) */
- if (read && size)
- ret = dbgp_bulk_read(ehci_debug, pipe, data, size);
- else if (!read && size)
- ret = dbgp_bulk_write(ehci_debug, pipe, data, size);
-
- /* Status stage in opposite direction */
- pipe->pid = USB_PID_DATA1;
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl = DBGP_LEN_UPDATE(ctrl, 0);
- if (read) {
- pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
- ctrl |= DBGP_OUT;
- } else {
- pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
- ctrl &= ~DBGP_OUT;
- }
-
- write32((unsigned long)&ehci_debug->pids, pids);
- ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
- if (ret2 < 0)
- return ret2;
-
- return ret;
-}
-
-static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
-{
- u32 portsc;
- u32 delay_time, delay_ms;
- int loop;
-
- /* Reset the usb debug port */
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
- portsc &= ~PORT_PE;
- portsc |= PORT_RESET;
- write32((unsigned long)&ehci_regs->port_status[port - 1], portsc);
-
- delay_ms = HUB_ROOT_RESET_TIME;
- for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
- delay_time += delay_ms) {
- dbgp_mdelay(delay_ms);
-
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
- if (portsc & PORT_RESET) {
- /* force reset to complete */
- loop = 2;
- write32((unsigned long)&ehci_regs->port_status[port - 1],
- portsc & ~(PORT_RWC_BITS | PORT_RESET));
- do {
- dbgp_mdelay(delay_ms);
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
- delay_time += delay_ms;
- } while ((portsc & PORT_RESET) && (--loop > 0));
- if (!loop) {
- printk(BIOS_DEBUG, "ehci_reset_port forced done");
- }
- }
-
- /* Device went away? */
- if (!(portsc & PORT_CONNECT))
- return -1; //-ENOTCONN;
-
- /* bomb out completely if something weird happened */
- if ((portsc & PORT_CSC))
- return -2; //-EINVAL;
-
- /* If we've finished resetting, then break out of the loop */
- if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
- return 0;
- }
- return -3; //-EBUSY;
-}
-
-static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
-{
- u32 status;
- int ret, reps;
-
- for (reps = 0; reps < 3; reps++) {
- dbgp_mdelay(100);
- status = read32((unsigned long)&ehci_regs->status);
- if (status & STS_PCD) {
- ret = ehci_reset_port(ehci_regs, port);
- if (ret == 0)
- return 0;
- }
- }
- return -1; //-ENOTCONN;
-}
-
-#define USB_HUB_PORT_CONNECTION 0
-#define USB_HUB_PORT_ENABLED 1
-#define USB_HUB_PORT_RESET 4
-#define USB_HUB_PORT_POWER 8
-#define USB_HUB_C_PORT_CONNECTION 16
-#define USB_HUB_C_PORT_RESET 20
-
-#if CONFIG_USBDEBUG_OPTIONAL_HUB_PORT
-
-static int hub_port_status(const char * buf, int feature)
-{
- return !!(buf[feature>>3] & (1<<(feature&0x7)));
-}
-
-static int dbgp_hub_enable(struct ehci_dbg_port *ehci_debug, unsigned int port)
-{
- const u8 hub_addr = USB_DEBUG_DEVNUM-1;
- char status[8];
- int ret, loop;
-
- /* Move hub to address 126. */
- ret = dbgp_control_msg(ehci_debug, 0,
- USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_SET_ADDRESS, hub_addr, 0, NULL, 0);
- if (ret < 0)
- goto err;
-
- /* Enter configured state on hub. */
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0);
- if (ret < 0)
- goto err;
-
- /* Set PORT_POWER, poll for PORT_CONNECTION. */
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_SET_FEATURE, USB_HUB_PORT_POWER, port, NULL, 0);
- if (ret < 0)
- goto err;
-
- loop = 100;
- do {
- dbgp_mdelay(10);
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_GET_STATUS, 0, port, status, 4);
- if (ret < 0)
- goto err;
- if (hub_port_status(status, USB_HUB_PORT_CONNECTION))
- break;
- } while (--loop);
- if (! loop)
- goto err;
-
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_CLEAR_FEATURE, USB_HUB_C_PORT_CONNECTION, port, NULL, 0);
- if (ret < 0)
- goto err;
-
-
- /* Set PORT_RESET, poll for C_PORT_RESET. */
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_SET_FEATURE, USB_HUB_PORT_RESET, port, NULL, 0);
- if (ret < 0)
- goto err;
-
- loop = 100;
- do {
- dbgp_mdelay(10);
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_GET_STATUS, 0, port, status, 4);
- if (ret < 0)
- goto err;
- if (hub_port_status(status, USB_HUB_C_PORT_RESET))
- break;
- } while (--loop);
- if (! loop)
- goto err;
-
- ret = dbgp_control_msg(ehci_debug, hub_addr,
- USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
- USB_REQ_CLEAR_FEATURE, USB_HUB_C_PORT_RESET, port, NULL, 0);
- if (ret < 0)
- goto err;
-
- if (hub_port_status(status, USB_HUB_PORT_ENABLED))
- return 0;
-err:
- return -1;
-}
-#endif /* CONFIG_USBDEBUG_OPTIONAL_HUB_PORT */
-
-static void enable_usbdebug(void)
-{
-#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE
- pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
- pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR);
-#endif
-}
-
-static void set_debug_port(unsigned int port)
-{
- pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
- pci_ehci_dbg_set_port(dbg_dev, port);
-}
-
-static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info)
-{
- struct ehci_caps *ehci_caps;
- struct ehci_regs *ehci_regs;
- struct ehci_dbg_port *ehci_debug;
-
- struct usb_debug_descriptor dbgp_desc;
- u32 cmd, ctrl, status, portsc, hcs_params;
- u32 debug_port, new_debug_port = 0, n_ports;
- u32 devnum;
- int ret, i, configured;
- int loop;
- int port_map_tried;
- int playtimes = 3;
-
- ehci_caps = (struct ehci_caps *)ehci_bar;
- ehci_regs = (struct ehci_regs *)(ehci_bar +
- HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
- ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
- info->ehci_debug = (void *)0;
- memset(&info->ep_pipe, 0, sizeof (info->ep_pipe));
-
- if (CONFIG_USBDEBUG_DEFAULT_PORT > 0)
- set_debug_port(CONFIG_USBDEBUG_DEFAULT_PORT);
- else
- set_debug_port(1);
-
-try_next_time:
- port_map_tried = 0;
-
-try_next_port:
- hcs_params = read32((unsigned long)&ehci_caps->hcs_params);
- debug_port = HCS_DEBUG_PORT(hcs_params);
- n_ports = HCS_N_PORTS(hcs_params);
-
- dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar);
- dprintk(BIOS_INFO, "debug_port: %d\n", debug_port);
- dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
-
- for (i = 1; i <= n_ports; i++) {
- portsc = read32((unsigned long)&ehci_regs->port_status[i-1]);
- dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
- }
-
- if(port_map_tried && (new_debug_port != debug_port)) {
- if(--playtimes) {
- set_debug_port(debug_port);
- goto try_next_time;
- }
- return -1;
- }
-
- /* Wait until the controller is halted */
- status = read32((unsigned long)&ehci_regs->status);
- if (!(status & STS_HALT)) {
- cmd = read32((unsigned long)&ehci_regs->command);
- cmd &= ~CMD_RUN;
- write32((unsigned long)&ehci_regs->command, cmd);
- loop = 100;
- do {
- dbgp_mdelay(10);
- status = read32((unsigned long)&ehci_regs->status);
- } while (!(status & STS_HALT) && (--loop > 0));
- if (status & STS_HALT)
- dprintk(BIOS_INFO, "EHCI controller halted successfully.\n");
- else
- dprintk(BIOS_INFO, "EHCI controller is not halted. Reset may fail.\n");
- }
-
- loop = 100;
- /* Reset the EHCI controller */
- cmd = read32((unsigned long)&ehci_regs->command);
- cmd |= CMD_RESET;
- write32((unsigned long)&ehci_regs->command, cmd);
- do {
- dbgp_mdelay(10);
- cmd = read32((unsigned long)&ehci_regs->command);
- } while ((cmd & CMD_RESET) && (--loop > 0));
-
- if(!loop) {
- dprintk(BIOS_INFO, "Could not reset EHCI controller.\n");
- // on some systems it works without succeeding here.
- // return -2;
- } else {
- dprintk(BIOS_INFO, "EHCI controller reset successfully.\n");
- }
-
- /* Claim ownership, but do not enable yet */
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl |= DBGP_OWNER;
- ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
- write32((unsigned long)&ehci_debug->control, ctrl);
-
- /* Start EHCI controller */
- cmd = read32((unsigned long)&ehci_regs->command);
- cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
- cmd |= CMD_RUN;
- write32((unsigned long)&ehci_regs->command, cmd);
-
- /* Ensure everything is routed to the EHCI */
- write32((unsigned long)&ehci_regs->configured_flag, FLAG_CF);
-
- /* Wait until the controller is no longer halted */
- loop = 10;
- do {
- dbgp_mdelay(10);
- status = read32((unsigned long)&ehci_regs->status);
- } while ((status & STS_HALT) && (--loop > 0));
-
- if(!loop) {
- dprintk(BIOS_INFO, "EHCI could not be started.\n");
- return -3;
- }
- dprintk(BIOS_INFO, "EHCI started.\n");
-
- /* Wait for a device to show up in the debug port */
- ret = ehci_wait_for_port(ehci_regs, debug_port);
- if (ret < 0) {
- dprintk(BIOS_INFO, "No device found in debug port %d\n", debug_port);
- goto next_debug_port;
- }
- dprintk(BIOS_INFO, "EHCI done waiting for port.\n");
-
- /* Enable the debug port */
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl |= DBGP_CLAIM;
- write32((unsigned long)&ehci_debug->control, ctrl);
- ctrl = read32((unsigned long)&ehci_debug->control);
- if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
- dprintk(BIOS_INFO, "No device in EHCI debug port.\n");
- write32((unsigned long)&ehci_debug->control, ctrl & ~DBGP_CLAIM);
- ret = -4;
- goto err;
- }
- dprintk(BIOS_INFO, "EHCI debug port enabled.\n");
-
- /* Completely transfer the debug device to the debug controller */
- portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]);
- portsc &= ~PORT_PE;
- write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc);
-
- dbgp_mdelay(100);
-
-#if CONFIG_USBDEBUG_OPTIONAL_HUB_PORT
- ret = dbgp_hub_enable(ehci_debug, CONFIG_USBDEBUG_OPTIONAL_HUB_PORT);
- if (ret < 0) {
- dprintk(BIOS_INFO, "Could not enable USB hub on debug port.\n");
- ret = -6;
- goto err;
- }
-#endif
-
- /* Find the debug device and make it device number 127 */
- devnum = 0;
-debug_dev_retry:
- memset(&dbgp_desc, 0, sizeof(dbgp_desc));
- ret = dbgp_control_msg(ehci_debug, devnum,
- USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
- &dbgp_desc, sizeof(dbgp_desc));
- if (ret == sizeof(dbgp_desc)) {
- if (dbgp_desc.bLength == sizeof(dbgp_desc) && dbgp_desc.bDescriptorType==USB_DT_DEBUG)
- goto debug_dev_found;
- else
- dprintk(BIOS_INFO, "Invalid debug device descriptor.\n");
- }
- if (devnum == 0) {
- devnum = USB_DEBUG_DEVNUM;
- goto debug_dev_retry;
- } else {
- dprintk(BIOS_INFO, "Could not find attached debug device.\n");
- ret = -5;
- goto err;
- }
-debug_dev_found:
-
- /* Move the device to 127 if it isn't already there */
- if (devnum != USB_DEBUG_DEVNUM) {
- ret = dbgp_control_msg(ehci_debug, devnum,
- USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
- if (ret < 0) {
- dprintk(BIOS_INFO, "Could not move attached device to %d.\n",
- USB_DEBUG_DEVNUM);
- ret = -7;
- goto err;
- }
- devnum = USB_DEBUG_DEVNUM;
- dprintk(BIOS_INFO, "EHCI debug device renamed to 127.\n");
- }
-
- /* Enable the debug interface */
- ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
- USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
- if (ret < 0) {
- dprintk(BIOS_INFO, "Could not enable EHCI debug device.\n");
- ret = -8;
- goto err;
- }
- dprintk(BIOS_INFO, "EHCI debug interface enabled.\n");
-
- /* Prepare endpoint pipes. */
- for (i=1; i<DBGP_MAX_ENDPOINTS; i++) {
- info->ep_pipe[i].devnum = USB_DEBUG_DEVNUM;
- info->ep_pipe[i].pid = USB_PID_DATA0;
- info->ep_pipe[i].timeout = 1000;
- }
- info->ep_pipe[DBGP_CONSOLE_EPOUT].endpoint = dbgp_desc.bDebugOutEndpoint;
- info->ep_pipe[DBGP_CONSOLE_EPIN].endpoint = dbgp_desc.bDebugInEndpoint;
-
- /* Perform a small write. */
- configured = 0;
-small_write:
- ret = dbgp_bulk_write(ehci_debug, &info->ep_pipe[DBGP_CONSOLE_EPOUT], "USB\r\n",5);
- if (ret < 0) {
- dprintk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret);
- if (!configured) {
- /* Send Set Configure request to device. This is required for FX2
- (CY7C68013) to transfer from USB state Addressed to Configured,
- only then endpoints other than 0 are enabled. */
- if (dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
- USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
- USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0) >= 0) {
- configured = 1;
- goto small_write;
- }
- }
- ret = -9;
- goto err;
- }
- dprintk(BIOS_INFO, "Test write done\n");
-
- info->ehci_caps = ehci_caps;
- info->ehci_regs = ehci_regs;
- info->ehci_debug = ehci_debug;
-
- info->ep_pipe[DBGP_SETUP_EP0].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
- info->ep_pipe[DBGP_CONSOLE_EPOUT].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
- info->ep_pipe[DBGP_CONSOLE_EPIN].status |= DBGP_EP_ENABLED | DBGP_EP_VALID;
- return 0;
-err:
- /* Things didn't work so remove my claim */
- ctrl = read32((unsigned long)&ehci_debug->control);
- ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
- write32((unsigned long)(unsigned long)&ehci_debug->control, ctrl);
- //return ret;
-
-next_debug_port:
-#if CONFIG_USBDEBUG_DEFAULT_PORT==0
- port_map_tried |= (1 << (debug_port - 1));
- new_debug_port = ((debug_port-1 + 1) % n_ports) + 1;
- if (port_map_tried != ((1 << n_ports) - 1)) {
- set_debug_port(new_debug_port);
- goto try_next_port;
- }
- if (--playtimes) {
- set_debug_port(new_debug_port);
- goto try_next_time;
- }
-#else
- if (0)
- goto try_next_port;
- if (--playtimes)
- goto try_next_time;
-#endif
-
- return -10;
-}
-
-#if CONFIG_DEBUG_USBDEBUG
-static int dbgp_enabled(void)
-{
- struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
- return (globals->status & DBGP_EP_ENABLED);
-}
-#endif
-
-static int dbgp_try_get(struct dbgp_pipe *pipe)
-{
- struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
- if (!dbgp_ep_is_active(pipe) || (globals->status & DBGP_EP_BUSY))
- return 0;
- globals->status |= DBGP_EP_BUSY;
- pipe->status |= DBGP_EP_BUSY;
- return 1;
-}
-
-static void dbgp_put(struct dbgp_pipe *pipe)
-{
- struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0];
- globals->status &= ~DBGP_EP_BUSY;
- pipe->status &= ~DBGP_EP_BUSY;
-}
-
-void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data)
-{
- if (!dbgp_try_get(pipe))
- return;
- pipe->buf[pipe->bufidx++] = data;
- if (pipe->bufidx >= 8) {
- dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx);
- pipe->bufidx = 0;
- }
- dbgp_put(pipe);
-}
-
-void usbdebug_tx_flush(struct dbgp_pipe *pipe)
-{
- if (!dbgp_try_get(pipe))
- return;
- if (pipe->bufidx > 0) {
- dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx);
- pipe->bufidx = 0;
- }
- dbgp_put(pipe);
-}
-
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
-static void usbdebug_re_enable(unsigned ehci_base)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
- unsigned diff;
- int i;
-
- if (!dbg_info->ehci_debug)
- return;
-
- diff = (unsigned)dbg_info->ehci_caps - ehci_base;
- dbg_info->ehci_regs -= diff;
- dbg_info->ehci_debug -= diff;
- dbg_info->ehci_caps = (void*)ehci_base;
-
- for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
- dbg_info->ep_pipe[i].status |= DBGP_EP_ENABLED;
-}
-
-static void usbdebug_disable(void)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
- int i;
- for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
- dbg_info->ep_pipe[i].status &= ~DBGP_EP_ENABLED;
-}
-
-static void pci_ehci_set_resources(struct device *dev)
-{
- struct resource *res;
-
- printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev));
- usbdebug_disable();
-
- if (ehci_drv_ops->set_resources)
- ehci_drv_ops->set_resources(dev);
- res = find_resource(dev, EHCI_BAR_INDEX);
- if (!res)
- return;
-
- usbdebug_re_enable((u32)res->base);
- report_resource_stored(dev, res, "");
- printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev));
-}
-
-void pci_ehci_read_resources(struct device *dev)
-{
- pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
-
- if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) {
- memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops));
- ehci_drv_ops = dev->ops;
- ehci_dbg_ops.set_resources = pci_ehci_set_resources;
- dev->ops = &ehci_dbg_ops;
- printk(BIOS_DEBUG, "%s EHCI BAR hook registered\n", dev_path(dev));
- } else {
- printk(BIOS_DEBUG, "More than one caller of %s from %s\n", __func__, dev_path(dev));
- }
-
- pci_dev_read_resources(dev);
-}
-#endif
-
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
-static int get_usbdebug_from_cbmem(struct ehci_debug_info *info)
-{
- struct ehci_debug_info *dbg_info_cbmem;
-
- dbg_info_cbmem = cbmem_find(CBMEM_ID_EHCI_DEBUG);
- if (dbg_info_cbmem == NULL)
- return -1;
-
- memcpy(info, dbg_info_cbmem, sizeof (*info));
- printk(BIOS_DEBUG, "EHCI debug port found in CBMEM.\n");
-
- return 0;
-}
-
-#elif defined(__PRE_RAM__)
-static void migrate_ehci_debug(void)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
- struct ehci_debug_info *dbg_info_cbmem;
-
- dbg_info_cbmem = cbmem_add(CBMEM_ID_EHCI_DEBUG, sizeof(*dbg_info));
- if (dbg_info_cbmem == NULL)
- return;
-
- memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info));
-}
-CAR_MIGRATE(migrate_ehci_debug);
-#endif
-
-unsigned long pci_ehci_base_regs(pci_devfn_t sdev)
-{
-#ifdef __SIMPLE_DEVICE__
- unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f;
-#else
- device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
- unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f;
-#endif
- return base + HC_LENGTH(read32(base));
-}
-
-int dbgp_ep_is_active(struct dbgp_pipe *pipe)
-{
- return (pipe->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED);
-}
-
-struct dbgp_pipe *dbgp_console_output(void)
-{
- return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPOUT];
-}
-
-struct dbgp_pipe *dbgp_console_input(void)
-{
- return &dbgp_ehci_info()->ep_pipe[DBGP_CONSOLE_EPIN];
-}
-
-int usbdebug_init(void)
-{
- struct ehci_debug_info *dbg_info = dbgp_ehci_info();
-
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
- if (!get_usbdebug_from_cbmem(dbg_info))
- return 0;
-#endif
- enable_usbdebug();
- return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
-}
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index cce3925..258267e 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -22,7 +22,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "hudson.h"
diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c
index f5d0d4c..36eff6e 100644
--- a/src/southbridge/amd/agesa/hudson/usb.c
+++ b/src/southbridge/amd/agesa/hudson/usb.c
@@ -22,7 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
#include "hudson.h"
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index e2ecdc3..b03f13a 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -25,7 +25,7 @@
#include <device/smbus.h> /* smbus_bus_operations */
#include <pc80/mc146818rtc.h>
#include <console/console.h> /* printk */
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include "lpc.h" /* lpc_read_resources */
#include "Platform.h" /* Platfrom Specific Definitions */
#include "sb_cimx.h"
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 90b26ae..3a534cd 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -26,7 +26,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h> /* printk */
#include <arch/acpi.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include "lpc.h" /* lpc_read_resources */
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
#include "cfg.h" /* sb800 Cimx configuration */
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index d2ce72c..3cd603c 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -24,7 +24,7 @@
#include <device/smbus.h> /* smbus_bus_operations */
#include <pc80/mc146818rtc.h>
#include <console/console.h> /* printk */
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include "lpc.h" /* lpc_read_resources */
#include "SbPlatform.h" /* Platfrom Specific Definitions */
#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index 09fce2f..0f25ead 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -22,7 +22,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "sb600.h"
diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c
index d551661..d55f561 100644
--- a/src/southbridge/amd/sb600/usb.c
+++ b/src/southbridge/amd/sb600/usb.c
@@ -22,7 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
#include "sb600.h"
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 57798c1..3d23da0 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -23,7 +23,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "sb700.h"
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
index d3a9f3e..77dcf2e 100644
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -22,7 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
#include "sb700.h"
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index 34d7608..74e3d33 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -22,7 +22,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "sb800.h"
diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c
index 305a7e6..9304344 100644
--- a/src/southbridge/amd/sb800/usb.c
+++ b/src/southbridge/amd/sb800/usb.c
@@ -22,7 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
#include "sb800.h"
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index d2bf690..78f92d9 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
static void usb_ehci_init(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 2b8ae28..19c419f 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
static void usb_xhci_init(struct device *dev)
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index 9fe22cd..fecd716 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -23,7 +23,7 @@
#include <stdint.h>
#include <arch/io.h>
#include <console/console.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c
index 5dd5866..9e5c48e 100644
--- a/src/southbridge/intel/i82801dx/usb2.c
+++ b/src/southbridge/intel/i82801dx/usb2.c
@@ -24,7 +24,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include "i82801dx.h"
static void usb2_init(struct device *dev)
diff --git a/src/southbridge/intel/i82801ex/ehci.c b/src/southbridge/intel/i82801ex/ehci.c
index 045840a..28164c5 100644
--- a/src/southbridge/intel/i82801ex/ehci.c
+++ b/src/southbridge/intel/i82801ex/ehci.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include "i82801ex.h"
static void ehci_init(struct device *dev)
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index 8dcda39..bb176c7 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
static void usb_ehci_init(struct device *dev)
diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c
index b6c0edd..6276995 100644
--- a/src/southbridge/intel/i82801ix/usb_ehci.c
+++ b/src/southbridge/intel/i82801ix/usb_ehci.c
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801ix.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
static void usb_ehci_init(struct device *dev)
{
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index d941438..7dc7b03 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -24,7 +24,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
static void usb_ehci_init(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index 4382611..845129f 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -23,7 +23,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <arch/io.h>
#include "pch.h"
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index d98bc98..97e8ecb 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -26,7 +26,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "ck804.h"
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index b0afec2..23c2219 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -26,7 +26,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "mcp55.h"
diff --git a/src/southbridge/nvidia/mcp55/usb2.c b/src/southbridge/nvidia/mcp55/usb2.c
index 1f129ec..a9174f6 100644
--- a/src/southbridge/nvidia/mcp55/usb2.c
+++ b/src/southbridge/nvidia/mcp55/usb2.c
@@ -27,7 +27,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "mcp55.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
static void usb2_init(struct device *dev)
{
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index 0d7503d..274aeb7 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -28,7 +28,7 @@
#include <stdint.h>
#include <arch/io.h>
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "sis966.h"
diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c
index 195c982..e2112eb 100644
--- a/src/southbridge/sis/sis966/usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
@@ -30,7 +30,7 @@
#include <device/pci_ops.h>
#include <arch/io.h>
#include "sis966.h"
-#include <usbdebug.h>
+#include <device/pci_ehci.h>
static const u8 SiS_SiS7002_init[22][3]={
{0x04, 0x00, 0x06},
1
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05 Feb '14
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4289
-gerrit
commit a17336cc2794f75f240b5c43296acb8f6cb10901
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Thu Oct 17 18:50:13 2013 +0300
usbdebug: Add BeagleBone Black
Avoid some confusion as the selection of "BeagleBone" is not compatible
with the product "BeagleBone Black".
Change-Id: If73f80565cd26d2b41db972b4474ab85b609c1ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/console/Kconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 40903c1..45464dc 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -227,6 +227,11 @@ config USBDEBUG_DONGLE_BEAGLEBONE
help
Use this to configure the USB hub on BeagleBone board.
+config USBDEBUG_DONGLE_BEAGLEBONE_BLACK
+ bool "BeagleBone Black"
+ help
+ Use this with BeagleBone Black.
+
endchoice
config USBDEBUG_OPTIONAL_HUB_PORT
1
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