coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: cd7bff9 Add an xdr function for the cbfs_file header
by Alexandru Gagniuc 05 Feb '14

05 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5120 -gerrit commit cd7bff9b9c0adf272fb2fc57d3533cae1d73d153 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Tue Feb 4 17:35:44 2014 -0800 Add an xdr function for the cbfs_file header And use it in fit.c and remove one more use of htonl. Change-Id: Ibf18dcc0a7f08d75c2374115de0db7a4bf64ec1e Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> --- util/cbfstool/cbfs.h | 3 +++ util/cbfstool/common.h | 1 + util/cbfstool/fit.c | 19 +++++++++++++++---- util/cbfstool/xdr.c | 9 +++++++++ 4 files changed, 28 insertions(+), 4 deletions(-) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 527c867..1839646 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -126,6 +126,9 @@ uint32_t get_cbfs_entry_type(const char *name, uint32_t default_value); const char *get_cbfs_entry_type_name(uint32_t type); uint32_t get_cbfs_compression(const char *name, uint32_t unknown); +/* common.c */ +void cbfs_file_get_header(struct buffer *buf, struct cbfs_file *file); + /* elfheaders.c */ int elf_headers(const struct buffer *pinput, diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 5bcbcbe..5d3b900 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -110,5 +110,6 @@ struct xdr { /* xdr.c */ extern struct xdr xdr_le, xdr_be; +int bgets(struct buffer *input, void *output, size_t len); #endif diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index a368dad..84f0bff 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -188,17 +188,28 @@ static void add_microcodde_entries(struct cbfs_image *image, } } +static int fit_header(void *ptr, uint32_t *current_offset, uint32_t *file_length) +{ + struct buffer buf; + struct cbfs_file header; + buf.data = ptr; + buf.size = sizeof(header); + cbfs_file_get_header(&buf, &header); + *current_offset = header.offset; + *file_length = header.len; + return 0; +} + static int parse_microcode_blob(struct cbfs_image *image, struct cbfs_file *mcode_file, struct microcode_entry *mcus, int *total_mcus) { int num_mcus; - int current_offset; - int file_length; + uint32_t current_offset; + uint32_t file_length; current_offset = (int)((char *)mcode_file - image->buffer.data); - current_offset += ntohl(mcode_file->offset); - file_length = ntohl(mcode_file->len); + fit_header(mcode_file, &current_offset, &file_length); num_mcus = 0; while (file_length > sizeof(struct microcode_header)) diff --git a/util/cbfstool/xdr.c b/util/cbfstool/xdr.c index d779675..ddc282e 100644 --- a/util/cbfstool/xdr.c +++ b/util/cbfstool/xdr.c @@ -25,6 +25,15 @@ #include <stdint.h> #include "common.h" +int bgets(struct buffer *input, void *output, size_t len) +{ + len = input->size < len ? input->size : len; + memmove(output, input->data, len); + input->data += len; + input->size -= len; + return len; +} + /* The assumption in all this code is that we're given a pointer to enough data. * Hence, we do not check for underflow. */

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Patch merged into coreboot/master: 22d4072 mainboard/google: add initial rambi mainboard support
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 22d40720bfb9459d2b1f6ea9b514220497c8e76f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 4 16:00:07 2013 -0500 mainboard/google: add initial rambi mainboard support BUG=chrome-os-partner:23121 BRANCH=None TEST=None Change-Id: I283415be326e2d92e1e1bf7866954f17a7266edb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171940 Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> See http://review.coreboot.org/4865 for details. -gerrit

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Patch merged into coreboot/master: 96aaaad baytrail: initialize punit
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 96aaaad8ac0b6f885a1d018be4f56dffea929655 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 4 11:17:45 2013 -0500 baytrail: initialize punit The punit is responsible for a number of things. Without performing the sequence included it won't change processor frequency when requested and apparently there are some bizarre hangs introduced if this sequence isn't included either. Lastly, this needs to come after microcode has been loaded. As that is done in bootblock the ordering is correct. One other side effect is that this fixes the graphics devices' device id. Before it was showing up as the same device id of the SoC transaction router. BUG=chrome-os-partner:22880 BUG=chrome-os-partner:23085 BUG=chrome-os-partner:22876 BRANCH=None TEST=Built and booted. Change-Id: Ib7be1d4b365e9a45647c778ee5f91de497c55bf1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171862 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4864 for details. -gerrit

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Patch merged into coreboot/master: 4e9be94 baytrail: load microcode in bootblock
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 4e9be94fa562c6946257dda09e3328c36c48e979 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 4 11:15:48 2013 -0500 baytrail: load microcode in bootblock Start loading microcode in the bootblock. This way no caching has been set up and cache-as-ram mode will be running in a validated configruation (with ucode patch). BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and booted. Confirmed microcode is loaded. Change-Id: I6fd1d8e55bcc9d799b11d9faed771ac50dc120a2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171861 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4863 for details. -gerrit

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Patch merged into coreboot/master: 1fcaade baytrail: disable tco timer
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 1fcaade6d530cc924be2c8b0b3ee1d532457d107 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 4 11:11:52 2013 -0500 baytrail: disable tco timer The TCO timer always starts ticking out of reset. However, depending on microcode loading and punit initialization the TCO timing out has a different impact on the sytem. Without loading microcode or initializing the punit the tco times out and nothing happens. However, when microcode is loaded a timeout will reset the system. Lastly, if the punit is initialized but the microcode isn't loaded the TCO timeout will shut down the system. To fix all the weird symptoms disable the TCO. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and booted with microcode loading. Reset doesn't occur. Change-Id: I49cd62f510726a96bf734ae728a352c671d1561e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171860 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4862 for details. -gerrit

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Patch merged into coreboot/master: 3a24ff8 baytrail: program PUNIT memory-mapped base address
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 3a24ff8c704d9ad85e9e0e6669f0a91d9eb4984c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 3 12:56:37 2013 -0500 baytrail: program PUNIT memory-mapped base address Apparently there was another BAR living at 0x5c in the LPC bridge that mapped the PUNIT registers. EDS 2.0 released and this register is now documented. BUG=chrome-os-partner:23085 BRANCH=None TEST=Built and booted. Change-Id: I5892c2a14923b57826060e92b4335cb1952ea057 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171612 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4861 for details. -gerrit

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Patch merged into coreboot/master: 52261be baytrail: add 316 microcode
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 52261bec125a556632e9fa9f7a6ff19bf943ea4f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 3 09:01:45 2013 -0500 baytrail: add 316 microcode The 316 microcode is the newest version. Include that in the build. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and partially booted with microcode loading. Noted 316 loaded. Change-Id: Iba01dd58688737ae38bc58a84014ee9526540db1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171611 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4860 for details. -gerrit

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Patch merged into coreboot/master: 48535ef baytrail: additional iosf changes
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 48535ef14f63d9b9ba5f48d78247b80d6c99a995 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 3 08:57:17 2013 -0500 baytrail: additional iosf changes Allow for one to write an individual byte of a 32-bit register when sending a read/write through the IOSF messaging system. Add PUNIT registers and fields for early sequencing. BUG=chrome-os-partner:23085 BRANCH=None TEST=Built and partially booted with changes that use PUNIT registers and individual byte en fields. Change-Id: I929fb5c51d805c55c478cab884e3572254987fc7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171710 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4859 for details. -gerrit

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Patch merged into coreboot/master: 0087461 baytrail: import and use updated mrc_wrapper.h
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit 0087461bebb261f738bc7d401b351e0724f97377 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 2 11:06:31 2013 -0500 baytrail: import and use updated mrc_wrapper.h The mrc_wrapper.h was changed to protect against ABI differences between the two sets of compilers and flags used. This requires a prope shim for the console output funciton. BUG=chrome-os-partner:23048 BRANCH=None TEST=Built and booted successfully. Change-Id: I976e692e66dcfc0eacadae6173abfd9b81e31137 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171580 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4858 for details. -gerrit

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Patch merged into coreboot/master: f9347ec baytrail: Rearrange config options alphanumerically
by gerrit＠coreboot.org 05 Feb '14

05 Feb '14

the following patch was just integrated into master: commit f9347ec4150cc67f2725a6377f0eda20d298f806 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Sep 27 16:21:04 2013 -0700 baytrail: Rearrange config options alphanumerically This is a no-op change for easier maintenance. BUG=none TEST=manual . baitrail coreboot still builds and runs Change-Id: I0c0bd78c6f361e8f81979f19cce148e7f51865ee Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171002 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4857 for details. -gerrit

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coreboot-gerrit February 2014