coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch set updated for coreboot: 3b478e3 usbdebug: Improve receive speed
by Kyösti Mälkki 05 Feb '14

05 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4700 -gerrit commit 3b478e396bd2bd9f9d7f2bcf35159c8e10f45977 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jan 15 22:26:03 2014 +0200 usbdebug: Improve receive speed Read from USB endpoint_in 8 bytes at a time, the maximum what EHCI debug port capability has to offer. Change-Id: I3d012d758a24b24f894e587b301f620933331407 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/usbdebug_console.c | 7 +------ src/drivers/usb/ehci_debug.c | 18 ++++++++++++++++++ src/include/console/usb.h | 1 + 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c index 99726be..cb627bb 100644 --- a/src/console/usbdebug_console.c +++ b/src/console/usbdebug_console.c @@ -34,12 +34,7 @@ static void dbgp_tx_byte(unsigned char data) static unsigned char dbgp_rx_byte(void) { - unsigned char data = 0xff; - - if (dbgp_ep_is_active(dbgp_console_input())) - dbgp_bulk_read_x(dbgp_console_input(), &data, 1); - - return data; + return usbdebug_rx_byte(dbgp_console_input()); } static void dbgp_tx_flush(void) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 94625c0..b28208d 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -48,6 +48,7 @@ struct dbgp_pipe int timeout; u8 bufidx; + u8 buflen; char buf[8]; }; @@ -912,6 +913,23 @@ void usbdebug_tx_flush(struct dbgp_pipe *pipe) dbgp_put(pipe); } +unsigned char usbdebug_rx_byte(struct dbgp_pipe *pipe) +{ + unsigned char data = 0xff; + if (!dbgp_try_get(pipe)) + return 0xff; + while (pipe->bufidx >= pipe->buflen) { + pipe->buflen = 0; + pipe->bufidx = 0; + int count = dbgp_bulk_read_x(pipe, pipe->buf, 8); + if (count>0) + pipe->buflen = count; + } + data = pipe->buf[pipe->bufidx++]; + dbgp_put(pipe); + return data; +} + #if !defined(__PRE_RAM__) && !defined(__SMM__) static void usbdebug_re_enable(unsigned ehci_base) { diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 47f3d74..430557f 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -32,5 +32,6 @@ int dbgp_bulk_write_x(struct dbgp_pipe *pipe, const char *bytes, int size); int dbgp_bulk_read_x(struct dbgp_pipe *pipe, void *data, int size); void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data); void usbdebug_tx_flush(struct dbgp_pipe *pipe); +unsigned char usbdebug_rx_byte(struct dbgp_pipe *pipe); #endif /* _CONSOLE_USB_H_ */

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Patch set updated for coreboot: e3248d8 usbdebug: Fix data toggle on receive
by Kyösti Mälkki 05 Feb '14

05 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4775 -gerrit commit e3248d8ddb00a5caeb829c4af4ef735aef0fefea Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 21 10:44:08 2014 +0200 usbdebug: Fix data toggle on receive USB device end toggles data PID when we ACK'd the zero-length data packet. As USB host we need to toggle data PID too or the next data received would get discarded. Change-Id: I3203bc874c7ded9244c7548a666d7041a0fbb379 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/ehci_debug.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index b28208d..7413a8a 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -204,8 +204,7 @@ host_retry: /* If I get an ACK or in-sync DATA PID, we are done. */ if ((lpid == USB_PID_ACK) || (lpid == pipe->pid)) { - if (DBGP_LEN(rd_ctrl)) - pipe->pid ^= USB_PID_DATA_TOGGLE; + pipe->pid ^= USB_PID_DATA_TOGGLE; } /* If the port is getting full or it has dropped data

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Patch set updated for coreboot: 9a811f6 usbdebug: Reduce bus reset delays
by Kyösti Mälkki 05 Feb '14

05 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3863 -gerrit commit 9a811f64634b73ae9100dca69bd340dff7b88854 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Aug 12 21:35:20 2013 +0300 usbdebug: Reduce bus reset delays According to EHCI specification, host controller software stops the USB Reset condition by writing PORT_RESET=0. Software then poll-waits this bit until controller hardware has completed USB Reset sequence and read returns with PORT_RESET==0. Change-Id: I6033c4d904c2af9eb16f5f3c1eb825776648cc1d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/ehci_debug.c | 48 ++++++++++++++++++-------------------------- 1 file changed, 19 insertions(+), 29 deletions(-) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 7413a8a..e17f4cf 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -422,7 +422,6 @@ static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, i static int ehci_reset_port(struct ehci_regs *ehci_regs, int port) { u32 portsc; - u32 delay_time, delay_ms; int loop; /* Reset the usb debug port */ @@ -431,39 +430,30 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port) portsc |= PORT_RESET; write32((unsigned long)&ehci_regs->port_status[port - 1], portsc); - delay_ms = HUB_ROOT_RESET_TIME; - for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT; - delay_time += delay_ms) { - dbgp_mdelay(delay_ms); + dbgp_mdelay(HUB_ROOT_RESET_TIME); + portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]); + write32((unsigned long)&ehci_regs->port_status[port - 1], + portsc & ~(PORT_RWC_BITS | PORT_RESET)); + + loop = 100; + do { + dbgp_mdelay(1); portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]); - if (portsc & PORT_RESET) { - /* force reset to complete */ - loop = 2; - write32((unsigned long)&ehci_regs->port_status[port - 1], - portsc & ~(PORT_RWC_BITS | PORT_RESET)); - do { - dbgp_mdelay(delay_ms); - portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]); - delay_time += delay_ms; - } while ((portsc & PORT_RESET) && (--loop > 0)); - if (!loop) { - printk(BIOS_DEBUG, "ehci_reset_port forced done"); - } - } + } while ((portsc & PORT_RESET) && (--loop > 0)); - /* Device went away? */ - if (!(portsc & PORT_CONNECT)) - return -1; //-ENOTCONN; + /* Device went away? */ + if (!(portsc & PORT_CONNECT)) + return -1; //-ENOTCONN; - /* bomb out completely if something weird happened */ - if ((portsc & PORT_CSC)) - return -2; //-EINVAL; + /* bomb out completely if something weird happened */ + if ((portsc & PORT_CSC)) + return -2; //-EINVAL; + + /* If we've finished resetting, then break out of the loop */ + if (!(portsc & PORT_RESET) && (portsc & PORT_PE)) + return 0; - /* If we've finished resetting, then break out of the loop */ - if (!(portsc & PORT_RESET) && (portsc & PORT_PE)) - return 0; - } return -3; //-EBUSY; }

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Patch set updated for coreboot: fee54bb usbdebug: Remove duplicate port claim
by Kyösti Mälkki 05 Feb '14

05 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4709 -gerrit commit fee54bbb5faa59428cc0cca24961f5e343bc951c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 18 12:26:13 2014 +0200 usbdebug: Remove duplicate port claim This claim is useless when done before EHCI controller reset. Code in usbdebug_init_() already sets this properly after reset, see use of DBGP_OWNER. Change-Id: Ic17493fe4edbbbed6ebcbef35a264fbf188f1fba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/common/usb_debug.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index fecd716..d18cb0f 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -64,8 +64,6 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - u32 dbgctl; - /* Bail out. No console to complain in. */ if (!dev) return; @@ -75,9 +73,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); - - /* Force ownership of the Debug Port to the EHCI controller. */ - dbgctl = read32(base + CONFIG_EHCI_DEBUG_OFFSET); - dbgctl |= (1 << 30); - write32(base + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); }

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Patch set updated for coreboot: 4df9b2e usbdebug: Add optional quirk for old DIY debug part
by Kyösti Mälkki 05 Feb '14

05 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3868 -gerrit commit 4df9b2ea9e06605d7c6fa42917675c86bee039a5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 6 10:33:39 2013 +0300 usbdebug: Add optional quirk for old DIY debug part Not sure what this is about. Required for FX2. Change-Id: I86878f8f570911ed1ed3ec844c232ac91e934072 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/ehci_debug.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index e17f4cf..be9a508 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -720,10 +720,12 @@ try_next_port: } dprintk(BIOS_INFO, "EHCI debug port enabled.\n"); +#if 0 /* Completely transfer the debug device to the debug controller */ portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]); portsc &= ~PORT_PE; write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc); +#endif dbgp_mdelay(100);

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New patch to review for coreboot: eb81d9d boardstatus/towiki: Add AMD socket and chip names.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5128 -gerrit commit eb81d9d9f3019edee50626000d719ab65a8200f1 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 13:02:26 2014 +0100 boardstatus/towiki: Add AMD socket and chip names. Change-Id: I3fd34a8a9eb758845e0d3775963aae23208acc3c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/board_status/to-wiki/towiki.sh | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 7e2685e..6715f03 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -383,9 +383,19 @@ EOF RDC_R8610) cpu_nice="RDC 8610" socket_nice="—";; - AMD_AGESA_FAMILY14|AMD_AGESA_FAMILY15_TN|AMD_AGESA_FAMILY15_KB|AMD_AGESA_FAMILY16_KB|AMD_AGESA_FAMILY12) - cpu_nice="?" - socket_nice="?";; + AMD_AGESA_FAMILY15_TN|AMD_AGESA_FAMILY15_KB) + cpu_nice="AMD Phenom II / Athlon II / FX" + socket_nice="AM3+";; + + AMD_AGESA_FAMILY14) + cpu_nice="AMD APU (Bobcat)"; + socket_nice="FT1 BGA";; + AMD_AGESA_FAMILY16_KB) + cpu_nice="Kabini / Temash"; + socket_nice="FT3";; + AMD_AGESA_FAMILY12) + cpu_nice="AMD APU (Llano)"; + socket_nice="FM1";; *) cpu_nice="$northbridge" socket_nice="$northbridge";;

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New patch to review for coreboot: 5b5f490 boardstatus/towiki: Fix 1st gen i3/i5/i7 codename
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5127 -gerrit commit 5b5f490383b543d222ed2d9cd9823287361336d9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 13:01:47 2014 +0100 boardstatus/towiki: Fix 1st gen i3/i5/i7 codename It was a typo. Change-Id: I82964b5ed7e7749ba141aeb3ee8dc4c107bcd7a9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/board_status/to-wiki/towiki.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index bd6c8e9..7e2685e 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -378,7 +378,7 @@ EOF "") case $northbridge in INTEL_NEHALEM) - cpu_nice="Intel® 1st Gen (Haswell) Core i3/i5/i7" + cpu_nice="Intel® 1st Gen (Nehalem) Core i3/i5/i7" socket_nice="?";; RDC_R8610) cpu_nice="RDC 8610"

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New patch to review for coreboot: 4ac284e boardstatus/towiki: Describe qemu emulated northbridge.
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5126 -gerrit commit 4ac284ec96f021ed63b33d6f73427abbf5c0d6df Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 12:22:47 2014 +0100 boardstatus/towiki: Describe qemu emulated northbridge. Change-Id: I642f8d2320fae2af6baa65f70d2ea19ed488f7c0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/board_status/to-wiki/towiki.sh | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 5225f72..bd6c8e9 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -366,6 +366,12 @@ EOF socket_nice="?" ;; QEMU_X86) + case "$southbridge" in + INTEL_I82371EB) + northbridge_nice="Intel® I440FX";; + INTEL_I82801IX) + northbridge_nice="Intel® Q35";; + esac cpu_nice="QEMU x86"; socket_nice="—" ;;

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New patch to review for coreboot: d12199f boardstatus/towiki: Describe socket AM2 CPUs
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5125 -gerrit commit d12199f4c9b9462b4b72a19ec76513fec57f6d58 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 12:22:18 2014 +0100 boardstatus/towiki: Describe socket AM2 CPUs Change-Id: I1a12f0e9b8113a3573dfc9c5009f4199c9e98abc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/board_status/to-wiki/towiki.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 796a6f0..5225f72 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -246,7 +246,7 @@ EOF cpu_nice="AMD Opteron™ Magny-Cours/Interlagos"; socket_nice="Socket C32";; AMD_SOCKET_AM2) - cpu_nice="?"; + cpu_nice="AMD Athlon™ 64 / X2 / FX, Sempron™"; socket_nice="Socket AM2" ;; AMD_SOCKET_AM3)

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New patch to review for coreboot: e9846f0 boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs
by Vladimir Serbinenko 05 Feb '14

05 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5124 -gerrit commit e9846f012e4339a756b118f40a1ab8cabbb4b691 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 12:21:40 2014 +0100 boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs Change-Id: I3a38ca834606bb53e6f82cbe79c3a99288429aee Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/board_status/to-wiki/towiki.sh | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 46cc3c2..796a6f0 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -224,6 +224,8 @@ EOF case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" + northbridge_nice="Allwinner A10" + southbridge_nice="Allwinner A10" socket_nice="?";; AMD_GEODE_*) cpu_nice="AMD Geode™ ${cpu#AMD_GEODE_}"; @@ -272,22 +274,32 @@ EOF socket_nice="Socket 939" ;; AMD_SC520) - cpu_nice="AMD Élan™SC520"; + cpu_nice="AMD Élan™ SC520"; + northbridge_nice="AMD Élan™ SC520"; + southbridge_nice="AMD Élan™ SC520"; socket_nice="—";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; + northbridge_nice="ARM Cortex A9"; + southbridge_nice="ARM Cortex A9"; socket_nice="?";; DMP_VORTEX86EX) cpu_nice="DMP VORTEX86EX"; socket_nice="?";; SAMSUNG_EXYNOS5420) cpu_nice="Samsung Exynos 5420"; + northbridge_nice="Samsung Exynos 5420"; + southbridge_nice="Samsung Exynos 5420"; socket_nice="?";; SAMSUNG_EXYNOS5250) cpu_nice="Samsung Exynos 5250"; + northbridge_nice="Samsung Exynos 5250"; + southbridge_nice="Samsung Exynos 5250"; socket_nice="?";; TI_AM335X) cpu_nice="TI AM335X"; + southbridge_nice="TI AM335X"; + northbridge_nice="TI AM335X"; socket_nice="?";; INTEL_SLOT_1) cpu_nice="Intel® Pentium® II/III, Celeron®"; @@ -378,6 +390,16 @@ EOF socket_nice="$cpu";; esac + if [ x"$northbridge_nice" = x ]; then + if grep 'select SOC_INTEL_BAYTRAIL' "$vendor_board_dir/Kconfig" > /dev/null ; then + southbridge_nice="Intel® Baytrail" + northbridge_nice="Intel® Baytrail" + cpu_nice="Intel® Baytrail" + socket_nice="—" + fi + fi + + echo "|- bgcolor=\"#$color\"" echo "| $vendor_nice" echo -n "| [[Board:$vendor/$board|$board_nice]]"

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coreboot-gerrit February 2014