Patch set updated for coreboot: e757220 cbfstool: add code to serialize the header using the new xdr functions
by Alexandru Gagniuc 02 Feb '14
by Alexandru Gagniuc 02 Feb '14
02 Feb '14
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5100
-gerrit
commit e757220cfcb335a200d41cae990a4295e410ab0b
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Mon Jan 6 08:38:15 2014 -0800
cbfstool: add code to serialize the header using the new xdr functions
This change adds a header serialization function. Programmers can thus just
set up a header as needed, without worrying about forgetting if and how to
use the [hn]to[hn]* functions.
In the long term, we will work to remove swab.h, i.e. we need to get to the
point where programmers don't have to try to remember [hn]to[nh]* and where
it goes. To date, even the best programmers we have have made an error with
those functions, and those errors have persisted for 6 or 7 years now. It's
very easy to make that mistake.
BUG=None
TEST=Build a peppy image and verify that it's bit for bit the same. All
chromebooks use this code and build and boot correctly.
BRANCH=None
Change-Id: I0f9b8e7cac5f52d0ea330ba948650fa0803aa0d5
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/181552
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Ronald Minnich <rminnich(a)chromium.org>
---
util/cbfstool/cbfs_image.c | 41 ++++++++++++++++++++++++++++-------------
util/cbfstool/cbfs_image.h | 4 ++++
2 files changed, 32 insertions(+), 13 deletions(-)
diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 363691f..dddd480 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -139,6 +139,21 @@ static int cbfs_fix_legacy_size(struct cbfs_image *image)
return 0;
}
+void cbfs_put_header(void *dest, const struct cbfs_header *header)
+{
+ struct buffer outheader;
+
+ outheader.data = dest;
+ outheader.size = 0;
+
+ xdr_be.put32(&outheader, header->magic);
+ xdr_be.put32(&outheader, header->version);
+ xdr_be.put32(&outheader, header->romsize);
+ xdr_be.put32(&outheader, header->bootblocksize);
+ xdr_be.put32(&outheader, header->align);
+ xdr_be.put32(&outheader, header->offset);
+ xdr_be.put32(&outheader, header->architecture);
+}
int cbfs_image_create(struct cbfs_image *image,
uint32_t myarch,
size_t size,
@@ -148,7 +163,7 @@ int cbfs_image_create(struct cbfs_image *image,
int32_t header_offset,
int32_t entries_offset)
{
- struct cbfs_header *header;
+ struct cbfs_header header;
struct cbfs_file *entry;
uint32_t cbfs_len;
size_t entry_header_len;
@@ -156,7 +171,7 @@ int cbfs_image_create(struct cbfs_image *image,
DEBUG("cbfs_image_create: bootblock=0x%x+0x%zx, "
"header=0x%x+0x%zx, entries_offset=0x%x\n",
bootblock_offset, bootblock->size,
- header_offset, sizeof(*header), entries_offset);
+ header_offset, sizeof(header), entries_offset);
if (buffer_create(&image->buffer, size, "(new)") != 0)
return -1;
@@ -194,20 +209,20 @@ int cbfs_image_create(struct cbfs_image *image,
bootblock->size);
// Prepare header
- if (header_offset + sizeof(*header) > size) {
+ if (header_offset + sizeof(header) > size) {
ERROR("Header (0x%x+0x%zx) exceed ROM size (0x%zx)\n",
- header_offset, sizeof(*header), size);
+ header_offset, sizeof(header), size);
return -1;
}
- header = (struct cbfs_header *)(image->buffer.data + header_offset);
- image->header = header;
- header->magic = htonl(CBFS_HEADER_MAGIC);
- header->version = htonl(CBFS_HEADER_VERSION);
- header->romsize = htonl(size);
- header->bootblocksize = htonl(bootblock->size);
- header->align = htonl(align);
- header->offset = htonl(entries_offset);
- header->architecture = htonl(myarch);
+ image->header = (struct cbfs_header *)(image->buffer.data + header_offset);
+ header.magic = CBFS_HEADER_MAGIC;
+ header.version = CBFS_HEADER_VERSION;
+ header.romsize = size;
+ header.bootblocksize = bootblock->size;
+ header.align = align;
+ header.offset = entries_offset;
+ header.architecture = myarch;
+ cbfs_put_header(image->header, &header);
// Prepare entries
if (align_up(entries_offset, align) != entries_offset) {
diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h
index 7ad418a..8ea4e47 100644
--- a/util/cbfstool/cbfs_image.h
+++ b/util/cbfstool/cbfs_image.h
@@ -31,6 +31,10 @@ struct cbfs_image {
struct cbfs_header *header;
};
+/* Given a pointer, serialize the header from host-native byte format
+ * to cbfs format, i.e. big-endian. */
+void cbfs_put_header(void *dest, const struct cbfs_header *header);
+
/* Creates an empty CBFS image by given size, and description to its content
* (bootblock, align, header location, starting offset of CBFS entries.
* The output image will contain a valid cbfs_header, with one cbfs_file
1
0
Patch set updated for coreboot: 790e093 cbfstool: add code to serialize the header using the new xdr functions
by Ronald G. Minnich 02 Feb '14
by Ronald G. Minnich 02 Feb '14
02 Feb '14
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5100
-gerrit
commit 790e09346fefb3508169c1abf9717018dd353aef
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Mon Jan 6 08:38:15 2014 -0800
cbfstool: add code to serialize the header using the new xdr functions
This change adds a header serialization function. Programmers can thus just
set up a header as needed, without worrying about forgetting if and how to
use the [hn]to[hn]* functions.
In the long term, we will work to remove swab.h, i.e. we need to get to the
point where programmers don't have to try to remember [hn]to[nh]* and where
it goes. To date, even the best programmers we have have made an error with
those functions, and those errors have persisted for 6 or 7 years now. It's
very easy to make that mistake.
BUG=None
TEST=Build a peppy image and verify that it's bit for bit the same. All chromebooks use this code
and build and boot correctly.
BRANCH=None
Change-Id: I0f9b8e7cac5f52d0ea330ba948650fa0803aa0d5
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/181552
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Ronald Minnich <rminnich(a)chromium.org>
---
3rdparty | 2 +-
util/cbfstool/cbfs_image.c | 41 ++++++++++++++++++++++++++++-------------
util/cbfstool/cbfs_image.h | 4 ++++
3 files changed, 33 insertions(+), 14 deletions(-)
diff --git a/3rdparty b/3rdparty
index 324ec3c..aebd218 160000
--- a/3rdparty
+++ b/3rdparty
@@ -1 +1 @@
-Subproject commit 324ec3cb642a278d6d97ae809bc6098045bc6e65
+Subproject commit aebd21811dc9c9a171e629150d9d8a239a8b0338
diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 363691f..fd10015 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -139,6 +139,21 @@ static int cbfs_fix_legacy_size(struct cbfs_image *image)
return 0;
}
+void cbfs_put_header(void *dest, struct cbfs_header *header)
+{
+ struct buffer outheader;
+
+ outheader.data = dest;
+ outheader.size = 0;
+
+ xdr_be.put32(&outheader, header->magic);
+ xdr_be.put32(&outheader, header->version);
+ xdr_be.put32(&outheader, header->romsize);
+ xdr_be.put32(&outheader, header->bootblocksize);
+ xdr_be.put32(&outheader, header->align);
+ xdr_be.put32(&outheader, header->offset);
+ xdr_be.put32(&outheader, header->architecture);
+}
int cbfs_image_create(struct cbfs_image *image,
uint32_t myarch,
size_t size,
@@ -148,7 +163,7 @@ int cbfs_image_create(struct cbfs_image *image,
int32_t header_offset,
int32_t entries_offset)
{
- struct cbfs_header *header;
+ struct cbfs_header header;
struct cbfs_file *entry;
uint32_t cbfs_len;
size_t entry_header_len;
@@ -156,7 +171,7 @@ int cbfs_image_create(struct cbfs_image *image,
DEBUG("cbfs_image_create: bootblock=0x%x+0x%zx, "
"header=0x%x+0x%zx, entries_offset=0x%x\n",
bootblock_offset, bootblock->size,
- header_offset, sizeof(*header), entries_offset);
+ header_offset, sizeof(header), entries_offset);
if (buffer_create(&image->buffer, size, "(new)") != 0)
return -1;
@@ -194,20 +209,20 @@ int cbfs_image_create(struct cbfs_image *image,
bootblock->size);
// Prepare header
- if (header_offset + sizeof(*header) > size) {
+ if (header_offset + sizeof(header) > size) {
ERROR("Header (0x%x+0x%zx) exceed ROM size (0x%zx)\n",
- header_offset, sizeof(*header), size);
+ header_offset, sizeof(header), size);
return -1;
}
- header = (struct cbfs_header *)(image->buffer.data + header_offset);
- image->header = header;
- header->magic = htonl(CBFS_HEADER_MAGIC);
- header->version = htonl(CBFS_HEADER_VERSION);
- header->romsize = htonl(size);
- header->bootblocksize = htonl(bootblock->size);
- header->align = htonl(align);
- header->offset = htonl(entries_offset);
- header->architecture = htonl(myarch);
+ image->header = (struct cbfs_header *)(image->buffer.data + header_offset);
+ header.magic = CBFS_HEADER_MAGIC;
+ header.version = CBFS_HEADER_VERSION;
+ header.romsize = size;
+ header.bootblocksize = bootblock->size;
+ header.align = align;
+ header.offset = entries_offset;
+ header.architecture = myarch;
+ cbfs_put_header(image->header, &header);
// Prepare entries
if (align_up(entries_offset, align) != entries_offset) {
diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h
index 7ad418a..74c8f97 100644
--- a/util/cbfstool/cbfs_image.h
+++ b/util/cbfstool/cbfs_image.h
@@ -31,6 +31,10 @@ struct cbfs_image {
struct cbfs_header *header;
};
+/* Given a pointer, serialize the header from host-native byte format
+ * to cbfs format, i.e. big-endian. */
+void cbfs_put_header(void *dest, struct cbfs_header *header);
+
/* Creates an empty CBFS image by given size, and description to its content
* (bootblock, align, header location, starting offset of CBFS entries.
* The output image will contain a valid cbfs_header, with one cbfs_file
1
0
New patch to review for coreboot: b22f55c cbfstool: add code to serialize the header using the new xdr functions
by Ronald G. Minnich 02 Feb '14
by Ronald G. Minnich 02 Feb '14
02 Feb '14
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5100
-gerrit
commit b22f55c26fc83bcfffa3b788b772b341b41c4c82
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Mon Jan 6 08:38:15 2014 -0800
cbfstool: add code to serialize the header using the new xdr functions
This change adds a header serialization function. Programmers can thus just
set up a header as needed, without worrying about forgetting if and how to
use the [hn]to[hn]* functions.
In the long term, we will work to remove swab.h, i.e. we need to get to the
point where programmers don't have to try to remember [hn]to[nh]* and where
it goes. To date, even the best programmers we have have made an error with
those functions, and those errors have persisted for 6 or 7 years now. It's
very easy to make that mistake.
BUG=None
TEST=Build a peppy image and verify that it's bit for bit the same. All chromebooks use this code
and build and boot correctly.
BRANCH=None
Change-Id: I0f9b8e7cac5f52d0ea330ba948650fa0803aa0d5
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/181552
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Ronald Minnich <rminnich(a)chromium.org>
---
util/cbfstool/cbfs_image.c | 41 ++++++++++++++++++++++++++++-------------
util/cbfstool/cbfs_image.h | 4 ++++
2 files changed, 32 insertions(+), 13 deletions(-)
diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 363691f..d453899 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -139,6 +139,21 @@ static int cbfs_fix_legacy_size(struct cbfs_image *image)
return 0;
}
+void cbfs_put_header(void *dest, struct cbfs_header *header)
+{
+ struct buffer outheader;
+
+ outheader.data = dest;
+ outheader.size = 0;
+
+ xdr_be.put32(&outheader, header->magic);
+ xdr_be.put32(&outheader, header->version);
+ xdr_be.put32(&outheader, header->romsize);
+ xdr_be.put32(&outheader, header->bootblocksize);
+ xdr_be.put32(&outheader, header->align);
+ xdr_be.put32(&outheader, header->offset);
+ xdr_be.put32(&outheader, header->architecture);
+}
int cbfs_image_create(struct cbfs_image *image,
uint32_t myarch,
size_t size,
@@ -148,7 +163,7 @@ int cbfs_image_create(struct cbfs_image *image,
int32_t header_offset,
int32_t entries_offset)
{
- struct cbfs_header *header;
+ struct cbfs_header header;
struct cbfs_file *entry;
uint32_t cbfs_len;
size_t entry_header_len;
@@ -156,7 +171,7 @@ int cbfs_image_create(struct cbfs_image *image,
DEBUG("cbfs_image_create: bootblock=0x%x+0x%zx, "
"header=0x%x+0x%zx, entries_offset=0x%x\n",
bootblock_offset, bootblock->size,
- header_offset, sizeof(*header), entries_offset);
+ header_offset, sizeof(header), entries_offset);
if (buffer_create(&image->buffer, size, "(new)") != 0)
return -1;
@@ -194,20 +209,20 @@ int cbfs_image_create(struct cbfs_image *image,
bootblock->size);
// Prepare header
- if (header_offset + sizeof(*header) > size) {
+ if (header_offset + sizeof(header) > size) {
ERROR("Header (0x%x+0x%zx) exceed ROM size (0x%zx)\n",
- header_offset, sizeof(*header), size);
+ header_offset, sizeof(header), size);
return -1;
}
- header = (struct cbfs_header *)(image->buffer.data + header_offset);
- image->header = header;
- header->magic = htonl(CBFS_HEADER_MAGIC);
- header->version = htonl(CBFS_HEADER_VERSION);
- header->romsize = htonl(size);
- header->bootblocksize = htonl(bootblock->size);
- header->align = htonl(align);
- header->offset = htonl(entries_offset);
- header->architecture = htonl(myarch);
+ image->header = (struct cbfs_header *)(image->buffer.data + header_offset);
+ header.magic = CBFS_HEADER_MAGIC;
+ header.version = CBFS_HEADER_VERSION;
+ header.romsize = size;
+ header.bootblocksize = bootblock->size;
+ header.align = align;
+ header.offset = entries_offset;
+ header.architecture = architecture;
+ cbfs_put_header(image->header, &header);
// Prepare entries
if (align_up(entries_offset, align) != entries_offset) {
diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h
index 7ad418a..74c8f97 100644
--- a/util/cbfstool/cbfs_image.h
+++ b/util/cbfstool/cbfs_image.h
@@ -31,6 +31,10 @@ struct cbfs_image {
struct cbfs_header *header;
};
+/* Given a pointer, serialize the header from host-native byte format
+ * to cbfs format, i.e. big-endian. */
+void cbfs_put_header(void *dest, struct cbfs_header *header);
+
/* Creates an empty CBFS image by given size, and description to its content
* (bootblock, align, header location, starting offset of CBFS entries.
* The output image will contain a valid cbfs_header, with one cbfs_file
1
0
Patch merged into coreboot/master: f38f848 Add section header parsing and use it in the mk-payload step
by gerritï¼ coreboot.org 02 Feb '14
by gerritï¼ coreboot.org 02 Feb '14
02 Feb '14
the following patch was just integrated into master:
commit f38f84855f01b31a2de070d1237bb18f33584081
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Mon Dec 30 13:16:18 2013 -0800
Add section header parsing and use it in the mk-payload step
This completes the improvements to the ELF file parsing code. We can
now parse section headers too, across all 4 combinations of word size
and endianness. I had hoped to completely remove the use of htonl
until I found it in cbfs_image.c. That's a battle for another day.
There's now a handy macro to create magic numbers in host byte order.
I'm using it for all the PAYLOAD_SEGMENT_* constants and maybe
we can use it for the others too, but this is sensitive code and
I'd rather change one thing at a time.
To maximize the ease of use for users, elf parsing is accomplished with
just one function:
int
elf_headers(const struct buffer *pinput,
Elf64_Ehdr *ehdr,
Elf64_Phdr **pphdr,
Elf64_Shdr **pshdr)
which requires the ehdr and pphdr pointers to be non-NULL, but allows
the pshdr to be NULL. If pshdr is NULL, the code will not try to read
in section headers.
To satisfy our powerful scripts, I had to remove the ^M from an unrelated
microcode file.
BUG=None
TEST=Build a peppy image (known to boot) with old and new versions and verify they are bit-for-bit the same. This was also fully tested across all chromebooks for building and booting and running chromeos.
BRANCH=None
Change-Id: I54dad887d922428b6175fdb6a9cdfadd8a6bb889
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/181272
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Ronald Minnich <rminnich(a)chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
See http://review.coreboot.org/5098 for details.
-gerrit
1
0
Patch set updated for coreboot: 18c757a lenovo/x60: Unify volume button handling with common code.
by Vladimir Serbinenko 02 Feb '14
by Vladimir Serbinenko 02 Feb '14
02 Feb '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5099
-gerrit
commit 18c757a7331ac0cb3bd1cd2359b39d2202d31bd5
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Feb 2 18:44:42 2014 +0100
lenovo/x60: Unify volume button handling with common code.
Change-Id: I45fe44a91f9f83a510b204e01dbaff9e8a9696ca
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/ec/lenovo/h8/acpi/ec.asl | 2 --
src/mainboard/lenovo/x60/acpi/ec.asl | 23 -----------------------
2 files changed, 25 deletions(-)
diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
index 4b3fb12..b8c1625 100644
--- a/src/ec/lenovo/h8/acpi/ec.asl
+++ b/src/ec/lenovo/h8/acpi/ec.asl
@@ -227,7 +227,6 @@ Device(EC)
^HKEY.RHK (0x18)
}
-#if CONFIG_BOARD_LENOVO_X201
Method (_Q1C, 0, NotSerialized)
{
^HKEY.RHK (0x19)
@@ -237,7 +236,6 @@ Device(EC)
{
^HKEY.RHK (0x1A)
}
-#endif
Device (HKEY)
{
diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl
index fc02199..a92bc4a 100644
--- a/src/mainboard/lenovo/x60/acpi/ec.asl
+++ b/src/mainboard/lenovo/x60/acpi/ec.asl
@@ -20,26 +20,3 @@
*/
#include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
- /* Volume down */
- Method(_Q1C, 0, NotSerialized)
- {
- Trap(SMI_SAVE_CMOS)
- }
-
- /* Volume up */
- Method(_Q1D, 0, NotSerialized)
- {
- Trap(SMI_SAVE_CMOS)
- }
-
- /* Mute key pressed */
- Method(_Q1E, 0, NotSerialized)
- {
- Trap(SMI_SAVE_CMOS)
- }
-
-
-}
1
0
New patch to review for coreboot: 8fe57eb lenovo/x60: Unify volume button handling with common code.
by Vladimir Serbinenko 02 Feb '14
by Vladimir Serbinenko 02 Feb '14
02 Feb '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5099
-gerrit
commit 8fe57eb46d26747d202a77887b735120b375936b
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Feb 2 18:44:42 2014 +0100
lenovo/x60: Unify volume button handling with common code.
Change-Id: I45fe44a91f9f83a510b204e01dbaff9e8a9696ca
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/ec/lenovo/h8/acpi/ec.asl | 8 ++++++--
src/mainboard/lenovo/x60/acpi/ec.asl | 23 -----------------------
2 files changed, 6 insertions(+), 25 deletions(-)
diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
index 4b3fb12..75533cc 100644
--- a/src/ec/lenovo/h8/acpi/ec.asl
+++ b/src/ec/lenovo/h8/acpi/ec.asl
@@ -227,7 +227,6 @@ Device(EC)
^HKEY.RHK (0x18)
}
-#if CONFIG_BOARD_LENOVO_X201
Method (_Q1C, 0, NotSerialized)
{
^HKEY.RHK (0x19)
@@ -237,7 +236,12 @@ Device(EC)
{
^HKEY.RHK (0x1A)
}
-#endif
+
+ /* Mute */
+ Method (_Q1D, 0, NotSerialized)
+ {
+ ^HKEY.RHK (0x17)
+ }
Device (HKEY)
{
diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl
index fc02199..a92bc4a 100644
--- a/src/mainboard/lenovo/x60/acpi/ec.asl
+++ b/src/mainboard/lenovo/x60/acpi/ec.asl
@@ -20,26 +20,3 @@
*/
#include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
- /* Volume down */
- Method(_Q1C, 0, NotSerialized)
- {
- Trap(SMI_SAVE_CMOS)
- }
-
- /* Volume up */
- Method(_Q1D, 0, NotSerialized)
- {
- Trap(SMI_SAVE_CMOS)
- }
-
- /* Mute key pressed */
- Method(_Q1E, 0, NotSerialized)
- {
- Trap(SMI_SAVE_CMOS)
- }
-
-
-}
1
0
New patch to review for coreboot: f38f848 Add section header parsing and use it in the mk-payload step
by Ronald G. Minnich 02 Feb '14
by Ronald G. Minnich 02 Feb '14
02 Feb '14
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5098
-gerrit
commit f38f84855f01b31a2de070d1237bb18f33584081
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Mon Dec 30 13:16:18 2013 -0800
Add section header parsing and use it in the mk-payload step
This completes the improvements to the ELF file parsing code. We can
now parse section headers too, across all 4 combinations of word size
and endianness. I had hoped to completely remove the use of htonl
until I found it in cbfs_image.c. That's a battle for another day.
There's now a handy macro to create magic numbers in host byte order.
I'm using it for all the PAYLOAD_SEGMENT_* constants and maybe
we can use it for the others too, but this is sensitive code and
I'd rather change one thing at a time.
To maximize the ease of use for users, elf parsing is accomplished with
just one function:
int
elf_headers(const struct buffer *pinput,
Elf64_Ehdr *ehdr,
Elf64_Phdr **pphdr,
Elf64_Shdr **pshdr)
which requires the ehdr and pphdr pointers to be non-NULL, but allows
the pshdr to be NULL. If pshdr is NULL, the code will not try to read
in section headers.
To satisfy our powerful scripts, I had to remove the ^M from an unrelated
microcode file.
BUG=None
TEST=Build a peppy image (known to boot) with old and new versions and verify they are bit-for-bit the same. This was also fully tested across all chromebooks for building and booting and running chromeos.
BRANCH=None
Change-Id: I54dad887d922428b6175fdb6a9cdfadd8a6bb889
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/181272
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Ronald Minnich <rminnich(a)chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
---
.../intel/baytrail/microcode/M0C3067_00000313.h | 26112 +++++++++----------
util/cbfstool/Makefile | 2 +-
util/cbfstool/Makefile.inc | 1 +
util/cbfstool/cbfs-mkpayload.c | 166 +-
util/cbfstool/cbfs-mkstage.c | 241 +-
util/cbfstool/cbfs.h | 39 +-
util/cbfstool/cbfs_image.c | 1 +
util/cbfstool/cbfstool.c | 1 +
util/cbfstool/common.c | 2 +-
util/cbfstool/common.h | 12 +-
util/cbfstool/elfheaders.c | 343 +
util/cbfstool/fit.c | 1 +
12 files changed, 13530 insertions(+), 13391 deletions(-)
diff --git a/src/soc/intel/baytrail/microcode/M0C3067_00000313.h b/src/soc/intel/baytrail/microcode/M0C3067_00000313.h
index fb2256f..6861e89 100644
--- a/src/soc/intel/baytrail/microcode/M0C3067_00000313.h
+++ b/src/soc/intel/baytrail/microcode/M0C3067_00000313.h
@@ -1,13056 +1,13056 @@
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+0x08bfc599f,
+0x013414ca4,
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+0x0a1c280fd,
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+0x01b63466f,
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+0x0296949df,
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+0x0850b10d6,
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+0x0eedc7dfa,
+0x07499280e,
+0x0c07cabe7,
+0x0e4e41fc6,
+0x0c46f3a8c,
+0x0e7938cc5,
+0x08989be85,
+0x05509ff04,
+0x00103b6f9,
+0x06f39a300,
+0x0fa6b8175,
+0x0de21596e,
+0x0982f9875,
+0x06d5b1d5a,
+0x009c97f3a,
+0x0d26b9f9f,
+0x0889c5d14,
+0x0c81912e1,
+0x097602046,
+0x05dea1f3a,
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index b5f74b8..5064782 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -13,7 +13,7 @@ LDFLAGS += -g
BINARY:=$(obj)/cbfstool
COMMON:=cbfstool.o common.o cbfs_image.o compress.o fit.o
-COMMON+=cbfs-mkstage.o cbfs-mkpayload.o xdr.o
+COMMON+=elfheaders.o cbfs-mkstage.o cbfs-mkpayload.o xdr.o
# LZMA
COMMON+=lzma/lzma.o
COMMON+=lzma/C/LzFind.o lzma/C/LzmaDec.o lzma/C/LzmaEnc.o
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 4270d75..f3596fb 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -5,6 +5,7 @@ cbfsobj += compress.o
cbfsobj += cbfs_image.o
cbfsobj += cbfs-mkstage.o
cbfsobj += cbfs-mkpayload.o
+cbfsobj += elfheaders.o
cbfsobj += xdr.o
cbfsobj += fit.o
# LZMA
diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c
index 78988a0..b1dd1c0 100644
--- a/util/cbfstool/cbfs-mkpayload.c
+++ b/util/cbfstool/cbfs-mkpayload.c
@@ -23,18 +23,39 @@
#include <stdlib.h>
#include <string.h>
+#include "elf.h"
#include "common.h"
#include "cbfs.h"
-#include "elf.h"
#include "fv.h"
#include "coff.h"
+/* serialize the seg array into the buffer.
+ * The buffer is assumed to be large enough.
+ */
+static void xdr_segs(struct buffer *output,
+ struct cbfs_payload_segment *segs, int nseg)
+{
+ struct buffer outheader;
+ int i;
+
+ outheader.data = output->data;
+ outheader.size = 0;
+
+ for(i = 0; i < nseg; i++){
+ xdr_be.put32(&outheader, segs[i].type);
+ xdr_be.put32(&outheader, segs[i].compression);
+ xdr_be.put32(&outheader, segs[i].offset);
+ xdr_be.put64(&outheader, segs[i].load_addr);
+ xdr_be.put32(&outheader, segs[i].len);
+ xdr_be.put32(&outheader, segs[i].mem_len);
+ }
+}
int parse_elf_to_payload(const struct buffer *input,
struct buffer *output, comp_algo algo)
{
- Elf32_Phdr *phdr;
- Elf32_Ehdr *ehdr = (Elf32_Ehdr *)input->data;
- Elf32_Shdr *shdr;
+ Elf64_Phdr *phdr;
+ Elf64_Ehdr ehdr;
+ Elf64_Shdr *shdr;
char *header;
char *strtab;
int headers;
@@ -44,39 +65,26 @@ int parse_elf_to_payload(const struct buffer *input,
struct cbfs_payload_segment *segs;
int i;
- if(!iself((unsigned char *)input->data)){
- INFO("The payload file is not in ELF format!\n");
- return -1;
- }
-
- // The tool may work in architecture-independent way.
- if (arch != CBFS_ARCHITECTURE_UNKNOWN &&
- !((ehdr->e_machine == EM_ARM) && (arch == CBFS_ARCHITECTURE_ARMV7)) &&
- !((ehdr->e_machine == EM_386) && (arch == CBFS_ARCHITECTURE_X86))) {
- ERROR("The payload file has the wrong architecture\n");
- return -1;
- }
-
comp_func_ptr compress = compression_function(algo);
if (!compress)
return -1;
- DEBUG("start: parse_elf_to_payload\n");
- headers = ehdr->e_phnum;
- header = (char *)ehdr;
+ if (elf_headers(input, &ehdr, &phdr, &shdr) < 0)
+ return -1;
- phdr = (Elf32_Phdr *) & (header[ehdr->e_phoff]);
- shdr = (Elf32_Shdr *) & (header[ehdr->e_shoff]);
+ DEBUG("start: parse_elf_to_payload\n");
+ headers = ehdr.e_phnum;
+ header = input->data;
- strtab = &header[shdr[ehdr->e_shstrndx].sh_offset];
+ strtab = &header[shdr[ehdr.e_shstrndx].sh_offset];
/* Count the number of headers - look for the .notes.pinfo
* section */
- for (i = 0; i < ehdr->e_shnum; i++) {
+ for (i = 0; i < ehdr.e_shnum; i++) {
char *name;
- if (i == ehdr->e_shstrndx)
+ if (i == ehdr.e_shstrndx)
continue;
if (shdr[i].sh_size == 0)
@@ -106,29 +114,39 @@ int parse_elf_to_payload(const struct buffer *input,
segments++;
}
-
+ /* allocate the segment header array */
+ segs = calloc(segments, sizeof(*segs));
+ if (segs == NULL)
+ return -1;
/* Allocate a block of memory to store the data in */
if (buffer_create(output, (segments * sizeof(*segs)) + isize,
input->name) != 0)
return -1;
memset(output->data, 0, output->size);
- doffset = (segments * sizeof(struct cbfs_payload_segment));
-
- segs = (struct cbfs_payload_segment *)output->data;
+ doffset = (segments * sizeof(*segs));
+
+ /* set up for output marshaling. This is a bit
+ * tricky as we are marshaling the headers at the front,
+ * and the data starting after the headers. We need to convert
+ * the headers to the right format but the data
+ * passes through unchanged. Unlike most XDR code,
+ * we are doing these two concurrently. The doffset is
+ * used to compute the address for the raw data, and the
+ * outheader is used to marshal the headers. To make it simpler
+ * for The Reader, we set up the headers in a separate array,
+ * then marshal them all at once to the output.
+ */
segments = 0;
- for (i = 0; i < ehdr->e_shnum; i++) {
+ for (i = 0; i < ehdr.e_shnum; i++) {
char *name;
-
- if (i == ehdr->e_shstrndx)
+ if (i == ehdr.e_shstrndx)
continue;
if (shdr[i].sh_size == 0)
continue;
-
name = (char *)(strtab + shdr[i].sh_name);
-
if (!strcmp(name, ".note.pinfo")) {
segs[segments].type = PAYLOAD_SEGMENT_PARAMS;
segs[segments].load_addr = 0;
@@ -148,17 +166,13 @@ int parse_elf_to_payload(const struct buffer *input,
for (i = 0; i < headers; i++) {
if (phdr[i].p_type != PT_LOAD)
continue;
-
if (phdr[i].p_memsz == 0)
continue;
-
if (phdr[i].p_filesz == 0) {
segs[segments].type = PAYLOAD_SEGMENT_BSS;
- segs[segments].load_addr =
- (uint64_t)htonll(phdr[i].p_paddr);
- segs[segments].mem_len =
- (uint32_t)htonl(phdr[i].p_memsz);
- segs[segments].offset = htonl(doffset);
+ segs[segments].load_addr = phdr[i].p_paddr;
+ segs[segments].mem_len = phdr[i].p_memsz;
+ segs[segments].offset = doffset;
segments++;
continue;
@@ -168,37 +182,37 @@ int parse_elf_to_payload(const struct buffer *input,
segs[segments].type = PAYLOAD_SEGMENT_CODE;
else
segs[segments].type = PAYLOAD_SEGMENT_DATA;
- segs[segments].load_addr = (uint64_t)htonll(phdr[i].p_paddr);
- segs[segments].mem_len = (uint32_t)htonl(phdr[i].p_memsz);
- segs[segments].compression = htonl(algo);
- segs[segments].offset = htonl(doffset);
+ segs[segments].load_addr = phdr[i].p_paddr;
+ segs[segments].mem_len = phdr[i].p_memsz;
+ segs[segments].compression = algo;
+ segs[segments].offset = doffset;
int len;
compress((char *)&header[phdr[i].p_offset],
phdr[i].p_filesz, output->data + doffset, &len);
- segs[segments].len = htonl(len);
+ segs[segments].len = len;
/* If the compressed section is larger, then use the
original stuff */
if ((unsigned int)len > phdr[i].p_filesz) {
segs[segments].compression = 0;
- segs[segments].len = htonl(phdr[i].p_filesz);
-
+ segs[segments].len = phdr[i].p_filesz;
memcpy(output->data + doffset,
&header[phdr[i].p_offset], phdr[i].p_filesz);
}
- doffset += ntohl(segs[segments].len);
- osize += ntohl(segs[segments].len);
+ doffset += segs[segments].len;
+ osize += segs[segments].len;
segments++;
}
segs[segments].type = PAYLOAD_SEGMENT_ENTRY;
- segs[segments++].load_addr = htonll(ehdr->e_entry);
+ segs[segments++].load_addr = ehdr.e_entry;
- output->size = (segments * sizeof(struct cbfs_payload_segment)) + osize;
+ output->size = (segments * sizeof(*segs)) + osize;
+ xdr_segs(output, segs, segments);
return 0;
}
@@ -209,7 +223,7 @@ int parse_flat_binary_to_payload(const struct buffer *input,
comp_algo algo)
{
comp_func_ptr compress;
- struct cbfs_payload_segment *segs;
+ struct cbfs_payload_segment segs[2];
int doffset, len = 0;
compress = compression_function(algo);
@@ -217,36 +231,35 @@ int parse_flat_binary_to_payload(const struct buffer *input,
return -1;
DEBUG("start: parse_flat_binary_to_payload\n");
- if (buffer_create(output, (2 * sizeof(*segs) + input->size),
+ if (buffer_create(output, (sizeof(segs) + input->size),
input->name) != 0)
return -1;
memset(output->data, 0, output->size);
- segs = (struct cbfs_payload_segment *)output->data;
doffset = (2 * sizeof(*segs));
/* Prepare code segment */
segs[0].type = PAYLOAD_SEGMENT_CODE;
- segs[0].load_addr = htonll(loadaddress);
- segs[0].mem_len = htonl(input->size);
- segs[0].offset = htonl(doffset);
+ segs[0].load_addr = loadaddress;
+ segs[0].mem_len = input->size;
+ segs[0].offset = doffset;
compress(input->data, input->size, output->data + doffset, &len);
- segs[0].compression = htonl(algo);
- segs[0].len = htonl(len);
+ segs[0].compression = algo;
+ segs[0].len = len;
if ((unsigned int)len >= input->size) {
WARN("Compressing data would make it bigger - disabled.\n");
segs[0].compression = 0;
- segs[0].len = htonl(input->size);
+ segs[0].len = input->size;
memcpy(output->data + doffset, input->data, input->size);
}
/* prepare entry point segment */
segs[1].type = PAYLOAD_SEGMENT_ENTRY;
- segs[1].load_addr = htonll(entrypoint);
- output->size = doffset + ntohl(segs[0].len);
-
+ segs[1].load_addr = entrypoint;
+ output->size = doffset + segs[0].len;
+ xdr_segs(output, segs, 2);
return 0;
}
@@ -254,7 +267,7 @@ int parse_fv_to_payload(const struct buffer *input,
struct buffer *output, comp_algo algo)
{
comp_func_ptr compress;
- struct cbfs_payload_segment *segs;
+ struct cbfs_payload_segment segs[2];
int doffset, len = 0;
firmware_volume_header_t *fv;
ffs_file_header_t *fh;
@@ -343,37 +356,36 @@ int parse_fv_to_payload(const struct buffer *input,
return -1;
}
- if (buffer_create(output, (2 * sizeof(*segs) + input->size),
+ if (buffer_create(output, (sizeof(segs) + input->size),
input->name) != 0)
return -1;
memset(output->data, 0, output->size);
- segs = (struct cbfs_payload_segment *)output->data;
- doffset = (2 * sizeof(*segs));
+ doffset = (sizeof(segs));
/* Prepare code segment */
segs[0].type = PAYLOAD_SEGMENT_CODE;
- segs[0].load_addr = htonll(loadaddress);
- segs[0].mem_len = htonl(input->size);
- segs[0].offset = htonl(doffset);
+ segs[0].load_addr = loadaddress;
+ segs[0].mem_len = input->size;
+ segs[0].offset = doffset;
compress(input->data, input->size, output->data + doffset, &len);
- segs[0].compression = htonl(algo);
- segs[0].len = htonl(len);
+ segs[0].compression = algo;
+ segs[0].len = len;
if ((unsigned int)len >= input->size) {
WARN("Compressing data would make it bigger - disabled.\n");
segs[0].compression = 0;
- segs[0].len = htonl(input->size);
+ segs[0].len = input->size;
memcpy(output->data + doffset, input->data, input->size);
}
/* prepare entry point segment */
segs[1].type = PAYLOAD_SEGMENT_ENTRY;
- segs[1].load_addr = htonll(entrypoint);
- output->size = doffset + ntohl(segs[0].len);
-
+ segs[1].load_addr = entrypoint;
+ output->size = doffset + segs[0].len;
+ xdr_segs(output, segs, 2);
return 0;
}
diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c
index 5c8014f..6a5f6f7 100644
--- a/util/cbfstool/cbfs-mkstage.c
+++ b/util/cbfstool/cbfs-mkstage.c
@@ -24,246 +24,9 @@
#include <stdlib.h>
#include <string.h>
+#include "elf.h"
#include "common.h"
#include "cbfs.h"
-#include "elf.h"
-
-/*
- * Short form: this is complicated, but we've tried making it simple
- * and we keep hitting problems with our ELF parsing.
- *
- * The ELF parsing situation has always been a bit tricky. In fact,
- * we (and most others) have been getting it wrong in small ways for
- * years. Recently this has caused real trouble for the ARM V8 build.
- * In this file we attempt to finally get it right for all variations
- * of endian-ness and word size and target architectures and
- * architectures we might get run on. Phew!. To do this we borrow a
- * page from the FreeBSD NFS xdr model (see elf_ehdr and elf_phdr),
- * the Plan 9 endianness functions (see xdr.c), and Go interfaces (see
- * how we use buffer structs in this file). This ends up being a bit
- * wordy at the lowest level, but greatly simplifies the elf parsing
- * code and removes a common source of bugs, namely, forgetting to
- * flip type endianness when referencing a struct member.
- *
- * ELF files can have four combinations of data layout: 32/64, and
- * big/little endian. Further, to add to the fun, depending on the
- * word size, the size of the ELF structs varies. The coreboot SELF
- * format is simpler in theory: it's supposed to be always BE, and the
- * various struct members allow room for growth: the entry point is
- * always 64 bits, for example, so the size of a SELF struct is
- * constant, regardless of target architecture word size. Hence, we
- * need to do some transformation of the ELF files.
- *
- * A given architecture, realistically, only supports one of the four
- * combinations at a time as the 'native' format. Hence, our code has
- * been sprinkled with every variation of [nh]to[hn][sll] over the
- * years. We've never quite gotten it all right, however, and a quick
- * pass over this code revealed another bug. It's all worked because,
- * until now, all the working platforms that had CBFS were 32 LE. Even then,
- * however, bugs crept in: we recently realized that we're not
- * transforming the entry point to big format when we store into the
- * SELF image.
- *
- * The problem is essentially an XDR operation:
- * we have something in a foreign format and need to transform it.
- * It's most like XDR because:
- * 1) the byte order can be wrong
- * 2) the word size can be wrong
- * 3) the size of elements in the stream depends on the value
- * of other elements in the stream
- * it's not like XDR because:
- * 1) the byte order can be right
- * 2) the word size can be right
- * 3) the struct members are all on a natural alignment
- *
- * Hence, this new approach. To cover word size issues, we *always*
- * transform the two structs we care about, the file header and
- * program header, into a native struct in the 64 bit format:
- *
- * [32,little] -> [Elf64_Ehdr, Elf64_Phdr]
- * [64,little] -> [Elf64_Ehdr, Elf64_Phdr]
- * [32,big] -> [Elf64_Ehdr, Elf64_Phdr]
- * [64,big] -> [Elf64_Ehdr, Elf64_Phdr]
- * Then we just use those structs, and all the need for inline ntoh* goes away,
- * as well as all the chances for error.
- * This works because all the SELF structs have fields large enough for
- * the largest ELF 64 struct members, and all the Elf64 struct members
- * are at least large enough for all ELF 32 struct members.
- * We end up with one function to do all our ELF parsing, and two functions
- * to transform the headers. For the put case, we also have
- * XDR functions, and hopefully we'll never again spend 5 years with the
- * wrong endian-ness on an output value :-)
- * This should work for all word sizes and endianness we hope to target.
- * I *really* don't want to be here for 128 bit addresses.
- *
- * The parse functions are called with a pointer to an input buffer
- * struct. One might ask: are there enough bytes in the input buffer?
- * We know there need to be at *least* sizeof(Elf32_Ehdr) +
- * sizeof(Elf32_Phdr) bytes. Realistically, there has to be some data
- * too. If we start to worry, though we have not in the past, we
- * might apply the simple test: the input buffer needs to be at least
- * sizeof(Elf64_Ehdr) + sizeof(Elf64_Phdr) bytes because, even if it's
- * ELF 32, there's got to be *some* data! This is not theoretically
- * accurate but it is actually good enough in practice. It allows the
- * header transformation code to ignore the possibility of underrun.
- *
- * We also must accomodate different ELF files, and hence formats,
- * in the same cbfs invocation. We might load a 64-bit payload
- * on a 32-bit machine; we might even have a mixed armv7/armv8
- * SOC or even a system with an x86/ARM!
- *
- * A possibly problematic (though unlikely to be so) assumption
- * is that we expect the BIOS to remain in the lowest 32 bits
- * of the physical address space. Since ARMV8 has standardized
- * on that, and x86_64 also has, this seems a safe assumption.
- *
- * To repeat, ELF structs are different sizes because ELF struct
- * members are different sizes, depending on values in the ELF file
- * header. For this we use the functions defined in xdr.c, which
- * consume bytes, convert the endianness, and advance the data pointer
- * in the buffer struct.
- */
-
-/* Get the ident array, so we can figure out
- * endian-ness, word size, and in future other useful
- * parameters
- */
-static void
-elf_eident(struct buffer *input, Elf64_Ehdr *ehdr)
-{
- memmove(ehdr->e_ident, input->data, sizeof(ehdr->e_ident));
- input->data += sizeof(ehdr->e_ident);
- input->size -= sizeof(ehdr->e_ident);
-}
-
-
-static void
-elf_ehdr(struct buffer *input, Elf64_Ehdr *ehdr, struct xdr *xdr, int bit64)
-{
- ehdr->e_type = xdr->get16(input);
- ehdr->e_machine = xdr->get16(input);
- ehdr->e_version = xdr->get32(input);
- if (bit64){
- ehdr->e_entry = xdr->get64(input);
- ehdr->e_phoff = xdr->get64(input);
- ehdr->e_shoff = xdr->get64(input);
- } else {
- ehdr->e_entry = xdr->get32(input);
- ehdr->e_phoff = xdr->get32(input);
- ehdr->e_shoff = xdr->get32(input);
- }
- ehdr->e_flags = xdr->get32(input);
- ehdr->e_ehsize = xdr->get16(input);
- ehdr->e_phentsize = xdr->get16(input);
- ehdr->e_phnum = xdr->get16(input);
- ehdr->e_shentsize = xdr->get16(input);
- ehdr->e_shnum = xdr->get16(input);
- ehdr->e_shstrndx = xdr->get16(input);
-}
-
-static void
-elf_phdr(struct buffer *pinput, Elf64_Phdr *phdr,
- int entsize, struct xdr *xdr, int bit64)
-{
- /*
- * The entsize need not be sizeof(*phdr).
- * Hence, it is easier to keep a copy of the input,
- * as the xdr functions may not advance the input
- * pointer the full entsize; rather than get tricky
- * we just advance it below.
- */
- struct buffer input = *pinput;
- if (bit64){
- phdr->p_type = xdr->get32(&input);
- phdr->p_flags = xdr->get32(&input);
- phdr->p_offset = xdr->get64(&input);
- phdr->p_vaddr = xdr->get64(&input);
- phdr->p_paddr = xdr->get64(&input);
- phdr->p_filesz = xdr->get64(&input);
- phdr->p_memsz = xdr->get64(&input);
- phdr->p_align = xdr->get64(&input);
- } else {
- phdr->p_type = xdr->get32(&input);
- phdr->p_offset = xdr->get32(&input);
- phdr->p_vaddr = xdr->get32(&input);
- phdr->p_paddr = xdr->get32(&input);
- phdr->p_filesz = xdr->get32(&input);
- phdr->p_memsz = xdr->get32(&input);
- phdr->p_flags = xdr->get32(&input);
- phdr->p_align = xdr->get32(&input);
- }
- pinput->size -= entsize;
- pinput->data += entsize;
-}
-
-/* Get the headers from the buffer.
- * Return -1 in the event of an error.
- */
-static int
-elf_headers(const struct buffer *pinput, Elf64_Ehdr *ehdr, Elf64_Phdr **pphdr)
-{
- int i;
- struct xdr *xdr = &xdr_le;
- int bit64 = 0;
- struct buffer input = *(struct buffer *)pinput;
- struct buffer phdr_buf;
- Elf64_Phdr *phdr;
-
- if (!iself((unsigned char *)pinput->data)) {
- ERROR("The stage file is not in ELF format!\n");
- return -1;
- }
-
- elf_eident(&input, ehdr);
- bit64 = ehdr->e_ident[EI_CLASS] == ELFCLASS64;
- /* Assume LE unless we are sure otherwise.
- * We're not going to take on the task of
- * fully validating the ELF file. That way
- * lies madness.
- */
- if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB)
- xdr = &xdr_be;
-
- elf_ehdr(&input, ehdr, xdr, bit64);
-
- // The tool may work in architecture-independent way.
- if (arch != CBFS_ARCHITECTURE_UNKNOWN &&
- !((ehdr->e_machine == EM_ARM) && (arch == CBFS_ARCHITECTURE_ARMV7)) &&
- !((ehdr->e_machine == EM_386) && (arch == CBFS_ARCHITECTURE_X86))) {
- ERROR("The stage file has the wrong architecture\n");
- return -1;
- }
-
- if (pinput->size < ehdr->e_phoff){
- ERROR("The program header offset is greater than "
- "the remaining file size."
- "%ld bytes left, program header offset is %ld \n",
- pinput->size, ehdr->e_phoff);
- return -1;
- }
- /* cons up an input buffer for the headers.
- * Note that the program headers can be anywhere,
- * per the ELF spec, You'd be surprised how many ELF
- * readers miss this little detail.
- */
- phdr_buf.data = &pinput->data[ehdr->e_phoff];
- phdr_buf.size = ehdr->e_phentsize * ehdr->e_phnum;
- if (phdr_buf.size > (pinput->size - ehdr->e_phoff)){
- ERROR("The file is not large enough for the program headers."
- "%ld bytes left, %ld bytes of headers\n",
- pinput->size - ehdr->e_phoff, phdr_buf.size);
- return -1;
- }
- /* gather up all the phdrs.
- * We do them all at once because there is more
- * than one loop over all the phdrs.
- */
- phdr = calloc(sizeof(*phdr), ehdr->e_phnum);
- for (i = 0; i < ehdr->e_phnum; i++)
- elf_phdr(&phdr_buf, &phdr[i], ehdr->e_phentsize, xdr, bit64);
- *pphdr = phdr;
- return 0;
-}
/* returns size of result, or -1 if error.
* Note that, with the new code, this function
@@ -287,7 +50,7 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output,
DEBUG("start: parse_elf_to_stage(location=0x%x)\n", *location);
- if (elf_headers(input, &ehdr, &phdr) < 0)
+ if (elf_headers(input, &ehdr, &phdr, NULL) < 0)
return -1;
headers = ehdr.e_phnum;
diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h
index 35d0670..585a26d 100644
--- a/util/cbfstool/cbfs.h
+++ b/util/cbfstool/cbfs.h
@@ -20,6 +20,18 @@
#define __CBFS_H
#include <stdint.h>
+#include "elf.h"
+
+/* create a magic number in host-byte order.
+ * b3 is the high order byte.
+ * in the coreboot tools, we go with the 32-bit
+ * magic number convention.
+ * This was an inline func but that breaks anything
+ * that uses it in a case statement.
+ */
+
+#define makemagic(b3, b2, b1, b0)\
+ (((b3)<<24) | ((b2) << 16) | ((b1) << 8) | (b0))
#define CBFS_HEADER_MAGIC 0x4F524243
#define CBFS_HEADPTR_ADDR_X86 0xFFFFFFFC
@@ -60,11 +72,11 @@ struct cbfs_stage {
uint32_t memlen;
} __attribute__ ((packed));
-#define PAYLOAD_SEGMENT_CODE 0x45444F43
-#define PAYLOAD_SEGMENT_DATA 0x41544144
-#define PAYLOAD_SEGMENT_BSS 0x20535342
-#define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY 0x52544E45
+#define PAYLOAD_SEGMENT_CODE makemagic('C', 'O', 'D', 'E')
+#define PAYLOAD_SEGMENT_DATA makemagic('D', 'A', 'T', 'A')
+#define PAYLOAD_SEGMENT_BSS makemagic(' ', 'B', 'S', 'S')
+#define PAYLOAD_SEGMENT_PARAMS makemagic('P', 'A', 'R', 'A')
+#define PAYLOAD_SEGMENT_ENTRY makemagic('E', 'N', 'T', 'R')
struct cbfs_payload_segment {
uint32_t type;
@@ -110,7 +122,22 @@ struct cbfs_payload {
int cbfs_file_header(unsigned long physaddr);
#define CBFS_NAME(_c) (((char *) (_c)) + sizeof(struct cbfs_file))
#define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) )
-
+/* cbfs_image.c */
+uint32_t get_cbfs_entry_type(const char *name, uint32_t default_value);
+const char *get_cbfs_entry_type_name(uint32_t type);
+uint32_t get_cbfs_compression(const char *name, uint32_t unknown);
+
+/* common.c */
+int find_master_header(void *romarea, size_t size);
+void recalculate_rom_geometry(void *romarea);
struct cbfs_file *cbfs_create_empty_file(uint32_t physaddr, uint32_t size);
+const char *strfiletype(uint32_t number);
+
+/* elfheaders.c */
+int
+elf_headers(const struct buffer *pinput,
+ Elf64_Ehdr *ehdr,
+ Elf64_Phdr **pphdr,
+ Elf64_Shdr **pshdr);
#endif
diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 2cd0c7a..363691f 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -24,6 +24,7 @@
#include <string.h>
#include "common.h"
+#include "elf.h"
#include "cbfs_image.h"
/* The file name align is not defined in CBFS spec -- only a preference by
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 34002a9..9935f51 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -26,6 +26,7 @@
#include <unistd.h>
#include <getopt.h>
#include "common.h"
+#include "elf.h"
#include "cbfs.h"
#include "cbfs_image.h"
#include "fit.h"
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index 8f38a4a..356ba2f 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -23,9 +23,9 @@
#include <stdlib.h>
#include <string.h>
#include <libgen.h>
+#include "elf.h"
#include "common.h"
#include "cbfs.h"
-#include "elf.h"
/* Utilities */
diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h
index ed75a7f..e49a3f6 100644
--- a/util/cbfstool/common.h
+++ b/util/cbfstool/common.h
@@ -144,17 +144,7 @@ struct xdr {
void (*put64)(struct buffer *input, uint64_t val);
};
-/* common.c */
-
-int find_master_header(void *romarea, size_t size);
-void recalculate_rom_geometry(void *romarea);
-const char *strfiletype(uint32_t number);
-
-/* cbfs_image.c */
-uint32_t get_cbfs_entry_type(const char *name, uint32_t default_value);
-const char *get_cbfs_entry_type_name(uint32_t type);
-uint32_t get_cbfs_compression(const char *name, uint32_t unknown);
-
+/* xdr.c */
extern struct xdr xdr_le, xdr_be;
#endif
diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c
new file mode 100644
index 0000000..fd7a1a1
--- /dev/null
+++ b/util/cbfstool/elfheaders.c
@@ -0,0 +1,343 @@
+/*
+ * elf header parsing.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "elf.h"
+#include "common.h"
+#include "cbfs.h"
+
+/*
+ * Short form: this is complicated, but we've tried making it simple
+ * and we keep hitting problems with our ELF parsing.
+ *
+ * The ELF parsing situation has always been a bit tricky. In fact,
+ * we (and most others) have been getting it wrong in small ways for
+ * years. Recently this has caused real trouble for the ARM V8 build.
+ * In this file we attempt to finally get it right for all variations
+ * of endian-ness and word size and target architectures and
+ * architectures we might get run on. Phew!. To do this we borrow a
+ * page from the FreeBSD NFS xdr model (see elf_ehdr and elf_phdr),
+ * the Plan 9 endianness functions (see xdr.c), and Go interfaces (see
+ * how we use buffer structs in this file). This ends up being a bit
+ * wordy at the lowest level, but greatly simplifies the elf parsing
+ * code and removes a common source of bugs, namely, forgetting to
+ * flip type endianness when referencing a struct member.
+ *
+ * ELF files can have four combinations of data layout: 32/64, and
+ * big/little endian. Further, to add to the fun, depending on the
+ * word size, the size of the ELF structs varies. The coreboot SELF
+ * format is simpler in theory: it's supposed to be always BE, and the
+ * various struct members allow room for growth: the entry point is
+ * always 64 bits, for example, so the size of a SELF struct is
+ * constant, regardless of target architecture word size. Hence, we
+ * need to do some transformation of the ELF files.
+ *
+ * A given architecture, realistically, only supports one of the four
+ * combinations at a time as the 'native' format. Hence, our code has
+ * been sprinkled with every variation of [nh]to[hn][sll] over the
+ * years. We've never quite gotten it all right, however, and a quick
+ * pass over this code revealed another bug. It's all worked because,
+ * until now, all the working platforms that had CBFS were 32 LE. Even then,
+ * however, bugs crept in: we recently realized that we're not
+ * transforming the entry point to big format when we store into the
+ * SELF image.
+ *
+ * The problem is essentially an XDR operation:
+ * we have something in a foreign format and need to transform it.
+ * It's most like XDR because:
+ * 1) the byte order can be wrong
+ * 2) the word size can be wrong
+ * 3) the size of elements in the stream depends on the value
+ * of other elements in the stream
+ * it's not like XDR because:
+ * 1) the byte order can be right
+ * 2) the word size can be right
+ * 3) the struct members are all on a natural alignment
+ *
+ * Hence, this new approach. To cover word size issues, we *always*
+ * transform the two structs we care about, the file header and
+ * program header, into a native struct in the 64 bit format:
+ *
+ * [32,little] -> [Elf64_Ehdr, Elf64_Phdr]
+ * [64,little] -> [Elf64_Ehdr, Elf64_Phdr]
+ * [32,big] -> [Elf64_Ehdr, Elf64_Phdr]
+ * [64,big] -> [Elf64_Ehdr, Elf64_Phdr]
+ * Then we just use those structs, and all the need for inline ntoh* goes away,
+ * as well as all the chances for error.
+ * This works because all the SELF structs have fields large enough for
+ * the largest ELF 64 struct members, and all the Elf64 struct members
+ * are at least large enough for all ELF 32 struct members.
+ * We end up with one function to do all our ELF parsing, and two functions
+ * to transform the headers. For the put case, we also have
+ * XDR functions, and hopefully we'll never again spend 5 years with the
+ * wrong endian-ness on an output value :-)
+ * This should work for all word sizes and endianness we hope to target.
+ * I *really* don't want to be here for 128 bit addresses.
+ *
+ * The parse functions are called with a pointer to an input buffer
+ * struct. One might ask: are there enough bytes in the input buffer?
+ * We know there need to be at *least* sizeof(Elf32_Ehdr) +
+ * sizeof(Elf32_Phdr) bytes. Realistically, there has to be some data
+ * too. If we start to worry, though we have not in the past, we
+ * might apply the simple test: the input buffer needs to be at least
+ * sizeof(Elf64_Ehdr) + sizeof(Elf64_Phdr) bytes because, even if it's
+ * ELF 32, there's got to be *some* data! This is not theoretically
+ * accurate but it is actually good enough in practice. It allows the
+ * header transformation code to ignore the possibility of underrun.
+ *
+ * We also must accomodate different ELF files, and hence formats,
+ * in the same cbfs invocation. We might load a 64-bit payload
+ * on a 32-bit machine; we might even have a mixed armv7/armv8
+ * SOC or even a system with an x86/ARM!
+ *
+ * A possibly problematic (though unlikely to be so) assumption
+ * is that we expect the BIOS to remain in the lowest 32 bits
+ * of the physical address space. Since ARMV8 has standardized
+ * on that, and x86_64 also has, this seems a safe assumption.
+ *
+ * To repeat, ELF structs are different sizes because ELF struct
+ * members are different sizes, depending on values in the ELF file
+ * header. For this we use the functions defined in xdr.c, which
+ * consume bytes, convert the endianness, and advance the data pointer
+ * in the buffer struct.
+ */
+
+/* Get the ident array, so we can figure out
+ * endian-ness, word size, and in future other useful
+ * parameters
+ */
+static void
+elf_eident(struct buffer *input, Elf64_Ehdr *ehdr)
+{
+ memmove(ehdr->e_ident, input->data, sizeof(ehdr->e_ident));
+ input->data += sizeof(ehdr->e_ident);
+ input->size -= sizeof(ehdr->e_ident);
+}
+
+
+static void
+elf_ehdr(struct buffer *input, Elf64_Ehdr *ehdr, struct xdr *xdr, int bit64)
+{
+ ehdr->e_type = xdr->get16(input);
+ ehdr->e_machine = xdr->get16(input);
+ ehdr->e_version = xdr->get32(input);
+ if (bit64){
+ ehdr->e_entry = xdr->get64(input);
+ ehdr->e_phoff = xdr->get64(input);
+ ehdr->e_shoff = xdr->get64(input);
+ } else {
+ ehdr->e_entry = xdr->get32(input);
+ ehdr->e_phoff = xdr->get32(input);
+ ehdr->e_shoff = xdr->get32(input);
+ }
+ ehdr->e_flags = xdr->get32(input);
+ ehdr->e_ehsize = xdr->get16(input);
+ ehdr->e_phentsize = xdr->get16(input);
+ ehdr->e_phnum = xdr->get16(input);
+ ehdr->e_shentsize = xdr->get16(input);
+ ehdr->e_shnum = xdr->get16(input);
+ ehdr->e_shstrndx = xdr->get16(input);
+}
+
+static void
+elf_phdr(struct buffer *pinput, Elf64_Phdr *phdr,
+ int entsize, struct xdr *xdr, int bit64)
+{
+ /*
+ * The entsize need not be sizeof(*phdr).
+ * Hence, it is easier to keep a copy of the input,
+ * as the xdr functions may not advance the input
+ * pointer the full entsize; rather than get tricky
+ * we just advance it below.
+ */
+ struct buffer input = *pinput;
+ if (bit64){
+ phdr->p_type = xdr->get32(&input);
+ phdr->p_flags = xdr->get32(&input);
+ phdr->p_offset = xdr->get64(&input);
+ phdr->p_vaddr = xdr->get64(&input);
+ phdr->p_paddr = xdr->get64(&input);
+ phdr->p_filesz = xdr->get64(&input);
+ phdr->p_memsz = xdr->get64(&input);
+ phdr->p_align = xdr->get64(&input);
+ } else {
+ phdr->p_type = xdr->get32(&input);
+ phdr->p_offset = xdr->get32(&input);
+ phdr->p_vaddr = xdr->get32(&input);
+ phdr->p_paddr = xdr->get32(&input);
+ phdr->p_filesz = xdr->get32(&input);
+ phdr->p_memsz = xdr->get32(&input);
+ phdr->p_flags = xdr->get32(&input);
+ phdr->p_align = xdr->get32(&input);
+ }
+ pinput->size -= entsize;
+ pinput->data += entsize;
+}
+
+static void
+elf_shdr(struct buffer *pinput, Elf64_Shdr *shdr,
+ int entsize, struct xdr *xdr, int bit64)
+{
+ /*
+ * The entsize need not be sizeof(*shdr).
+ * Hence, it is easier to keep a copy of the input,
+ * as the xdr functions may not advance the input
+ * pointer the full entsize; rather than get tricky
+ * we just advance it below.
+ */
+ struct buffer input = *pinput;
+ if (bit64){
+ shdr->sh_name = xdr->get32(&input);
+ shdr->sh_type = xdr->get32(&input);
+ shdr->sh_flags = xdr->get64(&input);
+ shdr->sh_addr = xdr->get64(&input);
+ shdr->sh_offset = xdr->get64(&input);
+ shdr->sh_size= xdr->get64(&input);
+ shdr->sh_link = xdr->get32(&input);
+ shdr->sh_info = xdr->get32(&input);
+ shdr->sh_addralign = xdr->get64(&input);
+ shdr->sh_entsize = xdr->get64(&input);
+ } else {
+ shdr->sh_name = xdr->get32(&input);
+ shdr->sh_type = xdr->get32(&input);
+ shdr->sh_flags = xdr->get32(&input);
+ shdr->sh_addr = xdr->get32(&input);
+ shdr->sh_offset = xdr->get32(&input);
+ shdr->sh_size = xdr->get32(&input);
+ shdr->sh_link = xdr->get32(&input);
+ shdr->sh_info = xdr->get32(&input);
+ shdr->sh_addralign = xdr->get32(&input);
+ shdr->sh_entsize = xdr->get32(&input);
+ }
+ pinput->size -= entsize;
+ pinput->data += entsize;
+}
+
+/* Get the headers from the buffer.
+ * Return -1 in the event of an error.
+ * The section headers are optional; if NULL
+ * is passed in for pshdr they won't be parsed.
+ * We don't (yet) make payload parsing optional
+ * because we've never seen a use case.
+ */
+int
+elf_headers(const struct buffer *pinput,
+ Elf64_Ehdr *ehdr,
+ Elf64_Phdr **pphdr,
+ Elf64_Shdr **pshdr)
+{
+ int i;
+ struct xdr *xdr = &xdr_le;
+ int bit64 = 0;
+ struct buffer input = *(struct buffer *)pinput;
+ struct buffer phdr_buf;
+ struct buffer shdr_buf;
+ Elf64_Phdr *phdr;
+ Elf64_Shdr *shdr;
+
+ if (!iself((unsigned char *)pinput->data)) {
+ ERROR("The stage file is not in ELF format!\n");
+ return -1;
+ }
+
+ elf_eident(&input, ehdr);
+ bit64 = ehdr->e_ident[EI_CLASS] == ELFCLASS64;
+ /* Assume LE unless we are sure otherwise.
+ * We're not going to take on the task of
+ * fully validating the ELF file. That way
+ * lies madness.
+ */
+ if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB)
+ xdr = &xdr_be;
+
+ elf_ehdr(&input, ehdr, xdr, bit64);
+
+ // The tool may work in architecture-independent way.
+ if (arch != CBFS_ARCHITECTURE_UNKNOWN &&
+ !((ehdr->e_machine == EM_ARM) && (arch == CBFS_ARCHITECTURE_ARMV7)) &&
+ !((ehdr->e_machine == EM_386) && (arch == CBFS_ARCHITECTURE_X86))) {
+ ERROR("The stage file has the wrong architecture\n");
+ return -1;
+ }
+
+ if (pinput->size < ehdr->e_phoff){
+ ERROR("The program header offset is greater than "
+ "the remaining file size."
+ "%ld bytes left, program header offset is %ld \n",
+ pinput->size, ehdr->e_phoff);
+ return -1;
+ }
+ /* cons up an input buffer for the headers.
+ * Note that the program headers can be anywhere,
+ * per the ELF spec, You'd be surprised how many ELF
+ * readers miss this little detail.
+ */
+ phdr_buf.data = &pinput->data[ehdr->e_phoff];
+ phdr_buf.size = ehdr->e_phentsize * ehdr->e_phnum;
+ if (phdr_buf.size > (pinput->size - ehdr->e_phoff)){
+ ERROR("The file is not large enough for the program headers."
+ "%ld bytes left, %ld bytes of headers\n",
+ pinput->size - ehdr->e_phoff, phdr_buf.size);
+ return -1;
+ }
+ /* gather up all the phdrs.
+ * We do them all at once because there is more
+ * than one loop over all the phdrs.
+ */
+ phdr = calloc(sizeof(*phdr), ehdr->e_phnum);
+ for (i = 0; i < ehdr->e_phnum; i++)
+ elf_phdr(&phdr_buf, &phdr[i], ehdr->e_phentsize, xdr, bit64);
+ *pphdr = phdr;
+
+ if (!pshdr)
+ return 0;
+
+ if (pinput->size < ehdr->e_shoff){
+ ERROR("The section header offset is greater than "
+ "the remaining file size."
+ "%ld bytes left, program header offset is %ld \n",
+ pinput->size, ehdr->e_shoff);
+ return -1;
+ }
+ /* cons up an input buffer for the section headers.
+ * Note that the section headers can be anywhere,
+ * per the ELF spec, You'd be surprised how many ELF
+ * readers miss this little detail.
+ */
+ shdr_buf.data = &pinput->data[ehdr->e_shoff];
+ shdr_buf.size = ehdr->e_shentsize * ehdr->e_shnum;
+ if (shdr_buf.size > (pinput->size - ehdr->e_shoff)){
+ ERROR("The file is not large enough for the section headers."
+ "%ld bytes left, %ld bytes of headers\n",
+ pinput->size - ehdr->e_shoff, shdr_buf.size);
+ return -1;
+ }
+ /* gather up all the shdrs. */
+
+ shdr = calloc(sizeof(*shdr), ehdr->e_shnum);
+ for (i = 0; i < ehdr->e_shnum; i++)
+ elf_shdr(&shdr_buf, &shdr[i], ehdr->e_shentsize, xdr, bit64);
+ *pshdr = shdr;
+
+ return 0;
+}
+
diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index f15ccf5..a368dad 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -23,6 +23,7 @@
#include <stdio.h>
#include "common.h"
+#include "elf.h"
#include "cbfs.h"
#include "cbfs_image.h"
#include "fit.h"
1
0
New patch to review for coreboot: accf891 Added ACPI support for the old HP DL145 G1
by Oskar Enoksson 02 Feb '14
by Oskar Enoksson 02 Feb '14
02 Feb '14
Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5097
-gerrit
commit accf891ba82434179f798522e803fe6a87881e48
Author: Oskar Enoksson <enok(a)lysator.liu.se>
Date: Sun Feb 2 15:26:37 2014 +0100
Added ACPI support for the old HP DL145 G1
Basic ACPI support for this old platform.
Works reasonably well under Linux, providing PowerNow, HPET-timers
and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44).
Not tested under Windows.
Change-Id: Ic4d2f9382b6770654eea8842a37ad38cf12de459
Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se>
---
src/mainboard/hp/dl145_g1/Kconfig | 5 +
src/mainboard/hp/dl145_g1/acpi/amd8111.asl | 616 +++++++++++++++++++++++++
src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl | 155 +++++++
src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl | 230 +++++++++
src/mainboard/hp/dl145_g1/acpi/amd8131.asl | 101 ++++
src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl | 2 +
src/mainboard/hp/dl145_g1/acpi_tables.c | 342 ++++++++++++++
src/mainboard/hp/dl145_g1/dsdt.asl | 314 +++++++++++++
src/mainboard/hp/dl145_g1/fadt.c | 182 ++++++++
src/mainboard/hp/dl145_g1/mptable.c | 16 +-
src/mainboard/hp/dl145_g1/romstage.c | 76 ++-
11 files changed, 2006 insertions(+), 33 deletions(-)
diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig
index 7e63077..23a0a20 100644
--- a/src/mainboard/hp/dl145_g1/Kconfig
+++ b/src/mainboard/hp/dl145_g1/Kconfig
@@ -8,14 +8,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_AMD_AMD8131
select SOUTHBRIDGE_AMD_AMD8111
select SUPERIO_WINBOND_W83627HF
+ select HAVE_BUS_CONFIG
+ select HAVE_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
+ select SET_FIDVID
+ select SET_FIDVID_DEBUG
select RAMINIT_SYSINFO
# select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select QRANK_DIMM_SUPPORT
select DRIVERS_I2C_I2CMUX
+ select HAVE_ACPI_TABLES
config MAINBOARD_DIR
string
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
new file mode 100644
index 0000000..3d86ed4
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
@@ -0,0 +1,616 @@
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111
+// APIC version of the interrupt routing table
+Name (APIC, Package (0x04) {
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
+})
+// PIC version of the interrupt routing table
+Name (PICM, Package (0x04) {
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
+})
+Name (DNCG, Ones)
+Method (_PRT, 0, NotSerialized) {
+ If (LEqual (^DNCG, Ones)) {
+ Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
+ // Update the Device Number according to SBDN
+ Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
+
+ Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
+
+ Store (0x00, ^DNCG)
+ }
+
+ If (LNot (PICF)) {
+ Return (PICM)
+ } Else {
+ Return (APIC)
+ }
+}
+
+// AMD8111 System Management I/O Mapped Registers (PMxx)
+OperationRegion (PMIO, SystemIO, PMBS, 0xDF)
+Field (PMIO, ByteAcc, NoLock, Preserve) {
+ Offset (0x1E),
+ SWSM, 8, // Software SMI Trigger (sets GSTS)
+ Offset (0x28),
+ GSTS, 16, // Global STatuS
+ GNBL, 16, // Global SMI enable
+ Offset (0x30),
+ STMC, 5, // Miscellaneous SMI Status
+ Offset (0x32),
+ ENMC, 5, // Miscellaneous SMI Enable
+ Offset (0x44),
+ STC0, 9, // TCO Status 1
+ Offset (0x46),
+ STC1, 4, // TCO Status 2
+ Offset (0xA8),
+ STHW, 20 // Device monitor SMI Interrupt Enable
+}
+Device (HPET) {
+ Name (HPT, 0x00)
+ Name (_HID, EisaId ("PNP0103"))
+ Name (_UID, 0x00)
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+ Method (_CRS, 0, NotSerialized) {
+ Name (BUF0, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
+ })
+ Return (BUF0)
+ }
+}
+#include "amd8111_pic.asl"
+#include "amd8111_isa.asl"
+
+Device (TP2P) {
+ // 8111 P2P and it should 0x00030000 when 8131 present
+ Method (_ADR, 0, NotSerialized) {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
+ }
+ Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
+ // result :
+ // [0] Bit index into GPEx_EN in the GPE block described by FADT.
+ // [1] The lowest power state from which the system can be awakened.
+ //If (CondRefOf (\_S3, Local0)) {
+ // Return (Package (0x02) { 0x08, 0x03 })
+ //} Else {
+ Return (Package (0x02) { 0x08, 0x01 })
+ //}
+ }
+ Device (ETHR) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
+ //If (CondRefOf (\_S3, Local0)) {
+ // Return (Package (0x02) { 0x08, 0x03 })
+ //} Else {
+ Return (Package (0x02) { 0x08, 0x01 })
+ //}
+ }
+ }
+ Device (USB0) {
+ Name (_ADR, 0x00000000)
+ Method (_PSW, 1, NotSerialized) { // Power State Wake
+ And (GNBL, 0x7FFF, GNBL)
+ }
+ Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
+ //If (CondRefOf (\_S3, Local0)) {
+ // Return (Package (0x02) { 0x0F, 0x03 })
+ //} Else {
+ Return (Package (0x02) { 0x0F, 0x01 })
+ //}
+ }
+ }
+ Device (USB1) {
+ Name (_ADR, 0x00000001)
+ Method (_PSW, 1, NotSerialized) { // Power State Wake
+ And (GNBL, 0x7FFF, GNBL)
+ }
+ Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
+ //If (CondRefOf (\_S3, Local0)) {
+ // Return (Package (0x02) { 0x0F, 0x03 })
+ //} Else {
+ Return (Package (0x02) { 0x0F, 0x01 })
+ //}
+ }
+ }
+ Name (APIC, Package (0x0C) {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
+ })
+ Name (PICM, Package (0x0C) {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized) {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+}
+Device (IDE0) {
+ Method (_ADR, 0, NotSerialized) {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010001))
+ }
+ Name (REGF, 0x01)
+ Method (_REG, 2, NotSerialized) {
+ If (LEqual (Arg0, 0x02)) {
+ Store (Arg1, REGF)
+ }
+ }
+ OperationRegion (BAR0, PCI_Config, 0x00, 0x60)
+ Field (BAR0, ByteAcc, NoLock, Preserve) {
+ Offset (0x40), // EIDE Controller Configuration Register
+ SCEN, 1, // Secondary Channel Enable
+ PCEN, 1, // Primary Channel Enable
+ , 10,
+ SPWB, 1, // Secondary Port posted-write buffer for PIO modes enable
+ SRPB, 1, // RW (controls nothing)
+ PPWB, 1, // Primary Port posted-write buffer for PIO modes enable
+ PRPB, 1, // RW (controls nothing)
+ PM80, 1, // High-speed 80-pin cable enable Primary Master
+ PS80, 1, // High-speed 80-pin cable enable Primary Slave
+ SM80, 1, // High-speed 80-pin cable enable Secondary Master
+ SS80, 1, // High-speed 80-pin cable enable Secondary Slave
+ , 4, // RW (controls nothing)
+ Offset (0x48),
+ SSRT, 4, //
+ SSPW, 4, //
+ SMRT, 4, //
+ SMPW, 4,
+ PSRT, 4,
+ PSPW, 4,
+ PMRT, 4,
+ PMPW, 4,
+ SSAD, 2,
+ SMAD, 2,
+ PSAD, 2,
+ PMAD, 2,
+ Offset (0x4E),
+ SXRT, 4,
+ SXPW, 4,
+ PXRT, 4,
+ PXPW, 4,
+ SSUD, 8,
+ SMUD, 8,
+ PSUD, 8,
+ PMUD, 8,
+ PPDN, 1,
+ PPDS, 1,
+ , 2,
+ SPDN, 1,
+ SPDS, 1
+ }
+ Name (TIM0, Package (0x06) {
+ Package (0x05) {
+ 0x78,
+ 0xB4,
+ 0xF0,
+ 0x0186,
+ 0x0258
+ },
+ Package (0x07) {
+ 0x78,
+ 0x5A,
+ 0x3C,
+ 0x2D,
+ 0x1E,
+ 0x14,
+ 0x0F
+ },
+ Package (0x08) {
+ 0x04,
+ 0x03,
+ 0x02,
+ 0x01,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00
+ },
+ Package (0x03) {
+ 0x02,
+ 0x01,
+ 0x00
+ },
+ Package (0x05) {
+ 0x20,
+ 0x22,
+ 0x42,
+ 0x65,
+ 0xA8
+ },
+ Package (0x07) {
+ 0xC2,
+ 0xC1,
+ 0xC0,
+ 0xC4,
+ 0xC5,
+ 0xC6,
+ 0xC7
+ }
+ })
+ Name (TMD0, Buffer (0x14) {})
+ CreateDWordField (TMD0, 0x00, PIO0)
+ CreateDWordField (TMD0, 0x04, DMA0)
+ CreateDWordField (TMD0, 0x08, PIO1)
+ CreateDWordField (TMD0, 0x0C, DMA1)
+ CreateDWordField (TMD0, 0x10, CHNF)
+ Device (CHN0) {
+ Name (_ADR, 0x00)
+ Method (_STA, 0, NotSerialized) {
+ If (PCEN) { Return (0x0F) }
+ Else { Return (0x09) }
+ }
+ Method (_GTM, 0, NotSerialized) {
+ Return (GTM (PMPW, PMRT, PSPW, PSRT, PMUD, PSUD))
+ }
+ Method (_STM, 3, NotSerialized) {
+ Store (Arg0, TMD0)
+ Store (STM (), Local0)
+ And (Local0, 0xFF, PSUD)
+ ShiftRight (Local0, 0x08, Local0)
+ And (Local0, 0xFF, PMUD)
+ ShiftRight (Local0, 0x08, Local0)
+ And (Local0, 0x0F, PSRT)
+ ShiftRight (Local0, 0x04, Local0)
+ And (Local0, 0x0F, PSPW)
+ ShiftRight (Local0, 0x04, Local0)
+ And (Local0, 0x0F, PMRT)
+ ShiftRight (Local0, 0x04, Local0)
+ And (Local0, 0x0F, PMPW)
+ Store (GTF (0x00, Arg1), ATA0)
+ Store (GTF (0x01, Arg2), ATA1)
+ }
+ Device (DRV0) {
+ Name (_ADR, 0x00)
+ Method (_GTF, 0, NotSerialized) {
+ Return (RATA (ATA0))
+ }
+ }
+ Device (DRV1) {
+ Name (_ADR, 0x01)
+ Method (_GTF, 0, NotSerialized) {
+ Return (RATA (ATA1))
+ }
+ }
+ }
+ Device (CHN1) {
+ Name (_ADR, 0x01)
+ Method (_STA, 0, NotSerialized) {
+ If (SCEN) { Return (0x0F) }
+ Else { Return (0x09) }
+ }
+ Method (_GTM, 0, NotSerialized) {
+ Return (GTM (SMPW, SMRT, SSPW, SSRT, SMUD, SSUD))
+ }
+ Method (_STM, 3, NotSerialized) {
+ Store (Arg0, TMD0)
+ Store (STM (), Local0)
+ And (Local0, 0xFF, SSUD)
+ ShiftRight (Local0, 0x08, Local0)
+ And (Local0, 0xFF, SMUD)
+ ShiftRight (Local0, 0x08, Local0)
+ And (Local0, 0x0F, SSRT)
+ ShiftRight (Local0, 0x04, Local0)
+ And (Local0, 0x0F, SSPW)
+ ShiftRight (Local0, 0x04, Local0)
+ And (Local0, 0x0F, SMRT)
+ ShiftRight (Local0, 0x04, Local0)
+ And (Local0, 0x0F, SMPW)
+ Store (GTF (0x00, Arg1), ATA2)
+ Store (GTF (0x01, Arg2), ATA3)
+ }
+ Device (DRV0) {
+ Name (_ADR, 0x00)
+ Method (_GTF, 0, NotSerialized) {
+ Return (RATA (ATA2))
+ }
+ }
+ Device (DRV1) {
+ Name (_ADR, 0x01)
+ Method (_GTF, 0, NotSerialized) {
+ Return (RATA (ATA3))
+ }
+ }
+ }
+ Method (GTM, 6, Serialized) {
+ Store (Ones, PIO0)
+ Store (Ones, PIO1)
+ Store (Ones, DMA0)
+ Store (Ones, DMA1)
+ Store (0x1A, CHNF)
+ If (REGF) {}
+ Else { Return (TMD0) }
+ Add (Arg0, Arg1, Local0)
+ Add (Local0, 0x02, Local0)
+ Multiply (Local0, 0x1E, PIO0)
+ Add (Arg2, Arg3, Local0)
+ Add (Local0, 0x02, Local0)
+ Multiply (Local0, 0x1E, PIO1)
+ If (And (Arg4, 0x40)) {
+ Or (CHNF, 0x01, CHNF)
+ And (Arg4, 0x07, Local0)
+ If (LLess (Local0, 0x04)) {
+ Add (Local0, 0x02, Local0)
+ Multiply (Local0, 0x1E, DMA0)
+ } Else {
+ If (LEqual (Local0, 0x04)) {
+ Store (0x2D, DMA0)
+ } Else {
+ If (LEqual (Local0, 0x05)) {
+ Store (0x1E, DMA0)
+ } Else {
+ If (LEqual (Local0, 0x06)) {
+ Store (0x14, DMA0)
+ } Else {
+ If (LEqual (Local0, 0x07)) {
+ Store (0x0F, DMA0)
+ } Else {
+ Store (PIO0, DMA0)
+ }
+ }
+ }
+ }
+ }
+ } Else {
+ Store (PIO0, DMA0)
+ }
+ If (And (Arg5, 0x40)) {
+ Or (CHNF, 0x04, CHNF)
+ And (Arg5, 0x07, Local0)
+ If (LLess (Local0, 0x04)) {
+ Add (Local0, 0x02, Local0)
+ Multiply (Local0, 0x1E, DMA1)
+ } Else {
+ If (LEqual (Local0, 0x04)) {
+ Store (0x2D, DMA1)
+ } Else {
+ If (LEqual (Local0, 0x05)) {
+ Store (0x1E, DMA1)
+ } Else {
+ If (LEqual (Local0, 0x06)) {
+ Store (0x14, DMA1)
+ } Else {
+ If (LEqual (Local0, 0x07)) {
+ Store (0x0F, DMA0)
+ } Else {
+ Store (PIO1, DMA1)
+ }
+ }
+ }
+ }
+ }
+ } Else {
+ Store (PIO1, DMA1)
+ }
+ Return (TMD0)
+ }
+ Method (STM, 0, Serialized) {
+ If (REGF) {}
+ Else { Return (0xFFFFFFFF) }
+ If (LEqual (PIO0, 0xFFFFFFFF)) {
+ Store (0xA8, Local1)
+ } Else {
+ And (Match (DerefOf (Index (TIM0, 0x00)),
+ MGE, PIO0, MTR,
+ 0x00, 0x00),
+ 0x07, Local0)
+ Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
+ Local1)
+ }
+ ShiftLeft (Local1, 0x08, Local1)
+ If (LEqual (PIO1, 0xFFFFFFFF)) {
+ Or (Local1, 0xA8, Local1)
+ } Else {
+ And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO1, MTR,
+ 0x00, 0x00), 0x07, Local0)
+ Or (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
+ Local1, Local1)
+ }
+ ShiftLeft (Local1, 0x08, Local1)
+ If (LEqual (DMA0, 0xFFFFFFFF)) {
+ Or (Local1, 0x03, Local1)
+ } Else {
+ If (And (CHNF, 0x01)) {
+ And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA0, MTR,
+ 0x00, 0x00), 0x07, Local0)
+ Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)),
+ Local1, Local1)
+ } Else {
+ Or (Local1, 0x03, Local1)
+ }
+ }
+ ShiftLeft (Local1, 0x08, Local1)
+ If (LEqual (DMA1, 0xFFFFFFFF)) {
+ Or (Local1, 0x03, Local1)
+ } Else {
+ If (And (CHNF, 0x04)) {
+ And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA1, MTR,
+ 0x00, 0x00), 0x07, Local0)
+ Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)),
+ Local1, Local1)
+ } Else {
+ Or (Local1, 0x03, Local1)
+ }
+ }
+ Return (Local1)
+ }
+ Name (AT01, Buffer (0x07) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF
+ })
+ Name (AT02, Buffer (0x07) {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90
+ })
+ Name (AT03, Buffer (0x07) {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6
+ })
+ Name (AT04, Buffer (0x07) {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91
+ })
+ Name (ATA0, Buffer (0x1D) {})
+ Name (ATA1, Buffer (0x1D) {})
+ Name (ATA2, Buffer (0x1D) {})
+ Name (ATA3, Buffer (0x1D) {})
+ Name (ATAB, Buffer (0x1D) {})
+ CreateByteField (ATAB, 0x00, CMDC)
+ Method (GTFB, 3, Serialized) {
+ Multiply (CMDC, 0x38, Local0)
+ Add (Local0, 0x08, Local1)
+ CreateField (ATAB, Local1, 0x38, CMDX)
+ Multiply (CMDC, 0x07, Local0)
+ CreateByteField (ATAB, Add (Local0, 0x02), A001)
+ CreateByteField (ATAB, Add (Local0, 0x06), A005)
+ Store (Arg0, CMDX)
+ Store (Arg1, A001)
+ Store (Arg2, A005)
+ Increment (CMDC)
+ }
+ Method (GTF, 2, Serialized) {
+ Store (Arg1, Debug)
+ Store (0x00, CMDC)
+ Name (ID49, 0x0C00)
+ Name (ID59, 0x00)
+ Name (ID53, 0x04)
+ Name (ID63, 0x0F00)
+ Name (ID88, 0x0F00)
+ Name (IRDY, 0x01)
+ Name (PIOT, 0x00)
+ Name (DMAT, 0x00)
+ If (LEqual (SizeOf (Arg1), 0x0200)) {
+ CreateWordField (Arg1, 0x62, IW49)
+ Store (IW49, ID49)
+ CreateWordField (Arg1, 0x6A, IW53)
+ Store (IW53, ID53)
+ CreateWordField (Arg1, 0x7E, IW63)
+ Store (IW63, ID63)
+ CreateWordField (Arg1, 0x76, IW59)
+ Store (IW59, ID59)
+ CreateWordField (Arg1, 0xB0, IW88)
+ Store (IW88, ID88)
+ }
+ Store (0xA0, Local7)
+ If (Arg0) {
+ Store (0xB0, Local7)
+ And (CHNF, 0x08, IRDY)
+ If (And (CHNF, 0x10)) {
+ Store (PIO1, PIOT)
+ } Else {
+ Store (PIO0, PIOT)
+ }
+ If (And (CHNF, 0x04)) {
+ If (And (CHNF, 0x10)) {
+ Store (DMA1, DMAT)
+ } Else {
+ Store (DMA0, DMAT)
+ }
+ } Else {
+ Store (PIO1, DMAT)
+ }
+ } Else {
+ And (CHNF, 0x02, IRDY)
+ Store (PIO0, PIOT)
+ If (And (CHNF, 0x01)) {
+ Store (DMA0, DMAT)
+ }
+ }
+ If (LAnd (LAnd (And (ID53, 0x04), And (ID88, 0xFF00)), DMAT)) {
+ Store (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMAT, MTR,
+ 0x00, 0x00), Local1)
+ If (LGreater (Local1, 0x06)) {
+ Store (0x06, Local1)
+ }
+ GTFB (AT01, Or (0x40, Local1), Local7)
+ } Else {
+ If (LAnd (And (ID63, 0xFF00), PIOT)) {
+ And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR,
+ 0x00, 0x00), 0x07, Local0)
+ If (Local0) {
+ If (And (Local0, 0x04)) {
+ Store (0x02, Local0)
+ } Else {
+ Store (0x01, Local0)
+ }
+ }
+ Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0
+ )), Local1)
+ GTFB (AT01, Local1, Local7)
+ }
+ }
+ If (IRDY) {
+ And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR,
+ 0x00, 0x00), 0x07, Local0)
+ Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0
+ )), Local1)
+ GTFB (AT01, Local1, Local7)
+ } Else {
+ If (And (ID49, 0x0400)) {
+ GTFB (AT01, 0x01, Local7)
+ }
+ }
+ If (LAnd (And (ID59, 0x0100), And (ID59, 0xFF))) {
+ GTFB (AT03, And (ID59, 0xFF), Local7)
+ }
+ Store (ATAB, Debug)
+ Return (ATAB)
+ }
+ Method (RATA, 1, NotSerialized) {
+ CreateByteField (Arg0, 0x00, CMDN)
+ Multiply (CMDN, 0x38, Local0)
+ CreateField (Arg0, 0x08, Local0, RETB)
+ Store (RETB, Debug)
+ Return (RETB)
+ }
+}
+Device (PMF) {
+ // acpi smbus it should be 0x00040003 if 8131 present
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
+ }
+ OperationRegion (BAR0, PCI_Config, 0x00, 0xff)
+ Field (BAR0, ByteAcc, NoLock, Preserve) {
+ Offset (0x56),
+ PIRA, 4,
+ PIRB, 4,
+ PIRC, 4,
+ PIRD, 4
+ }
+ //OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
+ //Field (TS3_, DWordAcc, NoLock, Preserve) {
+ // PTS3, 16
+ //}
+}
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl
new file mode 100644
index 0000000..a12be9d
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111 isa
+
+Device (ISA) {
+ // lpc 0x00040000
+ Method (_ADR, 0, NotSerialized) {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
+ }
+ /*
+ OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
+ Field (PIRY, ByteAcc, NoLock, Preserve) {
+ Z000, 2, // Parallel Port Range
+ , 1,
+ ECP , 1, // ECP Enable
+ FDC1, 1, // Floppy Drive Controller 1
+ FDC2, 1, // Floppy Drive Controller 2
+ Offset (0x01),
+ Z001, 3, // Serial Port A Range
+ SAEN, 1, // Serial Post A Enabled
+ Z002, 3, // Serial Port B Range
+ SBEN, 1 // Serial Post B Enabled
+ }
+ */
+ Device (PIC) {
+ Name (_HID, EisaId ("PNP0000"))
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) // Master Interrupt controller
+ IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) // Slave Interrupt controller
+ IRQ (Edge, ActiveHigh, Exclusive) {2}
+ })
+ }
+ Device (DMA1) {
+ Name (_HID, EisaId ("PNP0200"))
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) // Slave DMA controller
+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) // DMA page registers
+ IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) // Master DMA controller
+ DMA (Compatibility, NotBusMaster, Transfer16) {4}
+ })
+ }
+ Device (TMR) {
+ Name (_HID, EisaId ("PNP0100"))
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) // Programmable Interval timer
+ IRQ (Edge, ActiveHigh, Exclusive) {0}
+ })
+ }
+ Device (RTC) {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0070, 0x0070, 0x01, 0x04) // Realtime Clock and CMOS ram
+ IRQ (Edge, ActiveHigh, Exclusive) {8}
+ })
+ }
+ Device (SPKR) {
+ Name (_HID, EisaId ("PNP0800"))
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) // PC speaker
+ })
+ }
+ Device (COPR) { // Co-processor
+ Name (_HID, EisaId ("PNP0C04"))
+ Name (_CRS, ResourceTemplate () {
+ IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) // Floating point Error control
+ IRQ (Edge, ActiveHigh, Exclusive) {13}
+ })
+ }
+ Device (SYSR) { // System control registers (?)
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x00)
+ Name (CRS, ResourceTemplate () {
+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
+ IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
+ IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C)
+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x01)
+ IO (Decode16, 0x0084, 0x0084, 0x01, 0x03)
+ IO (Decode16, 0x0088, 0x0088, 0x01, 0x01)
+ IO (Decode16, 0x008C, 0x008C, 0x01, 0x03)
+ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
+ // IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ // EISA defined level triggered interrupt control registers
+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02)
+ // IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ // IO (Decode16, 0xDE00, 0xDE00, 0x00, 0x80)
+ // IO (Decode16, 0xDE80, 0xDE80, 0x00, 0x80)
+ IO (Decode16,0xDE00,0xDE00,0x00,0x80)
+ IO (Decode16,0xDE80,0xDE80,0x00,0x80)
+ // IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
+ // IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
+ IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0D) // PMBS block
+ IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0E) // SMBS block
+ IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0F) // GPBS block
+ })
+ Method (_CRS, 0, NotSerialized) {
+ CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MIN, GP00)
+ CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MAX, GP01)
+ CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._LEN, GP0L)
+ Store (PMBS, GP00)
+ Store (PMBS, GP01)
+ Store (PMLN, GP0L)
+ If (SMBS) {
+ CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MIN, GP10)
+ CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MAX, GP11)
+ CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._LEN, GP1L)
+ Store (SMBS, GP10)
+ Store (SMBS, GP11)
+ Store (SMBL, GP1L)
+ }
+ If (GPBS) {
+ CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MIN, GP20)
+ CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MAX, GP21)
+ CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._LEN, GP2L)
+ Store (GPBS, GP20)
+ Store (GPBS, GP21)
+ Store (GPLN, GP2L)
+ }
+ Return (CRS)
+ }
+ }
+ Device (MEM) {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x01)
+ Method (_CRS, 0, NotSerialized) {
+ Name (BUF0, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
+ Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
+ Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
+ Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
+ Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
+ Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ })
+// Read the Video Memory length
+ CreateDWordField (BUF0, 0x14, CLEN)
+ CreateDWordField (BUF0, 0x10, CBAS)
+
+ ShiftLeft (VGA1, 0x09, Local0)
+ Store (Local0, CLEN)
+
+ Return (BUF0)
+ }
+ }
+#include "superio/winbond/w83627hf/acpi/superio.asl"
+}
+
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl
new file mode 100644
index 0000000..3880d18
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111 pic LNKA B C D
+
+Device (LNKA) {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+ Method (_STA, 0, NotSerialized) {
+ If (LEqual (\_SB.PCI0.PMF.PIRA, 0x00) ) { Return (0x09) } //Disabled
+ Else { Return (0x0B) } //Enabled
+ }
+ Method (_PRS, 0, NotSerialized) {
+ Name (BUFA, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+ Method (_DIS, 0, NotSerialized) {
+ Store (0x00, \_SB.PCI0.PMF.PIRA )
+ }
+
+ Method (_CRS, 0, NotSerialized) {
+ Name (BUFA, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local2)
+ Store (0x00, Local3)
+ Store (\_SB.PCI0.PMF.PIRA, Local1)
+ If (LNot (LEqual (Local1, 0x00))) { // Routing enable
+ If (LGreater (Local1, 0x07)) {
+ Subtract (Local1, 0x08, Local1)
+ ShiftLeft (One, Local1, Local3)
+ } Else {
+ If (LGreater (Local1, 0x00)) {
+ ShiftLeft (One, Local1, Local2)
+ }
+ }
+ Store (Local2, IRA1)
+ Store (Local3, IRA2)
+ }
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized) {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00)) {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+ Store(Local1,\_SB.PCI0.PMF.PIRA)
+ }
+}
+
+Device (LNKB) {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized) {
+ If (LEqual (\_SB.PCI0.PMF.PIRB, 0x00) ) { Return (0x09) } //Disabled
+ Else { Return (0x0B) } //Enabled
+ }
+
+ Method (_PRS, 0, NotSerialized) {
+ Name (BUFB, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Store (0x00, \_SB.PCI0.PMF.PIRB )
+ }
+
+ Method (_CRS, 0, NotSerialized) {
+ Name (BUFB, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRA1)
+ CreateByteField (BUFB, 0x02, IRA2)
+ Store (0x00, Local2)
+ Store (0x00, Local3)
+ Store (\_SB.PCI0.PMF.PIRB, Local1)
+ If (LNot (LEqual (Local1, 0x00))) { // Routing enable
+ If (LGreater (Local1, 0x07)) {
+ Subtract (Local1, 0x08, Local1)
+ ShiftLeft (One, Local1, Local3)
+ } Else {
+ If (LGreater (Local1, 0x00)) {
+ ShiftLeft (One, Local1, Local2)
+ }
+ }
+ Store (Local2, IRA1)
+ Store (Local3, IRA2)
+ }
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized) {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00)) {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+ Store(Local1,\_SB.PCI0.PMF.PIRB)
+ }
+}
+
+Device (LNKC) {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+ Method (_STA, 0, NotSerialized) {
+ If (LEqual (\_SB.PCI0.PMF.PIRC, 0x00) ) { Return (0x09) } //Disabled
+ Else { Return (0x0B) } //Enabled
+ }
+
+ Method (_PRS, 0, NotSerialized) {
+ Name (BUFA, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized) {
+ Store (0x00, \_SB.PCI0.PMF.PIRC )
+ }
+
+ Method (_CRS, 0, NotSerialized) {
+ Name (BUFA, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local2)
+ Store (0x00, Local3)
+ Store (\_SB.PCI0.PMF.PIRC, Local1)
+ If (LNot (LEqual (Local1, 0x00))) { // Routing enable
+ If (LGreater (Local1, 0x07)) {
+ Subtract (Local1, 0x08, Local1)
+ ShiftLeft (One, Local1, Local3)
+ } Else {
+ If (LGreater (Local1, 0x00)) {
+ ShiftLeft (One, Local1, Local2)
+ }
+ }
+ Store (Local2, IRA1)
+ Store (Local3, IRA2)
+ }
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized) {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00)) {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+ Store(Local1,\_SB.PCI0.PMF.PIRC)
+ }
+}
+
+Device (LNKD) {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+ Method (_STA, 0, NotSerialized) {
+ If (LEqual (\_SB.PCI0.PMF.PIRD, 0x00) ) { Return (0x09) } //Disabled
+ Else { Return (0x0B) } //Enabled
+ }
+ Method (_PRS, 0, NotSerialized) {
+ Name (BUFB, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+ Method (_DIS, 0, NotSerialized) {
+ Store (0x00, \_SB.PCI0.PMF.PIRD )
+ }
+ Method (_CRS, 0, NotSerialized) {
+ Name (BUFB, ResourceTemplate () {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRA1)
+ CreateByteField (BUFB, 0x02, IRA2)
+ Store (0x00, Local2)
+ Store (0x00, Local3)
+ Store (\_SB.PCI0.PMF.PIRD, Local1)
+ If (LNot (LEqual (Local1, 0x00))) { // Routing enable
+ If (LGreater (Local1, 0x07)) {
+ Subtract (Local1, 0x08, Local1)
+ ShiftLeft (One, Local1, Local3)
+ } Else {
+ If (LGreater (Local1, 0x00)) {
+ ShiftLeft (One, Local1, Local2)
+ }
+ }
+ Store (Local2, IRA1)
+ Store (Local3, IRA2)
+ }
+ Return (BUFB)
+ }
+ Method (_SRS, 1, NotSerialized) {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00)) {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+ Store(Local1,\_SB.PCI0.PMF.PIRD)
+ }
+}
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8131.asl b/src/mainboard/hp/dl145_g1/acpi/amd8131.asl
new file mode 100644
index 0000000..fbbb37d
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8131.asl
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2005 AMD
+ * Copyright (C) 2011 Oskar Enoksson <enok(a)lysator.liu.se>
+ */
+
+Device (PG0A) {
+/* 8131 pcix bridge 1 */
+ Method (_ADR, 0, NotSerialized) {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+ Method (_PRW, 0, NotSerialized) {
+ //If (CondRefOf (\_S3, Local0)) {
+ // Return (Package (0x02) { 0x29, 0x03 })
+ //} Else {
+ Return (Package (0x02) { 0x29, 0x01 })
+ //}
+ }
+ Name (APIC, Package (0x0c) {
+ // Slot 3 - PIRQ BCDA ---- verified
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
+ // Slot 4 - PIRQ CDAB ---- verified
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //?
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
+ // Onboard NIC 1 - PIRQ DABC
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //?
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A },
+ // NIC 2 - PIRQ ABCD -- verified
+ // Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //?
+ // Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
+ // Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
+ // Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
+ // SERIAL ATA - PIRQ BCDA
+ // Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //?
+ // Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A },
+ // Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B },
+ // Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 }
+ })
+ Name (PICM, Package (0x0c) {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
+ // Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ // Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ // Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ // Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ // Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
+ // Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ // Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ // Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized) {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+}
+Device (PG0B) {
+/* 8131 pcix bridge 2 */
+ Method (_ADR, 0, NotSerialized) {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+ Method (_PRW, 0, NotSerialized) {
+ //If (CondRefOf (\_S3, Local0)) {
+ // Return (Package (0x02) { 0x22, 0x03 })
+ //} Else {
+ Return (Package (0x02) { 0x22, 0x01 })
+ //}
+ }
+ Name (APIC, Package (0x04) {
+ // Slot A - PIRQ CDAB -- verfied
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },// Slot 2
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1C },
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1D },
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1E }
+ })
+ Name (PICM, Package (0x04) {
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized) {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+}
diff --git a/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl b/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl
new file mode 100644
index 0000000..197346c
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl
@@ -0,0 +1,2 @@
+#include "amd8111.asl" //real SB at first
+#include "amd8131.asl"
diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c
new file mode 100644
index 0000000..9fa5f2c
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/acpi_tables.c
@@ -0,0 +1,342 @@
+/*
+ * Island Aruma ACPI support
+ * written by Stefan Reinauer <stepan(a)openbios.org>
+ * (C) 2005 Stefan Reinauer
+ *
+ *
+ * Copyright 2005 AMD
+ * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdk8_sysconf.h>
+#include "northbridge/amd/amdk8/acpi.h"
+#include "mb_sysconf.h"
+#include <cpu/amd/model_fxx_powernow.h>
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(unsigned start, unsigned end)
+{
+
+ unsigned i;
+ print_debug("dump_mem:");
+ for(i=start;i<end;i++) {
+ if((i & 0xf)==0) {
+ printk(BIOS_DEBUG, "\n%08x:", i);
+ }
+ printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
+ }
+ print_debug("\n");
+}
+#endif
+
+extern unsigned pm_base;
+
+extern const unsigned char AmlCode[];
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+extern const unsigned char AmlCode_ssdt2[];
+extern const unsigned char AmlCode_ssdt3[];
+extern const unsigned char AmlCode_ssdt4[];
+extern const unsigned char AmlCode_ssdt5[];
+#endif
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
+}
+
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ unsigned int gsi_base=0x18;
+
+ struct mb_sysconf_t *m;
+
+ m = sysconf.mb;
+
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write 8111 IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
+ IO_APIC_ADDR, 0);
+
+ /* Write all 8131 IOAPICs */
+ {
+ device_t dev;
+ struct resource *res;
+ dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_1,
+ res->base, gsi_base );
+ gsi_base+=4;
+
+ }
+ }
+ dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_2,
+ res->base, gsi_base );
+ gsi_base+=4;
+ }
+ }
+
+ /*
+ int i;
+ int j = 0;
+
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ unsigned d = 0;
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ // 8131 need to use +4
+
+ switch (sysconf.hcid[i]) {
+ case 1:
+ d = 7;
+ break;
+ case 3:
+ d = 4;
+ break;
+ }
+ switch (sysconf.hcid[i]) {
+ case 1:
+ case 3:
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
+ res->base, gsi_base );
+ gsi_base+=d;
+ }
+ }
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
+ res->base, gsi_base );
+ gsi_base+=d;
+
+ }
+ }
+ break;
+ }
+
+ j++;
+ }
+ */
+
+ }
+
+ current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 5 );
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edige-triggered, Active high*/
+
+
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapic_nmis(current, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) {
+ k8acpi_write_vars();
+#if CONFIG_SET_FIDVID
+ amd_model_fxx_generate_powernow(pm_base+0x10, 6, 1);
+ acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
+#endif
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_srat_t *srat;
+ acpi_slit_t *slit;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+
+
+ get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
+
+ /* Align ACPI tables to 16byte */
+ start = ( start + 0x0f ) & -0x10;
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp,hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current+=madt->header.length;
+ acpi_add_table(rsdp,madt);
+
+
+ /* SRAT */
+ printk(BIOS_DEBUG, "ACPI: * SRAT\n");
+ srat = (acpi_srat_t *) current;
+ acpi_create_srat(srat);
+ current+=srat->header.length;
+ acpi_add_table(rsdp,srat);
+
+ /* SLIT */
+ printk(BIOS_DEBUG, "ACPI: * SLIT\n");
+ slit = (acpi_slit_t *) current;
+ acpi_create_slit(slit);
+ current+=slit->header.length;
+ acpi_add_table(rsdp,slit);
+
+ /* SSDT */
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+
+ acpi_create_ssdt_generator(ssdt, "DYNADATA");
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+ int i;
+ void *p;
+ acpi_header_t *ssdtx;
+ //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
+
+ for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
+ if((sysconf.pci1234[i] & 1) != 1 ) continue;
+ uint8_t c;
+ if(i<7) {
+ c = (uint8_t) ('4' + i - 1);
+ }
+ else {
+ c = (uint8_t) ('A' + i - 1 - 6);
+ }
+ printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
+ current = ( current + 0x07) & -0x08;
+ ssdtx = (acpi_header_t *)current;
+ switch(sysconf.hcid[i]) {
+ case 1: //8132
+ p = &AmlCode_ssdt2;
+ break;
+ case 2: //8151
+ p = &AmlCode_ssdt3;
+ break;
+ case 3: //8131
+ p = &AmlCode_ssdt4;
+ break;
+ default:
+ //HTX no io apic
+ p = &AmlCode_ssdt5;
+ break;
+ }
+ memcpy(ssdtx, p, sizeof(acpi_header_t));
+ current += ssdtx->length;
+ memcpy(ssdtx, p, ssdtx->length);
+ update_ssdtx((void *)ssdtx, i);
+ ssdtx->checksum = 0;
+ ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length);
+ acpi_add_table(rsdp,ssdtx);
+ }
+#endif
+
+ /* FACS */
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* DSDT */
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *)current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+ /* FADT */
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ acpi_fadt_t *fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt,facs,dsdt);
+ acpi_add_table(rsdp,fadt);
+
+#if DUMP_ACPI_TABLES == 1
+ printk(BIOS_DEBUG, "rsdp\n");
+ dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+ printk(BIOS_DEBUG, "rsdt\n");
+ dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+ printk(BIOS_DEBUG, "xsdt\n");
+ dump_mem(rsdt, ((void *)xsdt) + sizeof(acpi_xsdt_t));
+
+ printk(BIOS_DEBUG, "madt\n");
+ dump_mem(madt, ((void *)madt) + madt->header.length);
+
+ printk(BIOS_DEBUG, "srat\n");
+ dump_mem(srat, ((void *)srat) + srat->header.length);
+
+ printk(BIOS_DEBUG, "slit\n");
+ dump_mem(slit, ((void *)slit) + slit->header.length);
+
+ printk(BIOS_DEBUG, "ssdt\n");
+ dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+ printk(BIOS_DEBUG, "fadt\n");
+ dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
+
diff --git a/src/mainboard/hp/dl145_g1/dsdt.asl b/src/mainboard/hp/dl145_g1/dsdt.asl
new file mode 100644
index 0000000..735e34b
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/dsdt.asl
@@ -0,0 +1,314 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz>
+ * Copyright (C) 2011 Oskar Enoksson <enok(a)lysator.liu.se>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{
+ // Name (SPIO, 0x2E) // SuperIO (w83627hf)
+ Name (SPI2, 0x4E) // Unknown National Semiconductors (EPM3128A?)
+ Name (IO1B, 0x0680) // GPIO Base (?)
+ Name (IO1L, 0x80)
+ //Name (IO2B, 0x0295) // Hardware monitor
+ //Name (IO2L, 0x02)
+ Name (PMBS, 0x2000) // Power Management Base
+ Name (PMLN, 0xC0) // Power Management Length
+ Name (GPBS, 0x20C0)
+ Name (GPLN, 0x20)
+ Name (SMBS, 0x20E0)
+ Name (SMBL, 0x20)
+
+#define NO_W83627HF_FDC // don't expose the floppy disk controller
+#define NO_W83627HF_FDC_ENUM // don't try to enumerate the connected floppy drives
+#define NO_W83627HF_PPORT // don't expose the parallel port
+//#define NO_W83627HF_UARTA // don't expose the first serial port
+#define NO_W83627HF_UARTB // don't expose the second serial port (already hidden
+ // if UARTB is configured as IRDA port by firmware)
+#define NO_W83627HF_IRDA // don't expose the IRDA port (already hidden if UARTB is
+ // configured as serial port by firmware)
+#define NO_W83627HF_CIR // don't expose the Consumer Infrared functionality
+//#define NO_W83627HF_KBC // don't expose the keyboard controller
+//#define NO_W83627HF_PS2M // don't expose the PS/2 mouse functionality of the
+ // keyboard controller
+#define NO_W83627HF_GAME // don't expose the game port
+#define NO_W83627HF_MIDI // don't expose the MIDI port
+// #define NO_W83627HF_HWMON // don't expose the hardware monitor as
+ // PnP "Motherboard Resource"
+// Scope (\_PR) and relevant CPU? objects are auto-generated in SSDT
+
+ Scope (\_SB) { // Root of the bus hierarchy
+ Device (PCI0) { // Top PCI device (AMD K8 Northbridge 1)
+
+ Device(MBRS) {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x01)
+ External(_CRS) /* Resource Template in SSDT */
+ }
+
+ // The following symbols are assumed to be created by coreboot
+ External (BUSN)
+ External (PCIO)
+ External (MMIO)
+ External (SBLK)
+ External (CBST)
+ External (SBDN)
+ External (TOM1) // Top Of Memory 1 (low 4GB ?)
+ External (HCLK) // Hypertransport possible CLocK frequencies
+ External (HCDN) // Hypertransport Controller Device Numbers
+
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00180000)
+ //Name (_UID, 0x00)
+ Name (_UID, 0x01)
+
+ Name (HCIN, 0x00) // HC1
+ Method (_BBN, 0, NotSerialized) {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+ Method (_CRS, 0, NotSerialized) {
+ Name (BUF0, ResourceTemplate () {
+ // PCI Configuration address space address/data
+ IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)
+ IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
+ IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x8100, // Address Range Minimum
+ 0xFFFF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x7F00,,,
+ , TypeStatic) //8100h-FFFFh
+ DWordMemory (ResourceProducer, PosDecode,
+ MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x000C0000, // Address Range Minimum
+ 0x000CFFFF, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00010000,,,
+ , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
+ Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x03AF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x03B0,,,
+ , TypeStatic) //0-CF7h
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x03E0, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0918,,,
+ , TypeStatic) //0-CF7h
+ })
+ \_SB.OSTP ()
+ CreateDWordField (BUF0, 0x3E, VLEN)
+ CreateDWordField (BUF0, 0x36, VMAX)
+ CreateDWordField (BUF0, 0x32, VMIN)
+ ShiftLeft (VGA1, 0x09, Local0)
+ Add (VMIN, Local0, VMAX)
+ Decrement (VMAX)
+ Store (Local0, VLEN)
+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+ Return (Local3)
+ }
+ #include "acpi/pci0_hc.asl"
+ }
+ Device (PCI1) {
+ Name (_HID, "PNP0A03")
+ Name (_ADR, 0x00190000)
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized) {
+ Return (\_SB.PCI0.CBST)
+ }
+ //Name (HCIN, 0x01) // HC2
+ //Method (_BBN, 0, NotSerialized) {
+ // Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ //}
+ Name (_BBN, 0x00)
+ }
+ Device (PWRB) {
+ Name (_HID, EisaId ("PNP0C0C"))
+ Name (_UID, 0xAA)
+ Name (_STA, 0x0B)
+ }
+ }
+ Scope (_GPE) {
+ Method (_L08, 0, NotSerialized) {
+ Notify (\_SB.PCI0, 0x02) //PME# Wakeup
+ Notify (\_SB.PCI0.TP2P.ETHR, 0x02)
+ Notify (\_SB.PWRB, 0x02)
+ }
+ Method (_L0F, 0, NotSerialized) {
+ Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
+ Notify (\_SB.PCI0.TP2P.USB1, 0x02)
+ Notify (\_SB.PWRB, 0x02)
+ }
+ Method (_L22, 0, NotSerialized) { // GPIO18 (LID) - Pogo 0 Bridge B
+ Notify (\_SB.PCI0.PG0B, 0x02)
+ Notify (\_SB.PWRB, 0x02)
+ }
+ Method (_L29, 0, NotSerialized) { // GPIO25 (Suspend) - Pogo 0 Bridge A
+ Notify (\_SB.PCI0.PG0A, 0x02)
+ Notify (\_SB.PWRB, 0x02)
+ }
+ }
+ OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?)
+ Field (KSB0, ByteAcc, NoLock, Preserve) {
+ KSBI, 8, // Index
+ KSBD, 8 // Data
+ }
+/*
+ OperationRegion (IHHM, SystemIO, IO2B, IO2L) // Hardware monitor
+ Field (IHHM, ByteAcc, NoLock, Preserve) {
+ HHMI, 8, // Index
+ HHMD, 8 // Data
+ }
+*/
+ // Method (_BFS, 1, NotSerialized) {
+ // Control method executed immediately following a wake event.
+ // Arg0 => Value of the sleeping state from which woken (1=S1, 2=S2 ...)
+ // Optional
+ //}
+
+ Method (_PTS, 1, NotSerialized) {
+ // Control method used to Prepare To Sleep.
+ // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...)
+ Or (Arg0, 0xF0, Local0)
+ Store (Local0, DBG8)
+ }
+
+ // Method (_GTS, 1, NotSerialized) {
+ // Control method executed just prior to setting the sleep enable (SLP_EN) bit.
+ // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...)
+ // Optional
+ //}
+
+ // System \_Sx states
+ // Four bytes must be stored for each supported power state:
+ // 0:7 Value for PM1a_CNT.SLP_TYP register to enter this system state.
+ // 8:f Value for PM1b_CNT.SLP_TYP register to enter this system state.
+ // To enter any given state, OSPM must write the PM1a_CNT.SLP_TYP
+ // register before the PM1b_CNT.SLP_TYP register.
+ // 10:1f Reserved
+ // The states are:
+ // S0 : Working
+ // S1 : Sleeping with Processor Context maintained
+ // S2 : Sleeping with Processor Context not maintained
+ // S3 : Same as S2, but more power saving (e.g. suspend to RAM)
+ // S4 : DRAM context not maintained (e.g. suspend to disk)
+ // S5 : Soft Off
+ // If only S0 and S5 are declared then no wake-up methods are needed
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+ // S1 support should work, but never wakes up, so it's commented out
+ //Name (\_S1, Package () { 0x01, 0x01, 0x01, 0x01 })
+ //Name (\_S3, Package () { 0x05, 0x05, 0x05, 0x05 })
+ Name (\_S5, Package () { 0x07, 0x07, 0x07, 0x07 })
+ //Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+ Method (WAK, 1, NotSerialized) {}
+
+ Name (WAKP, Package (0x02) { 0x00, 0x00 })
+ // Status
+ // 0: 0 Wake was signaled but failed due to lack of power.
+ // 1: 1 Wake was signaled but failed due to thermal condition
+ // 2:31 Reserved
+ // PSS
+ // 0:1f If non-zero, the effective S-state the power supply really entered.
+
+ Method (_WAK, 1, NotSerialized) {
+ // System Wake
+ // Arg0: The value of the sleeping state from which woken (1=S1, ...)
+ // Result: (2 DWORD package)
+ ShiftLeft (Arg0, 0x04, DBG8)
+ WAK (Arg0)
+ Store (0xFF, KSBI) // Clear 0xFF in CMOS RAM
+ Store (0x00, KSBD)
+ If (LEqual (Arg0, 0x01)) { // Wake from S1 state
+ And (\_SB.PCI0.GSTS, 0x10, Local0)
+ And (Local0, \_SB.PCI0.GNBL, Local0)
+ If (Local0) {
+ Notify (\_SB.PWRB, 0x02)
+ }
+ }
+ Store (\_SB.PCI0.GSTS, \_SB.PCI0.GSTS)
+ Store (\_SB.PCI0.STMC, \_SB.PCI0.STMC)
+ Store (\_SB.PCI0.STC0, \_SB.PCI0.STC0)
+ Store (\_SB.PCI0.STC1, \_SB.PCI0.STC1)
+ Store (\_SB.PCI0.STHW, \_SB.PCI0.STHW)
+ If (LEqual (Arg0, 0x03)) { // Wake from S3 state
+ Notify (\_SB.PCI0.TP2P.USB0, 0x01)
+ }
+ Store (0xC0, \_SB.PCI0.SWSM)
+ If (DerefOf (Index (WAKP, 0x00))) {
+ Store (0x00, Index (WAKP, 0x01))
+ } Else {
+ Store (Arg0, Index (WAKP, 0x01))
+ }
+ Return (WAKP)
+ }
+
+ Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
+ Method (_PIC, 1, NotSerialized) { //PIC Flag and Interface Method
+ // Control method that conveys interrupt model in use to the system
+ // firmware. OS reports interrupt model in use.
+ // 0 => PIC Mode
+ // 1 => APIC Mode
+ // 2 => SAPIC Mode
+ // 3.. => Reserved
+ Store (Arg0, PICF)
+ }
+ OperationRegion (DEB8, SystemIO, 0x80, 0x01)
+ Field (DEB8, ByteAcc, Lock, Preserve) {
+ DBG8, 8
+ }
+ OperationRegion (DEB9, SystemIO, 0x90, 0x01)
+ Field (DEB9, ByteAcc, Lock, Preserve) {
+ DBG9, 8
+ }
+ OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
+ Field (EXTM, WordAcc, Lock, Preserve) {
+ AMEM, 32
+ }
+ OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
+ Field (VGAM, ByteAcc, Lock, Preserve) {
+ VGA1, 8 // Video memory length (in 2k units?)
+ }
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve) {
+ Offset (0x10),
+ FLG0, 8
+ }
+ OperationRegion (Z007, SystemIO, 0x21, 0x01)
+ Field (Z007, ByteAcc, NoLock, Preserve) {
+ Z008, 8
+ }
+ OperationRegion (Z009, SystemIO, 0xA1, 0x01)
+ Field (Z009, ByteAcc, NoLock, Preserve) {
+ Z00A, 8
+ }
+ #include "northbridge/amd/amdk8/util.asl"
+}
diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c
new file mode 100644
index 0000000..c098cef
--- /dev/null
+++ b/src/mainboard/hp/dl145_g1/fadt.c
@@ -0,0 +1,182 @@
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ * (C) Copyright 2005 Stefan Reinauer <stepan(a)openbios.org>
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+
+extern unsigned pm_base; /* pm_base should be set in sb acpi */
+
+void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
+
+ acpi_header_t *header=&(fadt->header);
+
+ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+
+ /* Prepare the header */
+ memset((void *)fadt,0,sizeof(acpi_fadt_t));
+ memcpy(header->signature,"FACP",4);
+ header->length = 244;
+ header->revision = 3;
+ memcpy(header->oem_id,OEM_ID,6);
+ memcpy(header->oem_table_id,"COREBOOT",8);
+ memcpy(header->asl_compiler_id,ASLC,4);
+ header->asl_compiler_revision=0;
+
+ fadt->firmware_ctrl=(u32)facs;
+ fadt->dsdt= (u32)dsdt;
+ // 3=Workstation,4=Enterprise Server, 7=Performance Server
+ fadt->preferred_pm_profile=0x04;
+ fadt->sci_int=9;
+
+ // disable system management mode by setting to 0:
+ fadt->smi_cmd = 0;//pm_base+0x2f;
+ fadt->acpi_enable = 0xf0;
+ fadt->acpi_disable = 0xf1;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0xe2;
+
+ fadt->pm1a_evt_blk = pm_base;
+ fadt->pm1b_evt_blk = 0x0000;
+ fadt->pm1a_cnt_blk = pm_base+0x04;
+ fadt->pm1b_cnt_blk = 0x0000;
+ fadt->pm2_cnt_blk = 0x0000;
+ fadt->pm_tmr_blk = pm_base+0x08;
+ fadt->gpe0_blk = pm_base+0x20;
+ fadt->gpe1_blk = pm_base+0xb0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 0;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 4;
+ fadt->gpe1_blk_len = 8;
+ fadt->gpe1_base = 16;
+
+ fadt->cst_cnt = 0xe3;
+ fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state
+ fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state
+ fadt->flush_size = 0; // ignored if wbindv=1 in flags
+ fadt->flush_stride = 0; // ignored if wbindv=1 in flags
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3; // 0 means duty cycle not supported
+ // _alrm value 0 means RTC alarm feature not supported
+ fadt->day_alrm = 0; // 0x7d these have to be
+ fadt->mon_alrm = 0; // 0x7e added to cmos.layout
+ fadt->century = 0; // 0x7f to make rtc alrm work
+ fadt->iapc_boot_arch =
+ ACPI_FADT_LEGACY_DEVICES |
+ ACPI_FADT_8042 |
+ // ACPI_FADT_VGA_NOT_PRESENT |
+ // ACPI_FADT_MSI_NOT_SUPPORTED|
+ // ACPI_FADT_NO_PCIE_ASPM_CONTROL|
+ 0;
+
+ fadt->res2 = 0;
+
+ fadt->flags =
+ ACPI_FADT_WBINVD |
+ // ACPI_FADT_WBINVD_FLUSH |
+ ACPI_FADT_C1_SUPPORTED |
+ // ACPI_FADT_C2_MP_SUPPORTED |
+ // ACPI_FADT_POWER_BUTTON |
+ ACPI_FADT_SLEEP_BUTTON |
+ // ACPI_FADT_FIXED_RTC |
+ // ACPI_FADT_S4_RTC_WAKE |
+ // ACPI_FADT_32BIT_TIMER |
+ // ACPI_FADT_DOCKING_SUPPORTED|
+ // ACPI_FADT_RESET_REGISTER |
+ // ACPI_FADT_SEALED_CASE |
+ // ACPI_FADT_HEADLESS |
+ // ACPI_FADT_SLEEP_TYPE |
+ // ACPI_FADT_PCI_EXPRESS_WAKE |
+ // ACPI_FADT_PLATFORM_CLOCK |
+ // ACPI_FADT_S4_RTC_VALID |
+ // ACPI_FADT_REMOTE_POWER_ON |
+ // ACPI_FADT_APIC_CLUSTER |
+ // ACPI_FADT_APIC_PHYSICAL |
+ 0;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 6;
+
+ fadt->res3 = 0;
+ fadt->res4 = 0;
+ fadt->res5 = 0;
+
+ fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pm_base;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 4;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 2;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 0;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = 0x0;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 32;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pm_base+0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 64;
+ fadt->x_gpe1_blk.bit_offset = 16;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = pm_base+0xb0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+
+}
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index 35dedde..725220e 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -53,26 +53,26 @@ static void *smp_write_config_table(void *v)
//
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
// Integrated SMBus 2.0
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
// Integrated AMD AC97 Audio
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
// Integrated AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13);
// On board ATI Rage XL
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
// On board Broadcom nics
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00);
// On board LSI SCSI
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
// PCIX-133 Slot
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
+ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 67ce9c1..6d32336 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -44,18 +44,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
#define SMBUS_HUB 0x18
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- int ret,i;
- unsigned device=(ctrl->channel0[0])>>8;
- /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
- i=2;
- do {
- ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- } while ((ret!=0) && (i-->0));
- smbus_write_byte(SMBUS_HUB, 0x03, 0);
-}
-
static inline void change_i2c_mux(unsigned device)
{
int ret, i;
@@ -69,6 +57,11 @@ static inline void change_i2c_mux(unsigned device)
print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
}
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ change_i2c_mux(ctrl->channel0[0]>>8);
+}
+
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@@ -82,22 +75,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/model_fxx/init_cpus.c"
-
-#define RC0 ((1<<1)<<8)
-#define RC1 ((1<<2)<<8)
+#if CONFIG_SET_FIDVID
+#include "cpu/amd/model_fxx/fidvid.c"
+#endif
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const uint16_t spd_addr [] = {
- //first node
- RC0|DIMM0, RC0|DIMM2, 0, 0,
- RC0|DIMM1, RC0|DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
- RC1|DIMM0, RC1|DIMM2, 0, 0,
- RC1|DIMM1, RC1|DIMM3, 0, 0,
-#endif
- };
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset = 0;
@@ -126,6 +109,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
ht_setup_chains_x(sysinfo);
+#if CONFIG_SET_FIDVID
+ /* Check to see if processor is capable of changing FIDVID */
+ /* otherwise it will throw a GP# when reading FIDVID_STATUS */
+ struct cpuid_result cpuid1 = cpuid(0x80000007);
+ if ((cpuid1.edx & 0x6) == 0x6) {
+ {
+ /* Read FIDVID_STATUS */
+ msr_t msr;
+ msr=rdmsr(0xc0010042);
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ }
+
+ enable_fid_change();
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+ init_fidvid_bsp(bsp_apicid);
+
+ // show final fid and vid
+ {
+ msr_t msr;
+ msr=rdmsr(0xc0010042);
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ }
+
+ } else {
+ print_debug("Changing FIDVID not supported\n");
+ }
+#endif
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
@@ -138,6 +148,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
int i;
+#define RC0 ((1<<1)<<8)
+#define RC1 ((1<<2)<<8)
+
for(i=0;i<2;i++) {
activate_spd_rom(&sysinfo->ctrl[i]);
}
@@ -152,9 +165,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl now;
+ static const uint16_t spd_addr [] = {
+ //first node
+ RC0|DIMM0, RC0|DIMM2, 0, 0,
+ RC0|DIMM1, RC0|DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ //second node
+ RC1|DIMM0, RC1|DIMM2, 0, 0,
+ RC1|DIMM1, RC1|DIMM3, 0, 0,
+#endif
+ };
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
memreset_setup();
+#if CONFIG_SET_FIDVID
+ init_timer(); // Need to use TMICT to synconize FID/VID
+#endif
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
//dump_pci_devices();
1
0
New patch to review for coreboot: fdce34b NOTFORMERGE: lenovo/x201: Support digitizer on x201t variant
by Vladimir Serbinenko 02 Feb '14
by Vladimir Serbinenko 02 Feb '14
02 Feb '14
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5096
-gerrit
commit fdce34b8883f2b8c6f5ee13f15bdf7cdc0f94016
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Feb 1 18:39:26 2014 +0100
NOTFORMERGE: lenovo/x201: Support digitizer on x201t variant
Thanks to Peter Stuge for his helpful insights
Thanks to Carl-Daniel Hailfinger for info on PnP superio.
Thanks to Jens Erat for letting me to experiment with his X201t.
Change-Id: Idb504fabf1ac1a55d8ada8d2b2268038110e32e0
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/lenovo/x201/Kconfig | 1 +
src/mainboard/lenovo/x201/acpi/superio.asl | 17 +++++++++++++++++
src/mainboard/lenovo/x201/devicetree.cb | 20 ++++++++++++++++++++
src/mainboard/lenovo/x201/romstage.c | 2 +-
4 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig
index 8e7ebae..7fd8543 100644
--- a/src/mainboard/lenovo/x201/Kconfig
+++ b/src/mainboard/lenovo/x201/Kconfig
@@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select ARCH_X86
select NORTHBRIDGE_INTEL_NEHALEM
select SOUTHBRIDGE_INTEL_IBEXPEAK
+ select SUPERIO_NSC_PC87382
select EC_LENOVO_PMH7
select EC_LENOVO_H8
select DRIVERS_ICS_954309
diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl
index a2657f1..22b1afa 100644
--- a/src/mainboard/lenovo/x201/acpi/superio.asl
+++ b/src/mainboard/lenovo/x201/acpi/superio.asl
@@ -1 +1,18 @@
#include "../../../../drivers/pc80/ps2_controller.asl"
+
+
+ Device (DTR) // Digitizer
+ {
+ Name(_HID, EISAID("WACF004"))
+
+ Name(_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x200, 0x200, 0x01, 0x08)
+ IRQNoFlags () {5}
+ })
+
+ Method (_STA, 0)
+ {
+ Return (0xf)
+ }
+ }
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index 37a430c..e7c9c45 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -139,6 +139,26 @@ chip northbridge/intel/nehalem
end
device pci 1f.0 on # PCI-LPC bridge
subsystemid 0x17aa 0x2166
+ chip superio/nsc/pc87382
+ device pnp 164e.2 on # IR
+ io 0x60 = 0x2f8
+ end
+
+ device pnp 164e.3 on # Digitizer
+ io 0x60 = 0x200
+ irq 0x29 = 0xb0
+ irq 0x70 = 0x5
+ irq 0xf0 = 0x82
+ end
+
+ device pnp 164e.7 on # GPIO
+ io 0x60 = 0x1680
+ end
+
+ device pnp 164e.19 on # DLPC
+ io 0x60 = 0x164c
+ end
+ end
end
device pci 1f.2 on # IDE/SATA
subsystemid 0x17aa 0x2168
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index e3e0a62..5ed48a9 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -53,7 +53,7 @@ static void pch_enable_lpc(void)
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
- COMA_LPC_EN);
+ COMA_LPC_EN | GAMEL_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
1
0
Patch set updated for coreboot: 4cee01d Added powernow support for two new (old) AMD K8 CPU's
by Oskar Enoksson 02 Feb '14
by Oskar Enoksson 02 Feb '14
02 Feb '14
Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5095
-gerrit
commit 4cee01d8d428b9cea3a73fc3a4979898a3aaac00
Author: Oskar Enoksson <enok(a)lysator.liu.se>
Date: Sun Feb 2 12:23:52 2014 +0100
Added powernow support for two new (old) AMD K8 CPU's
The added CPU's are OSA248CEP5AU and a OSP280 processors.
The OSP280 VID/FID numbers have been found by experimentation
and extrapolation/guesses from similar models. It has been verified
to work fine under Linux (OpenSuse 12.2, kernel 3.4.63-2.44) with four different test-processors. Windows untested..
Change-Id: I3afa1cba5f55c8a78917b3636382af7706a80fee
Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se>
---
src/cpu/amd/model_fxx/powernow_acpi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c
index 02e0306..ab7497a 100644
--- a/src/cpu/amd/model_fxx/powernow_acpi.c
+++ b/src/cpu/amd/model_fxx/powernow_acpi.c
@@ -478,6 +478,10 @@ struct cpuentry entr[] = {
{850, 0x14, 0x20f51, 0x10, 0x10, 853,
{{2200, 1350, 853}, {2000, 1300, 827},
{1800, 1250, 702}, {1000, 1100, 301}}},
+ /* OSA248CEP5AU */
+ {248, 0x10, 0x00f5a, 0xe, 0xe, 890,
+ {{2000, 1400, 700}, {1800, 1300, 470},
+ {1000, 1200, 280}}},
/* begin OSK246FAA5BL */
{246, 0x12, 0x20f51, 0xc, 0xc, 547,
{{1800, 1350, 461}, {1000, 1100, 223}}},
@@ -561,6 +565,10 @@ struct cpuentry entr[] = {
{180, 0x2c, 0x20f32, 0x10, 0x10, 1100,
{{2200, 1300, 1056}, {2000, 1250, 891},
{1800, 1200, 748}, {1000, 1100, 466}}},
+ /* OSP280 */
+ {280, 0x31, 0x20f12, 0x10, 0x10, 680,
+ {{2200, 1250, 650}, {2000, 1200, 574},
+ {1800, 1150, 433}, {1000, 1100, 220}}},
/* AMA3000BEX5AR */
{3000, 0x4, 0xf4a, 0xa, 0x0, 815,
{{1600, 1400, 570}, {800, 1100, 190}}},
1
0