coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 0240b31 Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.
by Edward O'Callaghan 03 Feb '14

03 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4801 -gerrit commit 0240b31da21415e9a90324ddb740b9502a547f80 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jan 25 21:46:10 2014 +1100 Jetway NF81-T56N-LF [2/2]: actually implement mainboard support. Step 2: change the Persimmon code to adapt it to the new board's hardware. The NF81-T56N-LF is a IPC form factor embedded board: - AMD Fusion G-T56N (1.65 GHz dual core) APU - 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V) - VGA and LVDS (via Analogix ANX3110) - AMD A55E (Hudson-E1) southbridge - 6x USB 2.0/1.1 ports - 5x SATA3 6Gb/s, 1x mSATA socket - 6-Channel HD Audio (via VIA VT1705) - PCI and ISA (via ITE IT8888)?? - NEC uPD78F0532 microcontroller on I2C ("SEMA")?? - 2x RJ45 GbE (via Realtek RTL8111E x2) - Fintek F71869AD Super I/O - PS/2 KB/MS port - RS232 header (via Unisonic UTC 75232 RS232 driver/receiver) - GPIO header - CIR header - 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS) Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies* claiming the SPI flash is 16MB. They also use red pen over the chip so you wont see this deceit. Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/Kconfig | 3 ++ src/mainboard/jetway/nf81-t56n-lf/Kconfig | 18 ++++--- src/mainboard/jetway/nf81-t56n-lf/board_info.txt | 5 +- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 66 ++++++++++++++++-------- src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 3 ++ src/mainboard/jetway/nf81-t56n-lf/romstage.c | 7 +-- 6 files changed, 68 insertions(+), 34 deletions(-) diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig index 7e6e29d..5b55daa 100644 --- a/src/mainboard/jetway/Kconfig +++ b/src/mainboard/jetway/Kconfig @@ -11,6 +11,8 @@ config BOARD_JETWAY_J7F4K1G5D bool "J7F4K1G5D" config BOARD_JETWAY_PA78VM5 bool "PA78VM5 (Fam10)" +config BOARD_JETWAY_NF81_T56N_LF + bool "NF81_T56N_LF" endchoice @@ -18,6 +20,7 @@ source "src/mainboard/jetway/j7f2/Kconfig" source "src/mainboard/jetway/j7f4k1g2e/Kconfig" source "src/mainboard/jetway/j7f4k1g5d/Kconfig" source "src/mainboard/jetway/pa78vm5/Kconfig" +source "src/mainboard/jetway/nf81-t56n-lf/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index febd8dd..d602ffa 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,7 +18,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -if BOARD_AMD_PERSIMMON +if BOARD_JETWAY_NF81_T56N_LF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -25,22 +26,23 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_FINTEK_F81865F + select SUPERIO_FINTEK_F71869AD select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_ACPI_RESUME +# FIXME: Disable S3 for now. Enable by default once stabilised. +# select HAVE_ACPI_RESUME select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT select AMDMCT select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_2048 select GFXUMA config MAINBOARD_DIR string - default amd/persimmon + default jetway/nf81-t56n-lf config APIC_ID_OFFSET hex @@ -48,7 +50,7 @@ config APIC_ID_OFFSET config MAINBOARD_PART_NUMBER string - default "Persimmon" + default "NF81-T56N-LF" config HW_MEM_HOLE_SIZEK hex @@ -101,7 +103,7 @@ config VGA_BIOS config VGA_BIOS_ID string - default "1002,9802" + default "1002,9806" # FUSION_G_T56N config SB800_AHCI_ROM bool @@ -111,4 +113,4 @@ config DRIVERS_PS2_KEYBOARD bool default n -endif # BOARD_AMD_PERSIMMON +endif # BOARD_JETWAY_NF81_T56N_LF diff --git a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt index 85cb19a..6748751 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt +++ b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt @@ -1,5 +1,6 @@ -Board name: DBFT1-00-EVAL-KT (Persimmon) -Category: eval +Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T5… +Category: Mini-ITX +ROM package: SOIC8 ROM protocol: SPI ROM socketed: n Flashrom support: y diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 8b1acd5..347d4a6 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -29,7 +30,8 @@ chip northbridge/amd/agesa/family14/root_complex chip northbridge/amd/agesa/family14 # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC +# device pci 1.1 on end # Internal Audio P2P bridge 0x1314 + device pci 4.0 off end device pci 5.0 off end # PCIE P2P bridge device pci 6.0 on end # PCIE P2P bridge PCIe slot device pci 7.0 off end # PCIE P2P bridge @@ -50,47 +52,64 @@ chip northbridge/amd/agesa/family14/root_complex device i2c 51 on end end end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy + chip superio/fintek/f71869ad +# XXX: 4e is the default index port and .xy is the +# LDN indexing the pnp_info array found in the superio.c +# NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, +# see page 18 from Fintek F71869 V1.1 datasheet. + device pnp 2e.00 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 + device pnp 2e.01 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.11 on # COM2 +# COM2 not physically wired on board. + device pnp 2e.02 off # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - end # f81865f + device pnp 2e.03 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.04 on # Hardware Monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 2e.05 on # KBC + io 0x60 = 0x060 + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + end + device pnp 2e.06 off end # GPIO +# TODO: Verify BSEL register content with vendor BIOS using +# $ sudo isadump 0x4e 0x4f 0x7 +# which select logical device (LDN) 7. Then read that we have in 0x27, bit1 + device pnp 2e.07 on end # BSEL + device pnp 2e.0a off end # PME + end # f71869ad end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB + device pci 14.5 on end # OHCI FS/LS USB (0x4399) device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA + device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 + device pci 16.0 on end # OHCI USB 10-13 (0x4397) + device pci 16.2 on end # EHCI USB 10-13 (0x4396) register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - #set up SB800 Fan control registers and IMC fan controls + # Set up SB800 Fan control registers and IMC fan controls + # TODO: verify SB handles the HW monitor and not the super io (PME) register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common register "fan0_enabled" = "1" register "fan1_enabled" = "1" @@ -150,6 +169,11 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.6 on end device pci 18.7 on end +# +# TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD +# with i2cdump tool. +# Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus. +# register "spdAddrLookup" = " { { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index f084b2f..ce08bee 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -211,6 +212,7 @@ */ #define GEC_CONFIG 0 +/* FIXME: Verify this for sound to work! */ static const CODECENTRY persimmon_codec_alc269[] = { /* NID, PinConfig */ @@ -228,6 +230,7 @@ static const CODECENTRY persimmon_codec_alc269[] = {0xff, 0xffffffff} /* end of table */ }; +/* FIXME: Verify this for sound to work! */ static const CODECTBLLIST codec_tablelist[] = { {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 98c64ed..f8271f7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,7 +32,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "superio/fintek/f71869ad/f71869ad.h" #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" @@ -45,7 +46,7 @@ void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, F71869AD_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -70,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); }

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Patch set updated for coreboot: 90a096b asrock/e350m1: Serialize ACPI IDE methods to avoid races.
by Edward O'Callaghan 03 Feb '14

03 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5080 -gerrit commit 90a096bc762613fa6a9adb4bb43b9cb87b3f044d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 29 22:12:52 2014 +1100 asrock/e350m1: Serialize ACPI IDE methods to avoid races. Fix the remark introduced in ACPICA version 20130517 pertaining to blocking threads within a methods. If another thread attempts to use the method to create the same (named) object twice a race condition will occur. ACPICA BZ 909. Change-Id: I4bb20c9a75d3d7c89f1dbeb526328eface0fdc0c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asrock/e350m1/acpi/ide.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asrock/e350m1/acpi/ide.asl b/src/mainboard/asrock/e350m1/acpi/ide.asl index b3aed9c..4071f85 100644 --- a/src/mainboard/asrock/e350m1/acpi/ide.asl +++ b/src/mainboard/asrock/e350m1/acpi/ide.asl @@ -77,7 +77,7 @@ Method(GTTM, 1) /* get total time*/ Device(PRID) { Name (_ADR, Zero) - Method(_GTM, 0) + Method(_GTM, 0, Serialized) { NAME(OTBF, Buffer(20) { /* out buffer */ 0xFF, 0xFF, 0xFF, 0xFF, @@ -122,7 +122,7 @@ Device(PRID) Return(OTBF) /* out buffer */ } /* End Method(_GTM) */ - Method(_STM, 3, NotSerialized) + Method(_STM, 3, Serialized) { NAME(INBF, Buffer(20) { /* in buffer */ 0xFF, 0xFF, 0xFF, 0xFF, @@ -173,7 +173,7 @@ Device(PRID) Device(MST) { Name(_ADR, 0) - Method(_GTF) { + Method(_GTF, 0, Serialized) { Name(CMBF, Buffer(21) { 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, @@ -209,7 +209,7 @@ Device(PRID) Device(SLAV) { Name(_ADR, 1) - Method(_GTF) { + Method(_GTF, 0, Serialized) { Name(CMBF, Buffer(21) { 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,

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Patch set updated for coreboot: e33e6a4 Added powernow support for two new (old) AMD K8 CPU's
by Oskar Enoksson 03 Feb '14

03 Feb '14

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5095 -gerrit commit e33e6a43dfc43828f72d48bc85cbe68387806808 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Sun Feb 2 12:23:52 2014 +0100 Added powernow support for two new (old) AMD K8 CPU's The added CPU's are OSA248CEP5AU and a OSP280 processors. The OSP280 VID/FID numbers have been found by experimentation and extrapolation/guesses from similar models. It has been verified to work fine under Linux (OpenSuse 12.2, kernel 3.4.63-2.44) with four different test-processors. Windows is untested. Change-Id: I3afa1cba5f55c8a78917b3636382af7706a80fee Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> --- src/cpu/amd/model_fxx/powernow_acpi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 02e0306..ab7497a 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -478,6 +478,10 @@ struct cpuentry entr[] = { {850, 0x14, 0x20f51, 0x10, 0x10, 853, {{2200, 1350, 853}, {2000, 1300, 827}, {1800, 1250, 702}, {1000, 1100, 301}}}, + /* OSA248CEP5AU */ + {248, 0x10, 0x00f5a, 0xe, 0xe, 890, + {{2000, 1400, 700}, {1800, 1300, 470}, + {1000, 1200, 280}}}, /* begin OSK246FAA5BL */ {246, 0x12, 0x20f51, 0xc, 0xc, 547, {{1800, 1350, 461}, {1000, 1100, 223}}}, @@ -561,6 +565,10 @@ struct cpuentry entr[] = { {180, 0x2c, 0x20f32, 0x10, 0x10, 1100, {{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}}, + /* OSP280 */ + {280, 0x31, 0x20f12, 0x10, 0x10, 680, + {{2200, 1250, 650}, {2000, 1200, 574}, + {1800, 1150, 433}, {1000, 1100, 220}}}, /* AMA3000BEX5AR */ {3000, 0x4, 0xf4a, 0xa, 0x0, 815, {{1600, 1400, 570}, {800, 1100, 190}}},

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Patch merged into coreboot/master: e8940ea lenovo/x230: Enable msata port.
by gerrit＠coreboot.org 03 Feb '14

03 Feb '14

the following patch was just integrated into master: commit e8940eace8c54dc85cbce394a69c108607d9e43d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Jan 24 14:38:10 2014 +0100 lenovo/x230: Enable msata port. Port 2 is used by msata. Enable it. Change-Id: Ib75227f64c9d77f6cfca1902a78d63b5cdd23d76 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4789 for details. -gerrit

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Patch set updated for coreboot: e8940ea lenovo/x230: Enable msata port.
by Vladimir Serbinenko 03 Feb '14

03 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4789 -gerrit commit e8940eace8c54dc85cbce394a69c108607d9e43d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Jan 24 14:38:10 2014 +0100 lenovo/x230: Enable msata port. Port 2 is used by msata. Enable it. Change-Id: Ib75227f64c9d77f6cfca1902a78d63b5cdd23d76 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index f630e3d..a76de5f 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -55,8 +55,8 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "2" register "gpi8_routing" = "2" - # Enable SATA ports 0 & 1 - register "sata_port_map" = "0x3" + # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) + register "sata_port_map" = "0x7" # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3"

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Patch set updated for coreboot: 6b0e733 lenovo/x201: Support digitizer on x201t variant
by Vladimir Serbinenko 03 Feb '14

03 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5096 -gerrit commit 6b0e73308748bd9cf67af2ab28c955d344fad517 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 1 18:39:26 2014 +0100 lenovo/x201: Support digitizer on x201t variant Since ACPI declaration of Wacom tablet when there is none causes hangs, split x201 port to x201 and x201t. Thanks to Peter Stuge for his helpful insights Thanks to Carl-Daniel Hailfinger for info on PnP superio. Thanks to Jens Erat for letting me to experiment with his X201t. Change-Id: Idb504fabf1ac1a55d8ada8d2b2268038110e32e0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/device/device_util.c | 21 +++++++++++++++++++++ src/ec/acpi/Makefile.inc | 1 + src/ec/lenovo/h8/acpi/ec.asl | 2 +- src/ec/lenovo/h8/acpi/thermal.asl | 4 ++-- src/include/device/device.h | 1 + src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/x201/Kconfig | 6 +++++- src/mainboard/lenovo/x201/acpi/superio.asl | 18 ++++++++++++++++++ src/mainboard/lenovo/x201/devicetree.cb | 14 ++++++++++++++ src/mainboard/lenovo/x201/mainboard.c | 12 ++++++++++-- src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/lenovo/x201t/Kconfig | 22 ++++++++++++++++++++++ 12 files changed, 102 insertions(+), 7 deletions(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 38654fa..8faa0c3 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -94,6 +94,27 @@ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr) } /** + * Given a PnP port and a device number, find the device structure. + * + * @param bus The bus number. + * @param addr A device number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +struct device *dev_find_slot_pnp(unsigned int port, unsigned int device) +{ + struct device *dev; + + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_PNP) && + (dev->path.pnp.port == port) && + (dev->path.pnp.device == device)) { + return dev; + } + } + return 0; +} + +/** * Given a Local APIC ID, find the device structure. * * @param apic_id The Local APIC ID number. diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index b39aaa2..3b5712b 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c +romstage-$(CONFIG_BOARD_LENOVO_X201T) += ec.c diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 4b3fb12..9e983f0 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -227,7 +227,7 @@ Device(EC) ^HKEY.RHK (0x18) } -#if CONFIG_BOARD_LENOVO_X201 +#if CONFIG_BOARD_LENOVO_X201 || CONFIG_BOARD_LENOVO_X201T Method (_Q1C, 0, NotSerialized) { ^HKEY.RHK (0x19) diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 83d66c6..cecf520 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -1,6 +1,6 @@ Scope(\_TZ) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) Name (MEBT, 0) #endif @@ -24,7 +24,7 @@ Scope(\_TZ) Return (C2K(127)) } Method(_TMP) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED (CONFIG_BOARD_LENOVO_X201T) /* Avoid tripping alarm if ME isn't booted at all yet */ If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { Return (C2K(40)) diff --git a/src/include/device/device.h b/src/include/device/device.h index c1a2c3d..3801409 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -169,6 +169,7 @@ device_t dev_find_device (u16 vendor, u16 device, device_t from); device_t dev_find_class (unsigned int class, device_t from); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); +device_t dev_find_slot_pnp(unsigned int port, unsigned int device); device_t dev_find_lapic(unsigned apic_id); int dev_count_cpu(void); diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..27ffd66 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -17,6 +17,11 @@ config BOARD_LENOVO_X201 help Lenovo X201 laptop. Consult wiki for details. +config BOARD_LENOVO_X201T + bool "ThinkPad X201 Tablet" + help + Lenovo X201 convertible tablet. Consult wiki for details. + config BOARD_LENOVO_X230 bool "ThinkPad X230" help @@ -34,6 +39,7 @@ endchoice source "src/mainboard/lenovo/x60/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" +source "src/mainboard/lenovo/x201t/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 8e7ebae..344aa40 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X201 +if BOARD_LENOVO_X201 || BOARD_LENOVO_X201T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -23,6 +23,8 @@ config MAINBOARD_DIR string default lenovo/x201 +if BOARD_LENOVO_X201 + config MAINBOARD_PART_NUMBER string default "3626EN1" @@ -31,6 +33,8 @@ config MAINBOARD_VERSION string default "ThinkPad X201" +endif + config MAINBOARD_VENDOR string default "LENOVO" diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl index a2657f1..19bb4c5 100644 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ b/src/mainboard/lenovo/x201/acpi/superio.asl @@ -1 +1,19 @@ #include "../../../../drivers/pc80/ps2_controller.asl" + +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + Device (DTR) // Digitizer + { + Name(_HID, EISAID("WACF004")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x200, 0x200, 0x01, 0x08) + IRQNoFlags () {5} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } +#endif diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 37a430c..0b978de 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -139,6 +139,20 @@ chip northbridge/intel/nehalem end device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + # IR, not connected + device pnp 164e.2 off end + # GPIO, not connected + device pnp 164e.7 off end + # DLPC, not connected + device pnp 164e.19 off end + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index c16c3a4..775583a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -90,7 +90,11 @@ static int int15_handler(void) const char *smbios_mainboard_version(void) { - return "Lenovo X201"; +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + return "ThinkPad X201 Tablet"; +#else + return "ThinkPad X201"; +#endif } /* Audio Setup */ @@ -106,7 +110,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { - device_t dev0; + device_t dev0, devwacom; u16 pmbase; printk(BIOS_SPEW, "starting SPI configuration\n"); @@ -153,6 +157,10 @@ static void mainboard_enable(device_t dev) if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) ec_write(0x0c, 0xc7); + devwacom = dev_find_slot_pnp (0x164e, 3); + if (devwacom) + devwacom->enabled = IS_ENABLED(CONFIG_BOARD_LENOVO_X201T); + #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index e3e0a62..5ed48a9 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + COMA_LPC_EN | GAMEL_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); diff --git a/src/mainboard/lenovo/x201t/Kconfig b/src/mainboard/lenovo/x201t/Kconfig new file mode 100644 index 0000000..45e30a2 --- /dev/null +++ b/src/mainboard/lenovo/x201t/Kconfig @@ -0,0 +1,22 @@ +if BOARD_LENOVO_X201T + +config TABLET_SPECIFIC_OPTIONS # dummy + def_bool y + select SUPERIO_NSC_PC87382 + # Following ones are for scripts benefit + select ARCH_X86 + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select DRIVERS_ICS_954309 + +config MAINBOARD_PART_NUMBER + string + default "0831CTO" + +config MAINBOARD_VERSION + string + default "ThinkPad X201 Tablet" + +endif

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Patch set updated for coreboot: e04eca4 lenovo/x201: Support digitizer on x201t variant
by Vladimir Serbinenko 03 Feb '14

03 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5096 -gerrit commit e04eca4d50ff3b4e9ffa5a5bc27839d76e956bf7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 1 18:39:26 2014 +0100 lenovo/x201: Support digitizer on x201t variant Since ACPI declaration of Wacom tablet when there is none causes hangs, split x201 port to x201 and x201t. Thanks to Peter Stuge for his helpful insights Thanks to Carl-Daniel Hailfinger for info on PnP superio. Thanks to Jens Erat for letting me to experiment with his X201t. Change-Id: Idb504fabf1ac1a55d8ada8d2b2268038110e32e0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/device/device_util.c | 21 +++++++++++++++++++++ src/ec/acpi/Makefile.inc | 1 + src/ec/lenovo/h8/acpi/ec.asl | 2 +- src/ec/lenovo/h8/acpi/thermal.asl | 4 ++-- src/include/device/device.h | 1 + src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/x201/Kconfig | 7 ++++++- src/mainboard/lenovo/x201/acpi/superio.asl | 18 ++++++++++++++++++ src/mainboard/lenovo/x201/devicetree.cb | 14 ++++++++++++++ src/mainboard/lenovo/x201/mainboard.c | 12 ++++++++++-- src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/lenovo/x201t/Kconfig | 22 ++++++++++++++++++++++ 12 files changed, 103 insertions(+), 7 deletions(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 38654fa..8faa0c3 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -94,6 +94,27 @@ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr) } /** + * Given a PnP port and a device number, find the device structure. + * + * @param bus The bus number. + * @param addr A device number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +struct device *dev_find_slot_pnp(unsigned int port, unsigned int device) +{ + struct device *dev; + + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_PNP) && + (dev->path.pnp.port == port) && + (dev->path.pnp.device == device)) { + return dev; + } + } + return 0; +} + +/** * Given a Local APIC ID, find the device structure. * * @param apic_id The Local APIC ID number. diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index b39aaa2..3b5712b 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c +romstage-$(CONFIG_BOARD_LENOVO_X201T) += ec.c diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 4b3fb12..9e983f0 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -227,7 +227,7 @@ Device(EC) ^HKEY.RHK (0x18) } -#if CONFIG_BOARD_LENOVO_X201 +#if CONFIG_BOARD_LENOVO_X201 || CONFIG_BOARD_LENOVO_X201T Method (_Q1C, 0, NotSerialized) { ^HKEY.RHK (0x19) diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 83d66c6..cecf520 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -1,6 +1,6 @@ Scope(\_TZ) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) Name (MEBT, 0) #endif @@ -24,7 +24,7 @@ Scope(\_TZ) Return (C2K(127)) } Method(_TMP) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED (CONFIG_BOARD_LENOVO_X201T) /* Avoid tripping alarm if ME isn't booted at all yet */ If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { Return (C2K(40)) diff --git a/src/include/device/device.h b/src/include/device/device.h index c1a2c3d..3801409 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -169,6 +169,7 @@ device_t dev_find_device (u16 vendor, u16 device, device_t from); device_t dev_find_class (unsigned int class, device_t from); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); +device_t dev_find_slot_pnp(unsigned int port, unsigned int device); device_t dev_find_lapic(unsigned apic_id); int dev_count_cpu(void); diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..27ffd66 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -17,6 +17,11 @@ config BOARD_LENOVO_X201 help Lenovo X201 laptop. Consult wiki for details. +config BOARD_LENOVO_X201T + bool "ThinkPad X201 Tablet" + help + Lenovo X201 convertible tablet. Consult wiki for details. + config BOARD_LENOVO_X230 bool "ThinkPad X230" help @@ -34,6 +39,7 @@ endchoice source "src/mainboard/lenovo/x60/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" +source "src/mainboard/lenovo/x201t/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 8e7ebae..1ad1ffa 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -1,10 +1,11 @@ -if BOARD_LENOVO_X201 +if BOARD_LENOVO_X201 || BOARD_LENOVO_X201T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select NORTHBRIDGE_INTEL_NEHALEM select SOUTHBRIDGE_INTEL_IBEXPEAK + select SUPERIO_NSC_PC87382 select EC_LENOVO_PMH7 select EC_LENOVO_H8 select DRIVERS_ICS_954309 @@ -23,6 +24,8 @@ config MAINBOARD_DIR string default lenovo/x201 +if BOARD_LENOVO_X201 + config MAINBOARD_PART_NUMBER string default "3626EN1" @@ -31,6 +34,8 @@ config MAINBOARD_VERSION string default "ThinkPad X201" +endif + config MAINBOARD_VENDOR string default "LENOVO" diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl index a2657f1..19bb4c5 100644 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ b/src/mainboard/lenovo/x201/acpi/superio.asl @@ -1 +1,19 @@ #include "../../../../drivers/pc80/ps2_controller.asl" + +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + Device (DTR) // Digitizer + { + Name(_HID, EISAID("WACF004")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x200, 0x200, 0x01, 0x08) + IRQNoFlags () {5} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } +#endif diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 37a430c..0b978de 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -139,6 +139,20 @@ chip northbridge/intel/nehalem end device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + # IR, not connected + device pnp 164e.2 off end + # GPIO, not connected + device pnp 164e.7 off end + # DLPC, not connected + device pnp 164e.19 off end + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index c16c3a4..775583a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -90,7 +90,11 @@ static int int15_handler(void) const char *smbios_mainboard_version(void) { - return "Lenovo X201"; +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + return "ThinkPad X201 Tablet"; +#else + return "ThinkPad X201"; +#endif } /* Audio Setup */ @@ -106,7 +110,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { - device_t dev0; + device_t dev0, devwacom; u16 pmbase; printk(BIOS_SPEW, "starting SPI configuration\n"); @@ -153,6 +157,10 @@ static void mainboard_enable(device_t dev) if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) ec_write(0x0c, 0xc7); + devwacom = dev_find_slot_pnp (0x164e, 3); + if (devwacom) + devwacom->enabled = IS_ENABLED(CONFIG_BOARD_LENOVO_X201T); + #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index e3e0a62..5ed48a9 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + COMA_LPC_EN | GAMEL_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); diff --git a/src/mainboard/lenovo/x201t/Kconfig b/src/mainboard/lenovo/x201t/Kconfig new file mode 100644 index 0000000..45e30a2 --- /dev/null +++ b/src/mainboard/lenovo/x201t/Kconfig @@ -0,0 +1,22 @@ +if BOARD_LENOVO_X201T + +config TABLET_SPECIFIC_OPTIONS # dummy + def_bool y + select SUPERIO_NSC_PC87382 + # Following ones are for scripts benefit + select ARCH_X86 + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select DRIVERS_ICS_954309 + +config MAINBOARD_PART_NUMBER + string + default "0831CTO" + +config MAINBOARD_VERSION + string + default "ThinkPad X201 Tablet" + +endif

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Patch set updated for coreboot: 7a96bcd lenovo/x201: Support digitizer on x201t variant
by Vladimir Serbinenko 03 Feb '14

03 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5096 -gerrit commit 7a96bcdd9acb5920af0dd06481d7e1650ae1f4b8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 1 18:39:26 2014 +0100 lenovo/x201: Support digitizer on x201t variant Since ACPI declaration of Wacom tablet when there is none causes hangs, split x201 port to x201 and x201t. Thanks to Peter Stuge for his helpful insights Thanks to Carl-Daniel Hailfinger for info on PnP superio. Thanks to Jens Erat for letting me to experiment with his X201t. Change-Id: Idb504fabf1ac1a55d8ada8d2b2268038110e32e0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/device/device_util.c | 21 +++++++++++++++++++++ src/ec/acpi/Makefile.inc | 1 + src/ec/lenovo/h8/acpi/ec.asl | 2 +- src/ec/lenovo/h8/acpi/thermal.asl | 4 ++-- src/include/device/device.h | 1 + src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/x201/Kconfig | 7 ++++++- src/mainboard/lenovo/x201/acpi/superio.asl | 18 ++++++++++++++++++ src/mainboard/lenovo/x201/devicetree.cb | 8 ++++++++ src/mainboard/lenovo/x201/mainboard.c | 12 ++++++++++-- src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/lenovo/x201t/Kconfig | 22 ++++++++++++++++++++++ 12 files changed, 97 insertions(+), 7 deletions(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 38654fa..8faa0c3 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -94,6 +94,27 @@ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr) } /** + * Given a PnP port and a device number, find the device structure. + * + * @param bus The bus number. + * @param addr A device number. + * @return Pointer to the device structure (if found), 0 otherwise. + */ +struct device *dev_find_slot_pnp(unsigned int port, unsigned int device) +{ + struct device *dev; + + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type == DEVICE_PATH_PNP) && + (dev->path.pnp.port == port) && + (dev->path.pnp.device == device)) { + return dev; + } + } + return 0; +} + +/** * Given a Local APIC ID, find the device structure. * * @param apic_id The Local APIC ID number. diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index b39aaa2..3b5712b 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c +romstage-$(CONFIG_BOARD_LENOVO_X201T) += ec.c diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 4b3fb12..9e983f0 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -227,7 +227,7 @@ Device(EC) ^HKEY.RHK (0x18) } -#if CONFIG_BOARD_LENOVO_X201 +#if CONFIG_BOARD_LENOVO_X201 || CONFIG_BOARD_LENOVO_X201T Method (_Q1C, 0, NotSerialized) { ^HKEY.RHK (0x19) diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 83d66c6..cecf520 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -1,6 +1,6 @@ Scope(\_TZ) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) Name (MEBT, 0) #endif @@ -24,7 +24,7 @@ Scope(\_TZ) Return (C2K(127)) } Method(_TMP) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED (CONFIG_BOARD_LENOVO_X201T) /* Avoid tripping alarm if ME isn't booted at all yet */ If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { Return (C2K(40)) diff --git a/src/include/device/device.h b/src/include/device/device.h index c1a2c3d..3801409 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -169,6 +169,7 @@ device_t dev_find_device (u16 vendor, u16 device, device_t from); device_t dev_find_class (unsigned int class, device_t from); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); +device_t dev_find_slot_pnp(unsigned int port, unsigned int device); device_t dev_find_lapic(unsigned apic_id); int dev_count_cpu(void); diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..27ffd66 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -17,6 +17,11 @@ config BOARD_LENOVO_X201 help Lenovo X201 laptop. Consult wiki for details. +config BOARD_LENOVO_X201T + bool "ThinkPad X201 Tablet" + help + Lenovo X201 convertible tablet. Consult wiki for details. + config BOARD_LENOVO_X230 bool "ThinkPad X230" help @@ -34,6 +39,7 @@ endchoice source "src/mainboard/lenovo/x60/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" +source "src/mainboard/lenovo/x201t/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 8e7ebae..1ad1ffa 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -1,10 +1,11 @@ -if BOARD_LENOVO_X201 +if BOARD_LENOVO_X201 || BOARD_LENOVO_X201T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select NORTHBRIDGE_INTEL_NEHALEM select SOUTHBRIDGE_INTEL_IBEXPEAK + select SUPERIO_NSC_PC87382 select EC_LENOVO_PMH7 select EC_LENOVO_H8 select DRIVERS_ICS_954309 @@ -23,6 +24,8 @@ config MAINBOARD_DIR string default lenovo/x201 +if BOARD_LENOVO_X201 + config MAINBOARD_PART_NUMBER string default "3626EN1" @@ -31,6 +34,8 @@ config MAINBOARD_VERSION string default "ThinkPad X201" +endif + config MAINBOARD_VENDOR string default "LENOVO" diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl index a2657f1..19bb4c5 100644 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ b/src/mainboard/lenovo/x201/acpi/superio.asl @@ -1 +1,19 @@ #include "../../../../drivers/pc80/ps2_controller.asl" + +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + Device (DTR) // Digitizer + { + Name(_HID, EISAID("WACF004")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x200, 0x200, 0x01, 0x08) + IRQNoFlags () {5} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } +#endif diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 37a430c..6632f40 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -139,6 +139,14 @@ chip northbridge/intel/nehalem end device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index c16c3a4..775583a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -90,7 +90,11 @@ static int int15_handler(void) const char *smbios_mainboard_version(void) { - return "Lenovo X201"; +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + return "ThinkPad X201 Tablet"; +#else + return "ThinkPad X201"; +#endif } /* Audio Setup */ @@ -106,7 +110,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { - device_t dev0; + device_t dev0, devwacom; u16 pmbase; printk(BIOS_SPEW, "starting SPI configuration\n"); @@ -153,6 +157,10 @@ static void mainboard_enable(device_t dev) if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) ec_write(0x0c, 0xc7); + devwacom = dev_find_slot_pnp (0x164e, 3); + if (devwacom) + devwacom->enabled = IS_ENABLED(CONFIG_BOARD_LENOVO_X201T); + #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index e3e0a62..5ed48a9 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + COMA_LPC_EN | GAMEL_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); diff --git a/src/mainboard/lenovo/x201t/Kconfig b/src/mainboard/lenovo/x201t/Kconfig new file mode 100644 index 0000000..45e30a2 --- /dev/null +++ b/src/mainboard/lenovo/x201t/Kconfig @@ -0,0 +1,22 @@ +if BOARD_LENOVO_X201T + +config TABLET_SPECIFIC_OPTIONS # dummy + def_bool y + select SUPERIO_NSC_PC87382 + # Following ones are for scripts benefit + select ARCH_X86 + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select DRIVERS_ICS_954309 + +config MAINBOARD_PART_NUMBER + string + default "0831CTO" + +config MAINBOARD_VERSION + string + default "ThinkPad X201 Tablet" + +endif

1 0

Patch merged into coreboot/master: e757220 cbfstool: add code to serialize the header using the new xdr functions
by gerrit＠coreboot.org 02 Feb '14

02 Feb '14

the following patch was just integrated into master: commit e757220cfcb335a200d41cae990a4295e410ab0b Author: Ronald G. Minnich <rminnich(a)google.com> Date: Mon Jan 6 08:38:15 2014 -0800 cbfstool: add code to serialize the header using the new xdr functions This change adds a header serialization function. Programmers can thus just set up a header as needed, without worrying about forgetting if and how to use the [hn]to[hn]* functions. In the long term, we will work to remove swab.h, i.e. we need to get to the point where programmers don't have to try to remember [hn]to[nh]* and where it goes. To date, even the best programmers we have have made an error with those functions, and those errors have persisted for 6 or 7 years now. It's very easy to make that mistake. BUG=None TEST=Build a peppy image and verify that it's bit for bit the same. All chromebooks use this code and build and boot correctly. BRANCH=None Change-Id: I0f9b8e7cac5f52d0ea330ba948650fa0803aa0d5 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/181552 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Commit-Queue: Ronald Minnich <rminnich(a)chromium.org> Tested-by: Ronald Minnich <rminnich(a)chromium.org> See http://review.coreboot.org/5100 for details. -gerrit

1 0

New patch to review for coreboot: 8658df4 AMD K8 boards’ `romstage.c`: Spell sync*hr*onize correctly
by Paul Menzel 02 Feb '14

02 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5101 -gerrit commit 8658df41411e3f054bbe9f1efbf521eb974b4696 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 2 22:05:48 2014 +0100 AMD K8 boards’ `romstage.c`: Spell sync*hr*onize correctly $ git grep -l synconize | xargs sed -i 's/synconize/synchronize/g' Change-Id: I92e6e7f1292f66642aa0336064a4eccba104dd08 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/serengeti_cheetah/romstage.c | 2 +- src/mainboard/asus/m2n-e/romstage.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 +- src/mainboard/gigabyte/m57sli/romstage.c | 2 +- src/mainboard/hp/dl145_g3/romstage.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/iwill/dk8_htx/romstage.c | 2 +- src/mainboard/iwill/dk8s2/romstage.c | 2 +- src/mainboard/iwill/dk8x/romstage.c | 2 +- src/mainboard/msi/ms7260/romstage.c | 2 +- src/mainboard/msi/ms9185/romstage.c | 2 +- src/mainboard/msi/ms9282/romstage.c | 2 +- src/mainboard/msi/ms9652_fam10/romstage.c | 2 +- src/mainboard/nvidia/l1_2pvv/romstage.c | 2 +- src/mainboard/supermicro/h8dme/romstage.c | 2 +- src/mainboard/supermicro/h8dmr/romstage.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +- src/mainboard/tyan/s2912/romstage.c | 2 +- src/mainboard/tyan/s2912_fam10/romstage.c | 2 +- 20 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index b103389..98793af 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -219,7 +219,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID +// init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 2f3baf6..b6b79cc 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* TODO: FIDVID */ - init_timer(); /* Need to use TMICT to synconize FID/VID. */ + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 4d215ae..9fc932e 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -193,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID +// init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 77eae09..e551e84 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - init_timer(); // Need to use TMICT to synconize FID/VID + init_timer(); // Need to use TMICT to synchronize FID/VID needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 0d8e9d2..61408ff 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -206,7 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ - // init_timer(); // Need to use TMICT to synconize FID/VID + // init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 8e109c5..5fb5602 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID +// init_timer(); // Need to use TMICT to synchronize FID/VID printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 070fb07..3db0d96 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ - init_timer(); // Need to use TMICT to synconize FID/VID + init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 7c8d4a5..6cfed96 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ - init_timer(); // Need to use TMICT to synconize FID/VID + init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index b5a1d71..ee7cd10 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ - init_timer(); // Need to use TMICT to synconize FID/VID + init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 947de0b..206ded3 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - init_timer(); /* Need to use TMICT to synconize FID/VID. */ + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 2cb38a4..16e714e 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -211,7 +211,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID +// init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 7f8d0e7..f6bd838 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - init_timer(); /* Need to use TMICT to synconize FID/VID. */ + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index b21fb02..2a38fb3 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -202,7 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif - init_timer(); /* Need to use TMICT to synconize FID/VID. */ + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ wants_reset = mcp55_early_setup_x(); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index d6ee6c6..75448e6 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - init_timer(); /* Need to use TMICT to synconize FID/VID. */ + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index df5e2c8..ae1d35d 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - init_timer(); /* Need to use TMICT to synconize FID/VID. */ + init_timer(); /* Need to use TMICT to synchronize FID/VID. */ needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 8ed7e6d..ff17b97 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -162,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - init_timer(); // Need to use TMICT to synconize FID/VID + init_timer(); // Need to use TMICT to synchronize FID/VID needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 3f6ea70..328e1f5 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -199,7 +199,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) msr.hi, msr.lo); #endif - init_timer(); // Need to use TMICT to synconize FID/VID + init_timer(); // Need to use TMICT to synchronize FID/VID wants_reset = mcp55_early_setup_x(); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index cca464c..f3a6a23 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif - init_timer(); // Need to use TMICT to synconize FID/VID + init_timer(); // Need to use TMICT to synchronize FID/VID wants_reset = mcp55_early_setup_x(); diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index e4a1c65..9e2edb6 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - init_timer(); // Need to use TMICT to synconize FID/VID + init_timer(); // Need to use TMICT to synchronize FID/VID needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 9c86157..821ed1e 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -199,7 +199,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif - init_timer(); // Need to use TMICT to synconize FID/VID + init_timer(); // Need to use TMICT to synchronize FID/VID wants_reset = mcp55_early_setup_x();

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coreboot-gerrit February 2014