coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 5d88cd3 asrock/e350m1: Serialize ACPI IDE methods to avoid races.
by Edward O'Callaghan 02 Feb '14

02 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5080 -gerrit commit 5d88cd31608c1be4b7361164ce15ba1f5565bf84 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 29 22:12:52 2014 +1100 asrock/e350m1: Serialize ACPI IDE methods to avoid races. Fix the remark introduced in ACPICA version 20130517 pertaining to blocking threads within a methods. If another thread attempts to use the method to create the same (named) object twice a race condition will occur. ACPICA BZ 909. Change-Id: I4bb20c9a75d3d7c89f1dbeb526328eface0fdc0c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asrock/e350m1/acpi/ide.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asrock/e350m1/acpi/ide.asl b/src/mainboard/asrock/e350m1/acpi/ide.asl index b3aed9c..4071f85 100644 --- a/src/mainboard/asrock/e350m1/acpi/ide.asl +++ b/src/mainboard/asrock/e350m1/acpi/ide.asl @@ -77,7 +77,7 @@ Method(GTTM, 1) /* get total time*/ Device(PRID) { Name (_ADR, Zero) - Method(_GTM, 0) + Method(_GTM, 0, Serialized) { NAME(OTBF, Buffer(20) { /* out buffer */ 0xFF, 0xFF, 0xFF, 0xFF, @@ -122,7 +122,7 @@ Device(PRID) Return(OTBF) /* out buffer */ } /* End Method(_GTM) */ - Method(_STM, 3, NotSerialized) + Method(_STM, 3, Serialized) { NAME(INBF, Buffer(20) { /* in buffer */ 0xFF, 0xFF, 0xFF, 0xFF, @@ -173,7 +173,7 @@ Device(PRID) Device(MST) { Name(_ADR, 0) - Method(_GTF) { + Method(_GTF, 0, Serialized) { Name(CMBF, Buffer(21) { 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, @@ -209,7 +209,7 @@ Device(PRID) Device(SLAV) { Name(_ADR, 1) - Method(_GTF) { + Method(_GTF, 0, Serialized) { Name(CMBF, Buffer(21) { 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,

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Patch merged into coreboot/master: b108141 AGESA f15tn: Fix GPP ports resume
by gerrit＠coreboot.org 01 Feb '14

01 Feb '14

the following patch was just integrated into master: commit b108141c09961aa35ccb2a266856a20bb583a447 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Jan 12 00:23:30 2014 +0100 AGESA f15tn: Fix GPP ports resume The AGESA resumes the GPP ports in the romstage using FchInitResetGpp(), which does FchGppPortInitS3Phase() for S3 resume. The PreInitGppLink() looks into CMOS to figure out what ports to just force to Gen1 or Gen2 PCIe. Then boot continues and in the ramstage the rest of GPP init is executed. There is a problem that nobody sets properly the PortDetected flags in the S3 path. As the consequence FchGppDynamicPowerSaving() thinks the GPP port is not enabled and shut downs it. The best fix would be also to remove the CMOS dependency which might be some left over, because AGESA does not use CMOS much for anything else. There could be also some way how to pass the GPP state structure from romstage to ramstage possibly via hudson/resume.c but I don't know how to do that. Similar problem is that the "late" stage of init again "forgets" the PortDetected state. This fix fixes the resume issue on Asus F2A85-M. With this patch applied both GPP ports (used as PCIe x1 and internal ethernet) are working again after resume. Change-Id: Idaf609043abb09441c6790504d66d23e0637588f Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> See http://review.coreboot.org/4671 for details. -gerrit

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Patch set updated for coreboot: 4deb1ef amd/agesa/hudson: Implement PNP resource setup in LPC bridge
by Rudolf Marek 01 Feb '14

01 Feb '14

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4497 -gerrit commit 4deb1ef15c47bb30ad995cf232dd356bf67fc7f7 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat Dec 7 22:29:36 2013 +0100 amd/agesa/hudson: Implement PNP resource setup in LPC bridge The previous SBxxx generations were setting up LPC bridge based on the PNP resources. Implement it also for AGESA Hudson. The AGESA itself opens one big region DFLT_SIO_PME_BASE_ADDRESS (512 bytes). Make the code smart enough to detect already used region and if any resource fits into AGESA defined region, do nothing. Change-Id: I718d034bc4c778697a7bd0506d4550c8f5a43159 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/southbridge/amd/agesa/hudson/lpc.c | 174 ++++++++++++++++++++++++++++++++- 1 file changed, 173 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 3af3eb8..a0dc072 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -129,8 +129,180 @@ static void hudson_lpc_set_resources(struct device *dev) */ static void hudson_lpc_enable_childrens_resources(device_t dev) { - printk(BIOS_DEBUG, "hudson_lpc_enable_childrens_resources\n"); + struct bus *link; + u32 reg, reg_x; + int var_num = 0; + u16 reg_var[3]; + u16 reg_size[1] = {512}; + u8 wiosize = pci_read_config8(dev, 0x74); + /* Be bit relaxed, tolerate that LPC region might be bigger than resource we try to fit, + * do it like this for all regions < 16 bytes. If there is a resource > 16 bytes + * it must be 512 bytes to be able to allocate the fresh LPC window. + * + * AGESA likes to enable already one LPC region in wide port base 0x64-0x65, + * using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size + * The code tries to check if resource can fit into this region + */ + + reg = pci_read_config32(dev, 0x44); + reg_x = pci_read_config32(dev, 0x48); + + /* check if ranges are free and not use them if entry is just already taken */ + if (reg_x & (1 << 2)) + var_num = 1; + /* just in case check if someone did not manually set other ranges too */ + if (reg_x & (1 << 24)) + var_num = 2; + + if (reg_x & (1 << 25)) + var_num = 3; + + /* check AGESA region size */ + if (wiosize & (1 << 0)) + reg_size[0] = 16; + + reg_var[2] = pci_read_config16(dev, 0x90); + reg_var[1] = pci_read_config16(dev, 0x66); + reg_var[0] = pci_read_config16(dev, 0x64); + + for (link = dev->link_list; link; link = link->next) { + device_t child; + for (child = link->children; child; + child = child->sibling) { + if (child->enabled + && (child->path.type == DEVICE_PATH_PNP)) { + struct resource *res; + for (res = child->resource_list; res; res = res->next) { + u32 base, end; /* don't need long long */ + u32 rsize, set = 0, set_x = 0; + if (!(res->flags & IORESOURCE_IO)) + continue; + base = res->base; + end = resource_end(res); + /* find a resource size */ + printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); + switch (base) { + case 0x60: /* KB */ + case 0x64: /* MS */ + set |= (1 << 29); + rsize = 1; + break; + case 0x3f8: /* COM1 */ + set |= (1 << 6); + rsize = 8; + break; + case 0x2f8: /* COM2 */ + set |= (1 << 7); + rsize = 8; + break; + case 0x378: /* Parallel 1 */ + set |= (1 << 0); + set |= (1 << 1); /* + 0x778 for ECP */ + rsize = 8; + break; + case 0x3f0: /* FD0 */ + set |= (1 << 26); + rsize = 8; + break; + case 0x220: /* 0x220 - 0x227 */ + set |= (1 << 8); + rsize = 8; + break; + case 0x228: /* 0x228 - 0x22f */ + set |= (1 << 9); + rsize = 8; + break; + case 0x238: /* 0x238 - 0x23f */ + set |= (1 << 10); + rsize = 8; + break; + case 0x300: /* 0x300 -0x301 */ + set |= (1 << 18); + rsize = 2; + break; + case 0x400: + set_x |= (1 << 16); + rsize = 0x40; + break; + case 0x480: + set_x |= (1 << 17); + rsize = 0x40; + case 0x500: + set_x |= (1 << 18); + rsize = 0x40; + break; + case 0x580: + set_x |= (1 << 19); + rsize = 0x40; + break; + case 0x4700: + set_x |= (1 << 22); + rsize = 0xc; + break; + case 0xfd60: + set_x |= (1 << 23); + rsize = 16; + break; + default: + rsize = 0; + /* try AGESA allocated region in region 0 */ + if ((var_num > 0) && ((base >=reg_var[0]) && + ((base + res->size) <= (reg_var[0] + reg_size[0])))) + rsize = reg_size[0]; + } + /* check if region found and matches the enable */ + if (res->size <= rsize) { + reg |= set; + reg_x |= set_x; + /* check if we can fit resource in variable range */ + } else if ((var_num < 3) && + ((res->size <= 16) || (res->size == 512))) { + /* use variable ranges if pre-defined do not match */ + switch (var_num) { + case 0: + reg_x |= (1 << 2); + if (res->size <= 16) { + wiosize |= (1 << 0); + } + break; + case 1: + reg_x |= (1 << 24); + if (res->size <= 16) + wiosize |= (1 << 2); + break; + case 2: + reg_x |= (1 << 25); + if (res->size <= 16) + wiosize |= (1 << 3); + break; + } + reg_var[var_num++] = + base & 0xffff; + } else { + printk(BIOS_ERR, "cannot fit LPC decode region:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); + } + } + } + } + } + pci_write_config32(dev, 0x44, reg); + pci_write_config32(dev, 0x48, reg_x); + /* Set WideIO for as many IOs found (fall through is on purpose) */ + switch (var_num) { + case 3: + pci_write_config16(dev, 0x90, reg_var[2]); + /* fall through */ + case 2: + pci_write_config16(dev, 0x66, reg_var[1]); + /* fall through */ + case 1: + pci_write_config16(dev, 0x64, reg_var[0]); + break; + } + pci_write_config8(dev, 0x74, wiosize); } static void hudson_lpc_enable_resources(device_t dev)

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Patch merged into coreboot/master: 86e14ef lenovo/x201: Skip AT24RF08 detection.
by gerrit＠coreboot.org 01 Feb '14

01 Feb '14

the following patch was just integrated into master: commit 86e14efcb193f3b167650c57da52b667261bca20 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jan 21 09:45:15 2014 +0100 lenovo/x201: Skip AT24RF08 detection. AT24RF08 was inherited from RE of original BIOS. As we don't really care if the chip in question is really AT24RF08 or a generic replacement, we can skip this check. Change-Id: I862dd66b2332314beb835f215f1c1cd838aa07b9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4769 for details. -gerrit

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Patch merged into coreboot/master: f53f0b8 pcengines/alix6: Make clone declaration in line with other clones.
by gerrit＠coreboot.org 01 Feb '14

01 Feb '14

the following patch was just integrated into master: commit f53f0b8479d4749eaa99f2816f0271009133bc46 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Jan 20 03:03:38 2014 +0100 pcengines/alix6: Make clone declaration in line with other clones. Change-Id: I4e56f6b37314bff569728b732b4115fb940f70dd Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4756 for details. -gerrit

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Patch merged into coreboot/master: b4bd65d AMD hudson and yangtze: add IMC fan control support
by gerrit＠coreboot.org 01 Feb '14

01 Feb '14

the following patch was just integrated into master: commit b4bd65daac691408b7298d7d6ea9e6ed0f3f8251 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Mon Dec 2 10:18:04 2013 +0800 AMD hudson and yangtze: add IMC fan control support imc_reg_init: init fan control related registers. enable_imc_thermal_zone: AGESA does not enable thermal zone. We enable it here. Change-Id: I93c729982d78b6d2c7c20bcb1a3e27a7dd0eba91 Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> See http://review.coreboot.org/4300 for details. -gerrit

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Patch merged into coreboot/master: f81b853 lenovo: Handle EEPROM/RFID chip.
by gerrit＠coreboot.org 01 Feb '14

01 Feb '14

the following patch was just integrated into master: commit f81b8536fbf817c582cbcc128f219f3daa80691c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 23 09:06:08 2014 +0100 lenovo: Handle EEPROM/RFID chip. EEPROM/RFID chip present in thinkpad should be locked in a way to avoid any potential RFID access. Read serial number, UUID and P/N from EEPROM. This info is stored on AT24RF08 chip acessible through SMBUS. Change-Id: Ia3e766d90a094f63c8c854cd37e165221ccd8acd Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4774 for details. -gerrit

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Patch merged into coreboot/master: 96bf3ed ibexpeak: add smbus_write_byte
by gerrit＠coreboot.org 01 Feb '14

01 Feb '14

the following patch was just integrated into master: commit 96bf3edabeed1555ce13178d8c0a81841e448fdc Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Jan 27 23:57:44 2014 +0100 ibexpeak: add smbus_write_byte Change-Id: I045f1cff794d3c965c502fff98dd2442af2143bd Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4839 for details. -gerrit

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Patch merged into coreboot/master: 4491687 bd82x6x: Add smbus_write_byte
by gerrit＠coreboot.org 01 Feb '14

01 Feb '14

the following patch was just integrated into master: commit 4491687c549eb27358d63ea1907160ea4c7f6f73 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Jan 27 23:48:27 2014 +0100 bd82x6x: Add smbus_write_byte Change-Id: Iaab076cc014a1ee463866c243636f4f71798ddc4 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4838 for details. -gerrit

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Patch merged into coreboot/master: be96510 smbus: Add guards to avoid calling NULL.
by gerrit＠coreboot.org 01 Feb '14

01 Feb '14

the following patch was just integrated into master: commit be9651002c3473df0f3950b24636743beb5e48f1 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Jan 27 23:46:46 2014 +0100 smbus: Add guards to avoid calling NULL. Many of SMBus functions are unavailable on many controllers. While calling unavailable function is bad, it shouldn't lead to spectacular crash. Change-Id: I7912f3bbbb438603893223a586dcedf57e8a7e28 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4837 for details. -gerrit

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coreboot-gerrit February 2014