February 2014 - coreboot-gerrit

Patch set updated for coreboot: 48a9113 cpu/allwinner/a10: Add minimal ramstage driver
by Alexandru Gagniuc Feb. 3, 2014

Feb. 3, 2014

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4698 -gerrit commit 48a91131e6b4a2297f4b31db3043fed0a4ab89a4 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 3 04:24:35 2014 -0500 cpu/allwinner/a10: Add minimal ramstage driver Change-Id: I857755976b17b0e492c086162f395a77933eeed8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 3 +++ src/cpu/allwinner/a10/cbmem.c | 26 +++++++++++++++++++++ src/cpu/allwinner/a10/chip.h | 11 +++++++++ src/cpu/allwinner/a10/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/ram_segs.h | 30 ++++++++++++++++++++++++ 5 files changed, 118 insertions(+) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 1b720bf..a86d719 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -8,6 +8,7 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c romstage-y += bootblock_media.c +romstage-y += cbmem.c romstage-y += clock.c romstage-y += pinmux.c romstage-y += timer.c @@ -16,7 +17,9 @@ romstage-y += uart.c romstage-y += uart_console.c ramstage-y += bootblock_media.c +ramstage-y += cbmem.c ramstage-y += clock.c +ramstage-y += cpu.c ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c diff --git a/src/cpu/allwinner/a10/cbmem.c b/src/cpu/allwinner/a10/cbmem.c new file mode 100644 index 0000000..c6a6502 --- /dev/null +++ b/src/cpu/allwinner/a10/cbmem.c @@ -0,0 +1,26 @@ +/* + * Provides cbmem utilities for romstage and ramstage + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "ram_segs.h" +#include <cbmem.h> + +#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM) + +void *cbmem_top(void) +{ + return a1x_get_cbmem_top(); +} + +#else + +void get_cbmem_table(u64 *base, u64 *size) +{ + *size = CONFIG_COREBOOT_TABLES_SIZE; + *base = (unsigned)a1x_get_cbmem_top() - CONFIG_COREBOOT_TABLES_SIZE; +} + +#endif diff --git a/src/cpu/allwinner/a10/chip.h b/src/cpu/allwinner/a10/chip.h new file mode 100644 index 0000000..16f60c0 --- /dev/null +++ b/src/cpu/allwinner/a10/chip.h @@ -0,0 +1,11 @@ +/* + * Allwinnwer A10 devicetree config struct + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <types.h> + +struct cpu_allwinner_a10_config { +}; diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c new file mode 100644 index 0000000..e0d4cdf --- /dev/null +++ b/src/cpu/allwinner/a10/cpu.c @@ -0,0 +1,48 @@ +/* + * Ramstage initialization for Allwinner CPUs + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cpu/cpu.h> +#include <cbmem.h> + + +static void cpu_enable_resources(device_t dev) +{ + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10, + CONFIG_DRAM_SIZE_MB << 10); + /* TODO: Declare CBFS cache as reserved? There's no guarantee we won't + * overwrite it. It seems to stay intact, being so high in RAM + */ +} + +static void cpu_init(device_t dev) +{ + /* TODO: Check if anything else needs to be explicitly initialized */ +} + +static void cpu_noop(device_t dev) +{ +} + +static struct device_operations cpu_ops = { + .read_resources = cpu_noop, + .set_resources = cpu_noop, + .enable_resources = cpu_enable_resources, + .init = cpu_init, + .scan_bus = NULL, +}; + +static void a1x_cpu_enable_dev(device_t dev) +{ + dev->ops = &cpu_ops; +} + +struct chip_operations cpu_allwinner_a10_ops = { + CHIP_NAME("CPU Allwinner A10") + .enable_dev = a1x_cpu_enable_dev, +}; diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h new file mode 100644 index 0000000..45141fe --- /dev/null +++ b/src/cpu/allwinner/a10/ram_segs.h @@ -0,0 +1,30 @@ +/* + * How we use DRAM on Allwinner CPUs + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <config.h> + +/* + * Put CBMEM at top of RAM + */ +static inline void *a1x_get_cbmem_top(void) +{ + return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20); +} + +/* + * By CBFS cache, we mean a cached copy, in RAM, of the entire CBFS region. + */ +static inline void *a1x_get_cbfs_cache_top(void) +{ + /* Arbitrary 16 MiB gap for cbmem tables and bouncebuffer */ + return a1x_get_cbmem_top() - (16 << 20); +} + +static inline void *a1x_get_cbfs_cache_base(void) +{ + return a1x_get_cbfs_cache_top() - CONFIG_ROM_SIZE; +}

1 0

Patch set updated for coreboot: c0cc416 cubieboard: Enable the SD controller and mux SD pins
by Alexandru Gagniuc Feb. 3, 2014

Feb. 3, 2014

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4745 -gerrit commit c0cc416a5dde0cd8a7dd7ea78754021ceb6c15cc Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Dec 28 15:10:28 2013 -0500 cubieboard: Enable the SD controller and mux SD pins This step needs to be done before calling any MMC functionality. Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/clock.h | 10 ++++++++++ src/mainboard/cubietech/cubieboard/bootblock.c | 15 +++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index 0be736c..0a9cfd6 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -66,6 +66,16 @@ /* DRAM_CLK values*/ #define DRAM_CTRL_DCLK_OUT (1 << 15) +/* SDx_CLK values */ +#define SDx_CLK_GATE (1 << 31) +#define SDx_CLK_SRC_MASK (3 << 24) +#define SDx_CLK_SRC_OSC24M (0 << 24) +#define SDx_CLK_SRC_PLL6 (1 << 24) +#define SDx_CLK_SRC_PLL5 (2 << 24) +#define SDx_RAT_EXP_N_MASK (3 << 16) +#define SDx_RAT_EXP_N(n) (((n) << 16) & SDx_RAT_EXP_N_MASK) +#define SDx_RAT_M_MASK (0xf << 0) +#define SDx_RAT_M(m) ((((m) - 1) << 0) & SDx_RAT_M_MASK) /** * \brief Clock gating definitions * diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 2e5929c..c994c57 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -27,6 +27,10 @@ #define GPB_UART0_FUNC 2 #define GPB_UART0_PINS ((1 << 22) | (1 << 23)) +#define GPF_SD0_FUNC 2 +#define GPF_SD0_PINS 0x3f /* PF0 thru PF5 */ +#define GPH1_SD0_DET_FUNC 5 + static void cubieboard_set_sys_clock(void) { u32 reg32; @@ -60,6 +64,13 @@ static void cubieboard_setup_clocks(void) write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0), &ccm->apb1_clk_div_cfg); + /* Configure the clock for SD0 */ + write32(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) + | SDx_RAT_M(1), &ccm->sd0_clk_cfg); + + /* Enable clock to SD0 */ + a1x_periph_clock_enable(A1X_CLKEN_MMC0); + } static void cubieboard_setup_gpios(void) @@ -71,6 +82,10 @@ static void cubieboard_setup_gpios(void) /* Mux UART pins */ gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC); + + /* Mux SD pins */ + gpio_set_multipin_func(GPF, GPF_SD0_PINS, GPF_SD0_FUNC); + gpio_set_pin_func(GPH, 1, GPH1_SD0_DET_FUNC); } static void cubieboard_enable_uart(void)

1 0

Patch set updated for coreboot: e8eeb81 HP DL145 G1 motherboard: Adding ACPI support
by Oskar Enoksson Feb. 3, 2014

Feb. 3, 2014

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5097 -gerrit commit e8eeb81aa431e044701a7eb209fb55ba33c07f3b Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Sun Feb 2 15:26:37 2014 +0100 HP DL145 G1 motherboard: Adding ACPI support Basic ACPI support for this old platform. Created by copying and tweaking similar motherboard ACPI implementations in coreboot. Works reasonably well under Linux, providing PowerNow, HPET-timers and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44). Not tested under Windows. Change-Id: Ic4d2f9382b6770654eea8842a37ad38cf12de459 Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> --- src/mainboard/hp/dl145_g1/Kconfig | 5 + src/mainboard/hp/dl145_g1/acpi/amd8111.asl | 617 +++++++++++++++++++++++++ src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl | 156 +++++++ src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl | 231 +++++++++ src/mainboard/hp/dl145_g1/acpi/amd8131.asl | 101 ++++ src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl | 6 + src/mainboard/hp/dl145_g1/acpi_tables.c | 342 ++++++++++++++ src/mainboard/hp/dl145_g1/dsdt.asl | 314 +++++++++++++ src/mainboard/hp/dl145_g1/fadt.c | 183 ++++++++ src/mainboard/hp/dl145_g1/mptable.c | 20 +- src/mainboard/hp/dl145_g1/romstage.c | 81 +++- 11 files changed, 2023 insertions(+), 33 deletions(-) diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 7e63077..23a0a20 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -8,14 +8,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF + select HAVE_BUS_CONFIG + select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select SET_FIDVID + select SET_FIDVID_DEBUG select RAMINIT_SYSINFO # select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT select DRIVERS_I2C_I2CMUX + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl new file mode 100644 index 0000000..80e7a74 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl @@ -0,0 +1,617 @@ +/* + * Copyright 2005 AMD + * Copyright (C) 2011 Oskar Enoksson <enok(a)lysator.liu.se> + */ +//AMD8111 +// APIC version of the interrupt routing table +Name (APIC, Package (0x04) { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} +}) +// PIC version of the interrupt routing table +Name (PICM, Package (0x04) { + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00} +}) +Name (DNCG, Ones) +Method (_PRT, 0, NotSerialized) { + If (LEqual (^DNCG, Ones)) { + Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0) + // Update the Device Number according to SBDN + Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0)) + + Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) + + Store (0x00, ^DNCG) + } + + If (LNot (PICF)) { + Return (PICM) + } Else { + Return (APIC) + } +} + +// AMD8111 System Management I/O Mapped Registers (PMxx) +OperationRegion (PMIO, SystemIO, PMBS, 0xDF) +Field (PMIO, ByteAcc, NoLock, Preserve) { + Offset (0x1E), + SWSM, 8, // Software SMI Trigger (sets GSTS) + Offset (0x28), + GSTS, 16, // Global STatuS + GNBL, 16, // Global SMI enable + Offset (0x30), + STMC, 5, // Miscellaneous SMI Status + Offset (0x32), + ENMC, 5, // Miscellaneous SMI Enable + Offset (0x44), + STC0, 9, // TCO Status 1 + Offset (0x46), + STC1, 4, // TCO Status 2 + Offset (0xA8), + STHW, 20 // Device monitor SMI Interrupt Enable +} +Device (HPET) { + Name (HPT, 0x00) + Name (_HID, EisaId ("PNP0103")) + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) + }) + Return (BUF0) + } +} +#include "amd8111_pic.asl" +#include "amd8111_isa.asl" + +Device (TP2P) { + // 8111 P2P and it should 0x00030000 when 8131 present + Method (_ADR, 0, NotSerialized) { + Return (DADD(\_SB.PCI0.SBDN, 0x00000000)) + } + Method (_PRW, 0, NotSerialized) { // Power Resource for Wake + // result : + // [0] Bit index into GPEx_EN in the GPE block described by FADT. + // [1] The lowest power state from which the system can be awakened. + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x08, 0x03 }) + //} Else { + Return (Package (0x02) { 0x08, 0x01 }) + //} + } + Device (ETHR) { + Name (_ADR, 0x00010000) + Method (_PRW, 0, NotSerialized) { // Power Resource for Wake + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x08, 0x03 }) + //} Else { + Return (Package (0x02) { 0x08, 0x01 }) + //} + } + } + Device (USB0) { + Name (_ADR, 0x00000000) + Method (_PSW, 1, NotSerialized) { // Power State Wake + And (GNBL, 0x7FFF, GNBL) + } + Method (_PRW, 0, NotSerialized) { // Power Resource for Wake + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x0F, 0x03 }) + //} Else { + Return (Package (0x02) { 0x0F, 0x01 }) + //} + } + } + Device (USB1) { + Name (_ADR, 0x00000001) + Method (_PSW, 1, NotSerialized) { // Power State Wake + And (GNBL, 0x7FFF, GNBL) + } + Method (_PRW, 0, NotSerialized) { // Power Resource for Wake + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x0F, 0x03 }) + //} Else { + Return (Package (0x02) { 0x0F, 0x01 }) + //} + } + } + Name (APIC, Package (0x0C) { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6 + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5 + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } + }) + Name (PICM, Package (0x0C) { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6 + Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5 + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } + }) + Method (_PRT, 0, NotSerialized) { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } +} +Device (IDE0) { + Method (_ADR, 0, NotSerialized) { + Return (DADD(\_SB.PCI0.SBDN, 0x00010001)) + } + Name (REGF, 0x01) + Method (_REG, 2, NotSerialized) { + If (LEqual (Arg0, 0x02)) { + Store (Arg1, REGF) + } + } + OperationRegion (BAR0, PCI_Config, 0x00, 0x60) + Field (BAR0, ByteAcc, NoLock, Preserve) { + Offset (0x40), // EIDE Controller Configuration Register + SCEN, 1, // Secondary Channel Enable + PCEN, 1, // Primary Channel Enable + , 10, + SPWB, 1, // Secondary Port posted-write buffer for PIO modes enable + SRPB, 1, // RW (controls nothing) + PPWB, 1, // Primary Port posted-write buffer for PIO modes enable + PRPB, 1, // RW (controls nothing) + PM80, 1, // High-speed 80-pin cable enable Primary Master + PS80, 1, // High-speed 80-pin cable enable Primary Slave + SM80, 1, // High-speed 80-pin cable enable Secondary Master + SS80, 1, // High-speed 80-pin cable enable Secondary Slave + , 4, // RW (controls nothing) + Offset (0x48), + SSRT, 4, // + SSPW, 4, // + SMRT, 4, // + SMPW, 4, + PSRT, 4, + PSPW, 4, + PMRT, 4, + PMPW, 4, + SSAD, 2, + SMAD, 2, + PSAD, 2, + PMAD, 2, + Offset (0x4E), + SXRT, 4, + SXPW, 4, + PXRT, 4, + PXPW, 4, + SSUD, 8, + SMUD, 8, + PSUD, 8, + PMUD, 8, + PPDN, 1, + PPDS, 1, + , 2, + SPDN, 1, + SPDS, 1 + } + Name (TIM0, Package (0x06) { + Package (0x05) { + 0x78, + 0xB4, + 0xF0, + 0x0186, + 0x0258 + }, + Package (0x07) { + 0x78, + 0x5A, + 0x3C, + 0x2D, + 0x1E, + 0x14, + 0x0F + }, + Package (0x08) { + 0x04, + 0x03, + 0x02, + 0x01, + 0x00, + 0x00, + 0x00, + 0x00 + }, + Package (0x03) { + 0x02, + 0x01, + 0x00 + }, + Package (0x05) { + 0x20, + 0x22, + 0x42, + 0x65, + 0xA8 + }, + Package (0x07) { + 0xC2, + 0xC1, + 0xC0, + 0xC4, + 0xC5, + 0xC6, + 0xC7 + } + }) + Name (TMD0, Buffer (0x14) {}) + CreateDWordField (TMD0, 0x00, PIO0) + CreateDWordField (TMD0, 0x04, DMA0) + CreateDWordField (TMD0, 0x08, PIO1) + CreateDWordField (TMD0, 0x0C, DMA1) + CreateDWordField (TMD0, 0x10, CHNF) + Device (CHN0) { + Name (_ADR, 0x00) + Method (_STA, 0, NotSerialized) { + If (PCEN) { Return (0x0F) } + Else { Return (0x09) } + } + Method (_GTM, 0, NotSerialized) { + Return (GTM (PMPW, PMRT, PSPW, PSRT, PMUD, PSUD)) + } + Method (_STM, 3, NotSerialized) { + Store (Arg0, TMD0) + Store (STM (), Local0) + And (Local0, 0xFF, PSUD) + ShiftRight (Local0, 0x08, Local0) + And (Local0, 0xFF, PMUD) + ShiftRight (Local0, 0x08, Local0) + And (Local0, 0x0F, PSRT) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, PSPW) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, PMRT) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, PMPW) + Store (GTF (0x00, Arg1), ATA0) + Store (GTF (0x01, Arg2), ATA1) + } + Device (DRV0) { + Name (_ADR, 0x00) + Method (_GTF, 0, NotSerialized) { + Return (RATA (ATA0)) + } + } + Device (DRV1) { + Name (_ADR, 0x01) + Method (_GTF, 0, NotSerialized) { + Return (RATA (ATA1)) + } + } + } + Device (CHN1) { + Name (_ADR, 0x01) + Method (_STA, 0, NotSerialized) { + If (SCEN) { Return (0x0F) } + Else { Return (0x09) } + } + Method (_GTM, 0, NotSerialized) { + Return (GTM (SMPW, SMRT, SSPW, SSRT, SMUD, SSUD)) + } + Method (_STM, 3, NotSerialized) { + Store (Arg0, TMD0) + Store (STM (), Local0) + And (Local0, 0xFF, SSUD) + ShiftRight (Local0, 0x08, Local0) + And (Local0, 0xFF, SMUD) + ShiftRight (Local0, 0x08, Local0) + And (Local0, 0x0F, SSRT) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, SSPW) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, SMRT) + ShiftRight (Local0, 0x04, Local0) + And (Local0, 0x0F, SMPW) + Store (GTF (0x00, Arg1), ATA2) + Store (GTF (0x01, Arg2), ATA3) + } + Device (DRV0) { + Name (_ADR, 0x00) + Method (_GTF, 0, NotSerialized) { + Return (RATA (ATA2)) + } + } + Device (DRV1) { + Name (_ADR, 0x01) + Method (_GTF, 0, NotSerialized) { + Return (RATA (ATA3)) + } + } + } + Method (GTM, 6, Serialized) { + Store (Ones, PIO0) + Store (Ones, PIO1) + Store (Ones, DMA0) + Store (Ones, DMA1) + Store (0x1A, CHNF) + If (REGF) {} + Else { Return (TMD0) } + Add (Arg0, Arg1, Local0) + Add (Local0, 0x02, Local0) + Multiply (Local0, 0x1E, PIO0) + Add (Arg2, Arg3, Local0) + Add (Local0, 0x02, Local0) + Multiply (Local0, 0x1E, PIO1) + If (And (Arg4, 0x40)) { + Or (CHNF, 0x01, CHNF) + And (Arg4, 0x07, Local0) + If (LLess (Local0, 0x04)) { + Add (Local0, 0x02, Local0) + Multiply (Local0, 0x1E, DMA0) + } Else { + If (LEqual (Local0, 0x04)) { + Store (0x2D, DMA0) + } Else { + If (LEqual (Local0, 0x05)) { + Store (0x1E, DMA0) + } Else { + If (LEqual (Local0, 0x06)) { + Store (0x14, DMA0) + } Else { + If (LEqual (Local0, 0x07)) { + Store (0x0F, DMA0) + } Else { + Store (PIO0, DMA0) + } + } + } + } + } + } Else { + Store (PIO0, DMA0) + } + If (And (Arg5, 0x40)) { + Or (CHNF, 0x04, CHNF) + And (Arg5, 0x07, Local0) + If (LLess (Local0, 0x04)) { + Add (Local0, 0x02, Local0) + Multiply (Local0, 0x1E, DMA1) + } Else { + If (LEqual (Local0, 0x04)) { + Store (0x2D, DMA1) + } Else { + If (LEqual (Local0, 0x05)) { + Store (0x1E, DMA1) + } Else { + If (LEqual (Local0, 0x06)) { + Store (0x14, DMA1) + } Else { + If (LEqual (Local0, 0x07)) { + Store (0x0F, DMA0) + } Else { + Store (PIO1, DMA1) + } + } + } + } + } + } Else { + Store (PIO1, DMA1) + } + Return (TMD0) + } + Method (STM, 0, Serialized) { + If (REGF) {} + Else { Return (0xFFFFFFFF) } + If (LEqual (PIO0, 0xFFFFFFFF)) { + Store (0xA8, Local1) + } Else { + And (Match (DerefOf (Index (TIM0, 0x00)), + MGE, PIO0, MTR, + 0x00, 0x00), + 0x07, Local0) + Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)), + Local1) + } + ShiftLeft (Local1, 0x08, Local1) + If (LEqual (PIO1, 0xFFFFFFFF)) { + Or (Local1, 0xA8, Local1) + } Else { + And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO1, MTR, + 0x00, 0x00), 0x07, Local0) + Or (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)), + Local1, Local1) + } + ShiftLeft (Local1, 0x08, Local1) + If (LEqual (DMA0, 0xFFFFFFFF)) { + Or (Local1, 0x03, Local1) + } Else { + If (And (CHNF, 0x01)) { + And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA0, MTR, + 0x00, 0x00), 0x07, Local0) + Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)), + Local1, Local1) + } Else { + Or (Local1, 0x03, Local1) + } + } + ShiftLeft (Local1, 0x08, Local1) + If (LEqual (DMA1, 0xFFFFFFFF)) { + Or (Local1, 0x03, Local1) + } Else { + If (And (CHNF, 0x04)) { + And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA1, MTR, + 0x00, 0x00), 0x07, Local0) + Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)), + Local1, Local1) + } Else { + Or (Local1, 0x03, Local1) + } + } + Return (Local1) + } + Name (AT01, Buffer (0x07) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF + }) + Name (AT02, Buffer (0x07) { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90 + }) + Name (AT03, Buffer (0x07) { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6 + }) + Name (AT04, Buffer (0x07) { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91 + }) + Name (ATA0, Buffer (0x1D) {}) + Name (ATA1, Buffer (0x1D) {}) + Name (ATA2, Buffer (0x1D) {}) + Name (ATA3, Buffer (0x1D) {}) + Name (ATAB, Buffer (0x1D) {}) + CreateByteField (ATAB, 0x00, CMDC) + Method (GTFB, 3, Serialized) { + Multiply (CMDC, 0x38, Local0) + Add (Local0, 0x08, Local1) + CreateField (ATAB, Local1, 0x38, CMDX) + Multiply (CMDC, 0x07, Local0) + CreateByteField (ATAB, Add (Local0, 0x02), A001) + CreateByteField (ATAB, Add (Local0, 0x06), A005) + Store (Arg0, CMDX) + Store (Arg1, A001) + Store (Arg2, A005) + Increment (CMDC) + } + Method (GTF, 2, Serialized) { + Store (Arg1, Debug) + Store (0x00, CMDC) + Name (ID49, 0x0C00) + Name (ID59, 0x00) + Name (ID53, 0x04) + Name (ID63, 0x0F00) + Name (ID88, 0x0F00) + Name (IRDY, 0x01) + Name (PIOT, 0x00) + Name (DMAT, 0x00) + If (LEqual (SizeOf (Arg1), 0x0200)) { + CreateWordField (Arg1, 0x62, IW49) + Store (IW49, ID49) + CreateWordField (Arg1, 0x6A, IW53) + Store (IW53, ID53) + CreateWordField (Arg1, 0x7E, IW63) + Store (IW63, ID63) + CreateWordField (Arg1, 0x76, IW59) + Store (IW59, ID59) + CreateWordField (Arg1, 0xB0, IW88) + Store (IW88, ID88) + } + Store (0xA0, Local7) + If (Arg0) { + Store (0xB0, Local7) + And (CHNF, 0x08, IRDY) + If (And (CHNF, 0x10)) { + Store (PIO1, PIOT) + } Else { + Store (PIO0, PIOT) + } + If (And (CHNF, 0x04)) { + If (And (CHNF, 0x10)) { + Store (DMA1, DMAT) + } Else { + Store (DMA0, DMAT) + } + } Else { + Store (PIO1, DMAT) + } + } Else { + And (CHNF, 0x02, IRDY) + Store (PIO0, PIOT) + If (And (CHNF, 0x01)) { + Store (DMA0, DMAT) + } + } + If (LAnd (LAnd (And (ID53, 0x04), And (ID88, 0xFF00)), DMAT)) { + Store (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMAT, MTR, + 0x00, 0x00), Local1) + If (LGreater (Local1, 0x06)) { + Store (0x06, Local1) + } + GTFB (AT01, Or (0x40, Local1), Local7) + } Else { + If (LAnd (And (ID63, 0xFF00), PIOT)) { + And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR, + 0x00, 0x00), 0x07, Local0) + If (Local0) { + If (And (Local0, 0x04)) { + Store (0x02, Local0) + } Else { + Store (0x01, Local0) + } + } + Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0 + )), Local1) + GTFB (AT01, Local1, Local7) + } + } + If (IRDY) { + And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR, + 0x00, 0x00), 0x07, Local0) + Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0 + )), Local1) + GTFB (AT01, Local1, Local7) + } Else { + If (And (ID49, 0x0400)) { + GTFB (AT01, 0x01, Local7) + } + } + If (LAnd (And (ID59, 0x0100), And (ID59, 0xFF))) { + GTFB (AT03, And (ID59, 0xFF), Local7) + } + Store (ATAB, Debug) + Return (ATAB) + } + Method (RATA, 1, NotSerialized) { + CreateByteField (Arg0, 0x00, CMDN) + Multiply (CMDN, 0x38, Local0) + CreateField (Arg0, 0x08, Local0, RETB) + Store (RETB, Debug) + Return (RETB) + } +} +Device (PMF) { + // acpi smbus it should be 0x00040003 if 8131 present + Method (_ADR, 0, NotSerialized) + { + Return (DADD(\_SB.PCI0.SBDN, 0x00010003)) + } + OperationRegion (BAR0, PCI_Config, 0x00, 0xff) + Field (BAR0, ByteAcc, NoLock, Preserve) { + Offset (0x56), + PIRA, 4, + PIRB, 4, + PIRC, 4, + PIRD, 4 + } + //OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) + //Field (TS3_, DWordAcc, NoLock, Preserve) { + // PTS3, 16 + //} +} diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl new file mode 100644 index 0000000..6423459 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl @@ -0,0 +1,156 @@ +/* + * Copyright 2005 AMD + * Copyright (C) 2011 Oskar Enoksson <enok(a)lysator.liu.se> + */ +//AMD8111 isa + +Device (ISA) { + // lpc 0x00040000 + Method (_ADR, 0, NotSerialized) { + Return (DADD(\_SB.PCI0.SBDN, 0x00010000)) + } + /* + OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers + Field (PIRY, ByteAcc, NoLock, Preserve) { + Z000, 2, // Parallel Port Range + , 1, + ECP , 1, // ECP Enable + FDC1, 1, // Floppy Drive Controller 1 + FDC2, 1, // Floppy Drive Controller 2 + Offset (0x01), + Z001, 3, // Serial Port A Range + SAEN, 1, // Serial Post A Enabled + Z002, 3, // Serial Port B Range + SBEN, 1 // Serial Post B Enabled + } + */ + Device (PIC) { + Name (_HID, EisaId ("PNP0000")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) // Master Interrupt controller + IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) // Slave Interrupt controller + IRQ (Edge, ActiveHigh, Exclusive) {2} + }) + } + Device (DMA1) { + Name (_HID, EisaId ("PNP0200")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) // Slave DMA controller + IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) // DMA page registers + IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) // Master DMA controller + DMA (Compatibility, NotBusMaster, Transfer16) {4} + }) + } + Device (TMR) { + Name (_HID, EisaId ("PNP0100")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) // Programmable Interval timer + IRQ (Edge, ActiveHigh, Exclusive) {0} + }) + } + Device (RTC) { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0070, 0x0070, 0x01, 0x04) // Realtime Clock and CMOS ram + IRQ (Edge, ActiveHigh, Exclusive) {8} + }) + } + Device (SPKR) { + Name (_HID, EisaId ("PNP0800")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) // PC speaker + }) + } + Device (COPR) { // Co-processor + Name (_HID, EisaId ("PNP0C04")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) // Floating point Error control + IRQ (Edge, ActiveHigh, Exclusive) {13} + }) + } + Device (SYSR) { // System control registers (?) + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x00) + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) + IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) + IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) + IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C) + IO (Decode16, 0x0080, 0x0080, 0x01, 0x01) + IO (Decode16, 0x0084, 0x0084, 0x01, 0x03) + IO (Decode16, 0x0088, 0x0088, 0x01, 0x01) + IO (Decode16, 0x008C, 0x008C, 0x01, 0x03) + IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) + // IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + // EISA defined level triggered interrupt control registers + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) + // IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + // IO (Decode16, 0xDE00, 0xDE00, 0x00, 0x80) + // IO (Decode16, 0xDE80, 0xDE80, 0x00, 0x80) + IO (Decode16,0xDE00,0xDE00,0x00,0x80) + IO (Decode16,0xDE80,0xDE80,0x00,0x80) + // IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM + // IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) + IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0D) // PMBS block + IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0E) // SMBS block + IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0F) // GPBS block + }) + Method (_CRS, 0, NotSerialized) { + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MIN, GP00) + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MAX, GP01) + CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._LEN, GP0L) + Store (PMBS, GP00) + Store (PMBS, GP01) + Store (PMLN, GP0L) + If (SMBS) { + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MIN, GP10) + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MAX, GP11) + CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._LEN, GP1L) + Store (SMBS, GP10) + Store (SMBS, GP11) + Store (SMBL, GP1L) + } + If (GPBS) { + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MIN, GP20) + CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MAX, GP21) + CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._LEN, GP2L) + Store (GPBS, GP20) + Store (GPBS, GP21) + Store (GPLN, GP2L) + } + Return (CRS) + } + } + Device (MEM) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF + Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 + Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC + Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM + Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + }) +// Read the Video Memory length + CreateDWordField (BUF0, 0x14, CLEN) + CreateDWordField (BUF0, 0x10, CBAS) + + ShiftLeft (VGA1, 0x09, Local0) + Store (Local0, CLEN) + + Return (BUF0) + } + } +#include "superio/winbond/w83627hf/acpi/superio.asl" +} + diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl new file mode 100644 index 0000000..319c42b --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi/amd8111_pic.asl @@ -0,0 +1,231 @@ +/* + * Copyright 2005 AMD + * Copyright (C) 2011 Oskar Enoksson <enok(a)lysator.liu.se> + */ +//AMD8111 pic LNKA B C D + +Device (LNKA) { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x01) + Method (_STA, 0, NotSerialized) { + If (LEqual (\_SB.PCI0.PMF.PIRA, 0x00) ) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + Method (_PRS, 0, NotSerialized) { + Name (BUFA, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + Method (_DIS, 0, NotSerialized) { + Store (0x00, \_SB.PCI0.PMF.PIRA ) + } + + Method (_CRS, 0, NotSerialized) { + Name (BUFA, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local2) + Store (0x00, Local3) + Store (\_SB.PCI0.PMF.PIRA, Local1) + If (LNot (LEqual (Local1, 0x00))) { // Routing enable + If (LGreater (Local1, 0x07)) { + Subtract (Local1, 0x08, Local1) + ShiftLeft (One, Local1, Local3) + } Else { + If (LGreater (Local1, 0x00)) { + ShiftLeft (One, Local1, Local2) + } + } + Store (Local2, IRA1) + Store (Local3, IRA2) + } + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + Store(Local1,\_SB.PCI0.PMF.PIRA) + } +} + +Device (LNKB) { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) { + If (LEqual (\_SB.PCI0.PMF.PIRB, 0x00) ) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + + Method (_PRS, 0, NotSerialized) { + Name (BUFB, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + + Method (_DIS, 0, NotSerialized) { + Store (0x00, \_SB.PCI0.PMF.PIRB ) + } + + Method (_CRS, 0, NotSerialized) { + Name (BUFB, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRA1) + CreateByteField (BUFB, 0x02, IRA2) + Store (0x00, Local2) + Store (0x00, Local3) + Store (\_SB.PCI0.PMF.PIRB, Local1) + If (LNot (LEqual (Local1, 0x00))) { // Routing enable + If (LGreater (Local1, 0x07)) { + Subtract (Local1, 0x08, Local1) + ShiftLeft (One, Local1, Local3) + } Else { + If (LGreater (Local1, 0x00)) { + ShiftLeft (One, Local1, Local2) + } + } + Store (Local2, IRA1) + Store (Local3, IRA2) + } + Return (BUFB) + } + + Method (_SRS, 1, NotSerialized) { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + Store(Local1,\_SB.PCI0.PMF.PIRB) + } +} + +Device (LNKC) { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x03) + Method (_STA, 0, NotSerialized) { + If (LEqual (\_SB.PCI0.PMF.PIRC, 0x00) ) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + + Method (_PRS, 0, NotSerialized) { + Name (BUFA, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + + Method (_DIS, 0, NotSerialized) { + Store (0x00, \_SB.PCI0.PMF.PIRC ) + } + + Method (_CRS, 0, NotSerialized) { + Name (BUFA, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local2) + Store (0x00, Local3) + Store (\_SB.PCI0.PMF.PIRC, Local1) + If (LNot (LEqual (Local1, 0x00))) { // Routing enable + If (LGreater (Local1, 0x07)) { + Subtract (Local1, 0x08, Local1) + ShiftLeft (One, Local1, Local3) + } Else { + If (LGreater (Local1, 0x00)) { + ShiftLeft (One, Local1, Local2) + } + } + Store (Local2, IRA1) + Store (Local3, IRA2) + } + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + Store(Local1,\_SB.PCI0.PMF.PIRC) + } +} + +Device (LNKD) { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x04) + Method (_STA, 0, NotSerialized) { + If (LEqual (\_SB.PCI0.PMF.PIRD, 0x00) ) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + Method (_PRS, 0, NotSerialized) { + Name (BUFB, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + Method (_DIS, 0, NotSerialized) { + Store (0x00, \_SB.PCI0.PMF.PIRD ) + } + Method (_CRS, 0, NotSerialized) { + Name (BUFB, ResourceTemplate () { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRA1) + CreateByteField (BUFB, 0x02, IRA2) + Store (0x00, Local2) + Store (0x00, Local3) + Store (\_SB.PCI0.PMF.PIRD, Local1) + If (LNot (LEqual (Local1, 0x00))) { // Routing enable + If (LGreater (Local1, 0x07)) { + Subtract (Local1, 0x08, Local1) + ShiftLeft (One, Local1, Local3) + } Else { + If (LGreater (Local1, 0x00)) { + ShiftLeft (One, Local1, Local2) + } + } + Store (Local2, IRA1) + Store (Local3, IRA2) + } + Return (BUFB) + } + Method (_SRS, 1, NotSerialized) { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + Store(Local1,\_SB.PCI0.PMF.PIRD) + } +} diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8131.asl b/src/mainboard/hp/dl145_g1/acpi/amd8131.asl new file mode 100644 index 0000000..fbbb37d --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi/amd8131.asl @@ -0,0 +1,101 @@ +/* + * Copyright 2005 AMD + * Copyright (C) 2011 Oskar Enoksson <enok(a)lysator.liu.se> + */ + +Device (PG0A) { +/* 8131 pcix bridge 1 */ + Method (_ADR, 0, NotSerialized) { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + } + Method (_PRW, 0, NotSerialized) { + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x29, 0x03 }) + //} Else { + Return (Package (0x02) { 0x29, 0x01 }) + //} + } + Name (APIC, Package (0x0c) { + // Slot 3 - PIRQ BCDA ---- verified + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, + // Slot 4 - PIRQ CDAB ---- verified + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //? + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, + // Onboard NIC 1 - PIRQ DABC + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //? + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A }, + // NIC 2 - PIRQ ABCD -- verified + // Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //? + // Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, + // Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + // Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + // SERIAL ATA - PIRQ BCDA + // Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //? + // Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A }, + // Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B }, + // Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 } + }) + Name (PICM, Package (0x0c) { + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3 + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 }, + // Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, + // Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 }, + // Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 }, + // Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }, + // Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + // Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }, + // Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 }, + // Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 } + }) + Method (_PRT, 0, NotSerialized) { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } +} +Device (PG0B) { +/* 8131 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + } + Method (_PRW, 0, NotSerialized) { + //If (CondRefOf (\_S3, Local0)) { + // Return (Package (0x02) { 0x22, 0x03 }) + //} Else { + Return (Package (0x02) { 0x22, 0x01 }) + //} + } + Name (APIC, Package (0x04) { + // Slot A - PIRQ CDAB -- verfied + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },// Slot 2 + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1C }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1D }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1E } + }) + Name (PICM, Package (0x04) { + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2 + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 } + }) + Method (_PRT, 0, NotSerialized) { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } +} diff --git a/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl b/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl new file mode 100644 index 0000000..559d8c7 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi/pci0_hc.asl @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2011, Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ +#include "amd8111.asl" //real SB at first +#include "amd8131.asl" diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c new file mode 100644 index 0000000..3b16f25 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/acpi_tables.c @@ -0,0 +1,342 @@ +/* + * Island Aruma ACPI support + * written by Stefan Reinauer <stepan(a)openbios.org> + * (C) 2005 Stefan Reinauer + * + * Copyright 2005 AMD + * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB + * + * Copyright (C) 2011 Oskar Enoksson <enok(a)lysator.liu.se> + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdk8_sysconf.h> +#include "northbridge/amd/amdk8/acpi.h" +#include "mb_sysconf.h" +#include <cpu/amd/model_fxx_powernow.h> + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(unsigned start, unsigned end) +{ + + unsigned i; + print_debug("dump_mem:"); + for(i=start;i<end;i++) { + if((i & 0xf)==0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); + } + print_debug("\n"); +} +#endif + +extern unsigned pm_base; + +extern const unsigned char AmlCode[]; + +#if CONFIG_ACPI_SSDTX_NUM >= 1 +extern const unsigned char AmlCode_ssdt2[]; +extern const unsigned char AmlCode_ssdt3[]; +extern const unsigned char AmlCode_ssdt4[]; +extern const unsigned char AmlCode_ssdt5[]; +#endif + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base=0x18; + + struct mb_sysconf_t *m; + + m = sysconf.mb; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write 8111 IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, + IO_APIC_ADDR, 0); + + /* Write all 8131 IOAPICs */ + { + device_t dev; + struct resource *res; + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_1, + res->base, gsi_base ); + gsi_base+=4; + + } + } + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_2, + res->base, gsi_base ); + gsi_base+=4; + } + } + + /* + int i; + int j = 0; + + for(i=1; i< sysconf.hc_possible_num; i++) { + unsigned d = 0; + if(!(sysconf.pci1234[i] & 0x1) ) continue; + // 8131 need to use +4 + + switch (sysconf.hcid[i]) { + case 1: + d = 7; + break; + case 3: + d = 4; + break; + } + switch (sysconf.hcid[i]) { + case 1: + case 3: + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], + res->base, gsi_base ); + gsi_base+=d; + } + } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], + res->base, gsi_base ); + gsi_base+=d; + + } + } + break; + } + + j++; + } + */ + + } + + current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) + current, 0, 0, 2, 5 ); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high*/ + + + /* create all subtables for processors */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); + /* 1: LINT1 connect to NMI */ + + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + k8acpi_write_vars(); +#if CONFIG_SET_FIDVID + amd_model_fxx_generate_powernow(pm_base+0x10, 6, 1); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); +#endif + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + + get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn + + /* Align ACPI tables to 16byte */ + start = ( start + 0x0f ) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp,hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current+=madt->header.length; + acpi_add_table(rsdp,madt); + + + /* SRAT */ + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current+=srat->header.length; + acpi_add_table(rsdp,srat); + + /* SLIT */ + printk(BIOS_DEBUG, "ACPI: * SLIT\n"); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdp,slit); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + +#if CONFIG_ACPI_SSDTX_NUM >= 1 + int i; + void *p; + acpi_header_t *ssdtx; + //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table + + for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + if((sysconf.pci1234[i] & 1) != 1 ) continue; + uint8_t c; + if(i<7) { + c = (uint8_t) ('4' + i - 1); + } + else { + c = (uint8_t) ('A' + i - 1 - 6); + } + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt + current = ( current + 0x07) & -0x08; + ssdtx = (acpi_header_t *)current; + switch(sysconf.hcid[i]) { + case 1: //8132 + p = &AmlCode_ssdt2; + break; + case 2: //8151 + p = &AmlCode_ssdt3; + break; + case 3: //8131 + p = &AmlCode_ssdt4; + break; + default: + //HTX no io apic + p = &AmlCode_ssdt5; + break; + } + memcpy(ssdtx, p, sizeof(acpi_header_t)); + current += ssdtx->length; + memcpy(ssdtx, p, ssdtx->length); + update_ssdtx((void *)ssdtx, i); + ssdtx->checksum = 0; + ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length); + acpi_add_table(rsdp,ssdtx); + } +#endif + + /* FACS */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FADT */ + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + acpi_fadt_t *fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt,facs,dsdt); + acpi_add_table(rsdp,fadt); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "xsdt\n"); + dump_mem(rsdt, ((void *)xsdt) + sizeof(acpi_xsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} + diff --git a/src/mainboard/hp/dl145_g1/dsdt.asl b/src/mainboard/hp/dl145_g1/dsdt.asl new file mode 100644 index 0000000..becf9ad --- /dev/null +++ b/src/mainboard/hp/dl145_g1/dsdt.asl @@ -0,0 +1,314 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2011 Oskar Enoksson <enok(a)lysator.liu.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +{ + // Name (SPIO, 0x2E) // SuperIO (w83627hf) + Name (SPI2, 0x4E) // Unknown National Semiconductors (EPM3128A?) + Name (IO1B, 0x0680) // GPIO Base (?) + Name (IO1L, 0x80) + //Name (IO2B, 0x0295) // Hardware monitor + //Name (IO2L, 0x02) + Name (PMBS, 0x2000) // Power Management Base + Name (PMLN, 0xC0) // Power Management Length + Name (GPBS, 0x20C0) + Name (GPLN, 0x20) + Name (SMBS, 0x20E0) + Name (SMBL, 0x20) + +#define NO_W83627HF_FDC // don't expose the floppy disk controller +#define NO_W83627HF_FDC_ENUM // don't try to enumerate the connected floppy drives +#define NO_W83627HF_PPORT // don't expose the parallel port +//#define NO_W83627HF_UARTA // don't expose the first serial port +#define NO_W83627HF_UARTB // don't expose the second serial port (already hidden + // if UARTB is configured as IRDA port by firmware) +#define NO_W83627HF_IRDA // don't expose the IRDA port (already hidden if UARTB is + // configured as serial port by firmware) +#define NO_W83627HF_CIR // don't expose the Consumer Infrared functionality +//#define NO_W83627HF_KBC // don't expose the keyboard controller +//#define NO_W83627HF_PS2M // don't expose the PS/2 mouse functionality of the + // keyboard controller +#define NO_W83627HF_GAME // don't expose the game port +#define NO_W83627HF_MIDI // don't expose the MIDI port +// #define NO_W83627HF_HWMON // don't expose the hardware monitor as + // PnP "Motherboard Resource" +// Scope (\_PR) and relevant CPU? objects are auto-generated in SSDT + + Scope (\_SB) { // Root of the bus hierarchy + Device (PCI0) { // Top PCI device (AMD K8 Northbridge 1) + + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + // The following symbols are assumed to be created by coreboot + External (BUSN) + External (PCIO) + External (MMIO) + External (SBLK) + External (CBST) + External (SBDN) + External (TOM1) // Top Of Memory 1 (low 4GB ?) + External (HCLK) // Hypertransport possible CLocK frequencies + External (HCDN) // Hypertransport Controller Device Numbers + + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180000) + //Name (_UID, 0x00) + Name (_UID, 0x01) + + Name (HCIN, 0x00) // HC1 + Method (_BBN, 0, NotSerialized) { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate () { + // PCI Configuration address space address/data + IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) + IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h + IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x8100, // Address Range Minimum + 0xFFFF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x7F00,,, + , TypeStatic) //8100h-FFFFh + DWordMemory (ResourceProducer, PosDecode, + MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x000C0000, // Address Range Minimum + 0x000CFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00010000,,, + , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh + Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x03AF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x03B0,,, + , TypeStatic) //0-CF7h + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x03E0, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0918,,, + , TypeStatic) //0-CF7h + }) + \_SB.OSTP () + CreateDWordField (BUF0, 0x3E, VLEN) + CreateDWordField (BUF0, 0x36, VMAX) + CreateDWordField (BUF0, 0x32, VMIN) + ShiftLeft (VGA1, 0x09, Local0) + Add (VMIN, Local0, VMAX) + Decrement (VMAX) + Store (Local0, VLEN) + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + #include "acpi/pci0_hc.asl" + } + Device (PCI1) { + Name (_HID, "PNP0A03") + Name (_ADR, 0x00190000) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) { + Return (\_SB.PCI0.CBST) + } + //Name (HCIN, 0x01) // HC2 + //Method (_BBN, 0, NotSerialized) { + // Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + //} + Name (_BBN, 0x00) + } + Device (PWRB) { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 0xAA) + Name (_STA, 0x0B) + } + } + Scope (_GPE) { + Method (_L08, 0, NotSerialized) { + Notify (\_SB.PCI0, 0x02) //PME# Wakeup + Notify (\_SB.PCI0.TP2P.ETHR, 0x02) + Notify (\_SB.PWRB, 0x02) + } + Method (_L0F, 0, NotSerialized) { + Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup + Notify (\_SB.PCI0.TP2P.USB1, 0x02) + Notify (\_SB.PWRB, 0x02) + } + Method (_L22, 0, NotSerialized) { // GPIO18 (LID) - Pogo 0 Bridge B + Notify (\_SB.PCI0.PG0B, 0x02) + Notify (\_SB.PWRB, 0x02) + } + Method (_L29, 0, NotSerialized) { // GPIO25 (Suspend) - Pogo 0 Bridge A + Notify (\_SB.PCI0.PG0A, 0x02) + Notify (\_SB.PWRB, 0x02) + } + } + OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?) + Field (KSB0, ByteAcc, NoLock, Preserve) { + KSBI, 8, // Index + KSBD, 8 // Data + } +/* + OperationRegion (IHHM, SystemIO, IO2B, IO2L) // Hardware monitor + Field (IHHM, ByteAcc, NoLock, Preserve) { + HHMI, 8, // Index + HHMD, 8 // Data + } +*/ + // Method (_BFS, 1, NotSerialized) { + // Control method executed immediately following a wake event. + // Arg0 => Value of the sleeping state from which woken (1=S1, 2=S2 ...) + // Optional + //} + + Method (_PTS, 1, NotSerialized) { + // Control method used to Prepare To Sleep. + // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...) + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG8) + } + + // Method (_GTS, 1, NotSerialized) { + // Control method executed just prior to setting the sleep enable (SLP_EN) bit. + // Arg0 => Value of the sleeping state (1=S1, 2=S2 ...) + // Optional + //} + + // System \_Sx states + // Four bytes must be stored for each supported power state: + // 0:7 Value for PM1a_CNT.SLP_TYP register to enter this system state. + // 8:f Value for PM1b_CNT.SLP_TYP register to enter this system state. + // To enter any given state, OSPM must write the PM1a_CNT.SLP_TYP + // register before the PM1b_CNT.SLP_TYP register. + // 10:1f Reserved + // The states are: + // S0 : Working + // S1 : Sleeping with Processor Context maintained + // S2 : Sleeping with Processor Context not maintained + // S3 : Same as S2, but more power saving (e.g. suspend to RAM) + // S4 : DRAM context not maintained (e.g. suspend to disk) + // S5 : Soft Off + // If only S0 and S5 are declared then no wake-up methods are needed + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + // S1 support should work, but never wakes up, so it's commented out + //Name (\_S1, Package () { 0x01, 0x01, 0x01, 0x01 }) + //Name (\_S3, Package () { 0x05, 0x05, 0x05, 0x05 }) + Name (\_S5, Package () { 0x07, 0x07, 0x07, 0x07 }) + //Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + Method (WAK, 1, NotSerialized) {} + + Name (WAKP, Package (0x02) { 0x00, 0x00 }) + // Status + // 0: 0 Wake was signaled but failed due to lack of power. + // 1: 1 Wake was signaled but failed due to thermal condition + // 2:31 Reserved + // PSS + // 0:1f If non-zero, the effective S-state the power supply really entered. + + Method (_WAK, 1, NotSerialized) { + // System Wake + // Arg0: The value of the sleeping state from which woken (1=S1, ...) + // Result: (2 DWORD package) + ShiftLeft (Arg0, 0x04, DBG8) + WAK (Arg0) + Store (0xFF, KSBI) // Clear 0xFF in CMOS RAM + Store (0x00, KSBD) + If (LEqual (Arg0, 0x01)) { // Wake from S1 state + And (\_SB.PCI0.GSTS, 0x10, Local0) + And (Local0, \_SB.PCI0.GNBL, Local0) + If (Local0) { + Notify (\_SB.PWRB, 0x02) + } + } + Store (\_SB.PCI0.GSTS, \_SB.PCI0.GSTS) + Store (\_SB.PCI0.STMC, \_SB.PCI0.STMC) + Store (\_SB.PCI0.STC0, \_SB.PCI0.STC0) + Store (\_SB.PCI0.STC1, \_SB.PCI0.STC1) + Store (\_SB.PCI0.STHW, \_SB.PCI0.STHW) + If (LEqual (Arg0, 0x03)) { // Wake from S3 state + Notify (\_SB.PCI0.TP2P.USB0, 0x01) + } + Store (0xC0, \_SB.PCI0.SWSM) + If (DerefOf (Index (WAKP, 0x00))) { + Store (0x00, Index (WAKP, 0x01)) + } Else { + Store (Arg0, Index (WAKP, 0x01)) + } + Return (WAKP) + } + + Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode + Method (_PIC, 1, NotSerialized) { //PIC Flag and Interface Method + // Control method that conveys interrupt model in use to the system + // firmware. OS reports interrupt model in use. + // 0 => PIC Mode + // 1 => APIC Mode + // 2 => SAPIC Mode + // 3.. => Reserved + Store (Arg0, PICF) + } + OperationRegion (DEB8, SystemIO, 0x80, 0x01) + Field (DEB8, ByteAcc, Lock, Preserve) { + DBG8, 8 + } + OperationRegion (DEB9, SystemIO, 0x90, 0x01) + Field (DEB9, ByteAcc, Lock, Preserve) { + DBG9, 8 + } + OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) + Field (EXTM, WordAcc, Lock, Preserve) { + AMEM, 32 + } + OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) + Field (VGAM, ByteAcc, Lock, Preserve) { + VGA1, 8 // Video memory length (in 2k units?) + } + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) { + Offset (0x10), + FLG0, 8 + } + OperationRegion (Z007, SystemIO, 0x21, 0x01) + Field (Z007, ByteAcc, NoLock, Preserve) { + Z008, 8 + } + OperationRegion (Z009, SystemIO, 0xA1, 0x01) + Field (Z009, ByteAcc, NoLock, Preserve) { + Z00A, 8 + } + #include "northbridge/amd/amdk8/util.asl" +} diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c new file mode 100644 index 0000000..e99149b --- /dev/null +++ b/src/mainboard/hp/dl145_g1/fadt.c @@ -0,0 +1,183 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * (C) Copyright 2005 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2011 Oskar Enoksson <enok(a)lysator.liu.se> + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> + +extern unsigned pm_base; /* pm_base should be set in sb acpi */ + +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ + + acpi_header_t *header=&(fadt->header); + + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt,0,sizeof(acpi_fadt_t)); + memcpy(header->signature,"FACP",4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id,OEM_ID,6); + memcpy(header->oem_table_id,"COREBOOT",8); + memcpy(header->asl_compiler_id,ASLC,4); + header->asl_compiler_revision=0; + + fadt->firmware_ctrl=(u32)facs; + fadt->dsdt= (u32)dsdt; + // 3=Workstation,4=Enterprise Server, 7=Performance Server + fadt->preferred_pm_profile=0x04; + fadt->sci_int=9; + + // disable system management mode by setting to 0: + fadt->smi_cmd = 0;//pm_base+0x2f; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + fadt->pm1a_evt_blk = pm_base; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = pm_base+0x04; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = 0x0000; + fadt->pm_tmr_blk = pm_base+0x08; + fadt->gpe0_blk = pm_base+0x20; + fadt->gpe1_blk = pm_base+0xb0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + fadt->gpe1_blk_len = 8; + fadt->gpe1_base = 16; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state + fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state + fadt->flush_size = 0; // ignored if wbindv=1 in flags + fadt->flush_stride = 0; // ignored if wbindv=1 in flags + fadt->duty_offset = 1; + fadt->duty_width = 3; // 0 means duty cycle not supported + // _alrm value 0 means RTC alarm feature not supported + fadt->day_alrm = 0; // 0x7d these have to be + fadt->mon_alrm = 0; // 0x7e added to cmos.layout + fadt->century = 0; // 0x7f to make rtc alrm work + fadt->iapc_boot_arch = + ACPI_FADT_LEGACY_DEVICES | + ACPI_FADT_8042 | + // ACPI_FADT_VGA_NOT_PRESENT | + // ACPI_FADT_MSI_NOT_SUPPORTED| + // ACPI_FADT_NO_PCIE_ASPM_CONTROL| + 0; + + fadt->res2 = 0; + + fadt->flags = + ACPI_FADT_WBINVD | + // ACPI_FADT_WBINVD_FLUSH | + ACPI_FADT_C1_SUPPORTED | + // ACPI_FADT_C2_MP_SUPPORTED | + // ACPI_FADT_POWER_BUTTON | + ACPI_FADT_SLEEP_BUTTON | + // ACPI_FADT_FIXED_RTC | + // ACPI_FADT_S4_RTC_WAKE | + // ACPI_FADT_32BIT_TIMER | + // ACPI_FADT_DOCKING_SUPPORTED| + // ACPI_FADT_RESET_REGISTER | + // ACPI_FADT_SEALED_CASE | + // ACPI_FADT_HEADLESS | + // ACPI_FADT_SLEEP_TYPE | + // ACPI_FADT_PCI_EXPRESS_WAKE | + // ACPI_FADT_PLATFORM_CLOCK | + // ACPI_FADT_S4_RTC_VALID | + // ACPI_FADT_REMOTE_POWER_ON | + // ACPI_FADT_APIC_CLUSTER | + // ACPI_FADT_APIC_PHYSICAL | + 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + + fadt->res3 = 0; + fadt->res4 = 0; + fadt->res5 = 0; + + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pm_base; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pm_base+4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pm_base+0x08; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pm_base+0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 64; + fadt->x_gpe1_blk.bit_offset = 16; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = pm_base+0xb0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index 35dedde..eaa29fc 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -1,3 +1,7 @@ +/* + * Copyright (c) 2014, Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ #include <console/console.h> #include <arch/smp/mpspec.h> #include <arch/ioapic.h> @@ -53,26 +57,26 @@ static void *smp_write_config_table(void *v) // /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ // Integrated SMBus 2.0 - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); // Integrated AMD AC97 Audio - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); // Integrated AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13); // On board ATI Rage XL - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); // On board Broadcom nics smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00); // On board LSI SCSI - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); // PCIX-133 Slot smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 67ce9c1..dd85e11 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -1,3 +1,7 @@ +/* + * Copyright (c) 2014, Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -44,18 +48,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); - smbus_write_byte(SMBUS_HUB, 0x03, 0); -} - static inline void change_i2c_mux(unsigned device) { int ret, i; @@ -69,6 +61,11 @@ static inline void change_i2c_mux(unsigned device) print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + change_i2c_mux(ctrl->channel0[0]>>8); +} + static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -82,22 +79,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" - -#define RC0 ((1<<1)<<8) -#define RC1 ((1<<2)<<8) +#if CONFIG_SET_FIDVID +#include "cpu/amd/model_fxx/fidvid.c" +#endif void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { - //first node - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC1|DIMM0, RC1|DIMM2, 0, 0, - RC1|DIMM1, RC1|DIMM3, 0, 0, -#endif - }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; @@ -126,6 +113,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif ht_setup_chains_x(sysinfo); +#if CONFIG_SET_FIDVID + /* Check to see if processor is capable of changing FIDVID */ + /* otherwise it will throw a GP# when reading FIDVID_STATUS */ + struct cpuid_result cpuid1 = cpuid(0x80000007); + if ((cpuid1.edx & 0x6) == 0x6) { + { + /* Read FIDVID_STATUS */ + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + + } else { + print_debug("Changing FIDVID not supported\n"); + } +#endif needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); @@ -138,6 +152,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); int i; + +#define RC0 ((1<<1)<<8) +#define RC1 ((1<<2)<<8) + for(i=0;i<2;i++) { activate_spd_rom(&sysinfo->ctrl[i]); } @@ -152,9 +170,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl now; + static const uint16_t spd_addr [] = { + //first node + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC1|DIMM0, RC1|DIMM2, 0, 0, + RC1|DIMM1, RC1|DIMM3, 0, 0, +#endif + }; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); +#if CONFIG_SET_FIDVID + init_timer(); // Need to use TMICT to synchronize FID/VID +#endif sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); //dump_pci_devices();

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Patch set updated for coreboot: 04a7dec cbfstool: Eliminate global variable "arch"
by Alexandru Gagniuc Feb. 3, 2014

Feb. 3, 2014

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5105 -gerrit commit 04a7dec02a2e1ebaea01e905f911bc1734abeaba Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Feb 2 22:37:28 2014 -0600 cbfstool: Eliminate global variable "arch" Now that unused functions have been removed, the global "arch" is only used in very few places. We can pack "arch" in the "param" structure and pass it down to where it is actually used. Change-Id: I255d1e2bc6b5ead91b6b4e94a0202523c4ab53dc Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/cbfs-mkpayload.c | 4 ++-- util/cbfstool/cbfs-mkstage.c | 4 ++-- util/cbfstool/cbfs.h | 1 + util/cbfstool/cbfstool.c | 19 ++++++++++++------- util/cbfstool/common.c | 3 --- util/cbfstool/common.h | 6 ++---- util/cbfstool/elfheaders.c | 1 + 7 files changed, 20 insertions(+), 18 deletions(-) diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index b1dd1c0..6e6e418 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -51,7 +51,7 @@ static void xdr_segs(struct buffer *output, } } int parse_elf_to_payload(const struct buffer *input, - struct buffer *output, comp_algo algo) + struct buffer *output, uint32_t arch, comp_algo algo) { Elf64_Phdr *phdr; Elf64_Ehdr ehdr; @@ -69,7 +69,7 @@ int parse_elf_to_payload(const struct buffer *input, if (!compress) return -1; - if (elf_headers(input, &ehdr, &phdr, &shdr) < 0) + if (elf_headers(input, arch, &ehdr, &phdr, &shdr) < 0) return -1; DEBUG("start: parse_elf_to_payload\n"); diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 6a5f6f7..233ec57 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -33,7 +33,7 @@ * works for all elf files, not just the restricted set. */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - comp_algo algo, uint32_t *location) + uint32_t arch, comp_algo algo, uint32_t *location) { Elf64_Phdr *phdr; Elf64_Ehdr ehdr; @@ -50,7 +50,7 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, DEBUG("start: parse_elf_to_stage(location=0x%x)\n", *location); - if (elf_headers(input, &ehdr, &phdr, NULL) < 0) + if (elf_headers(input, arch, &ehdr, &phdr, NULL) < 0) return -1; headers = ehdr.e_phnum; diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 92dd84a..9a5af5b 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -129,6 +129,7 @@ uint32_t get_cbfs_compression(const char *name, uint32_t unknown); /* elfheaders.c */ int elf_headers(const struct buffer *pinput, + uint32_t arch, Elf64_Ehdr *ehdr, Elf64_Phdr **pphdr, Elf64_Shdr **pshdr); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 9935f51..1d93981 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -56,6 +56,7 @@ static struct param { uint32_t pagesize; uint32_t offset; uint32_t top_aligned; + uint32_t arch; int fit_empty_entries; comp_algo algo; /* for linux payloads */ @@ -63,6 +64,7 @@ static struct param { char *cmdline; } param = { /* All variables not listed are initialized as zero. */ + .arch = CBFS_ARCHITECTURE_UNKNOWN, .algo = CBFS_COMPRESS_NONE, }; @@ -178,9 +180,13 @@ static int cbfs_add_component(const char *cbfs_name, return 0; } -static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset) { +static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset) +{ struct buffer output; - if (parse_elf_to_stage(buffer, &output, param.algo, offset) != 0) + int ret; + ret = parse_elf_to_stage(buffer, &output, param.arch, param.algo, + offset); + if (ret != 0) return -1; buffer_delete(buffer); // direct assign, no dupe. @@ -192,7 +198,7 @@ static int cbfstool_convert_mkpayload(struct buffer *buffer, uint32_t *offset) { struct buffer output; int ret; /* per default, try and see if payload is an ELF binary */ - ret = parse_elf_to_payload(buffer, &output, param.algo); + ret = parse_elf_to_payload(buffer, &output, param.arch, param.algo); /* If it's not an ELF, see if it's a UEFI FV */ if (ret != 0) @@ -334,8 +340,7 @@ static int cbfs_create(void) return 1; } - // TODO Remove arch or pack into param. - if (arch == CBFS_ARCHITECTURE_UNKNOWN) { + if (param.arch == CBFS_ARCHITECTURE_UNKNOWN) { ERROR("You need to specify -m/--machine arch.\n"); return 1; } @@ -368,7 +373,7 @@ static int cbfs_create(void) } if (cbfs_image_create(&image, - arch, + param.arch, param.size, param.alignment, &bootblock, @@ -701,7 +706,7 @@ int main(int argc, char **argv) verbose++; break; case 'm': - arch = string_to_arch(optarg); + param.arch = string_to_arch(optarg); break; case 'I': param.initrd = optarg; diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 715c5df..98d9517 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -103,9 +103,6 @@ void buffer_delete(struct buffer *buffer) { buffer->size = 0; } -/* FIXME: This global is more difficult to just remove */ -uint32_t arch = CBFS_ARCHITECTURE_UNKNOWN; - static struct { uint32_t arch; const char *name; diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index b8ff4a3..5bcbcbe 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -62,8 +62,6 @@ int buffer_write_file(struct buffer *buffer, const char *filename); /* Destroys a memory buffer. */ void buffer_delete(struct buffer *buffer); -extern uint32_t arch; - uint32_t string_to_arch(const char *arch_string); #define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) @@ -79,7 +77,7 @@ uint64_t intfiletype(const char *name); /* cbfs-mkpayload.c */ int parse_elf_to_payload(const struct buffer *input, - struct buffer *output, comp_algo algo); + struct buffer *output, uint32_t arch, comp_algo algo); int parse_fv_to_payload(const struct buffer *input, struct buffer *output, comp_algo algo); int parse_bzImage_to_payload(const struct buffer *input, @@ -92,7 +90,7 @@ int parse_flat_binary_to_payload(const struct buffer *input, comp_algo algo); /* cbfs-mkstage.c */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - comp_algo algo, uint32_t *location); + uint32_t arch, comp_algo algo, uint32_t *location); void print_supported_filetypes(void); diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c index fd7a1a1..0d874a1 100644 --- a/util/cbfstool/elfheaders.c +++ b/util/cbfstool/elfheaders.c @@ -241,6 +241,7 @@ elf_shdr(struct buffer *pinput, Elf64_Shdr *shdr, */ int elf_headers(const struct buffer *pinput, + uint32_t arch, Elf64_Ehdr *ehdr, Elf64_Phdr **pphdr, Elf64_Shdr **pshdr)

1 0

New patch to review for coreboot: 2d4a359 cbfstool: Eliminate global variable "arch"
by Alexandru Gagniuc Feb. 3, 2014

Feb. 3, 2014

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5105 -gerrit commit 2d4a359fbb92e96f95031256c2896fe7354b3621 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Feb 2 22:37:28 2014 -0600 cbfstool: Eliminate global variable "arch" Now that unused functions have been removed, the global "arch" is only used in very few places. We can pack "arch" in the "param" structure and pass it down to where it is actually used. Change-Id: I255d1e2bc6b5ead91b6b4e94a0202523c4ab53dc Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/cbfs-mkpayload.c | 4 ++-- util/cbfstool/cbfs-mkstage.c | 4 ++-- util/cbfstool/cbfs.h | 1 + util/cbfstool/cbfstool.c | 19 ++++++++++++------- util/cbfstool/common.c | 3 --- util/cbfstool/common.h | 6 ++---- util/cbfstool/elfheaders.c | 1 + 7 files changed, 20 insertions(+), 18 deletions(-) diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index b1dd1c0..6e6e418 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -51,7 +51,7 @@ static void xdr_segs(struct buffer *output, } } int parse_elf_to_payload(const struct buffer *input, - struct buffer *output, comp_algo algo) + struct buffer *output, uint32_t arch, comp_algo algo) { Elf64_Phdr *phdr; Elf64_Ehdr ehdr; @@ -69,7 +69,7 @@ int parse_elf_to_payload(const struct buffer *input, if (!compress) return -1; - if (elf_headers(input, &ehdr, &phdr, &shdr) < 0) + if (elf_headers(input, arch, &ehdr, &phdr, &shdr) < 0) return -1; DEBUG("start: parse_elf_to_payload\n"); diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 6a5f6f7..233ec57 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -33,7 +33,7 @@ * works for all elf files, not just the restricted set. */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - comp_algo algo, uint32_t *location) + uint32_t arch, comp_algo algo, uint32_t *location) { Elf64_Phdr *phdr; Elf64_Ehdr ehdr; @@ -50,7 +50,7 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, DEBUG("start: parse_elf_to_stage(location=0x%x)\n", *location); - if (elf_headers(input, &ehdr, &phdr, NULL) < 0) + if (elf_headers(input, arch, &ehdr, &phdr, NULL) < 0) return -1; headers = ehdr.e_phnum; diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 92dd84a..9a5af5b 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -129,6 +129,7 @@ uint32_t get_cbfs_compression(const char *name, uint32_t unknown); /* elfheaders.c */ int elf_headers(const struct buffer *pinput, + uint32_t arch, Elf64_Ehdr *ehdr, Elf64_Phdr **pphdr, Elf64_Shdr **pshdr); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 9935f51..1495082 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -56,6 +56,7 @@ static struct param { uint32_t pagesize; uint32_t offset; uint32_t top_aligned; + uint32_t arch; int fit_empty_entries; comp_algo algo; /* for linux payloads */ @@ -178,9 +179,13 @@ static int cbfs_add_component(const char *cbfs_name, return 0; } -static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset) { +static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset) +{ struct buffer output; - if (parse_elf_to_stage(buffer, &output, param.algo, offset) != 0) + int ret; + ret = parse_elf_to_stage(buffer, &output, param.arch, param.algo, + offset); + if (ret != 0) return -1; buffer_delete(buffer); // direct assign, no dupe. @@ -192,7 +197,7 @@ static int cbfstool_convert_mkpayload(struct buffer *buffer, uint32_t *offset) { struct buffer output; int ret; /* per default, try and see if payload is an ELF binary */ - ret = parse_elf_to_payload(buffer, &output, param.algo); + ret = parse_elf_to_payload(buffer, &output, param.arch, param.algo); /* If it's not an ELF, see if it's a UEFI FV */ if (ret != 0) @@ -334,8 +339,7 @@ static int cbfs_create(void) return 1; } - // TODO Remove arch or pack into param. - if (arch == CBFS_ARCHITECTURE_UNKNOWN) { + if (param.arch == CBFS_ARCHITECTURE_UNKNOWN) { ERROR("You need to specify -m/--machine arch.\n"); return 1; } @@ -368,7 +372,7 @@ static int cbfs_create(void) } if (cbfs_image_create(&image, - arch, + param.arch, param.size, param.alignment, &bootblock, @@ -600,6 +604,7 @@ int main(int argc, char **argv) } param.cbfs_name = argv[1]; + param.arch = CBFS_ARCHITECTURE_UNKNOWN; char *cmd = argv[2]; optind += 2; @@ -701,7 +706,7 @@ int main(int argc, char **argv) verbose++; break; case 'm': - arch = string_to_arch(optarg); + param.arch = string_to_arch(optarg); break; case 'I': param.initrd = optarg; diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 715c5df..98d9517 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -103,9 +103,6 @@ void buffer_delete(struct buffer *buffer) { buffer->size = 0; } -/* FIXME: This global is more difficult to just remove */ -uint32_t arch = CBFS_ARCHITECTURE_UNKNOWN; - static struct { uint32_t arch; const char *name; diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index b8ff4a3..5bcbcbe 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -62,8 +62,6 @@ int buffer_write_file(struct buffer *buffer, const char *filename); /* Destroys a memory buffer. */ void buffer_delete(struct buffer *buffer); -extern uint32_t arch; - uint32_t string_to_arch(const char *arch_string); #define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) @@ -79,7 +77,7 @@ uint64_t intfiletype(const char *name); /* cbfs-mkpayload.c */ int parse_elf_to_payload(const struct buffer *input, - struct buffer *output, comp_algo algo); + struct buffer *output, uint32_t arch, comp_algo algo); int parse_fv_to_payload(const struct buffer *input, struct buffer *output, comp_algo algo); int parse_bzImage_to_payload(const struct buffer *input, @@ -92,7 +90,7 @@ int parse_flat_binary_to_payload(const struct buffer *input, comp_algo algo); /* cbfs-mkstage.c */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - comp_algo algo, uint32_t *location); + uint32_t arch, comp_algo algo, uint32_t *location); void print_supported_filetypes(void); diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c index fd7a1a1..0d874a1 100644 --- a/util/cbfstool/elfheaders.c +++ b/util/cbfstool/elfheaders.c @@ -241,6 +241,7 @@ elf_shdr(struct buffer *pinput, Elf64_Shdr *shdr, */ int elf_headers(const struct buffer *pinput, + uint32_t arch, Elf64_Ehdr *ehdr, Elf64_Phdr **pphdr, Elf64_Shdr **pshdr)

1 0

New patch to review for coreboot: bc98cb2 cbfstool: Remove more unused functions from common.c
by Alexandru Gagniuc Feb. 3, 2014

Feb. 3, 2014

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5104 -gerrit commit bc98cb2688f4f35f38b834bae6a83152242032cb Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Feb 2 22:13:31 2014 -0600 cbfstool: Remove more unused functions from common.c A lot of the early functions have been re-implemented in a context- centric mode, rather than relying on global variables. Removing these has the nice side-effect of allowing us to remove more global variables. Change-Id: Iee716ef38729705432dd10d12758c886d38701a8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/cbfs.h | 7 - util/cbfstool/common.c | 578 +------------------------------------------------ util/cbfstool/common.h | 20 -- 3 files changed, 1 insertion(+), 604 deletions(-) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 585a26d..92dd84a 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -119,7 +119,6 @@ struct cbfs_payload { */ #define CBFS_COMPONENT_NULL 0xFFFFFFFF -int cbfs_file_header(unsigned long physaddr); #define CBFS_NAME(_c) (((char *) (_c)) + sizeof(struct cbfs_file)) #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) ) /* cbfs_image.c */ @@ -127,12 +126,6 @@ uint32_t get_cbfs_entry_type(const char *name, uint32_t default_value); const char *get_cbfs_entry_type_name(uint32_t type); uint32_t get_cbfs_compression(const char *name, uint32_t unknown); -/* common.c */ -int find_master_header(void *romarea, size_t size); -void recalculate_rom_geometry(void *romarea); -struct cbfs_file *cbfs_create_empty_file(uint32_t physaddr, uint32_t size); -const char *strfiletype(uint32_t number); - /* elfheaders.c */ int elf_headers(const struct buffer *pinput, diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 0aaeb13..715c5df 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -103,66 +103,9 @@ void buffer_delete(struct buffer *buffer) { buffer->size = 0; } -size_t getfilesize(const char *filename) -{ - size_t size; - FILE *file = fopen(filename, "rb"); - if (file == NULL) - return -1; - - fseek(file, 0, SEEK_END); - size = ftell(file); - fclose(file); - return size; -} - -void *loadfile(const char *filename, uint32_t * romsize_p, void *content, - int place) -{ - FILE *file = fopen(filename, "rb"); - if (file == NULL) - return NULL; - - fseek(file, 0, SEEK_END); - *romsize_p = ftell(file); - fseek(file, 0, SEEK_SET); - if (!content) { - content = malloc(*romsize_p); - if (!content) { - ERROR("Could not get %d bytes for file %s\n", - *romsize_p, filename); - exit(1); - } - } else if (place == SEEK_END) - content -= *romsize_p; - - if (!fread(content, *romsize_p, 1, file)) { - ERROR("Failed to read %s\n", filename); - return NULL; - } - fclose(file); - return content; -} - -/* N.B.: there are declarations here that were shadowed in functions. - * Hence the rather clumsy cbfstool_ prefixes. - */ -static struct cbfs_header *cbfstool_master_header; -static uint32_t phys_start, phys_end, align; -uint32_t romsize; -static void *cbfstool_offset; +/* FIXME: This global is more difficult to just remove */ uint32_t arch = CBFS_ARCHITECTURE_UNKNOWN; -static inline void *phys_to_virt(uint32_t addr) -{ - return cbfstool_offset + addr; -} - -static inline uint32_t virt_to_phys(void *addr) -{ - return (unsigned long)(addr - cbfstool_offset) & 0xffffffff; -} - static struct { uint32_t arch; const char *name; @@ -187,124 +130,6 @@ uint32_t string_to_arch(const char *arch_string) return ret; } -const char *arch_to_string(uint32_t a) -{ - int i; - const char *ret = NULL; - - for (i = 0; i < ARRAY_SIZE(arch_names); i++) { - if (a == arch_names[i].arch) { - ret = arch_names[i].name; - break; - } - } - - return ret; - -} - -int find_master_header(void *romarea, size_t size) -{ - size_t offset; - - if (cbfstool_master_header) - return 0; - - for (offset = 0; offset < size - sizeof(struct cbfs_header); offset++) { - struct cbfs_header *tmp = romarea + offset; - - if (tmp->magic == ntohl(CBFS_HEADER_MAGIC)) { - cbfstool_master_header = tmp; - break; - } - } - - return cbfstool_master_header ? 0 : 1; -} - -void recalculate_rom_geometry(void *romarea) -{ - if (find_master_header(romarea, romsize)) { - ERROR("Cannot find master header\n"); - exit(1); - } - - /* Update old headers */ - if (cbfstool_master_header->version == CBFS_HEADER_VERSION1 && - ntohl(cbfstool_master_header->architecture) == CBFS_ARCHITECTURE_UNKNOWN) { - DEBUG("Updating CBFS master header to version 2\n"); - cbfstool_master_header->architecture = htonl(CBFS_ARCHITECTURE_X86); - } - - arch = ntohl(cbfstool_master_header->architecture); - - switch (arch) { - case CBFS_ARCHITECTURE_ARMV7: - cbfstool_offset = romarea; - phys_start = (0 + ntohl(cbfstool_master_header->offset)) & 0xffffffff; - phys_end = romsize & 0xffffffff; - break; - case CBFS_ARCHITECTURE_X86: - cbfstool_offset = romarea + romsize - 0x100000000ULL; - phys_start = (0 - romsize + ntohl(cbfstool_master_header->offset)) & - 0xffffffff; - phys_end = (0 - ntohl(cbfstool_master_header->bootblocksize) - - sizeof(struct cbfs_header)) & 0xffffffff; - break; - default: - ERROR("Unknown architecture\n"); - exit(1); - } - - align = ntohl(cbfstool_master_header->align); -} - -void *loadrom(const char *filename) -{ - void *romarea = loadfile(filename, &romsize, 0, SEEK_SET); - if (romarea == NULL) - return NULL; - recalculate_rom_geometry(romarea); - return romarea; -} - -int writerom(const char *filename, void *start, uint32_t size) -{ - FILE *file = fopen(filename, "wb"); - if (!file) { - ERROR("Could not open '%s' for writing: ", filename); - perror(""); - return 1; - } - - if (fwrite(start, size, 1, file) != 1) { - ERROR("Could not write to '%s': ", filename); - perror(""); - return 1; - } - - fclose(file); - return 0; -} - -int cbfs_file_header(unsigned long physaddr) -{ - /* maybe improve this test */ - return (strncmp(phys_to_virt(physaddr), "LARCHIVE", 8) == 0); -} - -struct cbfs_file *cbfs_create_empty_file(uint32_t physaddr, uint32_t size) -{ - struct cbfs_file *nextfile = (struct cbfs_file *)phys_to_virt(physaddr); - memcpy((char *)(nextfile->magic), "LARCHIVE", 8); - nextfile->len = htonl(size); - nextfile->type = htonl(0xffffffff); - nextfile->checksum = 0; // FIXME? - nextfile->offset = htonl(sizeof(struct cbfs_file) + 16); - memset(((void *)nextfile) + sizeof(struct cbfs_file), 0, 16); - return nextfile; -} - int iself(unsigned char *input) { Elf32_Ehdr *ehdr = (Elf32_Ehdr *) input; @@ -340,15 +165,6 @@ void print_supported_filetypes(void) } } -const char *strfiletype(uint32_t number) -{ - size_t i; - for (i = 0; i < (sizeof(filetypes) / sizeof(struct filetypes_t)); i++) - if (filetypes[i].type == number) - return filetypes[i].name; - return "unknown"; -} - uint64_t intfiletype(const char *name) { size_t i; @@ -357,395 +173,3 @@ uint64_t intfiletype(const char *name) return filetypes[i].type; return -1; } - -void print_cbfs_directory(const char *filename) -{ - char *name = strdup(filename); - printf - ("%s: %d kB, bootblocksize %d, romsize %d, offset 0x%x\n" - "alignment: %d bytes, architecture: %s\n\n", - basename(name), romsize / 1024, ntohl(cbfstool_master_header->bootblocksize), - romsize, ntohl(cbfstool_master_header->offset), align, arch_to_string(arch)); - free(name); - printf("%-30s %-10s %-12s Size\n", "Name", "Offset", "Type"); - uint32_t current = phys_start; - while (current < phys_end) { - if (!cbfs_file_header(current)) { - current += align; - continue; - } - struct cbfs_file *thisfile = - (struct cbfs_file *)phys_to_virt(current); - uint32_t length = ntohl(thisfile->len); - const char *fname = (char *)(phys_to_virt(current) + sizeof(struct cbfs_file)); - if (strlen(fname) == 0) - fname = "(empty)"; - - printf("%-30s 0x%-8x %-12s %d\n", fname, - current - phys_start + ntohl(cbfstool_master_header->offset), - strfiletype(ntohl(thisfile->type)), length); - - /* note the components of the subheader are in host order ... */ - switch (ntohl(thisfile->type)) { - case CBFS_COMPONENT_STAGE: - { - struct cbfs_stage *stage = CBFS_SUBHEADER(thisfile); - INFO(" %s compression, entry: 0x%llx, load: 0x%llx, length: %d/%d\n", - stage->compression == CBFS_COMPRESS_LZMA ? "LZMA" : "no", - (unsigned long long)stage->entry, - (unsigned long long)stage->load, - stage->len, - stage->memlen); - break; - } - case CBFS_COMPONENT_PAYLOAD: - { - struct cbfs_payload_segment *payload = CBFS_SUBHEADER(thisfile); - while(payload) { - switch(payload->type) { - case PAYLOAD_SEGMENT_CODE: - case PAYLOAD_SEGMENT_DATA: - INFO(" %s (%s compression, offset: 0x%x, load: 0x%llx, length: %d/%d)\n", - payload->type == PAYLOAD_SEGMENT_CODE ? "code " : "data" , - payload->compression == CBFS_COMPRESS_LZMA ? "LZMA" : "no", - ntohl(payload->offset), - (unsigned long long)ntohll(payload->load_addr), - ntohl(payload->len), ntohl(payload->mem_len)); - break; - case PAYLOAD_SEGMENT_ENTRY: - INFO(" entry (0x%llx)\n", (unsigned long long)ntohll(payload->load_addr)); - break; - case PAYLOAD_SEGMENT_BSS: - INFO(" BSS (address 0x%016llx, length 0x%x)\n", (unsigned long long)ntohll(payload->load_addr), ntohl(payload->len)); - break; - case PAYLOAD_SEGMENT_PARAMS: - INFO(" parameters\n"); - break; - default: - INFO(" %x (%s compression, offset: 0x%x, load: 0x%llx, length: %d/%d\n", - payload->type, - payload->compression == CBFS_COMPRESS_LZMA ? "LZMA" : "no", - ntohl(payload->offset), - (unsigned long long)ntohll(payload->load_addr), - ntohl(payload->len), - ntohl(payload->mem_len)); - break; - } - - if(payload->type == PAYLOAD_SEGMENT_ENTRY) - payload=NULL; - else - payload++; - } - break; - } - default: - break; - } - current = - ALIGN(current + ntohl(thisfile->len) + - ntohl(thisfile->offset), align); - } -} - -int extract_file_from_cbfs(const char *filename, const char *payloadname, const char *outpath) -{ - FILE *outfile = NULL; - uint32_t current = phys_start; - while (current < phys_end) { - if (!cbfs_file_header(current)) { - current += align; - continue; - } - - // Locate the file start struct - struct cbfs_file *thisfile = - (struct cbfs_file *)phys_to_virt(current); - // And its length - uint32_t length = ntohl(thisfile->len); - // Locate the file name - char *fname = (char *)(phys_to_virt(current) + sizeof(struct cbfs_file)); - - // It's not the file we are looking for.. - if (strcmp(fname, payloadname) != 0) - { - current = - ALIGN(current + ntohl(thisfile->len) + - ntohl(thisfile->offset), align); - continue; - } - - // Else, it's our file. - LOG("Found file %.30s at 0x%x, type %.12s, size %d\n", fname, - current - phys_start, strfiletype(ntohl(thisfile->type)), - length); - - // If we are not dumping to stdout, open the out file. - outfile = fopen(outpath, "wb"); - if (!outfile) - { - ERROR("Could not open the file %s for writing.\n", outpath); - return 1; - } - - if (ntohl(thisfile->type) != CBFS_COMPONENT_RAW) - { - WARN("Only 'raw' files are safe to extract.\n"); - } - - fwrite(((char *)thisfile) - + ntohl(thisfile->offset), length, 1, outfile); - - fclose(outfile); - LOG("Successfully dumped the file.\n"); - - // We'll only dump one file. - return 0; - } - ERROR("File %s not found.\n", payloadname); - return 1; -} - - -int add_file_to_cbfs(void *content, uint32_t contentsize, uint32_t location) -{ - uint32_t current = phys_start; - while (current < phys_end) { - if (!cbfs_file_header(current)) { - current += align; - continue; - } - struct cbfs_file *thisfile = - (struct cbfs_file *)phys_to_virt(current); - uint32_t length = ntohl(thisfile->len); - - DEBUG("at %x, %x bytes\n", current, length); - /* Is this a free chunk? */ - if ((thisfile->type == CBFS_COMPONENT_DELETED) - || (thisfile->type == CBFS_COMPONENT_NULL)) { - DEBUG("null||deleted at %x, %x bytes\n", current, - length); - /* if this is the right size, and if specified, the right location, use it */ - if ((contentsize <= length) - && ((location == 0) || (current == location))) { - if (contentsize < length) { - DEBUG("this chunk is %x bytes, we need %x. create a new chunk at %x with %x bytes\n", - length, contentsize, - ALIGN(current + contentsize, - align), - length - contentsize); - uint32_t start = - ALIGN(current + contentsize, align); - uint32_t size = - current + ntohl(thisfile->offset) - + length - start - 16 - - sizeof(struct cbfs_file); - cbfs_create_empty_file(start, size); - } - DEBUG("copying data\n"); - memcpy(phys_to_virt(current), content, - contentsize); - return 0; - } - if (location != 0) { - /* CBFS has the constraint that the chain always moves up in memory. so once - we're past the place we seek, we don't need to look any further */ - if (current > location) { - ERROR("The requested space is not available\n"); - return 1; - } - - /* Is the requested location inside the current chunk? */ - if ((current < location) - && ((location + contentsize) <= - (current + length))) { - /* Split it up. In the next iteration the code will be at the right place. */ - DEBUG("split up. new length: %x\n", - location - current - - ntohl(thisfile->offset)); - thisfile->len = - htonl(location - current - - ntohl(thisfile->offset)); - cbfs_create_empty_file(location, - length - - (location - - current)); - } - } - } - current = - ALIGN(current + ntohl(thisfile->len) + - ntohl(thisfile->offset), align); - } - ERROR("Could not add the file to CBFS, it's probably too big.\n"); - ERROR("File size: %d bytes (%d KB).\n", contentsize, contentsize/1024); - return 1; -} - - -static struct cbfs_file *merge_adjacent_files(struct cbfs_file *first, - struct cbfs_file *second) -{ - uint32_t new_length = - ntohl(first->len) + ntohl(second->len) + ntohl(second->offset); - first->len = htonl(new_length); - first->checksum = 0; // FIXME? - return first; -} - -static struct cbfs_file *next_file(struct cbfs_file *prev) -{ - uint32_t pos = (prev == NULL) ? phys_start : - ALIGN(virt_to_phys(prev) + ntohl(prev->len) + ntohl(prev->offset), - align); - - for (; pos < phys_end; pos += align) { - if (cbfs_file_header(pos)) - return (struct cbfs_file *)phys_to_virt(pos); - } - return NULL; -} - - -int remove_file_from_cbfs(const char *filename) -{ - struct cbfs_file *prev = NULL; - struct cbfs_file *cur = next_file(prev); - struct cbfs_file *next = next_file(cur); - for (; cur; prev = cur, cur = next, next = next_file(next)) { - - /* Check if this is the file to remove. */ - char *name = (char *)cur + sizeof(*cur); - if (strcmp(name, filename)) - continue; - - /* Mark the file as free space and erase its name. */ - cur->type = CBFS_COMPONENT_NULL; - name[0] = '\0'; - - /* Merge it with the previous file if possible. */ - if (prev && prev->type == CBFS_COMPONENT_NULL) - cur = merge_adjacent_files(prev, cur); - - /* Merge it with the next file if possible. */ - if (next && next->type == CBFS_COMPONENT_NULL) - merge_adjacent_files(cur, next); - - return 0; - } - ERROR("CBFS file %s not found.\n", filename); - return 1; -} - - -/* returns new data block with cbfs_file header, suitable to dump into the ROM. location returns - the new location that points to the cbfs_file header */ -void *create_cbfs_file(const char *filename, void *data, uint32_t * datasize, - uint32_t type, uint32_t * location) -{ - uint32_t filename_len = ALIGN(strlen(filename) + 1, 16); - uint32_t headersize = sizeof(struct cbfs_file) + filename_len; - if ((location != 0) && (*location != 0)) { - uint32_t offset = *location % align; - /* If offset >= (headersize % align), we can stuff the header into the offset. - Otherwise the header has to be aligned itself, and put before the offset data */ - if (offset >= (headersize % align)) { - offset -= (headersize % align); - } else { - offset += align - (headersize % align); - } - headersize += offset; - *location -= headersize; - } - void *newdata = malloc(*datasize + headersize); - if (!newdata) { - ERROR("Could not get %d bytes for CBFS file.\n", *datasize + - headersize); - exit(1); - } - memset(newdata, 0xff, *datasize + headersize); - struct cbfs_file *nextfile = (struct cbfs_file *)newdata; - memcpy((char *)(nextfile->magic), "LARCHIVE", 8); - nextfile->len = htonl(*datasize); - nextfile->type = htonl(type); - nextfile->checksum = 0; // FIXME? - nextfile->offset = htonl(headersize); - strcpy(newdata + sizeof(struct cbfs_file), filename); - memcpy(newdata + headersize, data, *datasize); - *datasize += headersize; - return newdata; -} - -static int in_segment(int addr, int size, int gran) -{ - return ((addr & ~(gran - 1)) == ((addr + size) & ~(gran - 1))); -} - -uint32_t cbfs_find_location(const char *romfile, uint32_t filesize, - const char *filename, uint32_t alignment) -{ - void *rom; - size_t filename_size, headersize, totalsize; - int ret = 0; - uint32_t current; - - rom = loadrom(romfile); - if (rom == NULL) { - ERROR("Could not load ROM image '%s'.\n", romfile); - return 0; - } - - filename_size = strlen(filename); - headersize = sizeof(struct cbfs_file) + ALIGN(filename_size + 1, 16) + - sizeof(struct cbfs_stage); - totalsize = headersize + filesize; - - current = phys_start; - while (current < phys_end) { - uint32_t top; - struct cbfs_file *thisfile; - - if (!cbfs_file_header(current)) { - current += align; - continue; - } - - thisfile = (struct cbfs_file *)phys_to_virt(current); - - top = current + ntohl(thisfile->len) + ntohl(thisfile->offset); - - if (((ntohl(thisfile->type) == 0x0) - || (ntohl(thisfile->type) == 0xffffffff)) - && (ntohl(thisfile->len) + ntohl(thisfile->offset) >= - totalsize)) { - if (in_segment - (current + headersize, filesize, alignment)) { - ret = current + headersize; - break; - } - if ((ALIGN(current, alignment) + filesize < top) - && (ALIGN(current, alignment) - headersize > - current) - && in_segment(ALIGN(current, alignment), filesize, - alignment)) { - ret = ALIGN(current, alignment); - break; - } - if ((ALIGN(current, alignment) + alignment + filesize < - top) - && (ALIGN(current, alignment) + alignment - - headersize > current) - && in_segment(ALIGN(current, alignment) + alignment, - filesize, alignment)) { - ret = ALIGN(current, alignment) + alignment; - break; - } - } - current = - ALIGN(current + ntohl(thisfile->len) + - ntohl(thisfile->offset), align); - } - - free(rom); - return ret; -} diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index a50419b..b8ff4a3 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -62,21 +62,12 @@ int buffer_write_file(struct buffer *buffer, const char *filename); /* Destroys a memory buffer. */ void buffer_delete(struct buffer *buffer); -extern uint32_t romsize; -extern int host_bigendian; extern uint32_t arch; -const char *arch_to_string(uint32_t a); uint32_t string_to_arch(const char *arch_string); #define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) -size_t getfilesize(const char *filename); -void *loadfile(const char *filename, uint32_t * romsize_p, void *content, - int place); -void *loadrom(const char *filename); -int writerom(const char *filename, void *start, uint32_t size); - int iself(unsigned char *input); typedef void (*comp_func_ptr) (char *, int, char *, int *); @@ -103,17 +94,6 @@ int parse_flat_binary_to_payload(const struct buffer *input, int parse_elf_to_stage(const struct buffer *input, struct buffer *output, comp_algo algo, uint32_t *location); -void *create_cbfs_file(const char *filename, void *data, uint32_t * datasize, - uint32_t type, uint32_t * location); - -int add_file_to_cbfs(void *content, uint32_t contentsize, uint32_t location); -int remove_file_from_cbfs(const char *filename); -void print_cbfs_directory(const char *filename); -int extract_file_from_cbfs(const char *filename, const char *payloadname, const char *outpath); - -uint32_t cbfs_find_location(const char *romfile, uint32_t filesize, - const char *filename, uint32_t align); - void print_supported_filetypes(void); #define ARRAY_SIZE(a) (int)(sizeof(a) / sizeof((a)[0]))

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New patch to review for coreboot: f26decb cbfstool: remove unused function create_cbfs_image()
by Alexandru Gagniuc Feb. 3, 2014

Feb. 3, 2014

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5103 -gerrit commit f26decb8acd759445758595c955e793ed702dca1 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Feb 2 21:48:18 2014 -0600 cbfstool: remove unused function create_cbfs_image() It's not used anymore. Instead, we have the better replacements cbfs_image_create() and cbfs_image_from_file(). Change-Id: I7835f339805f6b41527fe3550028b29f79e35d13 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/common.c | 120 ------------------------------------------------- util/cbfstool/common.h | 3 -- 2 files changed, 123 deletions(-) diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index b646cec..0aaeb13 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -676,126 +676,6 @@ void *create_cbfs_file(const char *filename, void *data, uint32_t * datasize, return newdata; } -int create_cbfs_image(const char *romfile, uint32_t _romsize, - const char *bootblock, uint32_t create_align, uint32_t offs) -{ - uint32_t bootblocksize = 0; - struct cbfs_header *master_header; - unsigned char *romarea, *bootblk; - - romsize = _romsize; - romarea = malloc(romsize); - if (!romarea) { - ERROR("Could not get %d bytes of memory" - " for CBFS image.\n", romsize); - exit(1); - } - memset(romarea, 0xff, romsize); - - if (create_align == 0) - create_align = 64; - - bootblk = loadfile(bootblock, &bootblocksize, - romarea + romsize, SEEK_END); - if (!bootblk) { - ERROR("Could not load bootblock %s.\n", - bootblock); - free(romarea); - return 1; - } - - // TODO(hungte) Replace magic numbers by named constants. - switch (arch) { - case CBFS_ARCHITECTURE_ARMV7: - /* Set up physical/virtual mapping */ - cbfstool_offset = romarea; - - /* - * The initial jump instruction and bootblock will be placed - * before and after the master header, respectively. The - * bootblock image must contain a blank, aligned region large - * enough for the master header to fit. - * - * An anchor string must be left such that when cbfstool is run - * we can find it and insert the master header at the next - * aligned boundary. - */ - loadfile(bootblock, &bootblocksize, romarea + offs, SEEK_SET); - - unsigned char *p = romarea + offs; - while (1) { - /* FIXME: assumes little endian... */ - if (*(uint32_t *)p == 0xdeadbeef) - break; - if (p >= (romarea + _romsize)) { - ERROR("Could not determine CBFS " - "header location.\n"); - return 1; - } - p += (sizeof(unsigned int)); - } - unsigned int u = ALIGN((unsigned int)(p - romarea), align); - master_header = (struct cbfs_header *)(romarea + u); - - master_header->magic = ntohl(CBFS_HEADER_MAGIC); - master_header->version = ntohl(CBFS_HEADER_VERSION); - master_header->romsize = htonl(romsize); - master_header->bootblocksize = htonl(bootblocksize); - master_header->align = htonl(align); - master_header->offset = htonl( - ALIGN((0x40 + bootblocksize), align)); - master_header->architecture = htonl(CBFS_ARCHITECTURE_ARMV7); - - ((uint32_t *) phys_to_virt(0x4 + offs))[0] = - virt_to_phys(master_header); - - recalculate_rom_geometry(romarea); - - cbfs_create_empty_file( - offs + ALIGN((0x40 + bootblocksize), align), - romsize - offs - sizeof(struct cbfs_file) - - ALIGN((bootblocksize + 0x40), align)); - break; - - case CBFS_ARCHITECTURE_X86: - // Set up physical/virtual mapping - cbfstool_offset = romarea + romsize - 0x100000000ULL; - - loadfile(bootblock, &bootblocksize, romarea + romsize, - SEEK_END); - master_header = (struct cbfs_header *)(romarea + romsize - - bootblocksize - sizeof(struct cbfs_header)); - - master_header->magic = ntohl(CBFS_HEADER_MAGIC); - master_header->version = ntohl(CBFS_HEADER_VERSION); - master_header->romsize = htonl(romsize); - master_header->bootblocksize = htonl(bootblocksize); - master_header->align = htonl(align); - master_header->offset = htonl(offs); - master_header->architecture = htonl(CBFS_ARCHITECTURE_X86); - - ((uint32_t *) phys_to_virt(CBFS_HEADPTR_ADDR_X86))[0] = - virt_to_phys(master_header); - - recalculate_rom_geometry(romarea); - - cbfs_create_empty_file((0 - romsize + offs) & 0xffffffff, - romsize - offs - bootblocksize - - sizeof(struct cbfs_header) - - sizeof(struct cbfs_file) - 16); - break; - - default: - // Should not happen. - ERROR("You found a bug in cbfstool.\n"); - exit(1); - } - - writerom(romfile, romarea, romsize); - free(romarea); - return 0; -} - static int in_segment(int addr, int size, int gran) { return ((addr & ~(gran - 1)) == ((addr + size) & ~(gran - 1))); diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 4a0a632..a50419b 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -106,9 +106,6 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, void *create_cbfs_file(const char *filename, void *data, uint32_t * datasize, uint32_t type, uint32_t * location); -int create_cbfs_image(const char *romfile, uint32_t romsize, - const char *bootblock, uint32_t align, uint32_t offs); - int add_file_to_cbfs(void *content, uint32_t contentsize, uint32_t location); int remove_file_from_cbfs(const char *filename); void print_cbfs_directory(const char *filename);

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Patch set updated for coreboot: 883174f cbfstool: Hide cbfstool_offset from the global namespace
by Alexandru Gagniuc Feb. 3, 2014

Feb. 3, 2014

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5102 -gerrit commit 883174f2907786a6af3b614350ae9af7feffe6e5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Feb 2 21:34:15 2014 -0600 cbfstool: Hide cbfstool_offset from the global namespace This is part of a larger effort to reduce global variable usage in cbfstool. cbfstool_offset is particularly easy to hide since it's only used in common.c . Change-Id: Ic45349b5148d4407f31e12682ea0ad4b68136711 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/common.c | 12 +++++++++++- util/cbfstool/common.h | 11 ----------- 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 356ba2f..b646cec 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -150,9 +150,19 @@ void *loadfile(const char *filename, uint32_t * romsize_p, void *content, static struct cbfs_header *cbfstool_master_header; static uint32_t phys_start, phys_end, align; uint32_t romsize; -void *cbfstool_offset; +static void *cbfstool_offset; uint32_t arch = CBFS_ARCHITECTURE_UNKNOWN; +static inline void *phys_to_virt(uint32_t addr) +{ + return cbfstool_offset + addr; +} + +static inline uint32_t virt_to_phys(void *addr) +{ + return (unsigned long)(addr - cbfstool_offset) & 0xffffffff; +} + static struct { uint32_t arch; const char *name; diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index e49a3f6..4a0a632 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -62,7 +62,6 @@ int buffer_write_file(struct buffer *buffer, const char *filename); /* Destroys a memory buffer. */ void buffer_delete(struct buffer *buffer); -extern void *cbfstool_offset; extern uint32_t romsize; extern int host_bigendian; extern uint32_t arch; @@ -70,16 +69,6 @@ extern uint32_t arch; const char *arch_to_string(uint32_t a); uint32_t string_to_arch(const char *arch_string); -static inline void *phys_to_virt(uint32_t addr) -{ - return cbfstool_offset + addr; -} - -static inline uint32_t virt_to_phys(void *addr) -{ - return (unsigned long)(addr - cbfstool_offset) & 0xffffffff; -} - #define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) size_t getfilesize(const char *filename);

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New patch to review for coreboot: 0cbbb36 cbfstool: Hide cbfstool_offset From the global namespace
by Alexandru Gagniuc Feb. 3, 2014

Feb. 3, 2014

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5102 -gerrit commit 0cbbb3610975e47da0fefdd8c7859c066a8c89b6 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Feb 2 21:34:15 2014 -0600 cbfstool: Hide cbfstool_offset From the global namespace This is part of a larger effort to reduce global variable usage in cbfstool. cbfstool_offset is particularly easy to hide since it's only used in common.c . Change-Id: Ic45349b5148d4407f31e12682ea0ad4b68136711 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/cbfstool/common.c | 12 +++++++++++- util/cbfstool/common.h | 11 ----------- 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 356ba2f..b646cec 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -150,9 +150,19 @@ void *loadfile(const char *filename, uint32_t * romsize_p, void *content, static struct cbfs_header *cbfstool_master_header; static uint32_t phys_start, phys_end, align; uint32_t romsize; -void *cbfstool_offset; +static void *cbfstool_offset; uint32_t arch = CBFS_ARCHITECTURE_UNKNOWN; +static inline void *phys_to_virt(uint32_t addr) +{ + return cbfstool_offset + addr; +} + +static inline uint32_t virt_to_phys(void *addr) +{ + return (unsigned long)(addr - cbfstool_offset) & 0xffffffff; +} + static struct { uint32_t arch; const char *name; diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index e49a3f6..4a0a632 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -62,7 +62,6 @@ int buffer_write_file(struct buffer *buffer, const char *filename); /* Destroys a memory buffer. */ void buffer_delete(struct buffer *buffer); -extern void *cbfstool_offset; extern uint32_t romsize; extern int host_bigendian; extern uint32_t arch; @@ -70,16 +69,6 @@ extern uint32_t arch; const char *arch_to_string(uint32_t a); uint32_t string_to_arch(const char *arch_string); -static inline void *phys_to_virt(uint32_t addr) -{ - return cbfstool_offset + addr; -} - -static inline uint32_t virt_to_phys(void *addr) -{ - return (unsigned long)(addr - cbfstool_offset) & 0xffffffff; -} - #define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) size_t getfilesize(const char *filename);

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Patch set updated for coreboot: 5674253 jetway/nf81-t56n-lf: Serialize ACPI methods to avoid races.
by Edward O'Callaghan Feb. 3, 2014

Feb. 3, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5079 -gerrit commit 567425354e505ff782e2365d2f949dce5215d8ba Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 29 15:29:44 2014 +1100 jetway/nf81-t56n-lf: Serialize ACPI methods to avoid races. Fix the remark introduced in ACPICA version 20130517 that gives the following explanation: If a thread blocks within the method for any reason, and another thread enters the method, the method will fail because an attempt will be made to create the same (named) object twice. In this case, issue a remark that the method should be marked serialized. ACPICA BZ 909. Change-Id: I2b3605a31a8647c07be0830e54cd117d53985c81 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl index b3aed9c..4071f85 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl @@ -77,7 +77,7 @@ Method(GTTM, 1) /* get total time*/ Device(PRID) { Name (_ADR, Zero) - Method(_GTM, 0) + Method(_GTM, 0, Serialized) { NAME(OTBF, Buffer(20) { /* out buffer */ 0xFF, 0xFF, 0xFF, 0xFF, @@ -122,7 +122,7 @@ Device(PRID) Return(OTBF) /* out buffer */ } /* End Method(_GTM) */ - Method(_STM, 3, NotSerialized) + Method(_STM, 3, Serialized) { NAME(INBF, Buffer(20) { /* in buffer */ 0xFF, 0xFF, 0xFF, 0xFF, @@ -173,7 +173,7 @@ Device(PRID) Device(MST) { Name(_ADR, 0) - Method(_GTF) { + Method(_GTF, 0, Serialized) { Name(CMBF, Buffer(21) { 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, @@ -209,7 +209,7 @@ Device(PRID) Device(SLAV) { Name(_ADR, 1) - Method(_GTF) { + Method(_GTF, 0, Serialized) { Name(CMBF, Buffer(21) { 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,

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