coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 30496f1 libpayload: serial: Move the depthcharge serial drivers into libpayload.
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7224 -gerrit commit 30496f1afdbf32596cb8a7ebae386a12ba36ab16 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Apr 10 01:07:28 2014 -0700 libpayload: serial: Move the depthcharge serial drivers into libpayload. These drivers need to be ready right away and never really fit into the depthcharge driver model anyway. CQ-DEPEND=CL:194063 BUG=None TEST=Built and booted on nyan and peach_pit. Built for nyan_big, nyan_blaze, and daisy. BRANCH=None Original-Change-Id: I9570dee53c57d42ef4cd956f66a878ce39a2dc20 Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194057 Original-Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 26e18f680c93fc990a3d1057c164f19859634a9f) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia2233e2bd821d8de8d2d57a9423aeb74be7efd93 --- payloads/libpayload/Config.in | 10 ++ payloads/libpayload/drivers/Makefile.inc | 4 +- payloads/libpayload/drivers/serial.c | 245 ----------------------------- payloads/libpayload/drivers/serial/8250.c | 245 +++++++++++++++++++++++++++++ payloads/libpayload/drivers/serial/s5p.c | 106 +++++++++++++ payloads/libpayload/drivers/serial/tegra.c | 111 +++++++++++++ 6 files changed, 475 insertions(+), 246 deletions(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 2a5048c..f47d105 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -168,6 +168,16 @@ config 8250_SERIAL_CONSOLE default y if ARCH_X86 default n if !ARCH_X86 +config S5P_SERIAL_CONSOLE + bool "Exynos SOC, S5P compatible serial port driver" + depends on SERIAL_CONSOLE + default n + +config TEGRA_SERIAL_CONSOLE + bool "Tegra SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + config SERIAL_IOBASE ## This default is currently not used on non-x86 systems. hex "Default I/O base for the serial port (default 0x3f8)" diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index ed8fe41..5ce0a79 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -33,7 +33,9 @@ libc-$(CONFIG_LP_PCI) += pci.c libc-$(CONFIG_LP_SPEAKER) += speaker.c -libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial.c +libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial/8250.c +libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c +libc-$(CONFIG_LP_TEGRA_SERIAL_CONSOLE) += serial/tegra.c libc-$(CONFIG_LP_PC_KEYBOARD) += keyboard.c diff --git a/payloads/libpayload/drivers/serial.c b/payloads/libpayload/drivers/serial.c deleted file mode 100644 index a4c1b1a..0000000 --- a/payloads/libpayload/drivers/serial.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2008 Ulf Jordan <jordan(a)chalmers.se> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <libpayload-config.h> -#include <libpayload.h> - -#define IOBASE lib_sysinfo.serial->baseaddr -#define MEMBASE (phys_to_virt(IOBASE)) - -static int serial_hardware_is_present = 0; -static int serial_is_mem_mapped = 0; - -static uint8_t serial_read_reg(int offset) -{ -#ifdef CONFIG_LP_IO_ADDRESS_SPACE - if (!serial_is_mem_mapped) - return inb(IOBASE + offset); - else -#endif - return readb(MEMBASE + offset); -} - -static void serial_write_reg(uint8_t val, int offset) -{ -#ifdef CONFIG_LP_IO_ADDRESS_SPACE - if (!serial_is_mem_mapped) - outb(val, IOBASE + offset); - else -#endif - writeb(val, MEMBASE + offset); -} - -#ifdef CONFIG_LP_SERIAL_SET_SPEED -static void serial_hardware_init(int speed, int word_bits, - int parity, int stop_bits) -{ - unsigned char reg; - - /* Disable interrupts. */ - serial_write_reg(0, 0x01); - - /* Assert RTS and DTR. */ - serial_write_reg(3, 0x04); - - /* Set the divisor latch. */ - reg = serial_read_reg(0x03); - serial_write_reg(reg | 0x80, 0x03); - - /* Write the divisor. */ - uint16_t divisor = 115200 / speed; - serial_write_reg(divisor & 0xFF, 0x00); - serial_write_reg(divisor >> 8, 0x01); - - /* Restore the previous value of the divisor. - * And set 8 bits per character */ - serial_write_reg((reg & ~0x80) | 3, 0x03); -} -#endif - -static struct console_input_driver consin = { - .havekey = &serial_havechar, - .getchar = &serial_getchar -}; - -static struct console_output_driver consout = { - .putchar = &serial_putchar -}; - -void serial_init(void) -{ - if (!lib_sysinfo.serial) - return; - - serial_is_mem_mapped = - (lib_sysinfo.serial->type == CB_SERIAL_TYPE_MEMORY_MAPPED); - - if (!serial_is_mem_mapped) { -#ifdef CONFIG_LP_IO_ADDRESS_SPACE - if ((inb(IOBASE + 0x05) == 0xFF) && - (inb(IOBASE + 0x06) == 0xFF)) { - printf("IO space mapped serial not present."); - return; - } -#else - printf("IO space mapped serial not supported."); - return; -#endif - } - -#ifdef CONFIG_LP_SERIAL_SET_SPEED - serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1); -#endif -} - -void serial_console_init(void) -{ - if (!lib_sysinfo.serial) - return; - - serial_init(); - - console_add_input_driver(&consin); - console_add_output_driver(&consout); - serial_hardware_is_present = 1; -} - -void serial_putchar(unsigned int c) -{ - if (!serial_hardware_is_present) - return; - while ((serial_read_reg(0x05) & 0x20) == 0) ; - serial_write_reg(c, 0x00); -} - -int serial_havechar(void) -{ - if (!serial_hardware_is_present) - return 0; - return serial_read_reg(0x05) & 0x01; -} - -int serial_getchar(void) -{ - if (!serial_hardware_is_present) - return -1; - while (!serial_havechar()) ; - return serial_read_reg(0x00); -} - -/* These are thinly veiled vt100 functions used by curses */ - -#define VT100_CLEAR "\e[H\e[J" -/* These defines will fail if you use bold and reverse at the same time. - * Switching off one of them will switch off both. tinycurses knows about - * this and does the right thing. - */ -#define VT100_SBOLD "\e[1m" -#define VT100_EBOLD "\e[m" -#define VT100_SREVERSE "\e[7m" -#define VT100_EREVERSE "\e[m" -#define VT100_CURSOR_ADDR "\e[%d;%dH" -#define VT100_CURSOR_ON "\e[?25l" -#define VT100_CURSOR_OFF "\e[?25h" -/* The following smacs/rmacs are actually for xterm; a real vt100 has - enacs=\E(B\E)0, smacs=^N, rmacs=^O. */ -#define VT100_SMACS "\e(0" -#define VT100_RMACS "\e(B" -/* A vt100 doesn't do color, setaf/setab below are from xterm-color. */ -#define VT100_SET_COLOR "\e[3%d;4%dm" - -static void serial_putcmd(const char *str) -{ - while (*str) - serial_putchar(*(str++)); -} - -void serial_clear(void) -{ - serial_putcmd(VT100_CLEAR); -} - -void serial_start_bold(void) -{ - serial_putcmd(VT100_SBOLD); -} - -void serial_end_bold(void) -{ - serial_putcmd(VT100_EBOLD); -} - -void serial_start_reverse(void) -{ - serial_putcmd(VT100_SREVERSE); -} - -void serial_end_reverse(void) -{ - serial_putcmd(VT100_EREVERSE); -} - -void serial_start_altcharset(void) -{ - serial_putcmd(VT100_SMACS); -} - -void serial_end_altcharset(void) -{ - serial_putcmd(VT100_RMACS); -} - -/** - * Set the foreground and background colors on the serial console. - * - * @param fg Foreground color number. - * @param bg Background color number. - */ -void serial_set_color(short fg, short bg) -{ - char buffer[32]; - snprintf(buffer, sizeof(buffer), VT100_SET_COLOR, fg, bg); - serial_putcmd(buffer); -} - -void serial_set_cursor(int y, int x) -{ - char buffer[32]; - snprintf(buffer, sizeof(buffer), VT100_CURSOR_ADDR, y + 1, x + 1); - serial_putcmd(buffer); -} - -void serial_cursor_enable(int state) -{ - if (state) - serial_putcmd(VT100_CURSOR_ON); - else - serial_putcmd(VT100_CURSOR_OFF); -} diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c new file mode 100644 index 0000000..a4c1b1a --- /dev/null +++ b/payloads/libpayload/drivers/serial/8250.c @@ -0,0 +1,245 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Ulf Jordan <jordan(a)chalmers.se> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload-config.h> +#include <libpayload.h> + +#define IOBASE lib_sysinfo.serial->baseaddr +#define MEMBASE (phys_to_virt(IOBASE)) + +static int serial_hardware_is_present = 0; +static int serial_is_mem_mapped = 0; + +static uint8_t serial_read_reg(int offset) +{ +#ifdef CONFIG_LP_IO_ADDRESS_SPACE + if (!serial_is_mem_mapped) + return inb(IOBASE + offset); + else +#endif + return readb(MEMBASE + offset); +} + +static void serial_write_reg(uint8_t val, int offset) +{ +#ifdef CONFIG_LP_IO_ADDRESS_SPACE + if (!serial_is_mem_mapped) + outb(val, IOBASE + offset); + else +#endif + writeb(val, MEMBASE + offset); +} + +#ifdef CONFIG_LP_SERIAL_SET_SPEED +static void serial_hardware_init(int speed, int word_bits, + int parity, int stop_bits) +{ + unsigned char reg; + + /* Disable interrupts. */ + serial_write_reg(0, 0x01); + + /* Assert RTS and DTR. */ + serial_write_reg(3, 0x04); + + /* Set the divisor latch. */ + reg = serial_read_reg(0x03); + serial_write_reg(reg | 0x80, 0x03); + + /* Write the divisor. */ + uint16_t divisor = 115200 / speed; + serial_write_reg(divisor & 0xFF, 0x00); + serial_write_reg(divisor >> 8, 0x01); + + /* Restore the previous value of the divisor. + * And set 8 bits per character */ + serial_write_reg((reg & ~0x80) | 3, 0x03); +} +#endif + +static struct console_input_driver consin = { + .havekey = &serial_havechar, + .getchar = &serial_getchar +}; + +static struct console_output_driver consout = { + .putchar = &serial_putchar +}; + +void serial_init(void) +{ + if (!lib_sysinfo.serial) + return; + + serial_is_mem_mapped = + (lib_sysinfo.serial->type == CB_SERIAL_TYPE_MEMORY_MAPPED); + + if (!serial_is_mem_mapped) { +#ifdef CONFIG_LP_IO_ADDRESS_SPACE + if ((inb(IOBASE + 0x05) == 0xFF) && + (inb(IOBASE + 0x06) == 0xFF)) { + printf("IO space mapped serial not present."); + return; + } +#else + printf("IO space mapped serial not supported."); + return; +#endif + } + +#ifdef CONFIG_LP_SERIAL_SET_SPEED + serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1); +#endif +} + +void serial_console_init(void) +{ + if (!lib_sysinfo.serial) + return; + + serial_init(); + + console_add_input_driver(&consin); + console_add_output_driver(&consout); + serial_hardware_is_present = 1; +} + +void serial_putchar(unsigned int c) +{ + if (!serial_hardware_is_present) + return; + while ((serial_read_reg(0x05) & 0x20) == 0) ; + serial_write_reg(c, 0x00); +} + +int serial_havechar(void) +{ + if (!serial_hardware_is_present) + return 0; + return serial_read_reg(0x05) & 0x01; +} + +int serial_getchar(void) +{ + if (!serial_hardware_is_present) + return -1; + while (!serial_havechar()) ; + return serial_read_reg(0x00); +} + +/* These are thinly veiled vt100 functions used by curses */ + +#define VT100_CLEAR "\e[H\e[J" +/* These defines will fail if you use bold and reverse at the same time. + * Switching off one of them will switch off both. tinycurses knows about + * this and does the right thing. + */ +#define VT100_SBOLD "\e[1m" +#define VT100_EBOLD "\e[m" +#define VT100_SREVERSE "\e[7m" +#define VT100_EREVERSE "\e[m" +#define VT100_CURSOR_ADDR "\e[%d;%dH" +#define VT100_CURSOR_ON "\e[?25l" +#define VT100_CURSOR_OFF "\e[?25h" +/* The following smacs/rmacs are actually for xterm; a real vt100 has + enacs=\E(B\E)0, smacs=^N, rmacs=^O. */ +#define VT100_SMACS "\e(0" +#define VT100_RMACS "\e(B" +/* A vt100 doesn't do color, setaf/setab below are from xterm-color. */ +#define VT100_SET_COLOR "\e[3%d;4%dm" + +static void serial_putcmd(const char *str) +{ + while (*str) + serial_putchar(*(str++)); +} + +void serial_clear(void) +{ + serial_putcmd(VT100_CLEAR); +} + +void serial_start_bold(void) +{ + serial_putcmd(VT100_SBOLD); +} + +void serial_end_bold(void) +{ + serial_putcmd(VT100_EBOLD); +} + +void serial_start_reverse(void) +{ + serial_putcmd(VT100_SREVERSE); +} + +void serial_end_reverse(void) +{ + serial_putcmd(VT100_EREVERSE); +} + +void serial_start_altcharset(void) +{ + serial_putcmd(VT100_SMACS); +} + +void serial_end_altcharset(void) +{ + serial_putcmd(VT100_RMACS); +} + +/** + * Set the foreground and background colors on the serial console. + * + * @param fg Foreground color number. + * @param bg Background color number. + */ +void serial_set_color(short fg, short bg) +{ + char buffer[32]; + snprintf(buffer, sizeof(buffer), VT100_SET_COLOR, fg, bg); + serial_putcmd(buffer); +} + +void serial_set_cursor(int y, int x) +{ + char buffer[32]; + snprintf(buffer, sizeof(buffer), VT100_CURSOR_ADDR, y + 1, x + 1); + serial_putcmd(buffer); +} + +void serial_cursor_enable(int state) +{ + if (state) + serial_putcmd(VT100_CURSOR_ON); + else + serial_putcmd(VT100_CURSOR_OFF); +} diff --git a/payloads/libpayload/drivers/serial/s5p.c b/payloads/libpayload/drivers/serial/s5p.c new file mode 100644 index 0000000..1d23352 --- /dev/null +++ b/payloads/libpayload/drivers/serial/s5p.c @@ -0,0 +1,106 @@ +/* + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> +#include <stdint.h> + +struct s5p_uart +{ + uint32_t ulcon; // line control + uint32_t ucon; // control + uint32_t ufcon; // FIFO control + uint32_t umcon; // modem control + uint32_t utrstat; // Tx/Rx status + uint32_t uerstat; // Rx error status + uint32_t ufstat; // FIFO status + uint32_t umstat; // modem status + uint32_t utxh; // transmit buffer + uint32_t urxh; // receive buffer + uint32_t ubrdiv; // baud rate divisor + uint32_t ufracval; // divisor fractional value + uint32_t uintp; // interrupt pending + uint32_t uints; // interrupt source + uint32_t uintm; // interrupt mask +}; + +static struct s5p_uart *uart_regs; + +void serial_putchar(unsigned int c) +{ + const uint32_t TxFifoFullBit = (0x1 << 24); + + while (readl(&uart_regs->ufstat) & TxFifoFullBit) + {;} + + writeb(c, &uart_regs->utxh); + if (c == '\n') + serial_putchar('\r'); +} + +int serial_havechar(void) +{ + const uint32_t DataReadyMask = (0xf << 0) | (0x1 << 8); + + return (readl(&uart_regs->ufstat) & DataReadyMask) != 0; +} + +int serial_getchar(void) +{ + while (!serial_havechar()) + {;} + + return readb(&uart_regs->urxh); +} + +static struct console_output_driver s5p_serial_output = +{ + .putchar = &serial_putchar +}; + +static struct console_input_driver s5p_serial_input = +{ + .havekey = &serial_havechar, + .getchar = &serial_getchar +}; + +void serial_init(void) +{ + if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) + return; + + uart_regs = (struct s5p_uart *)lib_sysinfo.serial->baseaddr; +} + +void serial_console_init(void) +{ + serial_init(); + + if (uart_regs) { + console_add_output_driver(&s5p_serial_output); + console_add_input_driver(&s5p_serial_input); + } +} diff --git a/payloads/libpayload/drivers/serial/tegra.c b/payloads/libpayload/drivers/serial/tegra.c new file mode 100644 index 0000000..bcf7b19 --- /dev/null +++ b/payloads/libpayload/drivers/serial/tegra.c @@ -0,0 +1,111 @@ +/* + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> +#include <stdint.h> + +struct tegra_uart { + union { + uint32_t thr; // Transmit holding register. + uint32_t rbr; // Receive buffer register. + uint32_t dll; // Divisor latch lsb. + }; + union { + uint32_t ier; // Interrupt enable register. + uint32_t dlm; // Divisor latch msb. + }; + union { + uint32_t iir; // Interrupt identification register. + uint32_t fcr; // FIFO control register. + }; + uint32_t lcr; // Line control register. + uint32_t mcr; // Modem control register. + uint32_t lsr; // Line status register. + uint32_t msr; // Modem status register. +} __attribute__ ((packed)); + +enum { + TEGRA_UART_LSR_DR = 0x1 << 0, // Data ready. + TEGRA_UART_LSR_OE = 0x1 << 1, // Overrun. + TEGRA_UART_LSR_PE = 0x1 << 2, // Parity error. + TEGRA_UART_LSR_FE = 0x1 << 3, // Framing error. + TEGRA_UART_LSR_BI = 0x1 << 4, // Break. + TEGRA_UART_LSR_THRE = 0x1 << 5, // Xmit holding register empty. + TEGRA_UART_LSR_TEMT = 0x1 << 6, // Xmitter empty. + TEGRA_UART_LSR_ERR = 0x1 << 7 // Error. +}; + +static struct tegra_uart *uart_regs; + +void serial_putchar(unsigned int c) +{ + while (!(readb(&uart_regs->lsr) & TEGRA_UART_LSR_THRE)); + writeb(c, &uart_regs->thr); +} + +int serial_havechar(void) +{ + uint8_t lsr = readb(&uart_regs->lsr); + return (lsr & TEGRA_UART_LSR_DR) == TEGRA_UART_LSR_DR; +} + +int serial_getchar(void) +{ + while (!serial_havechar()) + {;} + + return readb(&uart_regs->rbr); +} + +static struct console_output_driver tegra_serial_output = +{ + .putchar = &serial_putchar +}; + +static struct console_input_driver tegra_serial_input = +{ + .havekey = &serial_havechar, + .getchar = &serial_getchar +}; + +void serial_init(void) +{ + if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) + return; + + uart_regs = (struct tegra_uart *)lib_sysinfo.serial->baseaddr; +} + +void serial_console_init(void) +{ + serial_init(); + + if (uart_regs) { + console_add_output_driver(&tegra_serial_output); + console_add_input_driver(&tegra_serial_input); + } +}

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New patch to review for coreboot: c42707a libpayload: usb: Remove automatic clear_stall() calls from transfers
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7223 -gerrit commit c42707a3a18908fbf161a803ae65d7c616dd1084 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Apr 8 13:37:39 2014 -0700 libpayload: usb: Remove automatic clear_stall() calls from transfers We've recently fixed a problem where an external hard drive would choke due to one too many CLEAR_FEATURE(HALT) commands in the XHCI stack with "libpayload: usb: xhci: Fix STALL endpoint handling". Clearing stall conditions from within the transfer function is wrong in general... this is really something that is host controller agnostic and should be left to the higher-level driver to decide. The mass storage driver (the only one that should really encounter stalls right now) already contains the proper amount of clear_stall() calls... any more than that is redundant and as we found out potentially dangerous. This patch removes automatic clear stalls from UHCI and OHCI drivers as well to make things consistent between host controllers. BUG=chromium:192866 TEST=None. I could borrow the original hard drive from Shawn and compile a Snow to only use the OHCI driver to reproduce/verify this, but alas, I am lazy (and it's really not that important). Original-Change-Id: Ie1e4d4d2d70fa4abf8b4dabd33b10d6d4012048a Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193732 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit d46e183f3e7e0b0130becdefa6fd3ef8097df54b) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ie8f4ab3db8ec0d9a2d1e91c62967833e59c46700 --- payloads/libpayload/drivers/usb/ohci.c | 3 +-- payloads/libpayload/drivers/usb/uhci.c | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 143f738..3aa7810 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -602,8 +602,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize) result = dalen - result; if (ep->direction == IN && data != src) memcpy(src, data, result); - } else - clear_stall(ep); + } return result; } diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index 2e3249e..cdba3de 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -452,8 +452,6 @@ uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize) size -= maxpsize; } if (run_schedule (ep->dev, tds) == 1) { - usb_debug("Stalled. Trying to clean up.\n"); - clear_stall (ep); free (tds); return -1; }

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New patch to review for coreboot: 0c4d63c libpayload: usb: Fix up usb_shutdown() code paths
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7222 -gerrit commit 0c4d63c85b84469dff95158bdbbb3e7d69162308 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Apr 8 12:54:25 2014 -0700 libpayload: usb: Fix up usb_shutdown() code paths This patch combines a few minor fixes and refactoring to the various host controller and root hub drivers to ensure they all do the right thing on a call to usb_exit(). It puts a usb_detach_device(0) call into detach_controller() so that the HCD doesn't need to remember to tear down the root hub itself, and makes sure all root hubs properly detach the subtree of devices connected to their ports first (as generic_hub and by extension XHCI had already been doing). It also fixes up some missing free() calls and replaces most 'ptr = malloc(); if (!ptr) fatal()' idioms with the new x(z)alloc(). BUG=chromium:343415 TEST=Tested EHCI on Big and OHCI, EHCI, and XHCI on Snow. Could not test UHCI (unless anyone volunteers to port coreboot to a ZGB? ;) ), but the changes are really tame. Original-Change-Id: I6eca51ff2685d0946fe4267ad7d3ec48ad7fc510 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193731 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 5791b546e5a21a360d0c65888a5b92d5f48f8178) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I00138f0aeceb12ed721f7368c7788c9b6bee227d --- payloads/libpayload/drivers/usb/ehci.c | 28 +++++++++------------------- payloads/libpayload/drivers/usb/ehci_rh.c | 16 +++++++++++++--- payloads/libpayload/drivers/usb/ohci.c | 20 ++++---------------- payloads/libpayload/drivers/usb/ohci_rh.c | 12 +++++++----- payloads/libpayload/drivers/usb/uhci.c | 15 +-------------- payloads/libpayload/drivers/usb/uhci_rh.c | 6 +++--- payloads/libpayload/drivers/usb/usb.c | 15 ++++++--------- payloads/libpayload/drivers/usb/xhci.c | 23 +++++------------------ 8 files changed, 48 insertions(+), 87 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 0c3e32d..b83712c 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -176,16 +176,17 @@ static int ehci_set_periodic_schedule(ehci_t *ehcic, int enable) static void ehci_shutdown (hci_t *controller) { detach_controller(controller); + /* Make sure periodic schedule is disabled */ ehci_set_periodic_schedule(EHCI_INST(controller), 0); - /* Free periodic frame list */ - free(phys_to_virt(EHCI_INST(controller)->operation->periodiclistbase)); - - /* Free dummy QH */ - free((void *)EHCI_INST(controller)->dummy_qh); + /* Give all ports back to companion controller */ EHCI_INST(controller)->operation->configflag = 0; + /* Free all dynamic allocations */ + free(EHCI_INST(controller)->dma_buffer); + free(phys_to_virt(EHCI_INST(controller)->operation->periodiclistbase)); + free((void *)EHCI_INST(controller)->dummy_qh); free(EHCI_INST(controller)); free(controller); } @@ -788,16 +789,8 @@ ehci_init (unsigned long physical_bar) { int i; hci_t *controller = new_controller (); - - if (!controller) - fatal("Could not create USB controller instance.\n"); - - controller->instance = malloc (sizeof (ehci_t)); - if(!controller->instance) - fatal("Not enough memory creating USB controller instance.\n"); - + controller->instance = xzalloc(sizeof (ehci_t)); controller->type = EHCI; - controller->start = ehci_start; controller->stop = ehci_stop; controller->reset = ehci_reset; @@ -811,13 +804,10 @@ ehci_init (unsigned long physical_bar) controller->create_intr_queue = ehci_create_intr_queue; controller->destroy_intr_queue = ehci_destroy_intr_queue; controller->poll_intr_queue = ehci_poll_intr_queue; - for (i = 0; i < 128; i++) { - controller->devices[i] = 0; - } init_device_entry (controller, 0); - EHCI_INST(controller)->capabilities = phys_to_virt(physical_bar); - EHCI_INST(controller)->operation = (hc_op_t *)(phys_to_virt(physical_bar) + EHCI_INST(controller)->capabilities->caplength); + EHCI_INST(controller)->capabilities = phys_to_virt(controller->reg_base); + EHCI_INST(controller)->operation = (hc_op_t *)(phys_to_virt(controller->reg_base) + EHCI_INST(controller)->capabilities->caplength); /* Set the high address word (aka segment) if controller is 64-bit */ if (EHCI_INST(controller)->capabilities->hccparams & 1) diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index 67f63cc..6109505 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -48,6 +48,17 @@ typedef struct { static void ehci_rh_destroy (usbdev_t *dev) { + int port; + + /* Tear down all devices below the root hub (in bottom-up order). */ + for (port = 0; port < RH_INST(dev)->n_ports; port++) { + if (RH_INST(dev)->devices[port] != -1) { + usb_detach_device(dev->controller, + RH_INST(dev)->devices[port]); + RH_INST(dev)->devices[port] = -1; + } + } + free (RH_INST(dev)->devices); free (RH_INST(dev)); } @@ -156,10 +167,10 @@ ehci_rh_init (usbdev_t *dev) dev->destroy = ehci_rh_destroy; dev->poll = ehci_rh_poll; - dev->data = malloc(sizeof(rh_inst_t)); - + dev->data = xmalloc(sizeof(rh_inst_t)); RH_INST(dev)->n_ports = EHCI_INST(dev->controller)->capabilities->hcsparams & HCS_NPORTS_MASK; RH_INST(dev)->ports = EHCI_INST(dev->controller)->operation->portsc; + RH_INST(dev)->devices = xmalloc(RH_INST(dev)->n_ports * sizeof(int)); usb_debug("root hub has %x ports\n", RH_INST(dev)->n_ports); @@ -175,7 +186,6 @@ ehci_rh_init (usbdev_t *dev) } mdelay(20); // ehci spec 2.3.9 - RH_INST(dev)->devices = malloc(RH_INST(dev)->n_ports * sizeof(int)); for (i=0; i < RH_INST(dev)->n_ports; i++) { RH_INST(dev)->devices[i] = -1; ehci_rh_scanport(dev, i); diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index e1664cc..143f738 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -172,16 +172,8 @@ ohci_init (unsigned long physical_bar) int i; hci_t *controller = new_controller (); - - if (!controller) - fatal("Could not create USB controller instance.\n"); - - controller->instance = malloc (sizeof (ohci_t)); - if(!controller->instance) - fatal("Not enough memory creating USB controller instance.\n"); - + controller->instance = xzalloc(sizeof (ohci_t)); controller->type = OHCI; - controller->start = ohci_start; controller->stop = ohci_stop; controller->reset = ohci_reset; @@ -195,9 +187,6 @@ ohci_init (unsigned long physical_bar) controller->create_intr_queue = ohci_create_intr_queue; controller->destroy_intr_queue = ohci_destroy_intr_queue; controller->poll_intr_queue = ohci_poll_intr_queue; - for (i = 0; i < 128; i++) { - controller->devices[i] = 0; - } init_device_entry (controller, 0); OHCI_INST (controller)->roothub = controller->devices[0]; @@ -279,8 +268,7 @@ ohci_shutdown (hci_t *controller) return; detach_controller (controller); ohci_stop(controller); - OHCI_INST (controller)->roothub->destroy (OHCI_INST (controller)-> - roothub); + free (OHCI_INST (controller)->hcca); free ((void *)OHCI_INST (controller)->periodic_ed); free (OHCI_INST (controller)); free (controller); @@ -289,13 +277,13 @@ ohci_shutdown (hci_t *controller) static void ohci_start (hci_t *controller) { -// TODO: turn on all operation of OHCI, but assume that it's initialized. + OHCI_INST (controller)->opreg->HcControl |= PeriodicListEnable; } static void ohci_stop (hci_t *controller) { -// TODO: turn off all operation of OHCI + OHCI_INST (controller)->opreg->HcControl &= ~PeriodicListEnable; } static int diff --git a/payloads/libpayload/drivers/usb/ohci_rh.c b/payloads/libpayload/drivers/usb/ohci_rh.c index b3bf7ef..5d82bd5 100644 --- a/payloads/libpayload/drivers/usb/ohci_rh.c +++ b/payloads/libpayload/drivers/usb/ohci_rh.c @@ -83,6 +83,11 @@ ohci_rh_enable_port (usbdev_t *dev, int port) static void ohci_rh_disable_port (usbdev_t *dev, int port) { + if (RH_INST (dev)->port[port] != -1) { + usb_detach_device(dev->controller, RH_INST (dev)->port[port]); + RH_INST (dev)->port[port] = -1; + } + OHCI_INST (dev->controller)->opreg->HcRhPortStatus[port] = ClearPortEnable; // disable port int timeout = 50; /* timeout after 50 * 100us == 5ms */ while ((OHCI_INST (dev->controller)->opreg->HcRhPortStatus[port] @@ -180,12 +185,9 @@ ohci_rh_init (usbdev_t *dev) dev->destroy = ohci_rh_destroy; dev->poll = ohci_rh_poll; - dev->data = malloc (sizeof (rh_inst_t)); - if (!dev->data) - fatal("Not enough memory for OHCI RH.\n"); - + dev->data = xmalloc (sizeof (rh_inst_t)); RH_INST (dev)->numports = OHCI_INST (dev->controller)->opreg->HcRhDescriptorA & NumberDownstreamPortsMask; - RH_INST (dev)->port = malloc(sizeof(int) * RH_INST (dev)->numports); + RH_INST (dev)->port = xmalloc(sizeof(int) * RH_INST (dev)->numports); usb_debug("%d ports registered\n", RH_INST (dev)->numports); for (i = 0; i < RH_INST (dev)->numports; i++) { diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index 3eff612..2e3249e 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -153,16 +153,8 @@ uhci_pci_init (pcidev_t addr) u16 reg16; hci_t *controller = new_controller (); - - if (!controller) - fatal("Could not create USB controller instance.\n"); - - controller->instance = malloc (sizeof (uhci_t)); - if(!controller->instance) - fatal("Not enough memory creating USB controller instance.\n"); - + controller->instance = xzalloc(sizeof (uhci_t)); controller->type = UHCI; - controller->start = uhci_start; controller->stop = uhci_stop; controller->reset = uhci_reset; @@ -176,9 +168,6 @@ uhci_pci_init (pcidev_t addr) controller->create_intr_queue = uhci_create_intr_queue; controller->destroy_intr_queue = uhci_destroy_intr_queue; controller->poll_intr_queue = uhci_poll_intr_queue; - for (i = 0; i < 128; i++) { - controller->devices[i] = 0; - } init_device_entry (controller, 0); UHCI_INST (controller)->roothub = controller->devices[0]; @@ -257,8 +246,6 @@ uhci_shutdown (hci_t *controller) if (controller == 0) return; detach_controller (controller); - UHCI_INST (controller)->roothub->destroy (UHCI_INST (controller)-> - roothub); uhci_reg_write16(controller, USBCMD, uhci_reg_read16(controller, USBCMD) & 0); // stop work free (UHCI_INST (controller)->framelistptr); diff --git a/payloads/libpayload/drivers/usb/uhci_rh.c b/payloads/libpayload/drivers/usb/uhci_rh.c index 5cb18b9..4668c4e 100644 --- a/payloads/libpayload/drivers/usb/uhci_rh.c +++ b/payloads/libpayload/drivers/usb/uhci_rh.c @@ -176,6 +176,8 @@ uhci_rh_report_port_changes (usbdev_t *dev) static void uhci_rh_destroy (usbdev_t *dev) { + usb_detach_device (dev->controller, 1); + usb_detach_device (dev->controller, 2); uhci_rh_disable_port (dev, 1); uhci_rh_disable_port (dev, 2); free (RH_INST (dev)); @@ -197,9 +199,7 @@ uhci_rh_init (usbdev_t *dev) uhci_rh_enable_port (dev, 1); uhci_rh_enable_port (dev, 2); - dev->data = malloc (sizeof (rh_inst_t)); - if (!dev->data) - fatal("Not enough memory for UHCI RH.\n"); + dev->data = xmalloc (sizeof (rh_inst_t)); RH_INST (dev)->port[0] = -1; RH_INST (dev)->port[1] = -1; diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 4f21e0c..eb23760 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -39,15 +39,9 @@ hci_t *usb_hcs = 0; hci_t * new_controller (void) { - hci_t *controller = malloc (sizeof (hci_t)); - - if (controller) { - /* atomic */ - controller->next = usb_hcs; - usb_hcs = controller; - /* atomic end */ - } - + hci_t *controller = xzalloc(sizeof (hci_t)); + controller->next = usb_hcs; + usb_hcs = controller; return controller; } @@ -56,6 +50,9 @@ detach_controller (hci_t *controller) { if (controller == NULL) return; + + usb_detach_device(controller, 0); /* tear down root hub tree */ + if (usb_hcs == controller) { usb_hcs = controller->next; } else { diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 2331485..2d2db31 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -150,11 +150,6 @@ xhci_init (unsigned long physical_bar) /* First, allocate and initialize static controller structures */ hci_t *const controller = new_controller(); - if (!controller) { - xhci_debug("Could not create USB controller instance\n"); - return controller; - } - controller->type = XHCI; controller->start = xhci_start; controller->stop = xhci_stop; @@ -170,17 +165,10 @@ xhci_init (unsigned long physical_bar) controller->destroy_intr_queue = xhci_destroy_intr_queue; controller->poll_intr_queue = xhci_poll_intr_queue; controller->pcidev = 0; - for (i = 0; i < 128; ++i) { - controller->devices[i] = NULL; - } - controller->instance = malloc(sizeof(xhci_t)); - if (!controller->instance) { - xhci_debug("Out of memory creating xHCI controller instance\n"); - goto _free_controller; - } + controller->reg_base = (u32)bar; + controller->instance = xzalloc(sizeof(xhci_t)); xhci_t *const xhci = (xhci_t *)controller->instance; - memset(xhci, 0x00, sizeof(*xhci)); init_device_entry(controller, 0); xhci->roothub = controller->devices[0]; @@ -282,6 +270,7 @@ xhci_init (unsigned long physical_bar) return controller; _free_xhci_structs: + free(xhci->dma_buffer); if (xhci->sp_ptrs) { for (i = 0; i < max_sp_bufs; ++i) { if (xhci->sp_ptrs[i]) @@ -410,13 +399,10 @@ xhci_shutdown(hci_t *const controller) if (controller == 0) return; - xhci_t *const xhci = XHCI_INST(controller); detach_controller(controller); - /* Detach device hierarchy (starting at root hub) */ - usb_detach_device(controller, 0); - + xhci_t *const xhci = XHCI_INST(controller); xhci_stop(controller); if (controller->pcidev) @@ -430,6 +416,7 @@ xhci_shutdown(hci_t *const controller) } } free(xhci->sp_ptrs); + free(xhci->dma_buffer); free(xhci->dcbaa); free(xhci->dev); free((void *)xhci->ev_ring_table);

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New patch to review for coreboot: 49e7eed libpayload: usb: ehci: Honor 10ms reset recovery period
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7221 -gerrit commit 49e7eed3e8837fd2525d571bd66c262afd4ede48 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Apr 2 17:28:46 2014 -0700 libpayload: usb: ehci: Honor 10ms reset recovery period This patch adds the 10ms TRSTRCY delay between a reset and the following Set Address command that is required by the USB 2.0 specification to the EHCI root hub driver. The generic_hub driver that's used for XHCI and external hubs already included this delay. This is such a glaring violation of the spec that I'm really amazed how many USB 2.0 devices we tested before seemed perfectly fine with responding to a Set Address within 2 microframes of the reset... It also increases the port reset hold delay by one millisecond to avoid an ugly race condition on Tegra SoCs: they decided to time the 50ms themselves instead of relying on the CPU to do it (fair enough), and to automatically transition Port Reset to 0 and Port Enable to 1 after that (bad idea). If the CPU's read-modify-write to clear Port Reset races exactly with the host controller setting Port Enable, we may end up clearing the bit again and going into the companion controller handoff path later on. The added millisecond shouldn't cause any problems for other host controllers and is not a big deal compared to other delays in this code path. BUG=chrome-os-partner:26749 TEST=Run several dozen reboot loops with The USB Stick of Death (TM) (a blue Patriot XT 13fe:5200 with bcdDevice = 1.00), make sure it always gets detected correctly. Original-Change-Id: Idd3329ae6d7e5e1c07a84a5475549b3459836b31 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/189872 Original-Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Original-Reviewed-by: Jim Lin <jilin(a)nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> (cherry picked from commit 4deca38e9d79f6373f4418fcaf51a6945232c8b8) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I68a29bfd2e0f30409fbfc330b2575f0f9f61a79d --- payloads/libpayload/drivers/usb/ehci_rh.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index 5c4daed..67f63cc 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -98,8 +98,8 @@ ehci_rh_scanport (usbdev_t *dev, int port) */ RH_INST(dev)->ports[port] = (RH_INST(dev)->ports[port] & ~P_PORT_ENABLE) | P_PORT_RESET; - /* Wait a bit while reset is active. */ - mdelay(50); // usb20 spec 7.1.7.5 (TDRSTR) + /* Wait a bit while reset is active (+1 to avoid Tegra race). */ + mdelay(50 + 1); // usb20 spec 7.1.7.5 (TDRSTR) /* Deassert reset. */ RH_INST(dev)->ports[port] &= ~P_PORT_RESET; @@ -113,6 +113,8 @@ ehci_rh_scanport (usbdev_t *dev, int port) return; } + mdelay(10); /* TRSTRCY (USB 2.0 spec 7.1.7.5) */ + /* If the host controller enabled the port, it's a high-speed * device, otherwise it's full-speed. */

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New patch to review for coreboot: 397e838 vboot: allow non-relocatable ramstage loading
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7220 -gerrit commit 397e83838f466715b8e789389e387c72f20d1a1d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 20 15:24:03 2014 -0500 vboot: allow non-relocatable ramstage loading The vboot implementation previously assumed that ramstage would be a relocatable module. Allow for ramstage not being a relocatable module. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built nyan with vboot. Original-Change-Id: Id3544533740d77e2db6be3960bef0c129173bacc Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190923 Original-Reviewed-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 756ee3a6987097c65588c8784ee9653fd6e735e4) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I813b07e1bec75640ad4066aca749ba8dccec31d4 --- src/lib/Makefile.inc | 3 +- src/vendorcode/google/chromeos/Kconfig | 1 + src/vendorcode/google/chromeos/vboot_loader.c | 57 +++++++++++++++++++++++++++ 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index c104ce3..fe4455b 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -101,7 +101,8 @@ ramstage-y += bootmode.c ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c -romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c +# Include rmodule.c in romstage if vboot verification is selected. +romstage-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += rmodule.c RMODULE_LDSCRIPT := $(src)/lib/rmodule.ld RMODULE_LDFLAGS := -nostartfiles -Wl,--emit-relocs -Wl,-z,defs -Wl,-Bsymbolic -Wl,-T,$(RMODULE_LDSCRIPT) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index a1a9d9a..8156758 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -80,6 +80,7 @@ config FLASHMAP_OFFSET config VBOOT_VERIFY_FIRMWARE bool "Verify firmware with vboot." default n + select RELOCATABLE_MODULES help Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the ramstage and boot loader. diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 2f786ad..cfdc5af 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -141,6 +141,7 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) vboot_run_stub(&context); } +#if CONFIG_RELOCATABLE_RAMSTAGE static void *vboot_load_ramstage(uint32_t cbmem_id, const char *name, const struct cbmem_entry **cbmem_entry) { @@ -204,6 +205,62 @@ static void *vboot_load_ramstage(uint32_t cbmem_id, const char *name, return rmod_load.entry; } +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ +static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, + struct romstage_handoff *handoff) +{ + struct cbfs_stage *stage; + const struct firmware_component *fwc; + + if (CONFIG_VBOOT_RAMSTAGE_INDEX >= MAX_PARSED_FW_COMPONENTS) { + printk(BIOS_ERR, "Invalid ramstage index: %d\n", + CONFIG_VBOOT_RAMSTAGE_INDEX); + return; + } + + /* Check for invalid address. */ + fwc = &vboot_handoff->components[CONFIG_VBOOT_RAMSTAGE_INDEX]; + if (fwc->address == 0) { + printk(BIOS_DEBUG, "RW ramstage image address invalid.\n"); + return; + } + + printk(BIOS_DEBUG, "RW ramstage image at 0x%08x, 0x%08x bytes.\n", + fwc->address, fwc->size); + + stage = vboot_get_region(fwc->address, fwc->size); + + if (stage == NULL) { + printk(BIOS_DEBUG, "Unable to get RW ramstage region.\n"); + return; + } + + timestamp_add_now(TS_START_COPYRAM); + + /* Stages rely the below clearing so that the bss is initialized. */ + memset((void *) (uintptr_t) stage->load, 0, stage->memlen); + + if (cbfs_decompress(stage->compression, + ((unsigned char *) stage) + + sizeof(struct cbfs_stage), + (void *) (uintptr_t) stage->load, + stage->len)) + return; + + timestamp_add_now(TS_END_COPYRAM); + +#if CONFIG_ARCH_X86 + __asm__ volatile ( + "movl $0, %%ebp\n" + "jmp *%%edi\n" + :: "D"(stage->entry) + ); +#elif CONFIG_ARCH_ARM + stage_exit((void *)(uintptr_t)stage->entry); +#endif +} +#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ + const struct ramstage_loader_ops vboot_ramstage_loader = { .name = "VBOOT",

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Patch merged into coreboot/master: 3e72ecf cpu/x86/smm/Makefile.inc: Correct SMM linkage under clang builds
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit 3e72ecfd3503553c6cdf3f1c56466f6524d57f1e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 14:51:30 2014 +1000 cpu/x86/smm/Makefile.inc: Correct SMM linkage under clang builds Ensure that the SMM build stage links properly using the compiler-rt runtime under a Clang build. Change-Id: Iead28c46d63f5bbb27757b7dc66fe06b4813d03c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6462 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/6462 for details. -gerrit

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Patch merged into coreboot/master: dd91c7f build: Allow clang build linkage to use libcompiler-rt
by gerrit＠coreboot.org 28 Oct '14

28 Oct '14

the following patch was just integrated into master: commit dd91c7f6d3538c0c86335dc256339f2330de5e0a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 03:02:52 2014 +1000 build: Allow clang build linkage to use libcompiler-rt Make use of '-print-librt-file-name' over '-print-libgcc-file-name' to use Compiler-RT runtime glue over libgcc glue. NOTE: *** Requires at least clang 3.6.x Change-Id: I7f63284473d6067bf775409970c8dd98f5d5a8d5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6144 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6144 for details. -gerrit

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New patch to review for coreboot: 87eb950 rambi: switch MCLK from 19.2Mhz to 25Mhz
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7219 -gerrit commit 87eb95004a9451f41401598c5f382079fbf454a0 Author: Kein Yuan <kein.yuan(a)intel.com> Date: Fri Apr 4 15:15:14 2014 -0700 rambi: switch MCLK from 19.2Mhz to 25Mhz With following settings 1.Coreboot 25Mhz 2.Maxim codec configured with MCLK=25Mhz 2.I2C 400Khz fixed 4.Including Enable/Disable SHDN bit when LRCLK starts/Stops 5.Removed PLL toggle workaround routine. audio playing is smooth before/after S3, no noise when recording so change MCLK from 19.2 back to 25Mhz. BUG=chrome-os-partner:26948 BRANCH=firmware-rambi-5216 TEST=test audio play and record on Rambi, works fine. Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6 Signed-off-by: Kein Yuan <kein.yuan(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/193881 Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/google/rambi/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 5587006..27dadca 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -24,7 +24,7 @@ chip soc/intel/baytrail register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" # LPE audio codec settings - register "lpe_codec_clk_freq" = "19" # 19.2MHz clock + register "lpe_codec_clk_freq" = "25" # 25MHz clock register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] # SD Card controller

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New patch to review for coreboot: be3f194 baytrail: Remove unused devicetree fields
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7218 -gerrit commit be3f1948821e88f00d635221d191bcbb6b65faf7 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Apr 9 12:45:57 2014 -0700 baytrail: Remove unused devicetree fields We're no longer configuring hotplug + backlight settings from devicetree, so remove these entries + fields. BUG=chrome-os-partner:27304 TEST=Compile only. BRANCH=rambi+squawks Change-Id: I7e27fbc070a9ea774e7dcbe551d61b1b1682a47f Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193831 (cherry picked from commit 4ab13fd3aa2634673bb099bdfd714a21adc3caa0) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/google/rambi/devicetree.cb | 2 -- src/soc/intel/baytrail/chip.h | 11 ----------- 2 files changed, 13 deletions(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 5d9eec5..5587006 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -40,14 +40,12 @@ chip soc/intel/baytrail register "pcie_wake_enable" = "1" # Enable PIPEA as DP_C - register "gpu_pipea_hotplug" = "6" # 6ms Pulse register "gpu_pipea_port_select" = "2" # DP_C register "gpu_pipea_power_cycle_delay" = "5" # 400ms register "gpu_pipea_power_on_delay" = "2000" # 200ms register "gpu_pipea_light_on_delay" = "10" # 1ms register "gpu_pipea_power_off_delay" = "500" # 50ms register "gpu_pipea_light_off_delay" = "2000" # 200ms - register "gpu_pipea_backlight_pwm" = "0x400" # VR PS2 control register "vnn_ps2_enable" = "1" diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 256ed4f..0860a96 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -72,30 +72,19 @@ struct soc_intel_baytrail_config { /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; - /* - * Digital Port Hotplug Enable: - * 0x04 = Enabled, 2ms short pulse - * 0x05 = Enabled, 4.5ms short pulse - * 0x06 = Enabled, 6ms short pulse - * 0x07 = Enabled, 100ms short pulse - */ - int gpu_pipea_hotplug; int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipea_power_on_delay; uint16_t gpu_pipea_light_on_delay; uint16_t gpu_pipea_power_off_delay; uint16_t gpu_pipea_light_off_delay; uint16_t gpu_pipea_power_cycle_delay; - uint32_t gpu_pipea_backlight_pwm; - int gpu_pipeb_hotplug; int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipeb_power_on_delay; uint16_t gpu_pipeb_light_on_delay; uint16_t gpu_pipeb_power_off_delay; uint16_t gpu_pipeb_light_off_delay; uint16_t gpu_pipeb_power_cycle_delay; - uint32_t gpu_pipeb_backlight_pwm; }; extern struct chip_operations soc_intel_baytrail_ops;

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New patch to review for coreboot: deb3ab5 baytrail: gfx: Don't configure hotplug + backlight registers
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7217 -gerrit commit deb3ab5c8e092baf466e519e5dd977720d4df160 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Apr 9 12:41:22 2014 -0700 baytrail: gfx: Don't configure hotplug + backlight registers - The hotplug register doesn't work in the way we describe. Just leave it at default. - The backlight registers will be configured by the OS driver. BUG=chrome-os-partner:27304 TEST=Manual on Rambi. Boot system in both dev and normal mode, verify that display comes up. Also verify that display functions after warm reboot and suspend / resume. BRANCH=rambi+squawks Change-Id: I5559c131f41c4a14e64e5cec66e18d3a4a46092c Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193830 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 3f287cc31e41fabef755c37361e2e65ca413c88c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/soc/intel/baytrail/gfx.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 4ed08c9..9d4768f 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -296,9 +296,6 @@ static void gfx_panel_setup(device_t dev) /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), - /* HOTPLUG */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(HOTPLUG_CTRL), - 0x1 | (config->gpu_pipea_hotplug << 2)), /* POWER ON */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), (config->gpu_pipea_port_select << 30 | @@ -311,21 +308,12 @@ static void gfx_panel_setup(device_t dev) /* DIVISOR */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), ~0x1f, config->gpu_pipea_power_cycle_delay), - /* BACKLIGHT */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL), - (config->gpu_pipea_backlight_pwm << 16) | - (config->gpu_pipea_backlight_pwm >> 1)), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL2), - BACKLIGHT_ENABLE), REG_SCRIPT_END }; struct reg_script gfx_pipeb_init[] = { /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), - /* HOTPLUG */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(HOTPLUG_CTRL), - 0x1 | (config->gpu_pipeb_hotplug << 2)), /* POWER ON */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), (config->gpu_pipeb_port_select << 30 | @@ -338,12 +326,6 @@ static void gfx_panel_setup(device_t dev) /* DIVISOR */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), ~0x1f, config->gpu_pipeb_power_cycle_delay), - /* BACKLIGHT */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL), - (config->gpu_pipeb_backlight_pwm << 16) | - (config->gpu_pipeb_backlight_pwm >> 1)), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL2), - BACKLIGHT_ENABLE), REG_SCRIPT_END };

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coreboot-gerrit October 2014