coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

1 participants
1026 discussions

New patch to review for coreboot: bf75e23 rambi: always show dev/rec screens on eDP connected panel
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7216 -gerrit commit bf75e231a1f3ad72750d04045fdc5f1e5b9c11f8 Author: Kein Yuan <kein.yuan(a)intel.com> Date: Tue Apr 1 10:13:38 2014 -0700 rambi: always show dev/rec screens on eDP connected panel bit: 7 6 5 4 3 2 1 0 LFP2 EFP2 EFP3 CRT2 LFP EFP TV CRT so int 15 0x5f35 need to return 0x8(LFP/eDP) instead of 0x2(TV). BUG=chrome-os-partner:26365 BUG=chrome-os-partner:27505 BRANCH=rambi TEST=Booted with and without HDMI connected monitor. DEV screen always showed on eDP panel on Rambi. Change-Id: I8f876e78383424f517689eb25e9229a27739957b Original-Change-Id: I77edbeb3c86549f90302b4296b5a2f50313ca675 Signed-off-by: Kein Yuan <kein.yuan(a)intle.com> Reviewed-on: https://chromium-review.googlesource.com/193303 Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit dd375462147f182331f336ba826108e58b4e0a47) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/google/rambi/mainboard.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 19579fb..cd3fc48 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -66,16 +66,16 @@ static int int15_handler(void) /* * Boot Display Device Hook: * bit 0 = CRT - * bit 1 = TV (eDP) * - * bit 2 = EFP - * bit 3 = LFP + * bit 1 = TV + * bit 2 = EFP (HDMI) + * bit 3 = LFP (eDP)* * bit 4 = CRT2 - * bit 5 = TV2 (eDP) + * bit 5 = TV2 * bit 6 = EFP2 * bit 7 = LFP2 */ X86_AX = 0x005f; - X86_CX = 0x0002; + X86_CX = 0x0008; res = 1; break; case 0x5f51:

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New patch to review for coreboot: 0866734 Baytrail/dptf: Always return 0 in TCPU._PPC
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7215 -gerrit commit 086673447deeff9948c675124c30b3f779d74dca Author: Kein Yuan <kein.yuan(a)intel.com> Date: Wed Apr 2 16:29:52 2014 -0700 Baytrail/dptf: Always return 0 in TCPU._PPC According to DPTF team _PPC in TCPU must return 0 always. BUG=chromium:355964 TEST=Pass build. BRANCH=rambi Change-Id: I76f0da27757ba4717f0e392bcd80e890d925061a Original-Change-Id: I8b9e17e5479e8a226cb11cd43ce888a3e4dead73 Signed-off-by: Kein Yuan <kein.yuan(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/193069 Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit 6dbcc677ceebbaf832e41e6db1e6cf171e2e231f) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/soc/intel/baytrail/acpi/dptf/cpu.asl | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl index 87f1d19..3cbfc5f 100644 --- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -2,7 +2,6 @@ External (\_PR.CPU0._TSS, MethodObj) External (\_PR.CPU0._TPC, MethodObj) External (\_PR.CPU0._PTC, PkgObj) External (\_PR.CPU0._TSD, PkgObj) -External (\_PR.CPU0._PPC, MethodObj) External (\_PR.CPU0._PSS, MethodObj) Device (TCPU) @@ -86,11 +85,7 @@ Device (TCPU) Method (_PPC) { - If (CondRefOf (\_PR.CPU0._PPC)) { - Return (\_PR.CPU0._PPC) - } Else { - Return (0) - } + Return (0) } Method (SPPC, 1)

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New patch to review for coreboot: 8efd704 baytrail: handle MRC being an ELF file
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7214 -gerrit commit 8efd704f7b93c302a6c8319a4fdb3e996092ff8b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Apr 2 20:46:13 2014 -0500 baytrail: handle MRC being an ELF file Provide the option to embed MRC as an ELF file and not just binary blob. This allows for MRC to be relocated. BUG=chrome-os-partner:27654 BRANCH=rambi TEST=Built and booted rambi. Change-Id: I2e177c155a3074e4e1d450b1a73b7299aebd5286 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192893 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit 89c97d5e2023b8c5cc780e1b1d532d0a586512f9) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/soc/intel/baytrail/Makefile.inc | 8 +++++++- src/soc/intel/baytrail/romstage/raminit.c | 15 +++++++++++---- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 94f3241..464b639 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -88,10 +88,16 @@ ifeq ($(CONFIG_HAVE_ME_BIN),y) mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif +# If an MRC file is an ELF file determine the entry address and first loadable +# section offset in the file. Subtract the offset from the entry address to +# determine the final location. +mrcelfoffset = $(shell readelf -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' ) +mrcelfentry = $(shell readelf -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }') + # Add memory reference code blob. cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) -mrc.bin-position := $(CONFIG_MRC_BIN_ADDRESS) +mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) mrc.bin-type := 0xab PHONY += baytrail_add_me diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index d5ee031..72d8e51 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -146,13 +146,20 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) #endif } - mrc_entry = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, - NULL); - - if (mrc_entry == NULL) { + /* Determine if mrc.bin is in the cbfs. */ + if (cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL) == + NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; } + + /* + * The entry point is currently the first instruction. Handle the + * case of an ELF file being put in the cbfs by setting the entry + * to the CONFIG_MRC_BIN_ADDRESS. + */ + mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; + if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) enable_smbus();

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New patch to review for coreboot: c12a381 baytrail: Configure MSR for 2-core and 4-core P-state configutation
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7213 -gerrit commit c12a38117dc1f68e82863d78a21cb8385a354d38 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 28 10:52:13 2014 -0700 baytrail: Configure MSR for 2-core and 4-core P-state configutation Suggested settings to try for performace regression: 2-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFE (HW_ALL) 4-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFC (SW_ALL) BUG=chrome-os-partner:26211 BRANCH=baytrail TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib68a86525204ae47a820c269257a7b8df9300a6a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192573 Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit 8c8c0be0000043610eaa56926eff978f352819b8) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/soc/intel/baytrail/acpi.c | 3 +-- src/soc/intel/baytrail/cpu.c | 32 ++++---------------------------- 2 files changed, 5 insertions(+), 30 deletions(-) diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 67e8c0c..aae0c99 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -354,8 +354,7 @@ static int generate_P_state_entries(int core, int cores_per_package) vid_min = pattrs->iacore_vids[IACORE_LFM]; /* Set P-states coordination type based on MSR disable bit */ - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - coord_type = (msr.lo & SINGLE_PCTL) ? SW_ALL : HW_ALL; + coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL; /* Max Non-Turbo Frequency */ clock_max = (ratio_max * pattrs->bclk_khz) / 1000; diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 97d1f04..e8f95ae 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -68,37 +68,16 @@ const struct reg_script package_msr_script[] = { /* Core level MSRs */ const struct reg_script core_msr_script[] = { - /* Dynamic L2 shrink enable and threshold */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), + /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ + REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), + REG_MSR_RMW(MSR_POWER_MISC, + ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), REG_MSR_OR(MSR_POWER_MISC, 0x44), REG_SCRIPT_END }; -/* Enable hardware coordination for 2-core, disable for 4-core */ -static void baytrail_set_pstate_coord(void) -{ - const struct pattrs *pattrs = pattrs_get(); - msr_t pmg_cst = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - msr_t power_misc = rdmsr(MSR_POWER_MISC); - - if (pattrs->num_cpus > 2) { - /* Disable hardware coordination */ - pmg_cst.lo |= SINGLE_PCTL; - power_misc.lo &= ~(ENABLE_ULFM_AUTOCM_MASK | - ENABLE_INDP_AUTOCM_MASK); - } else { - /* Enable hardware coordination */ - pmg_cst.lo &= ~SINGLE_PCTL; - power_misc.lo |= (ENABLE_ULFM_AUTOCM_MASK | - ENABLE_INDP_AUTOCM_MASK); - } - - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, pmg_cst); - wrmsr(MSR_POWER_MISC, power_misc); -} - void baytrail_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; @@ -156,9 +135,6 @@ static void baytrail_core_init(device_t cpu) /* Set core MSRs */ reg_script_run(core_msr_script); - /* Set P-State coordination */ - baytrail_set_pstate_coord(); - /* Set this core to max frequency ratio */ set_max_freq(); }

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New patch to review for coreboot: a39ce9d baytrail: move cache-as-ram base address to 0xfe000000
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7212 -gerrit commit a39ce9d4c4c20321be25364d2e347eba9ae170d8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Mar 19 11:48:33 2014 -0500 baytrail: move cache-as-ram base address to 0xfe000000 Moving the cache-as-ram base address to 0xfe000000 will provide more breathing room in the physical address space. It will also allow for larger SPI roms in the future. BUG=chrome-os-partner:27045 BRANCH=baytrail CQ-DEPEND=CL:*157278 TEST=Built and booted. Suspended and resumes. Vboot works, MRC settings are being saved as well. Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190700 Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> (cherry picked from commit 73c07a319d678f3e9be2fac64599c94f91c9ad9c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/soc/intel/baytrail/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 3669c30..bc90b11 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -113,7 +113,7 @@ endif # HAVE_MRC config DCACHE_RAM_BASE hex - default 0xff800000 + default 0xfe000000 config DCACHE_RAM_SIZE hex

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New patch to review for coreboot: 2cbfc21 baytrail: romstage: Add function to check SW WP status for vboot
by Marc Jones 28 Oct '14

28 Oct '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7211 -gerrit commit 2cbfc214e4a66ac1be9ace72690245c9d2dc18ae Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Mar 14 14:06:45 2014 -0700 baytrail: romstage: Add function to check SW WP status for vboot Implement vboot_get_sw_write_protect, which returns the FW SPI ROM SW WP status. BUG=chrome-os-partner:26777 TEST=Manual on Rambi with all patches in sequence: `crossystem sw_wpsw_boot` prints 0 `flashrom --wp-enable` + reboot `crossystem sw_wpsw_boot` prints 1 BRANCH=Rambi Original-Change-Id: I5da35c1b2d25b8679bf0084af65d08de224387f8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190097 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 5bba447654417c42952c49542ed047b4867d04d1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I739cbb8fca5f02462cf78c81f9b364aabfd3fe86 --- src/soc/intel/baytrail/baytrail/romstage.h | 1 + src/soc/intel/baytrail/baytrail/spi.h | 7 +++ src/soc/intel/baytrail/romstage/Makefile.inc | 1 + src/soc/intel/baytrail/romstage/early_spi.c | 65 ++++++++++++++++++++++++++++ src/soc/intel/baytrail/romstage/romstage.c | 9 ++++ 5 files changed, 83 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/baytrail/romstage.h index 43c60ec..9ea3564 100644 --- a/src/soc/intel/baytrail/baytrail/romstage.h +++ b/src/soc/intel/baytrail/baytrail/romstage.h @@ -50,6 +50,7 @@ void gfx_init(void); void tco_disable(void); void punit_init(void); void set_max_freq(void); +int early_spi_read_wpsr(u8 *sr); #if CONFIG_ENABLE_BUILTIN_COM1 void byt_config_com1_and_enable(void); diff --git a/src/soc/intel/baytrail/baytrail/spi.h b/src/soc/intel/baytrail/baytrail/spi.h index 9c0c29d..ef71ad5 100644 --- a/src/soc/intel/baytrail/baytrail/spi.h +++ b/src/soc/intel/baytrail/baytrail/spi.h @@ -24,7 +24,14 @@ /* These registers live behind SPI_BASE_ADDRESS. */ #define HSFSTS 0x04 +#define FDATA0 0x10 # define FLOCKDN (0x1 << 15) +#define SSFS 0x90 +# define CYCLE_DONE_STATUS (0x1 << 2) +# define FLASH_CYCLE_ERROR (0x1 << 3) +#define SSFC 0x91 +# define SPI_CYCLE_GO (0x1 << 1) +# define DATA_CYCLE (0x1 << 14) #define PREOP 0x94 #define OPTYPE 0x96 #define OPMENU0 0x98 diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index b8eeb41..345037d 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c +romstage-y += early_spi.c \ No newline at end of file diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c new file mode 100644 index 0000000..6188f07 --- /dev/null +++ b/src/soc/intel/baytrail/romstage/early_spi.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <delay.h> +#include <console/console.h> + +#include <baytrail/iomap.h> +#include <baytrail/romstage.h> +#include <baytrail/spi.h> + +#define SPI_CYCLE_DELAY 10 /* 10us */ +#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ + +#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x)) +#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x)) +#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x)) + +/* Minimal set of commands to read wpsr from SPI. Don't use this code outside + * romstage -- it trashes the opmenu table. + * Returns 0 on success, < 0 on failure. */ +int early_spi_read_wpsr(u8 *sr) +{ + int timeout = SPI_CYCLE_TIMEOUT; + + /* No address associated with rdsr */ + SPI8(OPTYPE) = 0x0; + /* Setup opcode[0] = read wpsr */ + SPI8(OPMENU0) = 0x5; + + /* Start transaction */ + SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; + + /* Wait for error / complete status */ + while(timeout--) { + u16 status = SPI16(SSFS); + if (status & FLASH_CYCLE_ERROR) { + printk(BIOS_ERR, "SPI rdsr failed\n"); + return -1; + } else if (status & CYCLE_DONE_STATUS) + break; + + udelay(SPI_CYCLE_DELAY); + } + + *sr = SPI32(FDATA0) & 0xff; + return 0; +} diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 1c08f33..b69b532 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -393,3 +393,12 @@ void ramstage_cache_invalid(struct ramstage_cache *cache) cold_reset(); #endif } + +#if CONFIG_CHROMEOS +int vboot_get_sw_write_protect(void) +{ + u8 status; + /* Return unprotected status if status read fails. */ + return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80)); +} +#endif

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New patch to review for coreboot: 3a472ef mainboard/google/stout: Fix usage of GNU field designator ext
by Edward O'Callaghan 28 Oct '14

28 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7210 -gerrit commit 3a472ef7edfe17c92d36a3fcc7cb2a72ca8e9641 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 28 10:03:47 2014 +1100 mainboard/google/stout: Fix usage of GNU field designator ext Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Id5c5d68048169b0cd400926cead2d1835194d1a5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/google/stout/romstage.c | 54 +++++++++++++++++------------------ 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index bfa4af7..728d74d 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -161,32 +161,32 @@ void main(unsigned long bist) int cbmem_was_initted; struct pei_data pei_data = { - pei_version: PEI_VERSION, - mchbar: DEFAULT_MCHBAR, - dmibar: DEFAULT_DMIBAR, - epbar: DEFAULT_EPBAR, - pciexbar: CONFIG_MMCONF_BASE_ADDRESS, - smbusbar: SMBUS_IO_BASE, - wdbbar: 0x4000000, - wdbsize: 0x1000, - hpet_address: CONFIG_HPET_ADDRESS, - rcba: DEFAULT_RCBABASE, - pmbase: DEFAULT_PMBASE, - gpiobase: DEFAULT_GPIOBASE, - thermalbase: 0xfed08000, - system_type: 0, // 0 Mobile, 1 Desktop/Server - tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xA0, 0x00,0xA4,0x00 }, - ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, - ec_present: 1, + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - dimm_channel0_disabled: 2, - dimm_channel1_disabled: 2, - max_ddr3_freq: 1600, - usb_port_config: { + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { /* enabled usb oc pin length */ { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ @@ -203,11 +203,11 @@ void main(unsigned long bist) { 0, 5, 0x0000 }, /* P12: Empty */ { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */ }, - usb3: { - mode: XHCI_MODE, - hs_port_switch_mask: XHCI_PORTS, - preboot_support: XHCI_PREBOOT, - xhci_streams: XHCI_STREAMS, + .usb3 = { + .mode = XHCI_MODE, + .hs_port_switch_mask = XHCI_PORTS, + .preboot_support = XHCI_PREBOOT, + .xhci_streams = XHCI_STREAMS, }, };

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Patch merged into coreboot/master: 2c9d2cf {arch, cpu, drivers, ec}: Don't hide pointers behind typedefs
by gerrit＠coreboot.org 27 Oct '14

27 Oct '14

the following patch was just integrated into master: commit 2c9d2cf75c6b12132f1f2c43ef9c01b51f741d26 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Oct 27 23:29:29 2014 +1100 {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/7146 Tested-by: build bot (Jenkins) See http://review.coreboot.org/7146 for details. -gerrit

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Patch set updated for coreboot: 5b2fdcd build: Allow clang build linkage to use libcompiler-rt
by Edward O'Callaghan 27 Oct '14

27 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6144 -gerrit commit 5b2fdcd6fd80bcafaeb99b9aa2f3f7490c5b7460 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 03:02:52 2014 +1000 build: Allow clang build linkage to use libcompiler-rt Make use of '-print-librt-file-name' over '-print-libgcc-file-name' to use Compiler-RT runtime glue over libgcc glue. NOTE: *** Requires at least clang 3.6.x Change-Id: I7f63284473d6067bf775409970c8dd98f5d5a8d5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 6 ++++-- src/arch/x86/Makefile.inc | 6 +++--- toolchain.inc | 1 + 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 49fbba5..42aaabd 100644 --- a/Makefile +++ b/Makefile @@ -117,8 +117,10 @@ else include $(HAVE_DOTCONFIG) ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) -# FIXME: arm/aarch64 won't build right now -CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-elf -m32 +# FIXME: armv7/aarch64 won't build right now +# NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a +# this means the triple is i386-linux-elf instead of i386-none-elf +CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 CC_x86_32:=clang ifneq ($(CONFIG_MMX),y) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 1480a66..50f5ada 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -209,7 +209,7 @@ romstage-libs ?= $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_null.ld + $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBCLANG_RT_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_null.ld else $(CC_romstage) $(CFLAGS_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif @@ -221,7 +221,7 @@ endif $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_xip.ld + $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --start-group $(romstage-objs) $(romstage-libs) $(LIBCLANG_RT_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_xip.ld else $(CC_romstage) $(CFLAGS_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif @@ -331,7 +331,7 @@ endif $(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_ramstage) -m elf_i386 -r -o $@ --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) --end-group + $(LD_ramstage) -m elf_i386 -r -o $@ --start-group $(ramstage-objs) $(ramstage-libs) $(LIBCLANG_RT_FILE_NAME_ramstage) --end-group else $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group endif diff --git a/toolchain.inc b/toolchain.inc index 2a68576..a572f98 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -93,6 +93,7 @@ READELF_$(1) := $(READELF_$(2)) CFLAGS_$(1) += $$(CFLAGS_common) $$(CFLAGS_$(2)) CPPFLAGS_$(1) += $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) LIBGCC_FILE_NAME_$(1) = $(wildcard $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-libgcc-file-name)) +LIBCLANG_RT_FILE_NAME_$(1) = $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-librt-file-name) endef # define_class: Allows defining any program as dynamic class and compiler tool

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New patch to review for coreboot: 0fda524 usbdebug: Refactor descriptor probing of dongle
by Kyösti Mälkki 27 Oct '14

27 Oct '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7209 -gerrit commit 0fda524f1434658c272b3eaff646f6d1316e11e5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Oct 27 14:07:28 2014 +0200 usbdebug: Refactor descriptor probing of dongle Organized such that it is easy to support devices that do not export special Debug Descriptor. Some of these can still work in a fixed configuration and/or require additional initialisation for UART clocks etc. Change-Id: Id07fd6b69007332d67d9e9a456f58fdbca1999cd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/ehci_debug.c | 119 +------------------------------------------ src/drivers/usb/ehci_debug.h | 5 ++ src/drivers/usb/gadget.c | 111 ++++++++++++++++++++++++++++++++++++++++ src/drivers/usb/usb_ch9.h | 28 ++++++++++ 4 files changed, 145 insertions(+), 118 deletions(-) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 69530f1..acdb34d 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -31,11 +31,6 @@ #include "usb_ch9.h" #include "ehci.h" -#define DBGP_MAX_ENDPOINTS 4 -#define DBGP_SETUP_EP0 0 /* Compulsory endpoint 0. */ -#define DBGP_CONSOLE_EPOUT 1 -#define DBGP_CONSOLE_EPIN 2 - struct ehci_debug_info { void *ehci_base; void *ehci_debug; @@ -54,33 +49,7 @@ static int dbgp_enabled(void); #endif #define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f)) -/* - * USB Packet IDs (PIDs) - */ -/* token */ -#define USB_PID_OUT 0xe1 -#define USB_PID_IN 0x69 -#define USB_PID_SOF 0xa5 -#define USB_PID_SETUP 0x2d -/* handshake */ -#define USB_PID_ACK 0xd2 -#define USB_PID_NAK 0x5a -#define USB_PID_STALL 0x1e -#define USB_PID_NYET 0x96 -/* data */ -#define USB_PID_DATA0 0xc3 -#define USB_PID_DATA1 0x4b -#define USB_PID_DATA2 0x87 -#define USB_PID_MDATA 0x0f -/* Special */ -#define USB_PID_PREAMBLE 0x3c -#define USB_PID_ERR 0x3c -#define USB_PID_SPLIT 0x78 -#define USB_PID_PING 0xb4 -#define USB_PID_UNDEF_0 0xf0 - -#define USB_PID_DATA_TOGGLE 0x88 #define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE) #define HUB_ROOT_RESET_TIME 50 /* times are in msec */ @@ -465,11 +434,9 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ struct ehci_caps *ehci_caps; struct ehci_regs *ehci_regs; - struct usb_debug_descriptor dbgp_desc; u32 cmd, ctrl, status, portsc, hcs_params; u32 debug_port, new_debug_port = 0, n_ports; - u32 devnum; - int ret, i, configured; + int ret, i; int loop; int port_map_tried; int playtimes = 3; @@ -615,90 +582,6 @@ try_next_port: goto err; } - /* Find the debug device and make it device number 127 */ - devnum = 0; -debug_dev_retry: - memset(&dbgp_desc, 0, sizeof(dbgp_desc)); - ret = dbgp_control_msg(ehci_debug, devnum, - USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE, - USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0, - &dbgp_desc, sizeof(dbgp_desc)); - if (ret == sizeof(dbgp_desc)) { - if (dbgp_desc.bLength == sizeof(dbgp_desc) && dbgp_desc.bDescriptorType==USB_DT_DEBUG) - goto debug_dev_found; - else - dprintk(BIOS_INFO, "Invalid debug device descriptor.\n"); - } - if (devnum == 0) { - devnum = USB_DEBUG_DEVNUM; - goto debug_dev_retry; - } else { - dprintk(BIOS_INFO, "Could not find attached debug device.\n"); - ret = -5; - goto err; - } -debug_dev_found: - - /* Move the device to 127 if it isn't already there */ - if (devnum != USB_DEBUG_DEVNUM) { - ret = dbgp_control_msg(ehci_debug, devnum, - USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, - USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0); - if (ret < 0) { - dprintk(BIOS_INFO, "Could not move attached device to %d.\n", - USB_DEBUG_DEVNUM); - ret = -7; - goto err; - } - devnum = USB_DEBUG_DEVNUM; - dprintk(BIOS_INFO, "EHCI debug device renamed to 127.\n"); - } - - /* Enable the debug interface */ - ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM, - USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, - USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0); - if (ret < 0) { - dprintk(BIOS_INFO, "Could not enable EHCI debug device.\n"); - ret = -8; - goto err; - } - dprintk(BIOS_INFO, "EHCI debug interface enabled.\n"); - - /* Prepare endpoint pipes. */ - for (i=1; i<DBGP_MAX_ENDPOINTS; i++) { - info->ep_pipe[i].devnum = USB_DEBUG_DEVNUM; - info->ep_pipe[i].pid = USB_PID_DATA0; - info->ep_pipe[i].timeout = 1000; - } - info->ep_pipe[DBGP_CONSOLE_EPOUT].endpoint = dbgp_desc.bDebugOutEndpoint; - info->ep_pipe[DBGP_CONSOLE_EPIN].endpoint = dbgp_desc.bDebugInEndpoint; - - /* Perform a small write. */ - configured = 0; -small_write: - ret = dbgp_bulk_write(ehci_debug, &info->ep_pipe[DBGP_CONSOLE_EPOUT], "USB\r\n",5); - if (ret < 0) { - dprintk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret); - if (!configured) { - /* Send Set Configure request to device. This is required for FX2 - (CY7C68013) to transfer from USB state Addressed to Configured, - only then endpoints other than 0 are enabled. */ - if (dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM, - USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, - USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0) >= 0) { - configured = 1; - goto small_write; - } - } - ret = -9; - goto err; - } - dprintk(BIOS_INFO, "Test write done\n"); - - info->ep_pipe[DBGP_SETUP_EP0].status |= DBGP_EP_ENABLED | DBGP_EP_VALID; - info->ep_pipe[DBGP_CONSOLE_EPOUT].status |= DBGP_EP_ENABLED | DBGP_EP_VALID; - info->ep_pipe[DBGP_CONSOLE_EPIN].status |= DBGP_EP_ENABLED | DBGP_EP_VALID; return 0; err: /* Things didn't work so remove my claim */ diff --git a/src/drivers/usb/ehci_debug.h b/src/drivers/usb/ehci_debug.h index d7ea91b..c060a70 100644 --- a/src/drivers/usb/ehci_debug.h +++ b/src/drivers/usb/ehci_debug.h @@ -37,6 +37,11 @@ void ehci_debug_select_port(unsigned int port); #define DBGP_EP_BUSY (1<<2) #define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED) +#define DBGP_MAX_ENDPOINTS 4 +#define DBGP_SETUP_EP0 0 /* Compulsory endpoint 0. */ +#define DBGP_CONSOLE_EPOUT 1 +#define DBGP_CONSOLE_EPIN 2 + struct ehci_dbg_port; struct dbgp_pipe diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index d3b4963..5dd7993 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -17,11 +17,13 @@ #include <stddef.h> #include <console/console.h> +#include <string.h> #include "ehci_debug.h" #include "usb_ch9.h" #include "ehci.h" +#define dprintk printk #define USB_HUB_PORT_CONNECTION 0 #define USB_HUB_PORT_ENABLED 1 @@ -120,6 +122,108 @@ err: return -1; } +static void ack_set_configuration(struct dbgp_pipe *pipe, u8 devnum, int timeout) +{ + int i = DBGP_SETUP_EP0; + while (++i < DBGP_MAX_ENDPOINTS) { + if (pipe[i].endpoint != 0) { + pipe[i].devnum = devnum; + pipe[i].pid = USB_PID_DATA0; + pipe[i].timeout = timeout; + } + } +} + +static void activate_endpoints(struct dbgp_pipe *pipe) +{ + int i = DBGP_SETUP_EP0; + pipe[i].status |= DBGP_EP_ENABLED | DBGP_EP_VALID; + while (++i < DBGP_MAX_ENDPOINTS) { + if (pipe[i].endpoint != 0) + pipe[i].status |= DBGP_EP_ENABLED | DBGP_EP_VALID; + } +} + +static int probe_for_debug_descriptor(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe) +{ + struct usb_debug_descriptor dbgp_desc; + int configured = 0, ret; + u8 devnum = 0; + + /* Find the debug device and make it device number 127 */ +debug_dev_retry: + memset(&dbgp_desc, 0, sizeof(dbgp_desc)); + ret = dbgp_control_msg(ehci_debug, devnum, + USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0, + &dbgp_desc, sizeof(dbgp_desc)); + if (ret == sizeof(dbgp_desc)) { + if (dbgp_desc.bLength == sizeof(dbgp_desc) && dbgp_desc.bDescriptorType==USB_DT_DEBUG) + goto debug_dev_found; + else + dprintk(BIOS_INFO, "Invalid debug device descriptor.\n"); + } + if (devnum == 0) { + devnum = USB_DEBUG_DEVNUM; + goto debug_dev_retry; + } else { + dprintk(BIOS_INFO, "Could not find attached debug device.\n"); + return -1; + } +debug_dev_found: + + /* Move the device to 127 if it isn't already there */ + if (devnum != USB_DEBUG_DEVNUM) { + ret = dbgp_control_msg(ehci_debug, devnum, + USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0); + if (ret < 0) { + dprintk(BIOS_INFO, "Could not move attached device to %d.\n", + USB_DEBUG_DEVNUM); + return -2; + } + devnum = USB_DEBUG_DEVNUM; + dprintk(BIOS_INFO, "EHCI debug device renamed to 127.\n"); + } + + /* Enable the debug interface */ + ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM, + USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0); + if (ret < 0) { + dprintk(BIOS_INFO, "Could not enable EHCI debug device.\n"); + return -3; + } + dprintk(BIOS_INFO, "EHCI debug interface enabled.\n"); + + pipe[DBGP_CONSOLE_EPOUT].endpoint = dbgp_desc.bDebugOutEndpoint; + pipe[DBGP_CONSOLE_EPIN].endpoint = dbgp_desc.bDebugInEndpoint; + + ack_set_configuration(pipe, devnum, 1000); + + /* Perform a small write. */ + configured = 0; +small_write: + ret = dbgp_bulk_write_x(&pipe[DBGP_CONSOLE_EPOUT], "USB\r\n",5); + if (ret < 0) { + dprintk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret); + if (!configured) { + /* Send Set Configure request to device. This is required for FX2 + (CY7C68013) to transfer from USB state Addressed to Configured, + only then endpoints other than 0 are enabled. */ + if (dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM, + USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0) >= 0) { + configured = 1; + goto small_write; + } + } + return -4; + } + dprintk(BIOS_INFO, "Test write done\n"); + return 0; +} + int dbgp_probe_gadget(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe) { @@ -134,5 +238,12 @@ int dbgp_probe_gadget(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe) } } + ret = probe_for_debug_descriptor(ehci_debug, pipe); + if (ret < 0) { + dprintk(BIOS_INFO, "Could not enable gadget using Debug Descriptor.\n"); + return ret; + } + + activate_endpoints(pipe); return 0; } diff --git a/src/drivers/usb/usb_ch9.h b/src/drivers/usb/usb_ch9.h index a609bdb..a4a3722 100644 --- a/src/drivers/usb/usb_ch9.h +++ b/src/drivers/usb/usb_ch9.h @@ -81,6 +81,34 @@ #define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */ +/* + * USB Packet IDs (PIDs) + */ + +/* token */ +#define USB_PID_OUT 0xe1 +#define USB_PID_IN 0x69 +#define USB_PID_SOF 0xa5 +#define USB_PID_SETUP 0x2d +/* handshake */ +#define USB_PID_ACK 0xd2 +#define USB_PID_NAK 0x5a +#define USB_PID_STALL 0x1e +#define USB_PID_NYET 0x96 +/* data */ +#define USB_PID_DATA0 0xc3 +#define USB_PID_DATA1 0x4b +#define USB_PID_DATA2 0x87 +#define USB_PID_MDATA 0x0f +/* Special */ +#define USB_PID_PREAMBLE 0x3c +#define USB_PID_ERR 0x3c +#define USB_PID_SPLIT 0x78 +#define USB_PID_PING 0xb4 +#define USB_PID_UNDEF_0 0xf0 + +#define USB_PID_DATA_TOGGLE 0x88 + struct usb_ctrlrequest { u8 bRequestType; u8 bRequest;

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coreboot-gerrit October 2014