coreboot-gerrit October 2014

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Patch set updated for coreboot: ad2fc51 i82801gx: Handle whole FADT in southbridge.
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7199 -gerrit commit ad2fc51af587507a09940326b401d63af16c9d44 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 25 15:18:25 2014 +0200 i82801gx: Handle whole FADT in southbridge. Do all the handling in SB code with few parameters from devicetree.cb instead of having mobo callbacks. Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpi.c | 5 ++-- src/arch/x86/include/arch/acpi.h | 3 +- src/mainboard/apple/macbook21/devicetree.cb | 3 ++ src/mainboard/apple/macbook21/fadt.c | 27 ----------------- src/mainboard/getac/p470/devicetree.cb | 4 +++ src/mainboard/getac/p470/fadt.c | 28 ------------------ src/mainboard/ibase/mb899/devicetree.cb | 3 ++ src/mainboard/ibase/mb899/fadt.c | 32 --------------------- src/mainboard/intel/d945gclf/devicetree.cb | 2 ++ src/mainboard/intel/d945gclf/fadt.c | 28 ------------------ src/mainboard/kontron/986lcd-m/devicetree.cb | 2 ++ src/mainboard/kontron/986lcd-m/fadt.c | 33 --------------------- src/mainboard/lenovo/t60/devicetree.cb | 3 ++ src/mainboard/lenovo/t60/fadt.c | 28 ------------------ src/mainboard/lenovo/x60/devicetree.cb | 4 +++ src/mainboard/lenovo/x60/fadt.c | 28 ------------------ src/mainboard/roda/rk886ex/devicetree.cb | 4 +++ src/mainboard/roda/rk886ex/fadt.c | 28 ------------------ src/southbridge/intel/i82801gx/chip.h | 3 ++ src/southbridge/intel/i82801gx/lpc.c | 43 +++++++++++++++++----------- 20 files changed, 58 insertions(+), 253 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index c3c946d..baea65c 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -660,7 +660,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt) memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 3; + header->revision = 4; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); @@ -680,8 +680,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt) fadt->preferred_pm_profile = PM_DESKTOP; } - southbridge_fill_fadt(fadt); - mainboard_fill_fadt(fadt); + acpi_fill_fadt(fadt); header->checksum = acpi_checksum((void *) fadt, header->length); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index ff59a01..313bdf1 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -495,8 +495,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt); #if IS_ENABLED(CONFIG_COMMON_FADT) -void southbridge_fill_fadt(acpi_fadt_t * fadt); -void mainboard_fill_fadt(acpi_fadt_t * fadt); +void acpi_fill_fadt(acpi_fadt_t * fadt); #endif void update_ssdt(void *ssdt); diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 5b11b52..9509c81 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -69,6 +69,9 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "1" register "c4onc3_enable" = "1" + register "c3_latency" = "0x23" + register "p_cnt_throttling_supported" = "1" + device pci 1b.0 on ioapic_irq 2 INTA 0x16 # Audio Controller subsystemid 0x8384 0x7680 diff --git a/src/mainboard/apple/macbook21/fadt.c b/src/mainboard/apple/macbook21/fadt.c deleted file mode 100644 index 314153d..0000000 --- a/src/mainboard/apple/macbook21/fadt.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 0x23; -} diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index fd97445..d88304e 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -60,6 +60,10 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0" + register "c3_latency" = "85" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1" + device pci 1b.0 on # High Definition Audio ioapic_irq 2 INTA 0x16 end diff --git a/src/mainboard/getac/p470/fadt.c b/src/mainboard/getac/p470/fadt.c deleted file mode 100644 index 8722743..0000000 --- a/src/mainboard/getac/p470/fadt.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 85; - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; -} diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index af04398..ccf6405 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -32,6 +32,9 @@ chip northbridge/intel/i945 register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x1" + register "c3_latency" = "85" + register "p_cnt_throttling_supported" = "0" + device pci 1b.0 on ioapic_irq 2 INTA 0x16 end # High Definition Audio diff --git a/src/mainboard/ibase/mb899/fadt.c b/src/mainboard/ibase/mb899/fadt.c deleted file mode 100644 index f2770a5..0000000 --- a/src/mainboard/ibase/mb899/fadt.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 85; - fadt->duty_width = 0; - fadt->iapc_boot_arch = 0x03; - - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_PLATFORM_CLOCK; -} diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index acbde2a..9f9afff 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -52,6 +52,8 @@ chip northbridge/intel/i945 register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0" + register "c3_latency" = "85" + register "p_cnt_throttling_supported" = "0" device pci 1b.0 on ioapic_irq 2 INTA 0x16 end # High Definition Audio diff --git a/src/mainboard/intel/d945gclf/fadt.c b/src/mainboard/intel/d945gclf/fadt.c deleted file mode 100644 index 74a0e7e..0000000 --- a/src/mainboard/intel/d945gclf/fadt.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 85; - fadt->duty_width = 0; - fadt->iapc_boot_arch = 0x03; - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_PLATFORM_CLOCK; -} diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 069660c..b701f78 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -32,6 +32,8 @@ chip northbridge/intel/i945 register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x1" register "sata_ahci" = "0x0" + register "c3_latency" = "85" + register "p_cnt_throttling_supported" = "0" device pci 1b.0 on ioapic_irq 2 INTA 0x16 diff --git a/src/mainboard/kontron/986lcd-m/fadt.c b/src/mainboard/kontron/986lcd-m/fadt.c deleted file mode 100644 index 92bf647..0000000 --- a/src/mainboard/kontron/986lcd-m/fadt.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 85; - fadt->duty_width = 0; - fadt->iapc_boot_arch = 0x03; - - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED - | ACPI_FADT_RESET_REGISTER |ACPI_FADT_PLATFORM_CLOCK; -} diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 5e2a4fe..1d5f549 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -69,6 +69,9 @@ chip northbridge/intel/i945 register "alt_gp_smi_en" = "0x1000" register "c4onc3_enable" = "1" + register "c3_latency" = "0x23" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1" device pci 1b.0 on ioapic_irq 2 INTA 0x16 # Audio Controller diff --git a/src/mainboard/lenovo/t60/fadt.c b/src/mainboard/lenovo/t60/fadt.c deleted file mode 100644 index 96767bd..0000000 --- a/src/mainboard/lenovo/t60/fadt.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 0x23; - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; -} diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index a067f92..af3d10d 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -67,6 +67,10 @@ chip northbridge/intel/i945 register "alt_gp_smi_en" = "0x1000" register "c4onc3_enable" = "1" + register "c3_latency" = "0x23" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1" + device pci 1b.0 on ioapic_irq 2 INTA 0x16 # Audio Controller subsystemid 0x17aa 0x2010 diff --git a/src/mainboard/lenovo/x60/fadt.c b/src/mainboard/lenovo/x60/fadt.c deleted file mode 100644 index 96767bd..0000000 --- a/src/mainboard/lenovo/x60/fadt.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 0x23; - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; -} diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 6e34b6f..8e4a665 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -53,6 +53,10 @@ chip northbridge/intel/i945 register "gpi7_routing" = "2" register "gpe0_en" = "0x20800007" + register "c3_latency" = "0x23" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1" + register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" diff --git a/src/mainboard/roda/rk886ex/fadt.c b/src/mainboard/roda/rk886ex/fadt.c deleted file mode 100644 index 96767bd..0000000 --- a/src/mainboard/roda/rk886ex/fadt.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t * fadt) -{ - fadt->p_lvl3_lat = 0x23; - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; -} diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index c61ec98..589c082 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -59,6 +59,9 @@ struct southbridge_intel_i82801gx_config { uint32_t sata_ports_implemented; int c4onc3_enable:1; + int docking_supported:1; + int p_cnt_throttling_supported:1; + int c3_latency; }; #endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 085906f..4fc5ff7 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -486,9 +486,11 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -void southbridge_fill_fadt(acpi_fadt_t * fadt) +void acpi_fill_fadt(acpi_fadt_t * fadt) { - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *chip = dev->chip_info; + u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -510,7 +512,7 @@ void southbridge_fill_fadt(acpi_fadt_t * fadt) fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0; @@ -519,56 +521,56 @@ void southbridge_fill_fadt(acpi_fadt_t * fadt) fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = pmbase; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1b_evt_blk.space_id = 0; fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; fadt->x_pm1a_cnt_blk.space_id = 1; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 0; fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; fadt->x_pm2_cnt_blk.space_id = 1; fadt->x_pm2_cnt_blk.bit_width = 8; fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_gpe0_blk.addrl = pmbase + 0x28; fadt->x_gpe0_blk.addrh = 0x0; fadt->x_gpe1_blk.space_id = 0; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; fadt->day_alrm = 0xd; @@ -585,14 +587,23 @@ void southbridge_fill_fadt(acpi_fadt_t * fadt) fadt->cst_cnt = APM_CNT_CST_CONTROL; fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 0x23; + fadt->p_lvl3_lat = chip->c3_latency; fadt->flush_size = 0; fadt->flush_stride = 0; fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->iapc_boot_arch = 0x00; - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE; + if (chip->p_cnt_throttling_supported) { + fadt->duty_width = 3; + } else { + fadt->duty_width = 0; + } + fadt->iapc_boot_arch = 0x03; + fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED + | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE + | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER + | ACPI_FADT_C2_MP_SUPPORTED); + if (chip->docking_supported) { + fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + } } static void i82801gx_lpc_read_resources(device_t dev)

1 0

Patch set updated for coreboot: ded4bbc i945: Consolidate acpi/platform.asl
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7086 -gerrit commit ded4bbca3399a7264a361604dff7b9f594e61016 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Oct 16 10:39:06 2014 +0200 i945: Consolidate acpi/platform.asl Change-Id: Iccb2dda8a427e483c04693e46b00e0bc2452a26b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/model_6dx/acpi/cpu.asl | 37 +++++++ src/mainboard/apple/macbook21/acpi/platform.asl | 119 +--------------------- src/mainboard/apple/macbook21/dsdt.asl | 3 + src/mainboard/getac/p470/acpi/ec.asl | 6 ++ src/mainboard/getac/p470/acpi/platform.asl | 123 +---------------------- src/mainboard/getac/p470/dsdt.asl | 4 + src/mainboard/ibase/mb899/acpi/platform.asl | 38 ------- src/mainboard/ibase/mb899/dsdt.asl | 4 + src/mainboard/intel/d945gclf/acpi/platform.asl | 38 ------- src/mainboard/intel/d945gclf/dsdt.asl | 3 + src/mainboard/kontron/986lcd-m/acpi/platform.asl | 38 ------- src/mainboard/kontron/986lcd-m/dsdt.asl | 3 + src/mainboard/lenovo/t60/acpi/platform.asl | 122 +--------------------- src/mainboard/lenovo/t60/dsdt.asl | 3 + src/mainboard/lenovo/x60/acpi/platform.asl | 122 +--------------------- src/mainboard/lenovo/x60/dsdt.asl | 3 + src/mainboard/roda/rk886ex/acpi/ec.asl | 3 + src/mainboard/roda/rk886ex/acpi/platform.asl | 122 +--------------------- src/mainboard/roda/rk886ex/dsdt.asl | 3 + src/southbridge/intel/i82801gx/acpi/platform.asl | 105 +++++++++++++++++++ 20 files changed, 182 insertions(+), 717 deletions(-) diff --git a/src/cpu/intel/model_6dx/acpi/cpu.asl b/src/cpu/intel/model_6dx/acpi/cpu.asl new file mode 100644 index 0000000..8928c38 --- /dev/null +++ b/src/cpu/intel/model_6dx/acpi/cpu.asl @@ -0,0 +1,37 @@ +/* These come from the dynamically created CPU SSDT */ +External(PDC0) +External(PDC1) + +// Power notification + +External (\_PR_.CPU0, DeviceObj) +External (\_PR_.CPU1, DeviceObj) +External (\_PR_.CPU0._PPC) +External (\_PR_.CPU1._PPC) + +Method (PNOT) +{ + If (MPEN) { + If(And(PDC0, 0x08)) { + Notify (\_PR_.CPU0, 0x80) // _PPC + + If (And(PDC0, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU0, 0x81) // _CST + } + } + + If(And(PDC1, 0x08)) { + Notify (\_PR_.CPU1, 0x80) // _PPC + If (And(PDC1, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU1, 0x81) // _CST + } + } + + } Else { // UP + Notify (\_PR_.CPU0, 0x80) + Sleep(0x64) + Notify(\_PR_.CPU0, 0x81) + } +} diff --git a/src/mainboard/apple/macbook21/acpi/platform.asl b/src/mainboard/apple/macbook21/acpi/platform.asl index 1c6ac6e..99efbb3 100644 --- a/src/mainboard/apple/macbook21/acpi/platform.asl +++ b/src/mainboard/apple/macbook21/acpi/platform.asl @@ -19,48 +19,6 @@ * MA 02110-1301 USA */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _WAK method is called on system wakeup */ Method(_WAK,1) @@ -85,38 +43,6 @@ Method(_WAK,1) Return(Package(){0,0}) } -// Power notification - -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) - -Method (PNOT) -{ - If (MPEN) { - If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC - - If (And(PDC0, 0x10)) { - Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST - } - } - - If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC - If (And(PDC1, 0x10)) { - Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST - } - } - - } Else { // UP - Notify (\_PR_.CPU0, 0x80) - Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) - } -} - /* System Bus */ Scope(\_SB) @@ -133,49 +59,7 @@ Scope(\_SB) // TRAP(71) // TODO - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI, Local0)) { - /* Linux answers _OSI with "True" for a couple of - * Windows version queries. But unlike Windows it - * needs a Video repost, so let's determine whether - * we're running Linux. - */ - - If (_OSI("Linux")) { - Store (1, LINX) - } - - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - } + \GOS() /* And the OS workarounds start right after we know what we're * running: Windows XP SP1 needs to have C-State coordination @@ -189,4 +73,3 @@ Scope(\_SB) // TRAP(43) // TODO } } - diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index fb0a34f..5bc25c9 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -37,6 +37,9 @@ DefinitionBlock( // global NVS and variables #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/i82801gx/acpi/platform.asl> + + #include <cpu/intel/model_6dx/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index b8e2954..1b1c157 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -120,6 +120,8 @@ Device(EC0) } PNOT() + Notify(\_SB.BAT0, 0x80) // Execute BAT0 _BST + Notify(\_SB.BAT1, 0x80) // Execute BAT1 _BST } Method (_Q02, 0) @@ -133,12 +135,16 @@ Device(EC0) } PNOT() + Notify(\_SB.BAT0, 0x80) // Execute BAT0 _BST + Notify(\_SB.BAT1, 0x80) // Execute BAT1 _BST } Method (_Q05, 0) { Notify(SLPB, 0x80) PNOT() + Notify(\_SB.BAT0, 0x80) // Execute BAT0 _BST + Notify(\_SB.BAT1, 0x80) // Execute BAT1 _BST } Method (_Q07, 0) diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index df9adc7..2b081e0 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -19,44 +19,6 @@ * MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ @@ -149,47 +111,6 @@ Method(_WAK,1) Return(Package(){0,0}) } -// Power notification - -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) -External (\_PR_.CPU0._PPC) -External (\_PR_.CPU1._PPC) -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - -Method (PNOT) -{ - If (MPEN) { - If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC - - If (And(PDC0, 0x10)) { - Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST - } - } - - If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC - If (And(PDC1, 0x10)) { - Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST - } - } - - } Else { // UP - Notify (\_PR_.CPU0, 0x80) - Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) - } - - // Notify the Batteries - Notify(\_SB.BAT0, 0x80) // Execute BAT0 _BST - Notify(\_SB.BAT1, 0x80) // Execute BAT1 _BST -} - // Hardcoded for now.. Name (CFGD, 0x113B69F1) @@ -210,49 +131,7 @@ Scope(\_SB) TRAP(0x47) } - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI, Local0)) { - /* Linux answers _OSI with "True" for a couple of - * Windows version queries. But unlike Windows it - * needs a Video repost, so let's determine whether - * we're running Linux. - */ - - If (_OSI("Linux")) { - Store (1, LINX) - } - - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - } + \GOS() /* And the OS workarounds start right after we know what we're * running: Windows XP SP1 needs to have C-State coordination diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index d89f75e..6cdea54 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -31,6 +31,8 @@ DefinitionBlock( 0x20090419 // OEM revision ) { + #include <southbridge/intel/i82801gx/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" @@ -46,6 +48,8 @@ DefinitionBlock( // Thermal Zone #include "acpi/thermal.asl" + #include <cpu/intel/model_6dx/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/mainboard/ibase/mb899/acpi/platform.asl b/src/mainboard/ibase/mb899/acpi/platform.asl index 6770348..9a7e62c 100644 --- a/src/mainboard/ibase/mb899/acpi/platform.asl +++ b/src/mainboard/ibase/mb899/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index 80d586a..52290b3 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -32,11 +32,15 @@ DefinitionBlock( // global NVS and variables #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/i82801gx/acpi/platform.asl> + // General Purpose Events //#include "acpi/gpe.asl" //#include "acpi/thermal.asl" + #include <cpu/intel/model_6dx/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl index 0c7e8a6..3d20c4b 100644 --- a/src/mainboard/intel/d945gclf/acpi/platform.asl +++ b/src/mainboard/intel/d945gclf/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index dd1f3a1..d4cdc3d 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -31,6 +31,7 @@ DefinitionBlock( // global NVS and variables #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/i82801gx/acpi/platform.asl> // General Purpose Events //#include "acpi/gpe.asl" @@ -41,6 +42,8 @@ DefinitionBlock( // Thermal Zone //#include "acpi/thermal.asl" + #include <cpu/intel/model_6dx/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/mainboard/kontron/986lcd-m/acpi/platform.asl b/src/mainboard/kontron/986lcd-m/acpi/platform.asl index 6770348..9a7e62c 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/platform.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 4e455cc..b83d28e 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -31,12 +31,15 @@ DefinitionBlock( // global NVS and variables #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/i82801gx/acpi/platform.asl> // General Purpose Events //#include "acpi/gpe.asl" //#include "acpi/thermal.asl" + #include <cpu/intel/model_6dx/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/mainboard/lenovo/t60/acpi/platform.asl b/src/mainboard/lenovo/t60/acpi/platform.asl index ddb8ff3..59df530 100644 --- a/src/mainboard/lenovo/t60/acpi/platform.asl +++ b/src/mainboard/lenovo/t60/acpi/platform.asl @@ -19,48 +19,6 @@ * MA 02110-1301 USA */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ @@ -95,42 +53,6 @@ Method(_WAK,1) Return(Package(){0,0}) } -// Power notification - -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) - -Method (PNOT) -{ - If (MPEN) { - If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC - - If (And(PDC0, 0x10)) { - Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST - } - } - - If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC - If (And(PDC1, 0x10)) { - Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST - } - } - - } Else { // UP - Notify (\_PR_.CPU0, 0x80) - Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) - } - - // Notify the Batteries - Notify(\_SB.PCI0.LPCB.EC.BAT0, 0x80) // Execute BAT1 _BST - Notify(\_SB.PCI0.LPCB.EC.BAT1, 0x80) // Execute BAT2 _BST -} - /* System Bus */ Scope(\_SB) @@ -147,49 +69,7 @@ Scope(\_SB) // TRAP(71) // TODO - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI, Local0)) { - /* Linux answers _OSI with "True" for a couple of - * Windows version queries. But unlike Windows it - * needs a Video repost, so let's determine whether - * we're running Linux. - */ - - If (_OSI("Linux")) { - Store (1, LINX) - } - - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - } + \GOS() /* And the OS workarounds start right after we know what we're * running: Windows XP SP1 needs to have C-State coordination diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 4122917..7807687 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -38,6 +38,7 @@ DefinitionBlock( // global NVS and variables #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/i82801gx/acpi/platform.asl> // General Purpose Events #include "acpi/gpe.asl" @@ -45,6 +46,8 @@ DefinitionBlock( // mainboard specific devices #include "acpi/mainboard.asl" + #include <cpu/intel/model_6dx/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/mainboard/lenovo/x60/acpi/platform.asl b/src/mainboard/lenovo/x60/acpi/platform.asl index ddb8ff3..59df530 100644 --- a/src/mainboard/lenovo/x60/acpi/platform.asl +++ b/src/mainboard/lenovo/x60/acpi/platform.asl @@ -19,48 +19,6 @@ * MA 02110-1301 USA */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ @@ -95,42 +53,6 @@ Method(_WAK,1) Return(Package(){0,0}) } -// Power notification - -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) - -Method (PNOT) -{ - If (MPEN) { - If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC - - If (And(PDC0, 0x10)) { - Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST - } - } - - If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC - If (And(PDC1, 0x10)) { - Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST - } - } - - } Else { // UP - Notify (\_PR_.CPU0, 0x80) - Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) - } - - // Notify the Batteries - Notify(\_SB.PCI0.LPCB.EC.BAT0, 0x80) // Execute BAT1 _BST - Notify(\_SB.PCI0.LPCB.EC.BAT1, 0x80) // Execute BAT2 _BST -} - /* System Bus */ Scope(\_SB) @@ -147,49 +69,7 @@ Scope(\_SB) // TRAP(71) // TODO - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI, Local0)) { - /* Linux answers _OSI with "True" for a couple of - * Windows version queries. But unlike Windows it - * needs a Video repost, so let's determine whether - * we're running Linux. - */ - - If (_OSI("Linux")) { - Store (1, LINX) - } - - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - } + \GOS() /* And the OS workarounds start right after we know what we're * running: Windows XP SP1 needs to have C-State coordination diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 4122917..7807687 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -38,6 +38,7 @@ DefinitionBlock( // global NVS and variables #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/i82801gx/acpi/platform.asl> // General Purpose Events #include "acpi/gpe.asl" @@ -45,6 +46,8 @@ DefinitionBlock( // mainboard specific devices #include "acpi/mainboard.asl" + #include <cpu/intel/model_6dx/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index fc0ae54..d174e98 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -107,6 +107,9 @@ Device(EC0) Store("_Q30: AC In/Out", Debug) Notify(ADP1, 0x80) // Tell the Power Adapter PNOT() // and the CPU and Battery + // Notify the Batteries + Notify(BAT1, 0x80) // Execute BAT1 _BST + Notify(BAT2, 0x80) // Execute BAT2 _BST } Method (_Q31, 0) diff --git a/src/mainboard/roda/rk886ex/acpi/platform.asl b/src/mainboard/roda/rk886ex/acpi/platform.asl index 0e30c4e..dbafb04 100644 --- a/src/mainboard/roda/rk886ex/acpi/platform.asl +++ b/src/mainboard/roda/rk886ex/acpi/platform.asl @@ -19,48 +19,6 @@ * MA 02110-1301 USA */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ @@ -95,42 +53,6 @@ Method(_WAK,1) Return(Package(){0,0}) } -// Power notification - -External (\_PR_.CPU0, DeviceObj) -External (\_PR_.CPU1, DeviceObj) - -Method (PNOT) -{ - If (MPEN) { - If(And(PDC0, 0x08)) { - Notify (\_PR_.CPU0, 0x80) // _PPC - - If (And(PDC0, 0x10)) { - Sleep(100) - Notify(\_PR_.CPU0, 0x81) // _CST - } - } - - If(And(PDC1, 0x08)) { - Notify (\_PR_.CPU1, 0x80) // _PPC - If (And(PDC1, 0x10)) { - Sleep(100) - Notify(\_PR_.CPU1, 0x81) // _CST - } - } - - } Else { // UP - Notify (\_PR_.CPU0, 0x80) - Sleep(0x64) - Notify(\_PR_.CPU0, 0x81) - } - - // Notify the Batteries - Notify(BAT1, 0x80) // Execute BAT1 _BST - Notify(BAT2, 0x80) // Execute BAT2 _BST -} - /* System Bus */ Scope(\_SB) @@ -147,49 +69,7 @@ Scope(\_SB) // TRAP(71) // TODO - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI, Local0)) { - /* Linux answers _OSI with "True" for a couple of - * Windows version queries. But unlike Windows it - * needs a Video repost, so let's determine whether - * we're running Linux. - */ - - If (_OSI("Linux")) { - Store (1, LINX) - } - - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - } + \GOS() /* And the OS workarounds start right after we know what we're * running: Windows XP SP1 needs to have C-State coordination diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index 43d1609..b23b568 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -33,6 +33,7 @@ DefinitionBlock( // global NVS and variables #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/i82801gx/acpi/platform.asl> // General Purpose Events #include "acpi/gpe.asl" @@ -43,6 +44,8 @@ DefinitionBlock( // Thermal Zone #include "acpi/thermal.asl" + #include <cpu/intel/model_6dx/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/southbridge/intel/i82801gx/acpi/platform.asl b/src/southbridge/intel/i82801gx/acpi/platform.asl new file mode 100644 index 0000000..2b8a59e --- /dev/null +++ b/src/southbridge/intel/i82801gx/acpi/platform.asl @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +Method(GOS, 0) +{ + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI, Local0)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + } +}

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Patch set updated for coreboot: d074544 macbook21: Move SB-specific early init to separate file
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7085 -gerrit commit d074544eefea62e988f092569c4d96202263ddaa Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 23:07:24 2014 +0200 macbook21: Move SB-specific early init to separate file Change-Id: I5995dd0c43a541c352af279a373bc783f51176a9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/Makefile.inc | 1 + src/mainboard/apple/macbook21/early_mainboard.h | 3 + src/mainboard/apple/macbook21/early_southbridge.c | 253 ++++++++++++++++++++++ src/mainboard/apple/macbook21/romstage.c | 231 +------------------- 4 files changed, 258 insertions(+), 230 deletions(-) diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc new file mode 100644 index 0000000..7b421c4 --- /dev/null +++ b/src/mainboard/apple/macbook21/Makefile.inc @@ -0,0 +1 @@ +romstage-y += early_southbridge.c \ No newline at end of file diff --git a/src/mainboard/apple/macbook21/early_mainboard.h b/src/mainboard/apple/macbook21/early_mainboard.h new file mode 100644 index 0000000..6c9dbe9 --- /dev/null +++ b/src/mainboard/apple/macbook21/early_mainboard.h @@ -0,0 +1,3 @@ +void ich7_enable_lpc(void); +void rcba_config(void); +void early_ich7_init(void); diff --git a/src/mainboard/apple/macbook21/early_southbridge.c b/src/mainboard/apple/macbook21/early_southbridge.c new file mode 100644 index 0000000..7e7b5a9 --- /dev/null +++ b/src/mainboard/apple/macbook21/early_southbridge.c @@ -0,0 +1,253 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "northbridge/intel/i945/i945.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include "early_mainboard.h" + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + + /* X60 GPIO: + * 1: HDD_PRESENCE# + * 6: Unknown (Pulled high by R215 to VCC3B) + * 7: BDC_PRESENCE# + * 8: H8_WAKE# + * 9: RTC_BAT_IN# + * 10: Unknown (Pulled high by R700 to VCC3M) + * 12: H8SCI# + * 13: SLICE_ON_3M# + * 14: Unknown (Pulled high by R321 to VCC3) + * 15: Unknown (Pulled high by R258 to VCC3) + * 19: Unknown (Pulled low by R594) + * 21: Unknown (Pulled high by R145 to VCC3) + * 22: FWH_WP# + * 25: MDC_KILL# + * 33: HDD_PRESENCE_2# + * 35: CLKREQ_SATA# + * 36: PLANARID0 + * 37: PLANARID1 + * 38: PLANARID2 + * 39: PLANARID3 + * 48: FWH_TBL# + */ + + outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00002082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // I/O Decode Ranges + // X60: 0x0210 == 00000010 00010000 + // Macbook21: 0x0010 == 00000000 00010000 + // Bit 9:8 LPT Decode Range. This field determines which range to + // decode for the LPT Port. + // 00 = 378h 37Fh and 778h 77Fh + // 10 = 3BCh 3BEh and 7BCh 7BEh + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + + // LPC_EN--LPC I/F Enables Register + // X60: 0x1f0d == 00011111 00001101 + // Macbook21: 0x3807 == 00111000 00000111 + // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh + // to the LPC interface. This range is used for + // Super I/O devices. + // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 62h and 66h + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 60h and 64h + // to the LPC interface. This range is used for a + // microcontroller. + // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 208h to 20Fh + // to the LPC interface. This range is used for a gameport. + // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable + // 0 = Disable. + // 1 = Enables the decoding of the I/O locations 200h to 207h + // to the LPC interface. This range is used for a gameport. + // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable + // 0 = Disable. + // 1 = Enables the decoding of the FDD range to the LPC + // interface. This range is selected in the LPC_FDD/LPT + // Decode Range Register (D31:F0:80h, bit 12). + // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable + // 0 = Disable. + // 1 = Enables the decoding of the LPT range to the LPC + // interface. This range is selected in the LPC_FDD/LPT + // Decode Range Register (D31:F0:80h, bit 9:8). + // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable + // 0 = Disable. + // 1 = Enables the decoding of the COMB range to the LPC + // interface. This range is selected in the LPC_COM Decode + // Range Register (D31:F0:80h, bits 6:4). + // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable + // 0 = Disable. + // 1 = Enables the decoding of the COMA range to the LPC + // interface. This range is selected in the LPC_COM Decode + // Range Register (D31:F0:80h, bits 3:2). + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); + + /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ + // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 + // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 + // Bit 31:24 Reserved. + // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any + // bit position indicates that any value in the corresponding + // address bit in a received cycle will be treated as a + // match. The corresponding bit in the Address field, below, + // is ignored. The mask is only provided for the lower 6 bits + // of the DWord address, allowing for decoding blocks up to + // 256 bytes in size. + // Bit 17:16 Reserved. + // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This + // address is aligned on a 128-byte boundary, and must have + // address lines 31:16 as 0. NOTE: The Intel ICH7 does not + // provide decode down to the word or byte level. + // Bit 1 Reserved. + // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. + // 0 = Disable. + // 1 = Enable the GEN1 I/O range to be forwarded to the LPC + // I/F + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); + + /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ + // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 + // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); + + /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ + // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 + // Macbook21: 0x0000 0x0000 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); + + /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ + // X60: 0x0000 0x0000 + // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); +} + +void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Disable unused devices */ + RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; + RCBA32(0x3418) |= (1 << 0); // Required. + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + // RCBA32(0x1e84) = 0x00020001; + // RCBA32(0x1e80) = 0x0000fe01; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} + +void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index d82569b..50a4dd6 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -26,241 +26,13 @@ #include <string.h> #include <arch/io.h> #include <device/pci_def.h> -#include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <lib.h> -#include <cbmem.h> #include <timestamp.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" - -void setup_ich7_gpios(void) -{ - printk(BIOS_DEBUG, " GPIOS..."); - - /* X60 GPIO: - * 1: HDD_PRESENCE# - * 6: Unknown (Pulled high by R215 to VCC3B) - * 7: BDC_PRESENCE# - * 8: H8_WAKE# - * 9: RTC_BAT_IN# - * 10: Unknown (Pulled high by R700 to VCC3M) - * 12: H8SCI# - * 13: SLICE_ON_3M# - * 14: Unknown (Pulled high by R321 to VCC3) - * 15: Unknown (Pulled high by R258 to VCC3) - * 19: Unknown (Pulled low by R594) - * 21: Unknown (Pulled high by R145 to VCC3) - * 22: FWH_WP# - * 25: MDC_KILL# - * 33: HDD_PRESENCE_2# - * 35: CLKREQ_SATA# - * 36: PLANARID0 - * 37: PLANARID1 - * 38: PLANARID2 - * 39: PLANARID3 - * 48: FWH_TBL# - */ - - outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - /* Output Control Registers */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ - /* Input Control Registers */ - outl(0x00002082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ -} - -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - - // I/O Decode Ranges - // X60: 0x0210 == 00000010 00010000 - // Macbook21: 0x0010 == 00000000 00010000 - // Bit 9:8 LPT Decode Range. This field determines which range to - // decode for the LPT Port. - // 00 = 378h 37Fh and 778h 77Fh - // 10 = 3BCh 3BEh and 7BCh 7BEh - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - - // LPC_EN--LPC I/F Enables Register - // X60: 0x1f0d == 00011111 00001101 - // Macbook21: 0x3807 == 00111000 00000111 - // Bit 13 CNF2_LPC_EN -- R/W. Microcontroller Enable # 2. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 4Eh and 4Fh - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 12 CNF1_LPC_EN -- R/W. Super I/O Enable. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 2Eh and 2Fh - // to the LPC interface. This range is used for - // Super I/O devices. - // Bit 11 MC_LPC_EN -- R/W. Microcontroller Enable # 1. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 62h and 66h - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 10 KBC_LPC_EN -- R/W. Keyboard Enable. - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 60h and 64h - // to the LPC interface. This range is used for a - // microcontroller. - // Bit 9 GAMEH_LPC_EN -- R/W. High Gameport Enable - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 208h to 20Fh - // to the LPC interface. This range is used for a gameport. - // Bit 8 GAMEL_LPC_EN -- R/W. Low Gameport Enable - // 0 = Disable. - // 1 = Enables the decoding of the I/O locations 200h to 207h - // to the LPC interface. This range is used for a gameport. - // Bit 3 FDD_LPC_EN -- R/W. Floppy Drive Enable - // 0 = Disable. - // 1 = Enables the decoding of the FDD range to the LPC - // interface. This range is selected in the LPC_FDD/LPT - // Decode Range Register (D31:F0:80h, bit 12). - // Bit 2 LPT_LPC_EN -- R/W. Parallel Port Enable - // 0 = Disable. - // 1 = Enables the decoding of the LPT range to the LPC - // interface. This range is selected in the LPC_FDD/LPT - // Decode Range Register (D31:F0:80h, bit 9:8). - // Bit 1 COMB_LPC_EN -- R/W. Com Port B Enable - // 0 = Disable. - // 1 = Enables the decoding of the COMB range to the LPC - // interface. This range is selected in the LPC_COM Decode - // Range Register (D31:F0:80h, bits 6:4). - // Bit 0 COMA_LPC_EN -- R/W. Com Port A Enable - // 0 = Disable. - // 1 = Enables the decoding of the COMA range to the LPC - // interface. This range is selected in the LPC_COM Decode - // Range Register (D31:F0:80h, bits 3:2). - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807); - - /* GEN1_DEC, LPC Interface Generic Decode Range 1 */ - // X60: 0x1601 0x007c == 00000000 01111100 00010110 00000001 - // Macbook21: 0x0681 0x000c == 00000000 00001100 00000110 10000001 - // Bit 31:24 Reserved. - // Bit 23:18 Generic I/O Decode Range Address[7:2] Mask: A `1' in any - // bit position indicates that any value in the corresponding - // address bit in a received cycle will be treated as a - // match. The corresponding bit in the Address field, below, - // is ignored. The mask is only provided for the lower 6 bits - // of the DWord address, allowing for decoding blocks up to - // 256 bytes in size. - // Bit 17:16 Reserved. - // Bit 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE). This - // address is aligned on a 128-byte boundary, and must have - // address lines 31:16 as 0. NOTE: The Intel ICH7 does not - // provide decode down to the word or byte level. - // Bit 1 Reserved. - // Bit 0 Generic Decode Range 1 Enable (GEN1_EN) -- R/W. - // 0 = Disable. - // 1 = Enable the GEN1 I/O range to be forwarded to the LPC - // I/F - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c); - - /* GEN2_DEC, LPC Interface Generic Decode Range 2 */ - // X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 - // Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); - - /* GEN3_DEC, LPC Interface Generic Decode Range 3 */ - // X60: 0x1681 0x001c == 00000000 00011100 00010110 10000001 - // Macbook21: 0x0000 0x0000 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); // obsolete, because it writes zeros? - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000); - - /* GEN4_DEC, LPC Interface Generic Decode Range 4 */ - // X60: 0x0000 0x0000 - // Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c); -} - -static void rcba_config(void) -{ - /* V0CTL Virtual Channel 0 Resource Control */ - RCBA32(0x0014) = 0x80000001; - /* V1CAP Virtual Channel 1 Resource Capability */ - RCBA32(0x001c) = 0x03128010; - - /* Disable unused devices */ - RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD; - RCBA32(0x3418) |= (1 << 0); // Required. - - /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - // RCBA32(0x1e84) = 0x00020001; - // RCBA32(0x1e80) = 0x0000fe01; - - /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(0x1e9c) = 0x000200f0; - RCBA32(0x1e98) = 0x000c0801; -} - -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA32(0x3418) |= (1 << 0); - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} +#include "early_mainboard.h" void main(unsigned long bist) { @@ -327,5 +99,4 @@ void main(unsigned long bist) i945_late_initialization(s3resume); timestamp_add_now(TS_END_ROMSTAGE); - }

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Patch set updated for coreboot: 198b772 sandy/ivy/nehalem: Remerge interrupt handling
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7130 -gerrit commit 198b772c84bd1d431a7590581e2137521f072f7c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 19 10:13:14 2014 +0200 sandy/ivy/nehalem: Remerge interrupt handling On those chipsets the pins are just a legacy concept. Real interrupts are messages on corresponding busses or some internal logic of chipset. Hence interrupt routing isn't anymore board-specific (dependent on layout) but depends only on configuration. Rather than attempting to sync real config, ACPI and legacy descriptors, just use the same interrupt routing per chipset covering all possible devices. Interrupt balancing may suffer from such merge but: a) Doesn't seem to be the case of this map on current systems b) Almost all OS use MSI nowadays bypassing this stuff completely c) If we want a good balancing we need to take into account that e.g. wlan card may be placed in a different slot and so would require complicated balancing on runtime. It's difficult to maintain with almost no benefit. Change-Id: I9f63d1d338c5587ebac7a52093e5b924f6e5ca2d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/acpi_tables.c | 18 ----- src/mainboard/google/butterfly/devicetree.cb | 9 --- src/mainboard/google/butterfly/romstage.c | 42 +---------- src/mainboard/google/link/acpi_tables.c | 18 ----- src/mainboard/google/link/devicetree.cb | 9 --- src/mainboard/google/link/romstage.c | 39 +--------- src/mainboard/google/parrot/acpi_tables.c | 18 ----- src/mainboard/google/parrot/devicetree.cb | 9 --- src/mainboard/google/parrot/romstage.c | 43 +---------- src/mainboard/google/stout/acpi_tables.c | 18 ----- src/mainboard/google/stout/devicetree.cb | 9 --- src/mainboard/google/stout/romstage.c | 43 +---------- src/mainboard/intel/cougar_canyon2/devicetree.cb | 9 --- src/mainboard/intel/emeraldlake2/acpi_tables.c | 18 ----- src/mainboard/intel/emeraldlake2/devicetree.cb | 9 --- src/mainboard/intel/emeraldlake2/romstage.c | 38 +--------- src/mainboard/kontron/ktqm77/acpi_tables.c | 18 ----- src/mainboard/kontron/ktqm77/devicetree.cb | 9 --- src/mainboard/kontron/ktqm77/romstage.c | 58 +-------------- .../lenovo/t520/acpi/sandybridge_pci_irqs.asl | 64 ---------------- src/mainboard/lenovo/t520/acpi_tables.c | 18 ----- src/mainboard/lenovo/t520/devicetree.cb | 9 --- src/mainboard/lenovo/t520/romstage.c | 42 ----------- .../lenovo/t530/acpi/sandybridge_pci_irqs.asl | 64 ---------------- src/mainboard/lenovo/t530/acpi_tables.c | 18 ----- src/mainboard/lenovo/t530/devicetree.cb | 9 --- src/mainboard/lenovo/t530/romstage.c | 42 ----------- .../lenovo/x201/acpi/nehalem_pci_irqs.asl | 86 ---------------------- src/mainboard/lenovo/x201/acpi_tables.c | 36 --------- src/mainboard/lenovo/x201/devicetree.cb | 9 --- src/mainboard/lenovo/x201/romstage.c | 40 +--------- src/mainboard/lenovo/x220/acpi_tables.c | 18 ----- src/mainboard/lenovo/x220/devicetree.cb | 9 --- src/mainboard/lenovo/x220/romstage.c | 42 ----------- .../lenovo/x230/acpi/sandybridge_pci_irqs.asl | 64 ---------------- src/mainboard/lenovo/x230/acpi_tables.c | 18 ----- src/mainboard/lenovo/x230/devicetree.cb | 9 --- src/mainboard/lenovo/x230/romstage.c | 42 ----------- .../packardbell/ms2290/acpi/nehalem_pci_irqs.asl | 86 ---------------------- src/mainboard/packardbell/ms2290/acpi_tables.c | 36 --------- src/mainboard/packardbell/ms2290/devicetree.cb | 9 --- src/mainboard/packardbell/ms2290/romstage.c | 41 ++--------- src/mainboard/samsung/lumpy/acpi_tables.c | 18 ----- src/mainboard/samsung/lumpy/devicetree.cb | 9 --- src/mainboard/samsung/lumpy/romstage.c | 36 +-------- src/mainboard/samsung/stumpy/acpi_tables.c | 18 ----- src/mainboard/samsung/stumpy/devicetree.cb | 9 --- src/mainboard/samsung/stumpy/romstage.c | 38 +--------- src/northbridge/intel/nehalem/acpi/hostbridge.asl | 63 +++++++++++++++- .../intel/sandybridge/acpi/hostbridge.asl | 51 ++++++++++++- .../intel/sandybridge/romstage_native.c | 1 + src/southbridge/intel/bd82x6x/Makefile.inc | 3 + src/southbridge/intel/bd82x6x/chip.h | 13 ---- src/southbridge/intel/bd82x6x/early_rcba.c | 69 +++++++++++++++++ src/southbridge/intel/bd82x6x/lpc.c | 27 ++++--- src/southbridge/intel/bd82x6x/madt.c | 45 +++++++++++ src/southbridge/intel/bd82x6x/pch.h | 2 + src/southbridge/intel/ibexpeak/Makefile.inc | 2 + src/southbridge/intel/ibexpeak/early_rcba.c | 61 +++++++++++++++ src/southbridge/intel/ibexpeak/lpc.c | 27 ++++--- src/southbridge/intel/ibexpeak/madt.c | 68 +++++++++++++++++ src/southbridge/intel/ibexpeak/pch.h | 1 + 62 files changed, 405 insertions(+), 1401 deletions(-) diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index dcaf384..cabc052 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -75,24 +75,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 9a7a1d5..e944639 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -39,15 +39,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 908b6d8..7528dec 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -62,47 +62,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index 14baad2..d1d4fcb 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -83,24 +83,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->lids = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 8f0ed3c..608bc84 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -42,15 +42,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 8236e20..f90d7e7 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -78,44 +78,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P3IP WLAN INTA -> PIRQB - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * TRACKPAD -> PIRQE (Edge Triggered) - * TOUCHSCREEN -> PIRQG (Edge Triggered) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index e4e1797..0041c98 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -74,24 +74,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->lids = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 59586cc..8496c9f 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -41,15 +41,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x8b" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index ce42b41..c25b419 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -62,48 +62,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P2IP WLAN INTA -> PIRQB - * D28IP_P3IP ETH0 INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQE - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - * - * Trackpad DVT PIRQA (16) - * Trackpad DVT PIRQE (20) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | - (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) | - (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) | - (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 504ae64..23c47f9 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -80,24 +80,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->xhci = XHCI_MODE; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 653d3fe..9f0be35 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -40,15 +40,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index bfa4af7..16ce978 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -68,48 +68,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D20IP_XHCI XHCI INTA -> PIRQD (MSI) - * D26IP_E2P EHCI #2 INTA -> PIRQF - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * D28IP_P2IP WLAN INTA -> PIRQD - * D28IP_P3IP Card Reader INTB -> PIRQE - * D28IP_P6IP LAN INTC -> PIRQB - * D29IP_E1P EHCI #1 INTA -> PIRQD - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | - (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | - (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | - (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - RCBA32(D20IP) = (INTA << D20IP_XHCIIP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC); - DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index c499a56..136a581 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -32,15 +32,6 @@ chip northbridge/intel/fsp_sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/fsp_bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - register "sata_port_map" = "0x3f" device pci 14.0 on end # XHCI diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 3d95586..f17e1f4 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -92,24 +92,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 0d81502..76c4ac9 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -32,15 +32,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 220b1d7..d50093e 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -73,43 +73,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index 0d90403..d2d70e9 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -63,24 +63,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index f6390ac..5dfd6cc 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -27,15 +27,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8b" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x8b" - register "pirqf_routing" = "0x8b" - register "pirqg_routing" = "0x8b" - register "pirqh_routing" = "0x8b" - # Enable all SATA ports 0-5 register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s (should be the default, anyway) diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 401314c..bfe7715 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -59,63 +59,7 @@ static void rcba_config(void) { u32 reg32; - /* - * D31IP_TTIP THRT INTC -> PIRQC - * D31IP_SIP2 SATA2 NOINT - * D31IP_SMIP SMBUS INTC -> PIRQC - * D31IP_SIP SATA INTB -> PIRQD (MSI) - * D29IP_E1P EHCI1 INTA -> PIRQH - * D28IP_P8IP Slot? INTD -> PIRQD - * D28IP_P7IP PCIEx1 INTC -> PIRQC - * D28IP_P6IP 1394 INTB -> PIRQB (MSI) - * D28IP_P5IP GbEPHY INTA -> PIRQA - * D28IP_P4IP ETH2 INTD -> PIRQD (MSI) - * D28IP_P3IP ETH1 INTC -> PIRQC (MSI) - * D28IP_P2IP Slot? INTB -> PIRQB - * D28IP_P1IP Slot? INTA -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - * D26IP_E2P EHCI2 INTA -> PIRQA - * D25IP_LIP ETH0 INTA -> PIRQE (MSI) - * D22IP_KTIP MEI NOINT - * D22IP_IDERIP MEI NOINT - * D22IP_MEI2IP MEI NOINT - * D22IP_MEI1IP MEI NOINT - * D20IP_XHCIIP XHCI INTA -> PIRQA (MSI) - * GFX INTA -> PIRQA (MSI) - * PEGx16 INTA -> PIRQA - * INTB -> PIRQB - * INTC -> PIRQC - * INTD -> PIRQD - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTC << D31IP_SMIP) | (INTB << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) | - (INTA << D28IP_P5IP) | (INTB << D28IP_P6IP) | - (INTC << D28IP_P7IP) | (INTD << D28IP_P8IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (INTA << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - RCBA32(D20IP) = (INTA << D20IP_XHCIIP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); - DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); - DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD); - DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); - DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index b4b81a2..0000000 --- a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P2IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P4IP EXC INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P5IP SDCARD INTC -> PIRQD - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) - Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH - Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index 26a459d..15b9d9a 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index c32e237..168e0e7 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -44,15 +44,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 83be0c7..f7866a8 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -60,48 +60,6 @@ void pch_enable_lpc(void) void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P2IP WLAN INTA -> PIRQB - * D28IP_P4IP EXC INTB -> PIRQF - * D28IP_P5IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P2IP) | (INTB << D28IP_P4IP) | - (INTC << D28IP_P5IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1ee51fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index 6c1c695..0000000 --- a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) - Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH - Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index 26a459d..15b9d9a 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index b44623b..ba33601 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -44,15 +44,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 115f83b..0a49ed0 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -47,48 +47,6 @@ void pch_enable_lpc(void) void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl b/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl deleted file mode 100644 index 3e9e1b3..0000000 --- a/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing. - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0001ffff, 0, 0, 0x10 }, - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x0003ffff, 0, 0, 0x10 }, - Package() { 0x0016ffff, 0, 0, 0x10 }, // ME - Package() { 0x0016ffff, 1, 0, 0x11 }, // ME - Package() { 0x0016ffff, 2, 0, 0x12 }, // ME - Package() { 0x0016ffff, 3, 0, 0x13 }, // ME - Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet - Package() { 0x001affff, 0, 0, 0x14 }, // USB - Package() { 0x001affff, 1, 0, 0x15 }, // USB - Package() { 0x001affff, 2, 0, 0x16 }, // USB - Package() { 0x001affff, 3, 0, 0x17 }, // USB - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x11 }, // SATA - Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS - }) - } Else { - Return (Package() { - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME - Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME - Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME - Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME - Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB - Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB - Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB - Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB - Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus - }) - } -} diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index b8979f4..85eabc7 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -48,42 +48,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs) gnvs->did[4] = 0x00000005; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 1, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, - MP_IRQ_POLARITY_DEFAULT | - MP_IRQ_TRIGGER_DEFAULT); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_LEVEL); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 2, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 3, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { /* Not implemented */ diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 7592cb0..6920d2a 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -93,15 +93,6 @@ chip northbridge/intel/nehalem subsystemid 0x17aa 0x215a end chip southbridge/intel/ibexpeak - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 2c3dfd1..e58f5f6 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -75,41 +75,9 @@ static void pch_enable_lpc(void) static void rcba_config(void) { + southbridge_configure_default_intmap(); + static const u32 rcba_dump3[] = { - /* 30fc */ 0x00000000, - /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321, - /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002, - /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000, - /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654, - /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210, - /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000, - /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -179,8 +147,8 @@ static void rcba_config(void) }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x30fc) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x30fc); + RCBA32(4 * i + 0x3310) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3310); } } diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index 26a459d..15b9d9a 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 8f4deaa..0ecec26 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -48,15 +48,6 @@ chip northbridge/intel/sandybridge end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index ba48fac..d9c8aa0 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -57,48 +57,6 @@ void pch_enable_lpc(void) void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x1fe41fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index 6c1c695..0000000 --- a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) - Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH - Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index 26a459d..15b9d9a 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index ae5e6d1..1560b0d 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -48,15 +48,6 @@ chip northbridge/intel/sandybridge end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 2c39741..0bb137e 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -60,48 +60,6 @@ void pch_enable_lpc(void) void rcba_config(void) { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * - * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG - - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); - /* Disable unused devices (board specific) */ RCBA32(FD) = 0x17f81fe3; RCBA32(BUC) = 0; diff --git a/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl b/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl deleted file mode 100644 index 1f782c8..0000000 --- a/src/mainboard/packardbell/ms2290/acpi/nehalem_pci_irqs.asl +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing. - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - Package() { 0x0001ffff, 0, 0, 0x10 }, - Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA - Package() { 0x0003ffff, 0, 0, 0x10 }, - Package() { 0x0016ffff, 0, 0, 0x10 }, // ME - Package() { 0x0016ffff, 1, 0, 0x11 }, // ME - Package() { 0x0016ffff, 2, 0, 0x12 }, // ME - Package() { 0x0016ffff, 3, 0, 0x13 }, // ME - Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet - Package() { 0x001affff, 0, 0, 0x14 }, // USB - Package() { 0x001affff, 1, 0, 0x15 }, // USB - Package() { 0x001affff, 2, 0, 0x16 }, // USB - Package() { 0x001affff, 3, 0, 0x17 }, // USB - Package() { 0x001bffff, 1, 0, 0x11 }, // Audio - Package() { 0x001cffff, 0, 0, 0x10 }, // PCI bridge - Package() { 0x001cffff, 1, 0, 0x11 }, // PCI bridge - Package() { 0x001cffff, 2, 0, 0x12 }, // PCI bridge - Package() { 0x001cffff, 3, 0, 0x13 }, // PCI bridge - Package() { 0x001dffff, 0, 0, 0x10 }, // USB - Package() { 0x001dffff, 1, 0, 0x11 }, // USB - Package() { 0x001dffff, 2, 0, 0x12 }, // USB - Package() { 0x001dffff, 3, 0, 0x13 }, // USB - Package() { 0x001fffff, 0, 0, 0x17 }, // LPC - Package() { 0x001fffff, 1, 0, 0x10 }, // IDE - Package() { 0x001fffff, 2, 0, 0x11 }, // SATA - Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS - }) - } Else { - Return (Package() { - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME - Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME - Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME - Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME - Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB - Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB - Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB - Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB - Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // PCI - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // PCI - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // PCI - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // PCI - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus - }) - } -} diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c index b8979f4..85eabc7 100644 --- a/src/mainboard/packardbell/ms2290/acpi_tables.c +++ b/src/mainboard/packardbell/ms2290/acpi_tables.c @@ -48,42 +48,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs) gnvs->did[4] = 0x00000005; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 1, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, - MP_IRQ_POLARITY_DEFAULT | - MP_IRQ_TRIGGER_DEFAULT); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_LEVEL); - - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 2, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 3, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { /* Not implemented */ diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 19f6c9c..2f4bce1 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -54,15 +54,6 @@ chip northbridge/intel/nehalem subsystemid 0x1025 0x0379 end chip southbridge/intel/ibexpeak - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index c4a278e..7d6c236 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -69,41 +69,9 @@ static void pch_enable_lpc(void) static void rcba_config(void) { + southbridge_configure_default_intmap(); + static const u32 rcba_dump3[] = { - /* 30fc */ 0x00000000, - /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321, - /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002, - /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000, - /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654, - /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210, - /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000, - /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -172,9 +140,10 @@ static void rcba_config(void) /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000, }; unsigned i; + for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x30fc) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x30fc); + RCBA32(4 * i + 0x3310) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3310); } } diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 24a0efd..6d8517c 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -93,24 +93,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->chromeos.vbt2 = ec_read(0xcb) ? ACTIVE_ECFW_RW : ACTIVE_ECFW_RO; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 69729d7..a5b96e2 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -42,15 +42,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index dc4161d..f37e87e 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -75,41 +75,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC (MSI) - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQB - * D31IP_SIP SATA INTA -> PIRQA (MSI) - * D31IP_SMIP SMBUS INTC -> PIRQH - * D31IP_TTIP THRT INTB -> PIRQG - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - * - * LIGHTSENSOR -> PIRQE (Edge Triggered) - * TRACKPAD -> PIRQF (Edge Triggered) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTC << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + southbridge_configure_default_intmap(); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 2d24822..dc2197a 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -93,24 +93,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ab03c79..9769ca4 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -33,15 +33,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 625903d..2c651ae 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -87,43 +87,7 @@ static void rcba_config(void) { u32 reg32; - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); - RCBA32(D30IP) = (NOINT << D30IP_PIP); - RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP); - RCBA32(D27IP) = (INTA << D27IP_ZIP); - RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); - - /* Device interrupt route registers */ - DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); - DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); - DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); - DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); - DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); - DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); - DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); - - /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; - /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index e826bd6..ee5d1c9 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -344,5 +344,64 @@ Method (_CRS, 0, Serialized) Return (MCRS) } -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/nehalem_pci_irqs.asl" +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 0x10 }, + Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA + Package() { 0x0003ffff, 0, 0, 0x10 }, + Package() { 0x0016ffff, 0, 0, 0x10 }, // ME + Package() { 0x0016ffff, 1, 0, 0x11 }, // ME + Package() { 0x0016ffff, 2, 0, 0x12 }, // ME + Package() { 0x0016ffff, 3, 0, 0x13 }, // ME + Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet + Package() { 0x001affff, 0, 0, 0x14 }, // USB + Package() { 0x001affff, 1, 0, 0x15 }, // USB + Package() { 0x001affff, 2, 0, 0x16 }, // USB + Package() { 0x001affff, 3, 0, 0x17 }, // USB + Package() { 0x001bffff, 1, 0, 0x11 }, // Audio + Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge + Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge + Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge + Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge + Package() { 0x001dffff, 0, 0, 0x10 }, // USB + Package() { 0x001dffff, 1, 0, 0x11 }, // USB + Package() { 0x001dffff, 2, 0, 0x12 }, // USB + Package() { 0x001dffff, 3, 0, 0x13 }, // USB + Package() { 0x001fffff, 0, 0, 0x17 }, // LPC + Package() { 0x001fffff, 1, 0, 0x10 }, // IDE + Package() { 0x001fffff, 2, 0, 0x11 }, // SATA + Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS + }) + } Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME + Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME + Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME + Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB + Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB + Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB + Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB + Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus + }) + } +} diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 690c072..4025a0f 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -379,5 +379,52 @@ Method (_CRS, 0, Serialized) Return (MCRS) } -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/sandybridge_pci_irqs.asl" +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // XHCI 0:14.0 (ivy only) + Package() { 0x0014ffff, 0, 0, 19 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // XHCI 0:14.0 (ivy only) + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 67c64d7..902d66d 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -91,6 +91,7 @@ void main(unsigned long bist) timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); + southbridge_configure_default_intmap(); rcba_config(); post_code(0x3d); diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 3d33edc..07c5c24 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -50,12 +50,15 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c romstage-y += early_smbus.c me_status.c gpio.c romstage-y += reset.c romstage-y += early_spi.c early_pch.c +romstage-y += early_rcba.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c early_usb.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c early_usb.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c +ramstage-y += madt.c + ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 0f2f0e9..d1d6401 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -22,19 +22,6 @@ struct southbridge_intel_bd82x6x_config { /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; - - /** * GPI Routing configuration * * Only the lower two bits have a meaning: diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c new file mode 100644 index 0000000..114b174 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "pch.h" +#include "northbridge/intel/sandybridge/sandybridge.h" + +void +southbridge_configure_default_intmap(void) +{ + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP SLOT1 INTA -> PIRQB + * D28IP_P2IP SLOT2 INTB -> PIRQF + * D28IP_P3IP SLOT3 INTC -> PIRQD + * D28IP_P5IP SLOT5 INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + + */ + + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); +} diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0e3a4f6..521e847 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -104,18 +104,17 @@ static void pch_enable_serial_irqs(struct device *dev) static void pch_pirq_init(device_t dev) { device_t irq_dev; - /* Get the chip configuration */ - config_t *config = dev->chip_info; + u8 pirq_routing[8] = { 0x8b, 0x8a, 0x8b, 0x8b, 0x80, 0x80, 0x80, 0x80 }; - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + pci_write_config8(dev, PIRQA_ROUT, pirq_routing[0]); + pci_write_config8(dev, PIRQB_ROUT, pirq_routing[1]); + pci_write_config8(dev, PIRQC_ROUT, pirq_routing[2]); + pci_write_config8(dev, PIRQD_ROUT, pirq_routing[3]); - pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + pci_write_config8(dev, PIRQE_ROUT, pirq_routing[4]); + pci_write_config8(dev, PIRQF_ROUT, pirq_routing[5]); + pci_write_config8(dev, PIRQG_ROUT, pirq_routing[6]); + pci_write_config8(dev, PIRQH_ROUT, pirq_routing[7]); /* Eric Biederman once said we should let the OS do this. * I am not so sure anymore he was right. @@ -130,10 +129,10 @@ static void pch_pirq_init(device_t dev) int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); switch (int_pin) { - case 1: /* INTA# */ int_line = config->pirqa_routing; break; - case 2: /* INTB# */ int_line = config->pirqb_routing; break; - case 3: /* INTC# */ int_line = config->pirqc_routing; break; - case 4: /* INTD# */ int_line = config->pirqd_routing; break; + case 1: /* INTA# */ int_line = pirq_routing[0]; break; + case 2: /* INTB# */ int_line = pirq_routing[1]; break; + case 3: /* INTC# */ int_line = pirq_routing[2]; break; + case 4: /* INTD# */ int_line = pirq_routing[3]; break; } if (!int_line) diff --git a/src/southbridge/intel/bd82x6x/madt.c b/src/southbridge/intel/bd82x6x/madt.c new file mode 100644 index 0000000..45b652b --- /dev/null +++ b/src/southbridge/intel/bd82x6x/madt.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 9b84c67..8147559 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -75,6 +75,8 @@ void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); +void +southbridge_configure_default_intmap(void); void early_pch_init_native(void); int southbridge_detect_s3_resume(void); diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 24cbe45..c264993 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,6 +42,7 @@ ramstage-y += ../bd82x6x/watchdog.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c ramstage-y += ../common/spi.c +ramstage-y += madt.c smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c @@ -49,6 +50,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c early_thermal.c romstage-y += ../bd82x6x/reset.c +romstage-y += early_rcba.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c diff --git a/src/southbridge/intel/ibexpeak/early_rcba.c b/src/southbridge/intel/ibexpeak/early_rcba.c new file mode 100644 index 0000000..5218ca7 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_rcba.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "pch.h" +#include "northbridge/intel/nehalem/nehalem.h" + +void +southbridge_configure_default_intmap(void) +{ + RCBA32(0x30fc) = 0; + (void)RCBA32(0x30fc); + + RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) | + (INTA << D31IP_SMIP) | (INTB << D31IP_SIP) | (INTD << 16); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = 0x40043210 | (INTD << D29IP_E1P); + + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) | + (INTA << D28IP_P5IP); + + RCBA32(D27IP) = (INTB << D27IP_ZIP); + RCBA32(D26IP) = (INTD << D26IP_E2P) | 0x30003210; + RCBA32(D25IP) = (INTA << D25IP_LIP); + RCBA32(0x311c) = 0x00000002; + RCBA32(0x3120) = 0x00000000; + RCBA32(D22IP) = (INTA << D22IP_MEI1IP) | (INTB << D22IP_MEI2IP) | (INTC << D22IP_IDERIP) | (INTB << D22IP_KTIP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQH, PIRQA, PIRQB, PIRQD); + DIR_ROUTE(D29IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D28IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQA, PIRQA); + DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQE, PIRQA, PIRQA, PIRQA); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0300; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); +} diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a833a3d..db8f54f 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -104,18 +104,17 @@ static void pch_enable_serial_irqs(struct device *dev) static void pch_pirq_init(device_t dev) { device_t irq_dev; - /* Get the chip configuration */ - config_t *config = dev->chip_info; + u8 pirq_routing[8] = { 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b }; - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + pci_write_config8(dev, PIRQA_ROUT, pirq_routing[0]); + pci_write_config8(dev, PIRQB_ROUT, pirq_routing[1]); + pci_write_config8(dev, PIRQC_ROUT, pirq_routing[2]); + pci_write_config8(dev, PIRQD_ROUT, pirq_routing[3]); - pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + pci_write_config8(dev, PIRQE_ROUT, pirq_routing[4]); + pci_write_config8(dev, PIRQF_ROUT, pirq_routing[5]); + pci_write_config8(dev, PIRQG_ROUT, pirq_routing[6]); + pci_write_config8(dev, PIRQH_ROUT, pirq_routing[7]); /* Eric Biederman once said we should let the OS do this. * I am not so sure anymore he was right. @@ -130,10 +129,10 @@ static void pch_pirq_init(device_t dev) int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); switch (int_pin) { - case 1: /* INTA# */ int_line = config->pirqa_routing; break; - case 2: /* INTB# */ int_line = config->pirqb_routing; break; - case 3: /* INTC# */ int_line = config->pirqc_routing; break; - case 4: /* INTD# */ int_line = config->pirqd_routing; break; + case 1: /* INTA# */ int_line = pirq_routing[0]; break; + case 2: /* INTB# */ int_line = pirq_routing[1]; break; + case 3: /* INTC# */ int_line = pirq_routing[2]; break; + case 4: /* INTD# */ int_line = pirq_routing[3]; break; } if (!int_line) diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c new file mode 100644 index 0000000..69a7b4b --- /dev/null +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 1, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, + MP_IRQ_POLARITY_DEFAULT | + MP_IRQ_TRIGGER_DEFAULT); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_LEVEL); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 2, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 3, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + return current; +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index df125f0..bd94689 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -79,6 +79,7 @@ int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); +void southbridge_configure_default_intmap(void); #endif #endif

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Patch merged into coreboot/master: 795f96e lenovo/x2[23]0: Handle Ricoh SD cardreader
by gerrit＠coreboot.org 27 Oct '14

27 Oct '14

the following patch was just integrated into master: commit 795f96e2b947a950e4c56e34d1706308f8b2cec6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Oct 27 02:45:22 2014 +0100 lenovo/x2[23]0: Handle Ricoh SD cardreader Change-Id: Id0aecbd3e45bdf9661168ebd0e55f17dc6febaaa Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7203 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7203 for details. -gerrit

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Patch set updated for coreboot: 52d5530 ACPI: slic support
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7202 -gerrit commit 52d55305a9fafcac2c4bc67eccf53b8b1452ca18 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 26 20:42:08 2014 +0100 ACPI: slic support Change-Id: Id0e7fe0a49b9cd50b5e43cd15030e1c2098728ec Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 4 --- src/arch/x86/boot/acpi.c | 61 +++++++++++++++++++++++------------ src/arch/x86/boot/tables.c | 6 ++-- src/arch/x86/include/arch/acpi.h | 8 ----- src/mainboard/getac/p470/Kconfig | 1 - src/mainboard/getac/p470/Makefile.inc | 1 - src/mainboard/getac/p470/acpi_slic.c | 38 ---------------------- 7 files changed, 43 insertions(+), 76 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b61ce63..029d349 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -342,10 +342,6 @@ config HAVE_ACPI_RESUME bool default n -config HAVE_ACPI_SLIC - bool - default n - config HAVE_HARD_RESET bool default n diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 7ef4697..4a4ed75 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -33,6 +33,7 @@ #include <cbmem.h> #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> +#include <cbfs.h> #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif @@ -504,14 +505,14 @@ void acpi_create_facs(acpi_facs_t *facs) facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */ } -void acpi_write_rsdt(acpi_rsdt_t *rsdt) +static void acpi_write_rsdt(acpi_rsdt_t *rsdt, char *oem_id, char *oem_table_id) { acpi_header_t *header = &(rsdt->header); /* Fill out header fields. */ memcpy(header->signature, "RSDT", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->oem_id, oem_id, 6); + memcpy(header->oem_table_id, oem_table_id, 8); memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_rsdt_t); @@ -523,14 +524,14 @@ void acpi_write_rsdt(acpi_rsdt_t *rsdt) header->checksum = acpi_checksum((void *)rsdt, sizeof(acpi_rsdt_t)); } -void acpi_write_xsdt(acpi_xsdt_t *xsdt) +static void acpi_write_xsdt(acpi_xsdt_t *xsdt, char *oem_id, char *oem_table_id) { acpi_header_t *header = &(xsdt->header); /* Fill out header fields. */ memcpy(header->signature, "XSDT", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->oem_id, oem_id, 6); + memcpy(header->oem_table_id, oem_table_id, 8); memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_xsdt_t); @@ -542,12 +543,13 @@ void acpi_write_xsdt(acpi_xsdt_t *xsdt) header->checksum = acpi_checksum((void *)xsdt, sizeof(acpi_xsdt_t)); } -void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt) +static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, + acpi_xsdt_t *xsdt, char *oem_id) { memset(rsdp, 0, sizeof(acpi_rsdp_t)); memcpy(rsdp->signature, RSDP_SIG, 8); - memcpy(rsdp->oem_id, OEM_ID, 6); + memcpy(rsdp->oem_id, oem_id, 6); rsdp->length = sizeof(acpi_rsdp_t); rsdp->rsdt_address = (u32)rsdt; @@ -708,15 +710,15 @@ unsigned long write_acpi_tables(unsigned long start) acpi_xsdt_t *xsdt; acpi_fadt_t *fadt; acpi_facs_t *facs; -#if CONFIG_HAVE_ACPI_SLIC - acpi_header_t *slic; -#endif + acpi_header_t *slic_file, *slic; acpi_header_t *ssdt; acpi_header_t *dsdt; acpi_mcfg_t *mcfg; acpi_madt_t *madt; device_t dev; unsigned long fw; + size_t slic_size; + char oem_id[6], oem_table_id[8]; current = start; @@ -727,6 +729,22 @@ unsigned long write_acpi_tables(unsigned long start) if (fw) return fw; + slic_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/slic", + CBFS_TYPE_RAW, &slic_size); + if (slic_file && (slic_file->length > slic_size + || slic_file->length < sizeof (acpi_header_t))) { + slic_file = 0; + } + + if (slic_file) { + memcpy(oem_id, slic_file->oem_id, 6); + memcpy(oem_table_id, slic_file->oem_table_id, 8); + } else { + memcpy(oem_id, OEM_ID, 6); + memcpy(oem_table_id, ACPI_TABLE_CREATOR, 8); + } + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); /* We need at least an RSDP and an RSDT Table */ @@ -743,9 +761,9 @@ unsigned long write_acpi_tables(unsigned long start) /* clear all table memory */ memset((void *) start, 0, current - start); - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); + acpi_write_rsdp(rsdp, rsdt, xsdt, oem_id); + acpi_write_rsdt(rsdt, oem_id, oem_table_id); + acpi_write_xsdt(xsdt, oem_id, oem_table_id); printk(BIOS_DEBUG, "ACPI: * FACS\n"); facs = (acpi_facs_t *) current; @@ -786,13 +804,14 @@ unsigned long write_acpi_tables(unsigned long start) acpi_create_fadt(fadt, facs, dsdt); acpi_add_table(rsdp, fadt); -#if CONFIG_HAVE_ACPI_SLIC - printk(BIOS_DEBUG, "ACPI: * SLIC\n"); - slic = (acpi_header_t *)current; - current += acpi_create_slic(current); - ALIGN_CURRENT; - acpi_add_table(rsdp, slic); -#endif + if (slic_file) { + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + memcpy(slic, slic_file, slic_file->length); + current += slic_file->length; + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); + } printk(BIOS_DEBUG, "ACPI: * SSDT\n"); ssdt = (acpi_header_t *)current; diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 9f2afd4..d412596 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -158,9 +158,9 @@ void write_tables(void) acpi_rsdp_t *low_rsdp = (acpi_rsdp_t *)rom_table_end, *high_rsdp = (acpi_rsdp_t *)acpi_start; - acpi_write_rsdp(low_rsdp, - (acpi_rsdt_t *)(high_rsdp->rsdt_address), - (acpi_xsdt_t *)((unsigned long)high_rsdp->xsdt_address)); + /* Technically rsdp length varies but coreboot always + writes longest size available. */ + memcpy(low_rsdp, high_rsdp, sizeof(acpi_rsdp_t)); } else { printk(BIOS_ERR, "ERROR: Didn't find RSDP in high table.\n"); } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 7fbaf7f..16d2f00 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -547,14 +547,6 @@ unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 segment, unsigned long acpi_fill_dmar(unsigned long); -#if CONFIG_HAVE_ACPI_SLIC -unsigned long acpi_create_slic(unsigned long current); -#endif - -void acpi_write_rsdt(acpi_rsdt_t *rsdt); -void acpi_write_xsdt(acpi_xsdt_t *xsdt); -void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt); - void acpi_write_hest(acpi_hest_t *hest); unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); unsigned long acpi_fill_hest(acpi_hest_t *hest); diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 919a8ef..3455872 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -35,7 +35,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_ACPI_SLIC select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/getac/p470/Makefile.inc b/src/mainboard/getac/p470/Makefile.inc index ebfdd49..1ba662e 100644 --- a/src/mainboard/getac/p470/Makefile.inc +++ b/src/mainboard/getac/p470/Makefile.inc @@ -17,4 +17,3 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-$(CONFIG_HAVE_ACPI_SLIC) += acpi_slic.c diff --git a/src/mainboard/getac/p470/acpi_slic.c b/src/mainboard/getac/p470/acpi_slic.c deleted file mode 100644 index b042f36..0000000 --- a/src/mainboard/getac/p470/acpi_slic.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -static const char slic[0x4] = { - 0x53, 0x4c, 0x49, 0x43 /* incomplete. */ - /* If you wish to compile coreboot images with a windows license key - * built in, you need to extract the ACPI SLIC from your machine and - * add it here. - */ -}; - -unsigned long acpi_create_slic(unsigned long current) -{ - memcpy((void *) current, slic, sizeof(slic)); - return sizeof(slic); -}

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Patch set updated for coreboot: f9351cb bd82x6x: Move to common fadt
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7200 -gerrit commit f9351cb3f845118533039fa083b0a527535bbd22 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 25 15:20:55 2014 +0200 bd82x6x: Move to common fadt Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/devicetree.cb | 3 + src/mainboard/google/butterfly/fadt.c | 169 ---------------------- src/mainboard/google/link/devicetree.cb | 3 + src/mainboard/google/link/fadt.c | 166 ---------------------- src/mainboard/google/parrot/devicetree.cb | 3 + src/mainboard/google/parrot/fadt.c | 166 ---------------------- src/mainboard/google/stout/devicetree.cb | 3 + src/mainboard/google/stout/fadt.c | 166 ---------------------- src/mainboard/intel/cougar_canyon2/devicetree.cb | 3 + src/mainboard/intel/cougar_canyon2/fadt.c | 171 ----------------------- src/mainboard/intel/emeraldlake2/devicetree.cb | 3 + src/mainboard/intel/emeraldlake2/fadt.c | 156 --------------------- src/mainboard/kontron/ktqm77/devicetree.cb | 3 + src/mainboard/kontron/ktqm77/fadt.c | 169 ---------------------- src/mainboard/lenovo/t520/devicetree.cb | 3 + src/mainboard/lenovo/t520/fadt.c | 160 --------------------- src/mainboard/lenovo/t530/devicetree.cb | 2 + src/mainboard/lenovo/t530/fadt.c | 160 --------------------- src/mainboard/lenovo/x220/devicetree.cb | 3 + src/mainboard/lenovo/x220/fadt.c | 160 --------------------- src/mainboard/lenovo/x230/devicetree.cb | 2 + src/mainboard/lenovo/x230/fadt.c | 160 --------------------- src/mainboard/samsung/lumpy/devicetree.cb | 3 + src/mainboard/samsung/lumpy/fadt.c | 156 --------------------- src/mainboard/samsung/stumpy/devicetree.cb | 3 + src/mainboard/samsung/stumpy/fadt.c | 156 --------------------- src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/chip.h | 4 + src/southbridge/intel/bd82x6x/lpc.c | 133 ++++++++++++++++++ src/southbridge/intel/fsp_bd82x6x/Kconfig | 1 + src/southbridge/intel/fsp_bd82x6x/chip.h | 3 + src/southbridge/intel/fsp_bd82x6x/lpc.c | 130 +++++++++++++++++ 32 files changed, 309 insertions(+), 2115 deletions(-) diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index e944639..b6d41f6 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -61,6 +61,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" /* c2 not supported */ + register "p_cnt_throttling_supported" = "1" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/butterfly/fadt.c b/src/mainboard/google/butterfly/fadt.c deleted file mode 100644 index b8da1be..0000000 --- a/src/mainboard/google/butterfly/fadt.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 608bc84..5333dfc 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -63,6 +63,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/link/fadt.c b/src/mainboard/google/link/fadt.c deleted file mode 100644 index 5ce9ab1..0000000 --- a/src/mainboard/google/link/fadt.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 8496c9f..a4baafd 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -61,6 +61,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/parrot/fadt.c b/src/mainboard/google/parrot/fadt.c deleted file mode 100644 index b96ec32..0000000 --- a/src/mainboard/google/parrot/fadt.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 9f0be35..4ac89f6 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -64,6 +64,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/stout/fadt.c b/src/mainboard/google/stout/fadt.c deleted file mode 100644 index 5ce9ab1..0000000 --- a/src/mainboard/google/stout/fadt.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index 136a581..c386853 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -34,6 +34,9 @@ chip northbridge/intel/fsp_sandybridge chip southbridge/intel/fsp_bd82x6x # Intel Series 6 Cougar Point PCH register "sata_port_map" = "0x3f" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 14.0 on end # XHCI device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 on end # Management Engine Interface 2 diff --git a/src/mainboard/intel/cougar_canyon2/fadt.c b/src/mainboard/intel/cougar_canyon2/fadt.c deleted file mode 100644 index 5191674..0000000 --- a/src/mainboard/intel/cougar_canyon2/fadt.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; - fadt->model = 0x00; /* reserved, should be 0 ACPI 3.0 */ - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x00; - fadt->pstate_cnt = 0x00; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */ - fadt->pm2_cnt_len = 1; /* 8 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 16; /* 128 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0x00; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->duty_offset = 1; - fadt->duty_width = 0; /* not supported */ - fadt->day_alrm = 0x0D; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->res3 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - - fadt->x_firmware_ctl_l = 0x00; /* set to 0 if firmware_ctrl is used */ - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0; - fadt->x_pm1b_evt_blk.addrh = 0; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x04; - fadt->x_pm1a_cnt_blk.addrh = 0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0; - fadt->x_pm1b_cnt_blk.addrh = 0; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x08; - fadt->x_pm_tmr_blk.addrh = 0; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 128; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0; - - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 76c4ac9..e5a8ea0 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -46,6 +46,9 @@ chip northbridge/intel/sandybridge # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/intel/emeraldlake2/fadt.c b/src/mainboard/intel/emeraldlake2/fadt.c deleted file mode 100644 index 315cb58..0000000 --- a/src/mainboard/intel/emeraldlake2/fadt.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 5dfd6cc..a627c81 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -41,6 +41,9 @@ chip northbridge/intel/sandybridge # Disable root port coalescing register "pcie_port_coalesce" = "0" + register "c2_latency" = "101" /* c2 not supported */ + register "p_cnt_throttling_supported" = "1" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/kontron/ktqm77/fadt.c b/src/mainboard/kontron/ktqm77/fadt.c deleted file mode 100644 index b8da1be..0000000 --- a/src/mainboard/kontron/ktqm77/fadt.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 168e0e7..0a1ba30 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -64,6 +64,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" /* c2 not supported */ + register "p_cnt_throttling_supported" = "1" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end device pci 16.2 off end diff --git a/src/mainboard/lenovo/t520/fadt.c b/src/mainboard/lenovo/t520/fadt.c deleted file mode 100644 index 27e6303..0000000 --- a/src/mainboard/lenovo/t520/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index ba33601..dc93089 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -63,6 +63,8 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" /* c2 not supported */ + register "p_cnt_throttling_supported" = "1" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/lenovo/t530/fadt.c b/src/mainboard/lenovo/t530/fadt.c deleted file mode 100644 index 27e6303..0000000 --- a/src/mainboard/lenovo/t530/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 1995b84..f4d3c5a 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -68,6 +68,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" /* c2 not supported */ + register "p_cnt_throttling_supported" = "1" + device pci 16.0 on subsystemid 0x17aa 0x21db end # Management Engine Interface 1 diff --git a/src/mainboard/lenovo/x220/fadt.c b/src/mainboard/lenovo/x220/fadt.c deleted file mode 100644 index 27e6303..0000000 --- a/src/mainboard/lenovo/x220/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index c59d802..7b4b76e 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -67,6 +67,8 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" /* c2 not supported */ + register "p_cnt_throttling_supported" = "1" device pci 14.0 on subsystemid 0x17aa 0x21fa diff --git a/src/mainboard/lenovo/x230/fadt.c b/src/mainboard/lenovo/x230/fadt.c deleted file mode 100644 index 27e6303..0000000 --- a/src/mainboard/lenovo/x230/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index a5b96e2..9b0fc40 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -56,6 +56,9 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x003c0a01" register "gen2_dec" = "0x003c0b01" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/samsung/lumpy/fadt.c b/src/mainboard/samsung/lumpy/fadt.c deleted file mode 100644 index 510b765..0000000 --- a/src/mainboard/samsung/lumpy/fadt.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 9769ca4..60b112b 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -42,6 +42,9 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/mainboard/samsung/stumpy/fadt.c b/src/mainboard/samsung/stumpy/fadt.c deleted file mode 100644 index 315cb58..0000000 --- a/src/mainboard/samsung/stumpy/fadt.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 4b1931f..767193e 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select PER_DEVICE_ACPI_TABLES + select COMMON_FADT config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index d1d6401..1256129 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -83,6 +83,10 @@ struct southbridge_intel_bd82x6x_config { uint8_t pcie_aspm_f5; uint8_t pcie_aspm_f6; uint8_t pcie_aspm_f7; + + int p_cnt_throttling_supported; + int c2_latency; + int docking_supported; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 521e847..0d05cc1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -32,6 +32,7 @@ #include <elog.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> +#include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> #include "pch.h" @@ -705,6 +706,138 @@ static void southbridge_inject_dsdt(void) } } +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *chip = dev->chip_info; + u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + int c2_latency; + + fadt->model = 1; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + c2_latency = chip->c2_latency; + if (!c2_latency) { + c2_latency = 101; /* c2 unsupported */ + } + fadt->p_lvl2_lat = c2_latency; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + if (chip->p_cnt_throttling_supported) { + fadt->duty_width = 3; + } else { + fadt->duty_width = 0; + } + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + if (chip->docking_supported) { + fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + } + if (c2_latency < 100) { + fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; + } + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index f628270..97bfcb0 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select PER_DEVICE_ACPI_TABLES + select COMMON_FADT config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_bd82x6x/chip.h b/src/southbridge/intel/fsp_bd82x6x/chip.h index 2415224..7d7ee87 100644 --- a/src/southbridge/intel/fsp_bd82x6x/chip.h +++ b/src/southbridge/intel/fsp_bd82x6x/chip.h @@ -87,6 +87,9 @@ struct southbridge_intel_fsp_bd82x6x_config { uint8_t pcie_aspm_f5; uint8_t pcie_aspm_f6; uint8_t pcie_aspm_f7; + + int p_cnt_throttling_supported; + int c2_latency; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e5d63b6..86cce06 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -33,6 +33,7 @@ #include <elog.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> +#include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> #include "pch.h" @@ -656,6 +657,135 @@ static void southbridge_inject_dsdt(void) } } +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *chip = dev->chip_info; + u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + int c2_latency; + + fadt->model = 1; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + c2_latency = chip->c2_latency; + if (!c2_latency) { + c2_latency = 101; /* c2 unsupported */ + } + fadt->p_lvl2_lat = c2_latency; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + if (chip->p_cnt_throttling_supported) { + fadt->duty_width = 3; + } else { + fadt->duty_width = 0; + } + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + if (c2_latency < 100) { + fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; + } + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, };

1 0

Patch set updated for coreboot: b21c7b0 ibexpeak: Move to common FADT
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7201 -gerrit commit b21c7b013b575bfa7a0f6496b0717257713201e9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 25 15:49:23 2014 +0200 ibexpeak: Move to common FADT Change-Id: Ibb4dcc4356876f6385e79c10d8296fb680937827 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/devicetree.cb | 2 +- src/mainboard/kontron/ktqm77/devicetree.cb | 2 +- src/mainboard/lenovo/t520/devicetree.cb | 2 +- src/mainboard/lenovo/t530/devicetree.cb | 2 +- src/mainboard/lenovo/x201/devicetree.cb | 4 + src/mainboard/lenovo/x201/fadt.c | 160 --------------------------- src/mainboard/lenovo/x220/devicetree.cb | 2 +- src/mainboard/lenovo/x230/devicetree.cb | 2 +- src/mainboard/packardbell/ms2290/fadt.c | 160 --------------------------- src/southbridge/intel/bd82x6x/lpc.c | 1 + src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/ibexpeak/lpc.c | 132 ++++++++++++++++++++++ 12 files changed, 144 insertions(+), 326 deletions(-) diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index b6d41f6..ed0d8d1 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -61,7 +61,7 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" /* c2 not supported */ + register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" device pci 14.0 on end # USB 3.0 Controller diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index a627c81..855fd5c 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -41,7 +41,7 @@ chip northbridge/intel/sandybridge # Disable root port coalescing register "pcie_port_coalesce" = "0" - register "c2_latency" = "101" /* c2 not supported */ + register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" device pci 14.0 on end # USB 3.0 Controller diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 0a1ba30..486e8d2 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -64,7 +64,7 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" /* c2 not supported */ + register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index dc93089..c1cbca2 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -63,7 +63,7 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" /* c2 not supported */ + register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" device pci 14.0 on end # USB 3.0 Controller diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6920d2a..d467e92 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -109,6 +109,10 @@ chip northbridge/intel/nehalem register "gen3_dec" = "0x1c1681" register "gen4_dec" = "0x040069" + register "p_cnt_throttling_supported" = "1" + register "c2_latency" = "1" + register "docking_supported" = "1" + device pci 16.2 on # IDE/SATA subsystemid 0x17aa 0x2161 end diff --git a/src/mainboard/lenovo/x201/fadt.c b/src/mainboard/lenovo/x201/fadt.c deleted file mode 100644 index 0639026..0000000 --- a/src/mainboard/lenovo/x201/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = - pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - 0x40) & 0xfffe; - - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 0; - - fadt->firmware_ctrl = (unsigned long)facs; - fadt->dsdt = (unsigned long)dsdt; - fadt->model = 0x00; - fadt->preferred_pm_profile = PM_MOBILE; - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 0x10; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = APM_CNT_CST_CONTROL; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 0x23; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x32; - fadt->iapc_boot_arch = 0x00; - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_DOCKING_SUPPORTED; - - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 0; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 0; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 32; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 0; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 0; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *)fadt, header->length); -} diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index f4d3c5a..c1ed116 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -68,7 +68,7 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" /* c2 not supported */ + register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" device pci 16.0 on diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 7b4b76e..f9f8d26 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -67,7 +67,7 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" /* c2 not supported */ + register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" device pci 14.0 on diff --git a/src/mainboard/packardbell/ms2290/fadt.c b/src/mainboard/packardbell/ms2290/fadt.c deleted file mode 100644 index 0639026..0000000 --- a/src/mainboard/packardbell/ms2290/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = - pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - 0x40) & 0xfffe; - - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 0; - - fadt->firmware_ctrl = (unsigned long)facs; - fadt->dsdt = (unsigned long)dsdt; - fadt->model = 0x00; - fadt->preferred_pm_profile = PM_MOBILE; - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 0x10; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = APM_CNT_CST_CONTROL; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 0x23; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x32; - fadt->iapc_boot_arch = 0x00; - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_DOCKING_SUPPORTED; - - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 0; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 0; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 32; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 0; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 0; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *)fadt, header->length); -} diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0d05cc1..20f20ae 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -35,6 +35,7 @@ #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> +#include <cpu/x86/smm.h> #include "pch.h" #include "nvs.h" diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index dfd8276..07a5ac2 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select HAVE_USBDEBUG_OPTIONS select PER_DEVICE_ACPI_TABLES + select COMMON_FADT config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index db8f54f..da609da 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -35,6 +35,7 @@ #include <drivers/intel/gma/i915.h> #include <cbmem.h> #include <string.h> +#include <cpu/x86/smm.h> #include "pch.h" #include "nvs.h" @@ -690,6 +691,137 @@ static void southbridge_inject_dsdt(void) } } +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *chip = dev->chip_info; + u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + int c2_latency; + + fadt->model = 1; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + c2_latency = chip->c2_latency; + if (!c2_latency) { + c2_latency = 101; /* c2 unsupported */ + } + fadt->p_lvl2_lat = c2_latency; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + if (chip->p_cnt_throttling_supported) { + fadt->duty_width = 3; + } else { + fadt->duty_width = 0; + } + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + if (chip->docking_supported) { + fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + } + if (c2_latency < 100) { + fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; + } + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, };

1 0

Patch set updated for coreboot: 351e880 lenovo/x2[23]0: Handle Ricoh SD cardreader
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7203 -gerrit commit 351e88093d9cb4a3fab345782fed91f2fabd6586 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Oct 27 02:45:22 2014 +0100 lenovo/x2[23]0: Handle Ricoh SD cardreader Change-Id: Id0aecbd3e45bdf9661168ebd0e55f17dc6febaaa Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/ricoh/rce822/Kconfig | 3 ++ src/drivers/ricoh/rce822/Makefile.inc | 1 + src/drivers/ricoh/rce822/chip.h | 29 ++++++++++++ src/drivers/ricoh/rce822/rce822.c | 79 +++++++++++++++++++++++++++++++++ src/mainboard/lenovo/x220/Kconfig | 1 + src/mainboard/lenovo/x220/devicetree.cb | 11 ++--- src/mainboard/lenovo/x230/Kconfig | 1 + src/mainboard/lenovo/x230/devicetree.cb | 11 ++--- 10 files changed, 128 insertions(+), 10 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 42d1583..12f9a79 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -39,3 +39,4 @@ source src/drivers/trident/Kconfig source src/drivers/uart/Kconfig source src/drivers/usb/Kconfig source src/drivers/xpowers/Kconfig +source src/drivers/ricoh/rce822/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index cb26643..7ae3eb2 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -38,3 +38,4 @@ subdirs-y += ipmi subdirs-y += elog subdirs-y += xpowers subdirs-$(CONFIG_ARCH_X86) += pc80 +subdirs-y += ricoh/rce822 diff --git a/src/drivers/ricoh/rce822/Kconfig b/src/drivers/ricoh/rce822/Kconfig new file mode 100644 index 0000000..6b0c790 --- /dev/null +++ b/src/drivers/ricoh/rce822/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_RICOH_RCE822 + bool + default n diff --git a/src/drivers/ricoh/rce822/Makefile.inc b/src/drivers/ricoh/rce822/Makefile.inc new file mode 100644 index 0000000..738bd0e --- /dev/null +++ b/src/drivers/ricoh/rce822/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_RICOH_RCE822) += rce822.c diff --git a/src/drivers/ricoh/rce822/chip.h b/src/drivers/ricoh/rce822/chip.h new file mode 100644 index 0000000..cfed32e --- /dev/null +++ b/src/drivers/ricoh/rce822/chip.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DRIVERS_RICOH_RC822_CHIP_H +#define DRIVERS_RICOH_RC822_CHIP_H + +struct drivers_ricoh_rce822_config { + u8 sdwppol:1; + u8 disable_mask; +}; + +#endif diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c new file mode 100644 index 0000000..2383f4b --- /dev/null +++ b/src/drivers/ricoh/rce822/rce822.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <kconfig.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "chip.h" + +static void rce822_enable(struct device *dev) +{ + struct drivers_ricoh_rce822_config *config = dev->chip_info; + + pci_write_config8(dev, 0xca, 0x57); + pci_write_config8(dev, 0xcb, config->disable_mask); + pci_write_config8(dev, 0xca, 0x00); +} + +static void rce822_init(struct device *dev) +{ + struct drivers_ricoh_rce822_config *config = dev->chip_info; + + pci_write_config8(dev, 0xf9, 0xfc); + pci_write_config8(dev, 0xfb, config->sdwppol << 1); + pci_write_config8(dev, 0xf9, 0x00); +} + +static void rce822_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + + if (!vendor || !device) { + pci_write_config32(dev, 0xac, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, 0xac, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations lops_pci = { + .set_subsystem = &rce822_set_subsystem, +}; + +static struct device_operations usb_ehci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = rce822_init, + .enable = rce822_enable, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const unsigned short pci_device_ids[] = { 0xe822, 0xe823, 0 }; + +static const struct pci_driver pch_usb_ehci __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_RICOH, + .devices = pci_device_ids, +}; diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 9a9b143..861f3a4 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select SANDYBRIDGE_LVDS + select DRIVERS_RICOH_RCE822 # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index c1ed116..c3b8ad9 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -100,11 +100,12 @@ chip northbridge/intel/sandybridge end # PCIe Port #4 device pci 1c.4 on subsystemid 0x17aa 0x21db - device pci 00.0 on - subsystemid 0x17aa 0x21db - end - device pci 00.1 on - subsystemid 0x17aa 0x21db + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on + subsystemid 0x17aa 0x21fa + end end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 839fc42..49dab80 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select IVYBRIDGE_LVDS + select DRIVERS_RICOH_RCE822 # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index f9f8d26..f2fed1f 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -90,11 +90,12 @@ chip northbridge/intel/sandybridge end # High Definition Audio device pci 1c.0 on subsystemid 0x17aa 0x21fa - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end - device pci 00.1 on - subsystemid 0x17aa 0x21fa + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on + subsystemid 0x17aa 0x21fa + end end end # PCIe Port #1 device pci 1c.1 on

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Patch set updated for coreboot: d7f5f70 autoport: Experimental stuff
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7131 -gerrit commit d7f5f70ff2aae202cca6ffc9f84f25bb01bb425a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 21:51:47 2014 +0200 autoport: Experimental stuff Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/autoport/azalia.go | 54 +++++ util/autoport/bd82x6x.go | 181 ++++++++++++++++ util/autoport/hardcoded.go | 407 +++++++++++++++++++++++++++++++++++ util/autoport/i82801gx.go | 265 +++++++++++++++++++++++ util/autoport/i945.go | 82 +++++++ util/autoport/log_maker.go | 77 +++++++ util/autoport/log_reader.go | 264 +++++++++++++++++++++++ util/autoport/main.go | 500 +++++++++++++++++++++++++++++++++++++++++++ util/autoport/root.go | 28 +++ util/autoport/sandybridge.go | 112 ++++++++++ 10 files changed, 1970 insertions(+) diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go new file mode 100644 index 0000000..97e3449 --- /dev/null +++ b/util/autoport/azalia.go @@ -0,0 +1,54 @@ +package main + +import ( + "fmt" +) + +type azalia struct { +} + +func (i azalia) Scan(ctx Context, addr PCIDevData) { + az := Create(ctx, "hda_verb.c") + defer az.Close() + + az.WriteString( + `#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +`) + + for _, codec := range ctx.InfoSource.GetAzaliaCodecs() { + fmt.Fprintf(az, "\t0x%08x, /* Codec Vendor / Device ID: %s */\n", + codec.VendorID, codec.Name) + fmt.Fprintf(az, "\t0x%08x, /* Subsystem ID */\n", + codec.SubsystemID) + fmt.Fprintf(az, "\n\t0x%08x, /* Number of 4 dword sets */\n", + len(codec.PinConfig)+1) + fmt.Fprintf(az, "\t/* NID 0x01: Subsystem ID. */\n") + fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n", + codec.CodecNo, codec.SubsystemID) + + for nid, val := range codec.PinConfig { + fmt.Fprintf(az, "\n\t/* NID 0x%02x: Subsystem ID. */\n", nid) + fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n", + codec.CodecNo, nid, val) + } + } + + az.WriteString( + `}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; +`) + + PutPCIDev(addr, "Audio controller") +} + +func init() { + /* I82801GX/I945 */ + RegisterPCI(0x8086, 0x27d8, azalia{}) + /* C216/ivybridge */ + RegisterPCI(0x8086, 0x1e20, azalia{}) +} diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go new file mode 100644 index 0000000..e7c6e75 --- /dev/null +++ b/util/autoport/bd82x6x.go @@ -0,0 +1,181 @@ +package main + +import ( + "fmt" + "os" +) + +type bd82x6x struct { + variant string +} + +func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + { "GPIO_MODE_NATIVE", "GPIO_MODE_GPIO" }, + { "GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT" }, + { "GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH" }, + { "GPIO_RESET_PWROK", "GPIO_RESET_RSMRST" }, + { "GPIO_NO_INVERT", "GPIO_INVERT" }, + { "GPIO_NO_BLINK", "GPIO_BLINK" }, + } + + for i := uint(0); i < max; i++ { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set - 1) * 32 + i, + bits[partno][(val >> i) & 1]) + } +} + + +func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) { + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMstageFile("gpio.c", "") + + gpio.WriteString(`#include "southbridge/intel/bd82x6x/gpio.h" +`) + + adresses := [3][6]int{ + { 0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18 }, + { 0x30, 0x34, 0x38, 0x64, -1, -1 }, + { 0x40, 0x44, 0x48, 0x68, -1, -1 }, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := adresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`static const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} + +func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + b.GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_" + b.variant] = true + /* FIMXE: move */ + KconfigBool["HAVE_SMI_HANDLER"] = true + KconfigInt["IRQ_SLOT_COUNT"] = 18 + /* FIXME: hardcoded */ + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + /* FIXME: hardcoded */ + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + /* FIXME: hardcoded */ + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + cur := DevTreeNode{ + Chip: "southbridge/intel/bd82x6x", + Comment: "Intel Series 6 Cougar Point PCH", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "alt_gp_smi_en": "0x0000", + "gpi1_routing": "2", + "gpi8_routing": "2", + "sata_port_map": "0x7", + "sata_interface_speed_support": "0x3", + "gen1_dec": "0x7c1601", + "gen2_dec": "0x0c15e1", + "gen4_dec": "0x0c06a1", + "pcie_port_coalesce": "1", + + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c2_latency": FormatHexLE16(FADT[96:98]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr:PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + PutChip("pcibus0", cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/pch.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x1e55, bd82x6x{variant:"C216"}) + RegisterPCI(0x8086, 0x1e31, GenericPCI{}) + RegisterPCI(0x8086, 0x1e26, GenericPCI{}) + RegisterPCI(0x8086, 0x1e2d, GenericPCI{}) + RegisterPCI(0x8086, 0x1e3a, GenericPCI{}) + RegisterPCI(0x8086, 0x1502, GenericPCI{}) + RegisterPCI(0x8086, 0x1e10, GenericPCI{}) + RegisterPCI(0x8086, 0x1e12, GenericPCI{}) + RegisterPCI(0x8086, 0x1e14, GenericPCI{}) + RegisterPCI(0x8086, 0x1e03, GenericPCI{}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) +} diff --git a/util/autoport/hardcoded.go b/util/autoport/hardcoded.go new file mode 100644 index 0000000..584ddd8 --- /dev/null +++ b/util/autoport/hardcoded.go @@ -0,0 +1,407 @@ +package main + +func Hardcoded(ctx Context) { + ai := Create(ctx, "acpi/ich7_pci_irqs.asl") + defer ai.Close() + + /* FIXME: hardcoded. */ + ai.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} +`) + ap := Create(ctx, "acpi/platform.asl") + defer ap.Close() + + /* FIXME: hardcoded. */ + ap.WriteString( + `Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Scope(\_SB) +{ + Method(_INI, 0) + { + \GOS() + } +} +`) + sh := Create(ctx, "smihandler.c") + defer sh.Close() + + /* FIXME: hardcoded. */ + sh.WriteString( + ` +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include <pc80/mc146818rtc.h> +#include <delay.h> + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + case APM_CNT_ACPI_DISABLE: + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + default: + break; + } + return 0; +} +`) + mb := Create(ctx, "mainboard.c") + defer mb.Close() + + /* FIXME: hardcoded. */ + mb.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <northbridge/intel/i945/i945.h> +#include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> +#include <drivers/intel/gma/int15.h> +#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} + +static void mainboard_init(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; +`) + + em := Create(ctx, "early_mainboard.h") + defer em.Close() + + /* FIXME: hardcoded. */ + em.WriteString( + `void ich7_enable_lpc(void); +void rcba_config(void); +void early_ich7_init(void); +`) + + rs := Create(ctx, "romstage.c") + defer rs.Close() + + /* FIXME: hardcoded. */ + rs.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <cpu/x86/lapic.h> +#include <timestamp.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "early_mainboard.h" + +void main(unsigned long bist) +{ + int s3resume = 0; + const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + + ich7_enable_lpc(); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, + "Soft reset detected, rebooting properly.\n"); + outb(0x6, 0xcf9); + while (1) + asm("hlt"); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(s3resume ? 2 : 0, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); + + timestamp_add_now(TS_END_ROMSTAGE); +} +`) + + at := Create(ctx, "acpi_tables.c") + defer at.Close() + + /* FIXME: hardcoded. */ + at.WriteString( + `#include <stdint.h> +#include "southbridge/intel/i82801gx/nvs.h" +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} +`) + + av := Create(ctx, "acpi/video.asl") + defer av.Close() + + ec := Create(ctx, "acpi/ec.asl") + defer ec.Close() + + si := Create(ctx, "acpi/superio.asl") + defer si.Close() +} diff --git a/util/autoport/i82801gx.go b/util/autoport/i82801gx.go new file mode 100644 index 0000000..f82de8a --- /dev/null +++ b/util/autoport/i82801gx.go @@ -0,0 +1,265 @@ +package main + +import ( + "fmt" + "os" +) + +type i82801gx struct { +} + +func (i i82801gx) writeGPIO(ctx Context, sb *os.File, inteltool InteltoolData, addr uint16, name string) { + fmt.Fprintf(sb, " outl(0x%08x, DEFAULT_GPIOBASE + %s);\n", + inteltool.GPIO[addr], name) +} + +func (i i82801gx) Scan(ctx Context, addr PCIDevData) { + + /* FIXME: Move to southbbridge. */ + KconfigBool["HAVE_MP_TABLE"] = true + + KconfigBool["SOUTHBRIDGE_INTEL_I82801GX"] = true + KconfigInt["IRQ_SLOT_COUNT"] = 18 + + sb := Create(ctx, "early_southbridge.c") + defer sb.Close() + AddROMstageFile("early_southbridge.c", "") + sb.WriteString(`#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "northbridge/intel/i945/i945.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include "early_mainboard.h" + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + +`) + inteltool := ctx.InfoSource.GetInteltool() + i.writeGPIO(ctx, sb, inteltool, 0x0, "GPIO_USE_SEL") + i.writeGPIO(ctx, sb, inteltool, 0x4, "GP_IO_SEL") + i.writeGPIO(ctx, sb, inteltool, 0xc, "GP_LVL") + i.writeGPIO(ctx, sb, inteltool, 0x18, "GPO_BLINK") + i.writeGPIO(ctx, sb, inteltool, 0x2c, "GPI_INV") + i.writeGPIO(ctx, sb, inteltool, 0x30, "GPIO_USE_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x34, "GP_IO_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x38, "GP_LVL2") + + sb.WriteString(`} + +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // Enable address decodes + /* FIXME: Make sure that all regions are properly reserved. */ +`) + + /* FIXME: Make sure that all regions are properly reserved. */ + RestorePCI16Simple(sb, addr, 0x80) + RestorePCI16Simple(sb, addr, 0x82) + RestorePCI16Simple(sb, addr, 0x84) + RestorePCI16Simple(sb, addr, 0x86) + RestorePCI16Simple(sb, addr, 0x88) + RestorePCI16Simple(sb, addr, 0x8a) + RestorePCI16Simple(sb, addr, 0x8c) + RestorePCI16Simple(sb, addr, 0x8e) + RestorePCI16Simple(sb, addr, 0x90) + RestorePCI16Simple(sb, addr, 0x92) + + /* Just use the same interrupt map for all boards: just registers have to match ACPI. */ + sb.WriteString(`} + +void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Disable devices. */ +`) + + RestoreRCBA32(sb, inteltool, 0x3418) + + sb.WriteString(` + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} +`) + + /* FIXME: does this one need adjustments? */ + sb.WriteString(`void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} +`) + + Hardcoded(ctx) + + ioapic := DevTreeNode{ + Chip: "drivers/generic/ioapic", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "have_isa_interrupts": "1", + "irq_on_fsb": "1", + "enable_virtual_wire": "0", + "base": "0xfec00000", + }, + Children: []DevTreeNode{ + { + Chip: "ioapic", + Dev: 2, + }, + }, + } + + PutChip("pcibus0", ioapic) + + ideConfig := PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 1}].ConfigDump[0x54] + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + cur := DevTreeNode{ + Chip: "southbridge/intel/i82801gx", + Comment: "Southbridge", + MissingParent: "southbridge", + Registers: map[string]string{ + /* FIXME: should be a CMOS config */ + "sata_ahci": "0x1", + /* FIXME: hardcoded. */ + "gpi1_routing": "2", + "gpi7_routing": "2", + "gpe0_en": "0x11000006", + "alt_gp_smi_en": "0x1000", + + "sata_ports_implemented": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0xf), + "ide_enable_primary": fmt.Sprintf("%d", (ideConfig>>1)&1), + "ide_enable_secondary": fmt.Sprintf("%d", (ideConfig>>3)&1), + "c4onc3_enable": fmt.Sprintf("%d", ((addr.ConfigDump[0xa0] >> 7) & 1)), + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c3_latency": FormatHexLE16(FADT[98:100]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr:PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 1}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 2}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 3}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 7}, writeEmpty: true, additionalComment: "USB EHCI"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 1}, writeEmpty: true, additionalComment: "IDE Controller"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + }, + } + + PutChip("pcibus0", cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x00}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x07}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1b}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1c}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x11, 0x10, 0x12, 0x13}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1d}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x17, 0x13, 0x12, 0x10}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1e}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0x14, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1f}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x12, 0x13, 0, 0x10}} + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/ich7.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x27b9, i82801gx{}) + RegisterPCI(0x8086, 0x27c8, GenericPCI{}) + RegisterPCI(0x8086, 0x27c9, GenericPCI{}) + RegisterPCI(0x8086, 0x27ca, GenericPCI{}) + RegisterPCI(0x8086, 0x27cb, GenericPCI{}) + RegisterPCI(0x8086, 0x27cc, GenericPCI{}) + + RegisterPCI(0x8086, 0x27d0, GenericPCI{}) + RegisterPCI(0x8086, 0x27d2, GenericPCI{}) + RegisterPCI(0x8086, 0x27d4, GenericPCI{}) + RegisterPCI(0x8086, 0x27d6, GenericPCI{}) + + RegisterPCI(0x8086, 0x2448, GenericPCI{}) + + RegisterPCI(0x8086, 0x27c5, GenericPCI{}) + RegisterPCI(0x8086, 0x27c4, GenericPCI{}) + RegisterPCI(0x8086, 0x27df, GenericPCI{}) + RegisterPCI(0x8086, 0x27da, GenericPCI{MissingParent:"smbus"}) +} diff --git a/util/autoport/i945.go b/util/autoport/i945.go new file mode 100644 index 0000000..013197e --- /dev/null +++ b/util/autoport/i945.go @@ -0,0 +1,82 @@ +package main + +type i945mc struct { +} + +func (i i945mc) Scan(ctx Context, addr PCIDevData) { + DevTree = DevTreeNode{ + Chip: "northbridge/intel/i945", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "gpu_hotplug": "0x00000220", + "gpu_lvds_use_spread_spectrum_clock": "1", + "gpu_lvds_is_dual_channel": "0", + "gpu_backlight": "0x1280128", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_mFCPGA478", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + }, + }, + { + Chip: "domain", + Dev: 0, + MissingParent: "pcibus0", + PCIController: true, + ChildPCIBus: 0, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME: Move part to northbridge? */ + /* FIXME: some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool["VGA"] = true + KconfigBool["MAINBOARD_DO_EDID"] = true + KconfigBool["EARLY_CBMEM_INIT"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_MFCPGA478"] = true + KconfigBool["NORTHBRIDGE_INTEL_I945"] = true + KconfigBool["CHANNEL_XOR_RANDOMIZATION"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigHex["DCACHE_RAM_BASE"] = 0xffdf8000 + KconfigHex["DCACHE_RAM_SIZE"] = 0x8000 + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 2 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_6dx/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/i945/acpi/i945.asl", + }) + + /* FIXME: when adding new i945 variants change this. */ + KconfigBool["NORTHBRIDGE_INTEL_SUBTYPE_I945GM"] = true +} + +func init() { + RegisterPCI(0x8086, 0x27a0, i945mc{}) + RegisterPCI(0x8086, 0x27ac, i945mc{}) + RegisterPCI(0x8086, 0x27a2, GenericVGA{GenericPCI{Comment:"VGA controller"}}) + RegisterPCI(0x8086, 0x27ae, GenericVGA{GenericPCI{Comment:"VGA controller"}}) + RegisterPCI(0x8086, 0x27a6, GenericPCI{Comment:"display controller"}) +} diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go new file mode 100644 index 0000000..f172520 --- /dev/null +++ b/util/autoport/log_maker.go @@ -0,0 +1,77 @@ +package main + +import ( + "io" + "io/ioutil" + "log" + "os" + "os/exec" + "strings" +) + +func RunAndSave(output string, name string, arg ...string) { + cmd := exec.Command(name, arg...) + + f, err := os.Create(output) + if err != nil { + log.Fatal(err) + } + + cmd.Stdout = f + cmd.Stderr = f + + err = cmd.Start() + if err != nil { + log.Fatal(err) + } + cmd.Wait() +} + +func MakeLogs(outDir string) { + os.MkdirAll(outDir, 0700) + RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx") + RunAndSave(outDir+"/dmidecode.log", "dmidecode") + RunAndSave(outDir+"/acpidump.log", "acpidump") + /* FIXME */ + RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", "-a") + + SysDir := "/sys/class/sound/card0/" + files, _ := ioutil.ReadDir(SysDir) + for _, f := range files { + if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { + in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + ProcDir := "/proc/asound/card0/" + files, _ = ioutil.ReadDir(ProcDir) + for _, f := range files { + if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { + in, err := os.Open(ProcDir + f.Name()) + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/" + f.Name()) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + /* + l.InputDirectory + "/inteltool.log" + */ +} diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go new file mode 100644 index 0000000..4e89cf2 --- /dev/null +++ b/util/autoport/log_reader.go @@ -0,0 +1,264 @@ +package main + +import ( + "bufio" + "flag" + "fmt" + "log" + "os" + "strconv" + "strings" +) + +type LogDevReader struct { + InputDirectory string + ACPITables map[string][]byte +} + +func isXDigit(x uint8) bool { + if x >= '0' && x <= '9' { + return true + } + if x >= 'a' && x <= 'f' { + return true + } + if x >= 'A' && x <= 'F' { + return true + } + return false +} + +type HexLine struct { + length uint + values [16]byte + start uint +} + +func (l *LogDevReader) ReadHexLine(line string) (hex HexLine) { + hex.start = 0 + line = strings.Trim(line, " ") + fmt.Sscanf(line, "%x:", &hex.start) + ll, _ := fmt.Sscanf(line, "%x: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x", &hex.start, + &hex.values[0], &hex.values[1], &hex.values[2], + &hex.values[3], &hex.values[4], &hex.values[5], + &hex.values[6], &hex.values[7], &hex.values[8], + &hex.values[9], &hex.values[10], &hex.values[11], + &hex.values[12], &hex.values[13], &hex.values[14], + &hex.values[15]) + hex.length = uint(ll - 1) + return +} + +func (l *LogDevReader) AssignHexLine(inp string, target []byte) []byte { + hex := l.ReadHexLine(inp) + if hex.start+hex.length > uint(len(target)) { + target = target[0 : hex.start+hex.length] + } + copy(target[hex.start:hex.start+hex.length], hex.values[0:hex.length]) + return target +} + +func (l *LogDevReader) GetACPI() (Tables map[string][]byte) { + if l.ACPITables != nil { + return l.ACPITables + } + l.ACPITables = Tables + + file, err := os.Open(l.InputDirectory + "/acpidump.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + Tables = map[string][]byte{} + + curTable := "" + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) >= 6 && line[5] == '@': + curTable = line[0:4] + Tables[curTable] = make([]byte, 0, 100000) + case len(line) > 7 && line[0:2] == " " && isXDigit(line[2]) && isXDigit(line[3]) && isXDigit(line[4]) && isXDigit(line[5]) && line[6] == ':': + Tables[curTable] = l.AssignHexLine(line, Tables[curTable]) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetPCIList() (PCIList []PCIDevData) { + file, err := os.Open(l.InputDirectory + "/lspci.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + PCIList = []PCIDevData{} + + for scanner.Scan() { + line := scanner.Text() + switch { + case !(len(line) < 7 || !isXDigit(line[0]) || !isXDigit(line[1]) || line[2] != ':' || !isXDigit(line[3]) || !isXDigit(line[4]) || line[5] != '.' || !isXDigit(line[6])): + cur := PCIDevData{} + fmt.Sscanf(line, "%x:%x.%x", &cur.Bus, &cur.Dev, &cur.Func) + lc := strings.LastIndex(line, ":") + li := strings.LastIndex(line[0:lc], "[") + if li < 0 { + continue + } + ven := 0 + dev := 0 + fmt.Sscanf(line[li+1:], "%x:%x", &ven, &dev) + cur.PCIDevID = uint16(dev) + cur.PCIVenID = uint16(ven) + cur.ConfigDump = make([]byte, 0x100, 0x1000) + PCIList = append(PCIList, cur) + case len(line) > 7 && isXDigit(line[0]) && line[1] == '0' && line[2] == ':': + start := 0 + fmt.Sscanf(line, "%x:", &start) + cur := &PCIList[len(PCIList)-1] + cur.ConfigDump = l.AssignHexLine(line, cur.ConfigDump) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetInteltool() (ret InteltoolData) { + file, err := os.Open(l.InputDirectory + "/inteltool.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + ret.GPIO = map[uint16]uint32{} + ret.RCBA = map[uint16]uint32{} + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "RCBA": + addr, value := 0, 0 + fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value) + ret.RCBA[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "gpiobase"): + addr, value := 0, 0 + fmt.Sscanf(line, "gpiobase+0x%x: 0x%x", &addr, &value) + ret.GPIO[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "============="): + paragraph = strings.Trim(line, "= ") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetDMI() (ret DMIData) { + file, err := os.Open(l.InputDirectory + "/dmidecode.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + for scanner.Scan() { + line := scanner.Text() + if !strings.HasPrefix(line, "\t") { + paragraph = strings.TrimSpace(line) + continue + } + idx := strings.Index(line, ":") + if idx < 0 { + continue + } + name := strings.TrimSpace(line[0:idx]) + value := strings.TrimSpace(line[idx+1:]) + switch paragraph + ":" + name { + case "System Information:Manufacturer": + ret.Vendor = value + case "System Information:Product Name": + ret.Model = value + case "System Information:Version": + ret.Version = value + case "Chassis Information:Type": + ret.IsLaptop = (value == "Notebook" || value == "Laptop") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetAzaliaCodecs() (ret []AzaliaCodec) { + for codecno := 0; codecno < 10; codecno++ { + cur := AzaliaCodec{CodecNo: codecno, PinConfig: map[int]uint32{}} + codec, err := os.Open(l.InputDirectory + "/codec#" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer codec.Close() + pin, err := os.Open(l.InputDirectory + "/pin_hwC0D" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer pin.Close() + + scanner := bufio.NewScanner(codec) + for scanner.Scan() { + line := scanner.Text() + if strings.HasPrefix(line, "Codec:") { + fmt.Sscanf(line, "Codec: %s", &cur.Name) + continue + } + if strings.HasPrefix(line, "Vendor Id:") { + fmt.Sscanf(line, "Vendor Id: 0x%x", &cur.VendorID) + continue + } + if strings.HasPrefix(line, "Subsystem Id:") { + fmt.Sscanf(line, "Subsystem Id: 0x%x", &cur.SubsystemID) + continue + } + } + + scanner = bufio.NewScanner(pin) + for scanner.Scan() { + line := scanner.Text() + addr := 0 + val := uint32(0) + fmt.Sscanf(line, "0x%x 0x%x", &addr, &val) + cur.PinConfig[addr] = val + } + ret = append(ret, cur) + } + return +} + +var FlagLogInput = flag.String("input_log", ".", "Input log directory") +var FlagLogMkLogs = flag.Bool("make_logs", false, "Dump logs") + +func MakeLogReader() *LogDevReader { + if *FlagLogMkLogs { + MakeLogs(*FlagLogInput) + } + return &LogDevReader{InputDirectory: *FlagLogInput} +} diff --git a/util/autoport/main.go b/util/autoport/main.go new file mode 100644 index 0000000..d24952e --- /dev/null +++ b/util/autoport/main.go @@ -0,0 +1,500 @@ +/* This is just an experiment. Full automatic porting + is probably not possible but a lot can be automated. */ +package main + +import ( + "flag" + "fmt" + "log" + "os" + "strings" +) + +type PCIAddr struct { + Bus int + Dev int + Func int +} + +type PCIDevData struct { + PCIAddr + PCIVenID uint16 + PCIDevID uint16 + ConfigDump []uint8 +} + +type PCIDevice interface { + Scan(ctx Context, addr PCIDevData) +} + +type InteltoolData struct { + GPIO map[uint16]uint32 + RCBA map[uint16]uint32 +} + +type DMIData struct { + Vendor string + Model string + Version string + IsLaptop bool +} + +type AzaliaCodec struct { + Name string + VendorID uint32 + SubsystemID uint32 + CodecNo int + PinConfig map[int]uint32 +} + +type DevReader interface { + GetPCIList() []PCIDevData + GetDMI() DMIData + GetInteltool() InteltoolData + GetAzaliaCodecs() []AzaliaCodec + GetACPI() map[string][]byte +} + +var ROMStageFiles map[string]string = map[string]string{} +var RAMStageFiles map[string]string = map[string]string{} + +type Context struct { + MoboID string + KconfigName string + Vendor string + Model string + BaseDirectory string + InfoSource DevReader +} + +type IOAPICIRQ struct { + APICID int + IRQNO [4]int +} + +var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{} +var KconfigBool map[string]bool = map[string]bool{} +var KconfigString map[string]string = map[string]string{} +var KconfigStringUnquoted map[string]string = map[string]string{} +var KconfigHex map[string]uint32 = map[string]uint32{} +var KconfigInt map[string]int = map[string]int{} + +func FormatHexLE16(inp []byte) string { + return fmt.Sprintf ("0x%04x", uint16(inp[0]) | (uint16(inp[1]) << 8)) +} + +func FormatBool(inp bool) string { + if inp { + return "1" + } else { + return "0" + } +} + +func sanitize(inp string) string { + result := strings.ToLower(inp) + result = strings.Replace(result, " ", "_", -1) + result = strings.Replace(result, ",", "_", -1) + for strings.HasSuffix(result, ".") { + result = result[0 : len(result)-1] + } + return result +} + +func AddROMstageFile(Name string, Condition string) { + ROMStageFiles[Name] = Condition +} + +func AddRAMstageFile(Name string, Condition string) { + RAMStageFiles[Name] = Condition +} + +var FlagOutDir = flag.String("coreboot_dir", ".", "Resulting coreboot directory") + +func writeMF(mf *os.File, files map[string]string, category string) { + for file, condition := range files { + if condition == "" { + fmt.Fprintf(mf, "%s-y += %s\n", category, file) + } else { + fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, + condition, file) + } + } +} + +func Create(ctx Context, name string) *os.File { + li := strings.LastIndex(name, "/") + if li > 0 { + os.MkdirAll(ctx.BaseDirectory+"/"+name[0:li], 0700) + } + mf, err := os.Create(ctx.BaseDirectory + "/" + name) + if err != nil { + log.Fatal(err) + } + return mf +} + +func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestoreRCBA32(f *os.File, inteltool InteltoolData, addr uint16) { + fmt.Fprintf(f, "\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr]) +} + +type PCISlot struct { + PCIAddr + additionalComment string + writeEmpty bool +} + +type DevTreeNode struct { + Bus int + Dev int + Func int + Disabled bool + Registers map[string]string + Children []DevTreeNode + PCISlots []PCISlot + PCIController bool + ChildPCIBus int + MissingParent string + SubVendor uint16 + SubSystem uint16 + Chip string + Comment string +} + +var DevTree DevTreeNode +var MissingChildren map[string][]DevTreeNode = map[string][]DevTreeNode{} +var unmatchedPCIDevices map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} + +func Offset(dt *os.File, offset int) { + for i := 0; i < offset; i++ { + fmt.Fprintf(dt, "\t") + } +} + +func MatchDev(dev *DevTreeNode) { + for _, slot := range dev.PCISlots { + slotDev, ok := unmatchedPCIDevices[slot.PCIAddr] + if !ok { + if slot.writeEmpty { + dev.Children = append(dev.Children, + DevTreeNode{ + Registers: map[string]string{}, + Chip: "pci", + Bus: slot.Bus, + Dev: slot.Dev, + Func: slot.Func, + Comment: slot.additionalComment, + Disabled: true, + }, + ) + } + continue + } + + if slot.additionalComment != "" && slotDev.Comment != "" { + slotDev.Comment = slot.additionalComment + " " + slotDev.Comment + } else { + slotDev.Comment = slot.additionalComment + slotDev.Comment + } + + dev.Children = append(dev.Children, slotDev) + delete (unmatchedPCIDevices, slot.PCIAddr) + } + + for idx := range dev.Children { + MatchDev(&dev.Children[idx]) + } + + if dev.MissingParent != "" { + for _, child := range MissingChildren[dev.MissingParent] { + MatchDev(&child) + dev.Children = append(dev.Children, child) + } + delete (MissingChildren, dev.MissingParent) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIDevices { + if slot.Bus == dev.ChildPCIBus { + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete (unmatchedPCIDevices, slot) + } + } + } +} + +func writeOn(dt *os.File, dev DevTreeNode) { + if dev.Disabled { + fmt.Fprintf(dt, "off") + } else { + fmt.Fprintf(dt, "on") + } +} + +func WriteDev(dt *os.File, offset int, dev DevTreeNode) { + Offset(dt, offset) + switch dev.Chip { + case "cpu_cluster", "lapic", "domain", "ioapic": + fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev) + writeOn(dt, dev) + case "pci": + fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func) + writeOn(dt, dev) + default: + fmt.Fprintf(dt, "chip %s", dev.Chip) + } + if dev.Comment != "" { + fmt.Fprintf(dt, " # %s", dev.Comment) + } + fmt.Fprintf(dt, "\n") + if dev.Chip == "pci" && dev.SubSystem != 0 && dev.SubVendor != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem) + } + + ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}] + if dev.Chip == "pci" && ok { + for pin, irq := range ioapic.IRQNO { + if irq != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq) + } + } + } + + for reg, val := range dev.Registers { + Offset(dt, offset+1) + fmt.Fprintf(dt, "register \"%s\" = \"%s\"\n", reg, val) + } + + for _, child := range dev.Children { + WriteDev(dt, offset+1, child) + } + + Offset(dt, offset) + fmt.Fprintf(dt, "end\n") +} + +func PutChip(domain string, cur DevTreeNode) { + MissingChildren[domain] = append(MissingChildren[domain], cur) +} + +func PutPCIDevParent(addr PCIDevData, comment string, parent string) { + cur := DevTreeNode{ + Registers: map[string]string{}, + SubVendor: uint16(addr.ConfigDump[0x2c]) | (uint16(addr.ConfigDump[0x2d]) << 8), + SubSystem: uint16(addr.ConfigDump[0x2e]) | (uint16(addr.ConfigDump[0x2f]) << 8), + Chip: "pci", + Bus: addr.Bus, + Dev: addr.Dev, + Func: addr.Func, + MissingParent: parent, + Comment: comment, + } + unmatchedPCIDevices[addr.PCIAddr] = cur +} + +func PutPCIDev(addr PCIDevData, comment string) { + PutPCIDevParent(addr, comment, "") +} + +type GenericPCI struct { + Comment string + Bus0Subdiv string + MissingParent string +} + +type GenericVGA struct { + GenericPCI +} + + +type DSDTInclude struct { + Comment string + File string +} + +var DSDTIncludes []DSDTInclude +var DSDTPCI0Includes []DSDTInclude + +func (g GenericPCI) Scan(ctx Context, addr PCIDevData) { + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func (g GenericVGA) Scan(ctx Context, addr PCIDevData) { + KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x.%04x", + addr.PCIVenID, + addr.PCIDevID) + KconfigString["VGA_BIOS_FILE"] = fmt.Sprintf("pci%04x,%04x.rom", + addr.PCIVenID, + addr.PCIDevID) + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func main() { + flag.Parse() + + ctx := Context{} + + ctx.InfoSource = MakeLogReader() + + dmi := ctx.InfoSource.GetDMI() + + ctx.Vendor = dmi.Vendor + + if dmi.Vendor == "LENOVO" { + ctx.Model = dmi.Version + } else { + ctx.Model = dmi.Model + } + + if dmi.IsLaptop { + KconfigBool["SYSTEM_TYPE_LAPTOP"] = true + } + ctx.MoboID = sanitize(ctx.Vendor) + "/" + sanitize(ctx.Model) + ctx.KconfigName = "BOARD_" + strings.ToUpper(sanitize(ctx.Vendor)+"_"+sanitize(ctx.Model)) + ctx.BaseDirectory = *FlagOutDir + "/src/mainboard/" + ctx.MoboID + KconfigStringUnquoted["MAINBOARD_DIR"] = ctx.MoboID + KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model + + /* Only x86 currently. */ + KconfigBool["ARCH_X86"] = true + + /* FIXME: hardcoded. */ + KconfigBool["BOARD_ROMSIZE_KB_2048"] = true + + os.MkdirAll(ctx.BaseDirectory, 0700) + + ScanRoot(ctx) + + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 { + mf := Create(ctx, "Makefile.inc") + defer mf.Close() + writeMF(mf, ROMStageFiles, "romstage") + } + + devtree := Create(ctx, "devicetree.cb") + defer devtree.Close() + + MatchDev(&DevTree) + WriteDev(devtree, 0, DevTree) + + bi := Create(ctx, "board_info.txt") + defer bi.Close() + + if dmi.IsLaptop { + bi.WriteString("Category: laptop") + } else { + /* FIXME: other categories. */ + bi.WriteString("Category: desktop") + } + + /* FIXME: flash chip. */ + + kc := Create(ctx, "Kconfig") + defer kc.Close() + + fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName) + + fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS # dummy\n\tdef_bool y\n") + for name, val := range KconfigBool { + if val { + fmt.Fprintf(kc, "\tselect %s\n", name) + } + } + + for name, val := range KconfigBool { + if !val { + fmt.Fprintf(kc, ` +config %s + string + default n +`, name) + } + } + + for name, val := range KconfigStringUnquoted { + fmt.Fprintf(kc, ` +config %s + string + default %s +`, name, val) + } + + for name, val := range KconfigString { + fmt.Fprintf(kc, ` +config %s + string + default "%s" +`, name, val) + } + + for name, val := range KconfigHex { + fmt.Fprintf(kc, ` +config %s + hex + default 0x%x +`, name, val) + } + + for name, val := range KconfigInt { + fmt.Fprintf(kc, ` +config %s + int + default %d +`, name, val) + } + + fmt.Fprintf(kc, "endif\n") + + dsdt := Create(ctx, "dsdt.asl") + defer dsdt.Close() + + dsdt.WriteString( + `DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" +`) + + for _, x := range DSDTIncludes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t#include <%s>\n", x.File) + } + + dsdt.WriteString(` + Scope (\_SB) { + Device (PCI0) + { +`) + /* FIXME: use scoping at another level. */ + for _, x := range DSDTPCI0Includes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) + } + dsdt.WriteString( + ` } + } +} +`) + +} diff --git a/util/autoport/root.go b/util/autoport/root.go new file mode 100644 index 0000000..9a32427 --- /dev/null +++ b/util/autoport/root.go @@ -0,0 +1,28 @@ +package main + +import "fmt" + +var supportedPCIDevices map[uint32]PCIDevice = map[uint32]PCIDevice{} +var PCIMap map[PCIAddr]PCIDevData = map[PCIAddr]PCIDevData{} + +func ScanRoot(ctx Context) { + for _, pciDev := range ctx.InfoSource.GetPCIList() { + PCIMap[pciDev.PCIAddr] = pciDev + } + for _, pciDev := range ctx.InfoSource.GetPCIList() { + vendevid := (uint32(pciDev.PCIDevID) << 16) | uint32(pciDev.PCIVenID) + + dev, ok := supportedPCIDevices[vendevid] + if !ok { + fmt.Printf("Unsupported PCI device %04x:%04x\n", + pciDev.PCIVenID, pciDev.PCIDevID) + continue + } + dev.Scan(ctx, pciDev) + } +} + +func RegisterPCI(VenID uint16, DevID uint16, dev PCIDevice) { + vendevid := (uint32(DevID) << 16) | uint32(VenID) + supportedPCIDevices[vendevid] = dev +} diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go new file mode 100644 index 0000000..ba4ec04 --- /dev/null +++ b/util/autoport/sandybridge.go @@ -0,0 +1,112 @@ +package main + +type sandybridgemc struct { + variant string +} + +func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { + DevTree = DevTreeNode{ + Chip: "northbridge/intel/sandybridge", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "gpu_dp_d_hotplug": "0x06", + "gpu_panel_port_select": "0", + "gpu_panel_power_cycle_delay": "5", + "gpu_panel_power_up_delay": "300", + "gpu_panel_power_down_delay": "300", + "gpu_panel_power_backlight_on_delay": "2000", + "gpu_panel_power_backlight_off_delay": "2000", + "gfx.use_spread_spectrum_clock": "1", + "gfx.lvds_dual_channel": "0", + "gfx.link_frequency_270_mhz": "1", + "gfx.lvds_num_lanes": "4", + "gpu_cpu_backlight": "0x1155", + "gpu_pch_backlight": "0x06100610", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_rPGA989", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + + { + Chip: "cpu/intel/model_206ax", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "pstate_coord_type": "0xfe", + "c1_acpower": "1", + "c2_acpower": "3", + "c3_acpower": "5", + "c1_battery": "1", + "c2_battery": "3", + "c3_battery": "5", + }, + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0xacac, + Disabled: true, + }, + }, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + MissingParent: "pcibus0", + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr:PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME: Move part to northbridge? */ + /* FIXME: some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool[i.variant+"BRIDGE_LVDS"] = true + + KconfigBool["VGA"] = true + KconfigBool["EARLY_CBMEM_INIT"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true + KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE_NATIVE"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigBool["HAVE_IFD_BIN"] = false + KconfigBool["HAVE_ME_BIN"] = false + + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 8 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_206ax/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/sandybridge/acpi/sandybridge.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0154, sandybridgemc{variant:"IVY"}) + RegisterPCI(0x8086, 0x0166, GenericVGA{GenericPCI{Comment:"VGA controller"}}) +}

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coreboot-gerrit October 2014