coreboot-gerrit October 2014

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Patch set updated for coreboot: 48e89ef {arch, cpu, drivers, ec}: Don't hide pointers behind typedefs
by Nico Huber 27 Oct '14

27 Oct '14

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7146 -gerrit commit 48e89ef4b953d0f91df4a465956780c2cc93a8ec Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Oct 27 23:29:29 2014 +1100 {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/arch/x86/boot/acpi.c | 6 +++--- src/arch/x86/boot/mpspec.c | 6 ++++-- src/arch/x86/boot/smbios.c | 6 +++--- src/cpu/allwinner/a10/cpu.c | 8 ++++---- src/cpu/intel/ep80579/ep80579_init.c | 2 +- src/cpu/intel/fsp_model_206ax/acpi.c | 2 +- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 6 +++--- src/cpu/intel/fsp_model_406dx/acpi.c | 2 +- src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 6 +++--- src/cpu/intel/haswell/acpi.c | 2 +- src/cpu/intel/haswell/haswell_init.c | 4 ++-- src/cpu/intel/haswell/smmrelocate.c | 6 +++--- src/cpu/intel/hyperthreading/intel_sibling.c | 4 ++-- src/cpu/intel/model_1067x/model_1067x_init.c | 6 +++--- src/cpu/intel/model_106cx/model_106cx_init.c | 2 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_2065x/model_2065x_init.c | 8 ++++---- src/cpu/intel/model_206ax/acpi.c | 2 +- src/cpu/intel/model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/model_65x/model_65x_init.c | 2 +- src/cpu/intel/model_67x/model_67x_init.c | 2 +- src/cpu/intel/model_68x/model_68x_init.c | 2 +- src/cpu/intel/model_69x/model_69x_init.c | 2 +- src/cpu/intel/model_6bx/model_6bx_init.c | 2 +- src/cpu/intel/model_6dx/model_6dx_init.c | 2 +- src/cpu/intel/model_6ex/model_6ex_init.c | 2 +- src/cpu/intel/model_6fx/model_6fx_init.c | 2 +- src/cpu/intel/model_6xx/model_6xx_init.c | 2 +- src/cpu/intel/model_f0x/model_f0x_init.c | 2 +- src/cpu/intel/model_f1x/model_f1x_init.c | 2 +- src/cpu/intel/model_f2x/model_f2x_init.c | 2 +- src/cpu/intel/model_f3x/model_f3x_init.c | 2 +- src/cpu/intel/model_f4x/model_f4x_init.c | 2 +- src/cpu/intel/speedstep/acpi.c | 2 +- src/cpu/via/c3/c3_init.c | 2 +- src/cpu/via/c7/c7_init.c | 2 +- src/cpu/via/nano/nano_init.c | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 8 ++++---- src/cpu/x86/mp_init.c | 4 ++-- src/drivers/ati/ragexl/xlinit.c | 2 +- src/drivers/dec/21143/21143.c | 2 +- src/drivers/emulation/qemu/bochs.c | 2 +- src/drivers/emulation/qemu/cirrus.c | 2 +- src/drivers/generic/ioapic/ioapic.c | 8 ++++---- src/drivers/i2c/adm1026/adm1026.c | 6 +++--- src/drivers/i2c/adm1027/adm1027.c | 6 +++--- src/drivers/i2c/adt7463/adt7463.c | 4 ++-- src/drivers/i2c/at24rf08c/at24rf08c.c | 6 +++--- src/drivers/i2c/at24rf08c/lenovo_serials.c | 14 +++++++------- src/drivers/i2c/i2cmux/i2cmux.c | 4 ++-- src/drivers/i2c/i2cmux2/i2cmux2.c | 4 ++-- src/drivers/i2c/lm63/lm63.c | 4 ++-- src/drivers/i2c/rtd2132/rtd2132.c | 24 ++++++++++++------------ src/drivers/i2c/w83793/w83793.c | 18 +++++++++--------- src/drivers/i2c/w83795/w83795.c | 6 +++--- src/drivers/ics/954309/ics954309.c | 4 ++-- src/ec/compal/ene932/ec.c | 8 ++++---- src/ec/google/chromeec/ec_lpc.c | 8 ++++---- src/ec/kontron/it8516e/ec.c | 4 ++-- src/ec/lenovo/h8/h8.c | 4 ++-- src/ec/lenovo/pmh7/pmh7.c | 2 +- src/ec/quanta/ene_kb3940q/ec.c | 8 ++++---- src/ec/quanta/it8518/ec.c | 8 ++++---- src/ec/smsc/mec1308/ec.c | 2 +- src/superio/fintek/f71869ad/f71869ad_hwm.c | 2 +- src/superio/fintek/f71869ad/f71869ad_multifunc.c | 2 +- src/superio/fintek/f71869ad/fintek_internal.h | 4 ++-- src/superio/ite/it8728f/it8728f_hwm.c | 2 +- src/superio/ite/it8728f/it8728f_internal.h | 2 +- src/superio/smsc/fdc37n972/fdc37n972.c | 2 +- src/superio/smsc/sio10n268/sio10n268.c | 2 +- src/superio/via/vt1211/vt1211.c | 4 ++-- 72 files changed, 159 insertions(+), 157 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index c3c946d..b506cb4 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -141,7 +141,7 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) unsigned long acpi_create_madt_lapics(unsigned long current) { - device_t cpu; + struct device *cpu; int index = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { @@ -278,7 +278,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) acpigen_set_current((char *) current); { #if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) - device_t dev; + struct device *dev; for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_fill_ssdt_generator) { dev->ops->acpi_fill_ssdt_generator(); @@ -708,7 +708,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt; acpi_mcfg_t *mcfg; acpi_madt_t *madt; - device_t dev; + struct device *dev; current = start; diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index d079d08..8049be4 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -166,7 +166,7 @@ void smp_write_processors(struct mp_config_table *mc) unsigned cpu_features; unsigned cpu_feature_flags; struct cpuid_result result; - device_t cpu; + struct device *cpu; boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; @@ -493,7 +493,9 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) struct drivers_generic_ioapic_config *ioapic_config; struct mp_config_table *mc; int isa_bus, pin, parentpin; - device_t dev, parent, oldparent; + struct device *dev; + struct device *parent; + struct device *oldparent; void *tmp, *v; int isaioapic = -1, have_fixed_entries; diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 724def3..64889f7 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -303,7 +303,7 @@ static int smbios_write_type11(unsigned long *current, int *handle) { struct smbios_type11 *t = (struct smbios_type11 *)*current; int len; - device_t dev; + struct device *dev; memset(t, 0, sizeof *t); t->type = SMBIOS_OEM_STRINGS; @@ -379,9 +379,9 @@ static int smbios_write_type127(unsigned long *current, int handle) return len; } -static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *current) +static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current) { - device_t dev; + struct device *dev; int len = 0; for(dev = tree; dev; dev = dev->next) { diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c index e0d4cdf..fac5730 100644 --- a/src/cpu/allwinner/a10/cpu.c +++ b/src/cpu/allwinner/a10/cpu.c @@ -11,7 +11,7 @@ #include <cbmem.h> -static void cpu_enable_resources(device_t dev) +static void cpu_enable_resources(struct device *dev) { ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10, CONFIG_DRAM_SIZE_MB << 10); @@ -20,12 +20,12 @@ static void cpu_enable_resources(device_t dev) */ } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { /* TODO: Check if anything else needs to be explicitly initialized */ } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -37,7 +37,7 @@ static struct device_operations cpu_ops = { .scan_bus = NULL, }; -static void a1x_cpu_enable_dev(device_t dev) +static void a1x_cpu_enable_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c index 433636d..2e66700 100644 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ b/src/cpu/intel/ep80579/ep80579_init.c @@ -28,7 +28,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> -static void ep80579_init(device_t dev) +static void ep80579_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/fsp_model_206ax/acpi.c b/src/cpu/intel/fsp_model_206ax/acpi.c index bf4a3ac..28aeb43 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi.c +++ b/src/cpu/intel/fsp_model_206ax/acpi.c @@ -89,7 +89,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_fsp_model_206ax_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index ebb3675..f5ca3f7 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -290,7 +290,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -313,7 +313,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -344,7 +344,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_206ax_init(device_t cpu) +static void model_206ax_init(struct device *cpu) { char processor_name[49]; struct cpuid_result cpuid_regs; diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index a3108ac..24f63cd 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -55,7 +55,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_model_406dx_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 3a36281..d892277 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -112,7 +112,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -135,7 +135,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -166,7 +166,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_406dx_init(device_t cpu) +static void model_406dx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 768511c..544436f 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -91,7 +91,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_haswell_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 68c7643..03935a0 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -597,7 +597,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { struct cpu_intel_haswell_config *conf; - device_t lapic; + struct device *lapic; msr_t msr; /* Find pointer to CPU configuration */ @@ -735,7 +735,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) } /* All CPUs including BSP will run the following function. */ -static void haswell_init(device_t cpu) +static void haswell_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 56d435c..d780beb 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -227,7 +227,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -237,7 +237,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -static void fill_in_relocation_params(device_t dev, +static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { u32 tseg_size; @@ -387,7 +387,7 @@ static int install_permanent_handler(int num_cpus, static int cpu_smm_setup(void) { - device_t dev; + struct device *dev; int num_cpus; msr_t msr; diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 16d8959..32c5e01 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -38,7 +38,7 @@ int intel_ht_sibling(void) return !!(lapicid() & (threads-1)); } -void intel_sibling_init(device_t cpu) +void intel_sibling_init(struct device *cpu) { unsigned i, siblings; struct cpuid_result result; @@ -74,7 +74,7 @@ void intel_sibling_init(device_t cpu) /* I am the primary cpu start up my siblings */ for(i = 1; i < siblings; i++) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 8e44c78..8b20107 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -86,7 +86,7 @@ static void configure_c_states(const int quad) msr_t msr; /* Find pointer to CPU configuration. */ - const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); const struct cpu_intel_model_1067x_config *const conf = (lapic && lapic->chip_info) ? lapic->chip_info : NULL; @@ -144,7 +144,7 @@ static void configure_p_states(const char stepping, const char cores) msr_t msr; /* Find pointer to CPU configuration. */ - const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); struct cpu_intel_model_1067x_config *const conf = (lapic && lapic->chip_info) ? lapic->chip_info : NULL; @@ -285,7 +285,7 @@ static void configure_pic_thermal_sensors(const int tm2, const int quad) wrmsr(PIC_SENS_CFG, msr); } -static void model_1067x_init(device_t cpu) +static void model_1067x_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 73ee5cd..b201474 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -110,7 +110,7 @@ static void configure_misc(void) wrmsr(IA32_MISC_ENABLE, msr); } -static void model_106cx_init(device_t cpu) +static void model_106cx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index d0be502..870020f 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -89,7 +89,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_model_2065x_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 9a2afa4..f79aba5 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -182,7 +182,7 @@ int cpu_config_tdp_levels(void) static void configure_thermal_target(void) { struct cpu_intel_model_2065x_config *conf; - device_t lapic; + struct device *lapic; msr_t msr; /* Find pointer to CPU configuration */ @@ -286,7 +286,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -309,7 +309,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -337,7 +337,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_2065x_init(device_t cpu) +static void model_2065x_init(struct device *cpu) { char processor_name[49]; struct cpuid_result cpuid_regs; diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index f2cd6a9..21f9c3e 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -89,7 +89,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_model_206ax_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index dbde512..1c5d1af 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -364,7 +364,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { struct cpu_intel_model_206ax_config *conf; - device_t lapic; + struct device *lapic; msr_t msr; /* Find pointer to CPU configuration */ @@ -477,7 +477,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -500,7 +500,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -531,7 +531,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_206ax_init(device_t cpu) +static void model_206ax_init(struct device *cpu) { char processor_name[49]; struct cpuid_result cpuid_regs; diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index a9f1811..6b21939 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -28,7 +28,7 @@ #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> -static void model_65x_init(device_t dev) +static void model_65x_init(struct device *dev) { /* Update the microcode */ intel_update_microcode_from_cbfs(); diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 467d3db..c72dfae 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -29,7 +29,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/l2_cache.h> -static void model_67x_init(device_t cpu) +static void model_67x_init(struct device *cpu) { /* Update the microcode */ intel_update_microcode_from_cbfs(); diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index d1b4463..fc016d2 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static void model_68x_init(device_t cpu) +static void model_68x_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index 4339274..214673a 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_69x_init(device_t dev) +static void model_69x_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index d166bfa..013a6a5 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static void model_6bx_init(device_t cpu) +static void model_6bx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 18c2fa4..190edf0 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_6dx_init(device_t dev) +static void model_6dx_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 8f9fbf8..54e59eb 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -141,7 +141,7 @@ static void configure_pic_thermal_sensors(void) wrmsr(PIC_SENS_CFG, msr); } -static void model_6ex_init(device_t cpu) +static void model_6ex_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 93635d4..1b52781 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -161,7 +161,7 @@ static void configure_pic_thermal_sensors(void) wrmsr(PIC_SENS_CFG, msr); } -static void model_6fx_init(device_t cpu) +static void model_6fx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 9b92dcc..d8acd5e 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_6xx_init(device_t dev) +static void model_6xx_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index ca40515..fe9ea3b 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_f0x_init(device_t dev) +static void model_f0x_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index dbb5cd0..3678bfe 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_f1x_init(device_t dev) +static void model_f1x_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 53eb75e..cf0b827 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -9,7 +9,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static void model_f2x_init(device_t cpu) +static void model_f2x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index f8d9ca6..2d3bc73 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -9,7 +9,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static void model_f3x_init(device_t cpu) +static void model_f3x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 260b60a..cbc042e 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -9,7 +9,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static void model_f4x_init(device_t cpu) +static void model_f4x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 483e813..98d1ee7 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -44,7 +44,7 @@ int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries static int determine_total_number_of_cores(void) { - device_t cpu; + struct device *cpu; int count = 0; for(cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c index 7d94384..fc6001b 100644 --- a/src/cpu/via/c3/c3_init.c +++ b/src/cpu/via/c3/c3_init.c @@ -26,7 +26,7 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> -static void c3_init(device_t dev) +static void c3_init(struct device *dev) { x86_enable_cache(); x86_setup_mtrrs(); diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 510e66d..7f22e59 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -147,7 +147,7 @@ static void set_c7_speed(int model) { printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff)); } -static void c7_init(device_t dev) +static void c7_init(struct device *dev) { u8 brand; struct cpuinfo_x86 c; diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 417119f..acb5f95 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -139,7 +139,7 @@ static void nano_power(void) wrmsr(MSR_IA32_MISC_ENABLE, msr); } -static void nano_init(device_t dev) +static void nano_init(struct device *dev) { struct cpuinfo_x86 c; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 09b6b9e..018924f 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -253,7 +253,7 @@ static void *stacks[CONFIG_MAX_CPUS]; volatile unsigned long secondary_stack; volatile unsigned int secondary_cpu_index; -int start_cpu(device_t cpu) +int start_cpu(struct device *cpu) { struct cpu_info *info; unsigned long stack_end; @@ -430,9 +430,9 @@ void asmlinkage secondary_cpu_init(unsigned int index) stop_this_cpu(); } -static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) +static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) { - device_t cpu; + struct device *cpu; /* Loop through the cpus once getting them started */ for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { @@ -465,7 +465,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) static void wait_other_cpus_stop(struct bus *cpu_bus) { - device_t cpu; + struct device *cpu; int old_active_count, active_count; long loopcount = 0; int i; diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index e83c23d..a97a4c5 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -86,7 +86,7 @@ struct mp_flight_plan { static struct mp_flight_plan mp_info; struct cpu_map { - device_t dev; + struct device *dev; int apic_id; }; @@ -328,7 +328,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) info = cpu_info(); for (i = 1; i < max_cpus; i++) { struct device_path cpu_path; - device_t new; + struct device *new; int apic_id; /* Build the cpu device path */ diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index cdcb862..41cea72 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -489,7 +489,7 @@ static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) info->mem_refresh_rate = i; } #endif /*CONFIG_CONSOLE_BTEXT */ -static void ati_ragexl_init(device_t dev) +static void ati_ragexl_init(struct device *dev) { u32 chip_id; int j; diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index 7ce3d6b..b26b22c 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <console/console.h> -static void dec_21143_enable(device_t dev) +static void dec_21143_enable(struct device *dev) { printk(BIOS_DEBUG, "Initializing DECchip 21143\n"); diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index f2e4dfb..cb0075a 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -58,7 +58,7 @@ static int bochs_read(int index) } #endif -static void bochs_init(device_t dev) +static void bochs_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) struct edid edid; diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index c96e032..1c659eb 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -212,7 +212,7 @@ write_hidden_dac (uint8_t data) } #endif -static void cirrus_init(device_t dev) +static void cirrus_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) uint8_t cr_ext, cr_overlay; diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 42b2f07..9c4bc7d 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -12,7 +12,7 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> -static void ioapic_init(device_t dev) +static void ioapic_init(struct device *dev) { struct drivers_generic_ioapic_config *config = dev->chip_info; u32 bsp_lapicid = lapicid(); @@ -86,15 +86,15 @@ static void ioapic_init(device_t dev) } } -static void ioapic_enable_resources(device_t dev) +static void ioapic_enable_resources(struct device *dev) { } -static void ioapic_nop(device_t dummy) +static void ioapic_nop(struct device *dummy) { } -static void ioapic_read_resources(device_t dev) +static void ioapic_read_resources(struct device *dev) { struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; struct resource *res; diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index ab85eb5..e8baea1 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -19,7 +19,7 @@ #define ADM1026_REG_CONFIG2 0x01 #define ADM1026_REG_CONFIG3 0x07 -static void adm1026_enable_monitoring(device_t dev) +static void adm1026_enable_monitoring(struct device *dev) { int result; result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); @@ -33,7 +33,7 @@ static void adm1026_enable_monitoring(device_t dev) } } -static void adm1026_init(device_t dev) +static void adm1026_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -44,7 +44,7 @@ static void adm1026_init(device_t dev) } } -static void adm1026_noop(device_t dummy) +static void adm1026_noop(struct device *dummy) { } diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index e83f2c4..9841c81 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -18,7 +18,7 @@ #define ADM1027_REG_CONFIG2 0x73 #define ADM1027_REG_CONFIG3 0x78 -static void adm1027_enable_monitoring(device_t dev) +static void adm1027_enable_monitoring(struct device *dev) { int result; @@ -39,7 +39,7 @@ static void adm1027_enable_monitoring(device_t dev) printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n"); } -static void adm1027_init(device_t dev) +static void adm1027_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -50,7 +50,7 @@ static void adm1027_init(device_t dev) } } -static void adm1027_noop(device_t dummy) +static void adm1027_noop(struct device *dummy) { } diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 9ca9f37..dd6d837 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -32,7 +32,7 @@ * See Analog Devices ADT7463 datasheet, Rev C (2004): * http://www.analog.com/en/prod/0,,766_825_ADT7463,00.html */ -static void adt7463_init(device_t adt7463) +static void adt7463_init(struct device *adt7463) { int result; @@ -85,7 +85,7 @@ static void adt7463_init(device_t adt7463) printk(BIOS_DEBUG, "ADT7463 properly initialized\n"); } -static void adt7463_noop(device_t dummy) +static void adt7463_noop(struct device *dummy) { } diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index a9cf2c5..a03564f 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -25,7 +25,7 @@ #include <smbios.h> #include <console/console.h> -static void at24rf08c_init(device_t dev) +static void at24rf08c_init(struct device *dev) { int i, j; @@ -52,7 +52,7 @@ static void at24rf08c_init(device_t dev) printk (BIOS_DEBUG, "init EEPROM done\n"); } -static void at24rf08c_noop(device_t dummy) +static void at24rf08c_noop(struct device *dummy) { } @@ -63,7 +63,7 @@ static struct device_operations at24rf08c_operations = { .init = at24rf08c_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &at24rf08c_operations; } diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 53e76da..65928be 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -28,16 +28,16 @@ #define ERROR_STRING "*INVALID*" -static device_t at24rf08c_find_bank(u8 bank) +static struct device *at24rf08c_find_bank(u8 bank) { - device_t dev; + struct device *dev; dev = dev_find_slot_on_smbus(1, 0x54 | bank); if (!dev) printk(BIOS_WARNING, "EEPROM not found\n"); return dev; } -static int at24rf08c_read_byte(device_t dev, u8 addr) +static int at24rf08c_read_byte(struct device *dev, u8 addr) { int t = -1; int j; @@ -54,7 +54,7 @@ static int at24rf08c_read_byte(device_t dev, u8 addr) return t; } -static void at24rf08c_read_string_dev(device_t dev, u8 start, +static void at24rf08c_read_string_dev(struct device *dev, u8 start, u8 len, char *result) { int i; @@ -72,7 +72,7 @@ static void at24rf08c_read_string_dev(device_t dev, u8 start, static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) { - device_t dev; + struct device *dev; dev = at24rf08c_find_bank(bank); if (dev == 0) { @@ -124,7 +124,7 @@ void smbios_mainboard_set_uuid(u8 *uuid) static char result[16]; unsigned i; static int already_read; - device_t dev; + struct device *dev; const int remap[16] = { /* UUID byteswap. */ 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 @@ -173,7 +173,7 @@ const char *smbios_mainboard_version(void) { static char result[100]; static int already_read; - device_t dev; + struct device *dev; int len; if (already_read) diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index b318508..d8ad40b 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void i2cmux_set_link(device_t dev, unsigned int link) +static void i2cmux_set_link(struct device *dev, unsigned int link) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -16,7 +16,7 @@ static void i2cmux_set_link(device_t dev, unsigned int link) } } -static void i2cmux_noop(device_t dummy) +static void i2cmux_noop(struct device *dummy) { } diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index a7d40e2..6b05508 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void i2cmux2_set_link(device_t dev, unsigned int link) +static void i2cmux2_set_link(struct device *dev, unsigned int link) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -15,7 +15,7 @@ static void i2cmux2_set_link(device_t dev, unsigned int link) } } -static void i2cmux2_noop(device_t dummy) +static void i2cmux2_noop(struct device *dummy) { } diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index 47a5489..b64751e 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void lm63_init(device_t dev) +static void lm63_init(struct device *dev) { int result; if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { @@ -21,7 +21,7 @@ static void lm63_init(device_t dev) } } -static void lm63_noop(device_t dummy) +static void lm63_noop(struct device *dummy) { } diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 44333ac..4dbfb41 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -75,7 +75,7 @@ #define RTD2132_DEBUG_REG 0 -static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) +static void rtd2132_write_reg(struct device *dev, u8 reg, u8 value) { if (RTD2132_DEBUG_REG) printk(BIOS_DEBUG, "RTD2132 0x%02x <- 0x%02x\n", reg, value); @@ -83,18 +83,18 @@ static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) smbus_write_byte(dev, RTD2132_DATA, value); } -static void rtd2132_firmware_stop(device_t dev) +static void rtd2132_firmware_stop(struct device *dev) { smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_STOP); mdelay(60); } -static void rtd2132_firmware_start(device_t dev) +static void rtd2132_firmware_start(struct device *dev) { smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_START); } -static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) +static void rtd2132_pps(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { /* T2, T5, and T7 register values are in units of 4ms. */ rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T1, cfg->t1); @@ -106,7 +106,7 @@ static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T7, cfg->t7 / 4); } -static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) +static void rtd2132_sscg_enable(struct device *dev, u8 sscg_percent) { /* SSCG_Config_0 */ rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, @@ -116,7 +116,7 @@ static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_1, sscg_percent); } -static void rtd2132_sscg_disable(device_t dev) +static void rtd2132_sscg_disable(struct device *dev) { /* SSCG_Config_0 */ rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, @@ -127,7 +127,7 @@ static void rtd2132_sscg_disable(device_t dev) RTD2132_SSCG_CONFIG_DISABLED); } -static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) +static void rtd2132_sscg(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { switch (cfg->sscg_percent) { case RTD2132_SSCG_PERCENT_0_0: @@ -152,7 +152,7 @@ static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) } } -static void rtd2132_lvds_swap(device_t dev, +static void rtd2132_lvds_swap(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { u8 swap_value = RTD2132_LVDS_SWAP_NORMAL; @@ -186,7 +186,7 @@ static void rtd2132_lvds_swap(device_t dev, rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); } -static void rtd2132_defaults(device_t dev) +static void rtd2132_defaults(struct device *dev) { static const struct def_setting { u8 reg; @@ -207,7 +207,7 @@ static void rtd2132_defaults(device_t dev) def_settings[i].value); } -static void rtd2132_setup(device_t dev) +static void rtd2132_setup(struct device *dev) { struct drivers_i2c_rtd2132_config *config = dev->chip_info; @@ -233,7 +233,7 @@ static void rtd2132_setup(device_t dev) rtd2132_firmware_start(dev); } -static void rtd2132_init(device_t dev) +static void rtd2132_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && ops_smbus_bus(get_pbus_smbus(dev))) { @@ -241,7 +241,7 @@ static void rtd2132_init(device_t dev) } } -static void rtd2132_noop(device_t dummy) +static void rtd2132_noop(struct device *dummy) { } diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c index 8dcfb28..732fdb4 100644 --- a/src/drivers/i2c/w83793/w83793.c +++ b/src/drivers/i2c/w83793/w83793.c @@ -25,18 +25,18 @@ #include <device/smbus.h> #include "chip.h" -static int w83793_fan_limit(device_t dev, int fan, uint16_t limit) +static int w83793_fan_limit(struct device *dev, int fan, uint16_t limit) { return smbus_write_byte(dev, 0x90 + fan * 2, limit >> 8) || smbus_write_byte(dev, 0x91 + fan * 2, limit & 0xff); } -static int w83793_bank(device_t dev, int bank) +static int w83793_bank(struct device *dev, int bank) { return smbus_write_byte(dev, 0, bank); } -static int w83793_td_level(device_t dev, int fan, const char *level) +static int w83793_td_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -50,7 +50,7 @@ static int w83793_td_level(device_t dev, int fan, const char *level) return 0; } -static int w83793_tr_level(device_t dev, int fan, const char *level) +static int w83793_tr_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -65,7 +65,7 @@ static int w83793_tr_level(device_t dev, int fan, const char *level) } -static int w83793_td_fan_level(device_t dev, int fan, const char *level) +static int w83793_td_fan_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -79,7 +79,7 @@ static int w83793_td_fan_level(device_t dev, int fan, const char *level) return 0; } -static int w83793_tr_fan_level(device_t dev, int fan, const char *level) +static int w83793_tr_fan_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -94,7 +94,7 @@ static int w83793_tr_fan_level(device_t dev, int fan, const char *level) } -static void w83793_init(device_t dev) +static void w83793_init(struct device *dev) { struct drivers_i2c_w83793_config *config = dev->chip_info; uint16_t id; @@ -220,7 +220,7 @@ static void w83793_init(device_t dev) } -static void w83793_noop(device_t dummy) +static void w83793_noop(struct device *dummy) { } @@ -231,7 +231,7 @@ static struct device_operations w83793_operations = { .init = w83793_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &w83793_operations; } diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 87aa7f5..5559666 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -221,7 +221,7 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) } } -static void w83795_hwm_init(device_t dev) +static void w83795_hwm_init(struct device *dev) { struct device *cpu; struct cpu_info *info; @@ -239,7 +239,7 @@ static void w83795_hwm_init(device_t dev) printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n"); } -static void w83795_noop(device_t dummy) +static void w83795_noop(struct device *dummy) { } @@ -250,7 +250,7 @@ static struct device_operations w83795_operations = { .init = w83795_hwm_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &w83795_operations; } diff --git a/src/drivers/ics/954309/ics954309.c b/src/drivers/ics/954309/ics954309.c index ef62879..0aa15c0 100644 --- a/src/drivers/ics/954309/ics954309.c +++ b/src/drivers/ics/954309/ics954309.c @@ -29,7 +29,7 @@ #include "chip.h" #include <string.h> -static void ics954309_init(device_t dev) +static void ics954309_init(struct device *dev) { struct drivers_ics_954309_config *config; u8 initdata[12]; @@ -55,7 +55,7 @@ static void ics954309_init(device_t dev) smbus_block_write(dev, 0, 12, initdata); } -static void ics954309_noop(device_t dummy) +static void ics954309_noop(struct device *dummy) { } diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 2e83b4c..4bf6727 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -132,7 +132,7 @@ static u8 ec_io_read(u16 addr) */ #ifndef __SMM__ -static void ene932_init(device_t dev) +static void ene932_init(struct device *dev) { if (!dev->enabled) return; @@ -143,13 +143,13 @@ static void ene932_init(device_t dev) } -static void ene932_read_resources(device_t dev) +static void ene932_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void ene932_enable_resources(device_t dev) +static void ene932_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -164,7 +164,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 4cd30f3..5344716 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -137,7 +137,7 @@ int google_chromeec_command(struct chromeec_command *cec_command) #ifndef __PRE_RAM__ #ifndef __SMM__ -static void lpc_ec_init(device_t dev) +static void lpc_ec_init(struct device *dev) { if (!dev->enabled) return; @@ -146,12 +146,12 @@ static void lpc_ec_init(device_t dev) google_chromeec_init(); } -static void lpc_ec_read_resources(device_t dev) +static void lpc_ec_read_resources(struct device *dev) { /* Nothing, but this function avoids an error on serial console. */ } -static void lpc_ec_enable_resources(device_t dev) +static void lpc_ec_enable_resources(struct device *dev) { /* Nothing, but this function avoids an error on serial console. */ } @@ -166,7 +166,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index 925b7ea..7827a1d 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -211,7 +211,7 @@ static void it8516e_set_fan_from_options(const config_t *const config, } } -static void it8516e_pm2_init(const device_t dev) +static void it8516e_pm2_init(struct device *dev) { const config_t *const config = dev->chip_info; @@ -251,7 +251,7 @@ static struct pnp_info it8516e_dev_infos[] = { { NULL, IT8516E_LDN_PM3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, }; -static void it8516e_enable(const device_t dev) +static void it8516e_enable(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(it8516e_dev_infos), it8516e_dev_infos); diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 79ef3cd..13b0483 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -167,7 +167,7 @@ u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) return i; } -static void h8_smbios_strings(device_t dev, struct smbios_type11 *t) +static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t) { char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; @@ -180,7 +180,7 @@ struct device_operations h8_dev_ops = { .get_smbios_strings = h8_smbios_strings }; -static void h8_enable(device_t dev) +static void h8_enable(struct device *dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; u8 val, tmp; diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index cb0e27b..f67fbda 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -102,7 +102,7 @@ void pmh7_register_write(int reg, int val) #ifndef __PRE_RAM__ #ifndef __SMM__ -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index f0a2308..dcd9c4a 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -141,7 +141,7 @@ static void ene_kb3940q_log_events(void) #endif } -static void ene_kb3940q_init(device_t dev) +static void ene_kb3940q_init(struct device *dev) { if (!dev->enabled) return; @@ -153,13 +153,13 @@ static void ene_kb3940q_init(device_t dev) } -static void ene_kb3940q_read_resources(device_t dev) +static void ene_kb3940q_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void ene_kb3940q_enable_resources(device_t dev) +static void ene_kb3940q_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -174,7 +174,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index b9cb68f..cd976e6 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -156,7 +156,7 @@ void ec_it8518_enable_wake_events(void) } #ifndef __SMM__ -static void it8518_init(device_t dev) +static void it8518_init(struct device *dev) { if (!dev->enabled) return; @@ -166,13 +166,13 @@ static void it8518_init(device_t dev) } -static void it8518_read_resources(device_t dev) +static void it8518_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void it8518_enable_resources(device_t dev) +static void it8518_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -187,7 +187,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index 4d3b30a..0a7c4ae 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -121,7 +121,7 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg) } #if !defined(__PRE_RAM__) && !defined(__SMM__) -static void mec1308_enable(device_t dev) +static void mec1308_enable(struct device *dev) { struct ec_smsc_mec1308_config *conf = dev->chip_info; diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c index 0475081..25bc1ff 100644 --- a/src/superio/fintek/f71869ad/f71869ad_hwm.c +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -62,7 +62,7 @@ static void pnp_write_index(u16 port, u8 reg, u8 value) } /* note: multifunc registers need to be tweaked before here */ -void f71869ad_hwm_init(device_t dev) +void f71869ad_hwm_init(struct device *dev) { const struct superio_fintek_f71869ad_config *conf = dev->chip_info; struct resource *res = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/fintek/f71869ad/f71869ad_multifunc.c b/src/superio/fintek/f71869ad/f71869ad_multifunc.c index e0182ed..3374ef1 100644 --- a/src/superio/fintek/f71869ad/f71869ad_multifunc.c +++ b/src/superio/fintek/f71869ad/f71869ad_multifunc.c @@ -30,7 +30,7 @@ #define MULTI_FUNC_SEL_REG4 0x2B #define MULTI_FUNC_SEL_REG5 0x2C -void f71869ad_multifunc_init(device_t dev) +void f71869ad_multifunc_init(struct device *dev) { const struct superio_fintek_f71869ad_config *conf = dev->chip_info; diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h index 6856c01..ac96a1e 100644 --- a/src/superio/fintek/f71869ad/fintek_internal.h +++ b/src/superio/fintek/f71869ad/fintek_internal.h @@ -24,7 +24,7 @@ #include <arch/io.h> #include <device/pnp.h> -void f71869ad_multifunc_init(device_t dev); -void f71869ad_hwm_init(device_t dev); +void f71869ad_multifunc_init(struct device *dev); +void f71869ad_hwm_init(struct device *dev); #endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */ diff --git a/src/superio/ite/it8728f/it8728f_hwm.c b/src/superio/ite/it8728f/it8728f_hwm.c index fd486a8..23fa9e8 100644 --- a/src/superio/ite/it8728f/it8728f_hwm.c +++ b/src/superio/ite/it8728f/it8728f_hwm.c @@ -41,7 +41,7 @@ static void pnp_write_index(u16 port, u8 reg, u8 value) outb(value, port + 1); } -void it8728f_hwm_ec_init(device_t dev) +void it8728f_hwm_ec_init(struct device *dev) { struct superio_ite_it8728f_config *conf = dev->chip_info; struct resource *res = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/ite/it8728f/it8728f_internal.h b/src/superio/ite/it8728f/it8728f_internal.h index 89aecb4..6eb16af 100644 --- a/src/superio/ite/it8728f/it8728f_internal.h +++ b/src/superio/ite/it8728f/it8728f_internal.h @@ -23,6 +23,6 @@ #include <device/device.h> -void it8728f_hwm_ec_init(device_t dev); +void it8728f_hwm_ec_init(struct device *dev); #endif /* SUPERIO_ITE_IT8728F_INTERNAL_H */ diff --git a/src/superio/smsc/fdc37n972/fdc37n972.c b/src/superio/smsc/fdc37n972/fdc37n972.c index 97dea9f..ff04526 100644 --- a/src/superio/smsc/fdc37n972/fdc37n972.c +++ b/src/superio/smsc/fdc37n972/fdc37n972.c @@ -24,7 +24,7 @@ #include "fdc37n972.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) return; diff --git a/src/superio/smsc/sio10n268/sio10n268.c b/src/superio/smsc/sio10n268/sio10n268.c index fab7c41..4635080 100644 --- a/src/superio/smsc/sio10n268/sio10n268.c +++ b/src/superio/smsc/sio10n268/sio10n268.c @@ -23,7 +23,7 @@ #include <pc80/keyboard.h> #include "sio10n268.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) return; diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index f7a5cd9..8e9904b 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -44,7 +44,7 @@ static u8 hwm_io_regs[] = { 0x5c,0x00, 0x5f,0x33, 0x40,0x01, }; -static void vt1211_set_iobase(device_t dev, u8 index, u16 iobase) +static void vt1211_set_iobase(struct device *dev, u8 index, u16 iobase) { switch (dev->path.pnp.device) { case VT1211_FDC: @@ -107,7 +107,7 @@ static void vt1211_init(struct device *dev) } } -static void vt1211_pnp_enable_resources(device_t dev) +static void vt1211_pnp_enable_resources(struct device *dev) { printk(BIOS_DEBUG, "%s - enabling\n", dev_path(dev)); pnp_enable_resources(dev);

1 0

Patch merged into coreboot/master: 06413ff drivers/spi: add Macronix MX25U6435F and MX25L6495F support
by gerrit＠coreboot.org 27 Oct '14

27 Oct '14

the following patch was just integrated into master: commit 06413ff513600ecb7ef7bf486d8871cce01b7d70 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Oct 26 01:20:20 2014 +0200 drivers/spi: add Macronix MX25U6435F and MX25L6495F support Contributed by MXIC: http://www.coreboot.org/pipermail/coreboot/2014-October/078835.html Change-Id: I07f872a5cbb2b0ea63794edb8fbca40d7856ce10 Author: Alex Lu <alexlu6(a)mxic.com.tw> Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-on: http://review.coreboot.org/7194 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7194 for details. -gerrit

1 0

Patch set updated for coreboot: ce2a8ae TEST
by Edward O'Callaghan 27 Oct '14

27 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7198 -gerrit commit ce2a8ae91662c5c9e9ba39fe237eae9e410decbf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 23:33:22 2014 +1100 TEST Change-Id: I6f29b198569eb4834328d36ca8f69d6550ded4cf Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/agesa/00730F01/model_16_init.c | 2 +- src/cpu/amd/agesa/amd_late_init.c | 2 +- src/cpu/amd/agesa/family10/model_10_init.c | 2 +- src/cpu/amd/agesa/family12/model_12_init.c | 2 +- src/cpu/amd/agesa/family14/model_14_init.c | 2 +- src/cpu/amd/agesa/family15/model_15_init.c | 2 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +- src/cpu/amd/dualcore/amd_sibling.c | 6 +++--- src/cpu/amd/geode_gx1/geode_gx1_init.c | 2 +- src/cpu/amd/geode_gx2/geode_gx2_init.c | 2 +- src/cpu/amd/geode_lx/geode_lx_init.c | 2 +- src/cpu/amd/model_10xxx/fidvid.c | 28 ++++++++++++++-------------- src/cpu/amd/model_10xxx/init_cpus.c | 2 +- src/cpu/amd/model_10xxx/model_10xxx_init.c | 2 +- src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/cpu/amd/model_fxx/model_fxx_init.c | 10 ++++++---- src/cpu/amd/quadcore/amd_sibling.c | 6 +++--- src/cpu/amd/sc520/sc520.c | 14 +++++++------- 19 files changed, 47 insertions(+), 45 deletions(-) diff --git a/src/cpu/amd/agesa/00730F01/model_16_init.c b/src/cpu/amd/agesa/00730F01/model_16_init.c index 8053fd1..78cfc06 100644 --- a/src/cpu/amd/agesa/00730F01/model_16_init.c +++ b/src/cpu/amd/agesa/00730F01/model_16_init.c @@ -37,7 +37,7 @@ #include <cpu/amd/agesa/s3_resume.h> #endif -static void model_16_init(device_t dev) +static void model_16_init(struct device *dev) { printk(BIOS_DEBUG, "Model 16 Init.\n"); diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index cab03a3..97f5425 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -42,7 +42,7 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdinitlate); #if (NORTHBRIDGE_00700F00) || (NORTHBRIDGE_00730F01) - device_t dev; + struct device *dev; u32 value; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 6fbfd1a..d00a105 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -34,7 +34,7 @@ #define MCI_STATUS 0x401 -static void model_10_init(device_t dev) +static void model_10_init(struct device *dev) { printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n"); diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 635bd81..a2061e7 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -35,7 +35,7 @@ #define MCI_STATUS 0x401 -static void model_12_init(device_t dev) +static void model_12_init(struct device *dev) { printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n"); diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 60a88c7..ca250b9 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -36,7 +36,7 @@ #define MCI_STATUS 0x401 -static void model_14_init(device_t dev) +static void model_14_init(struct device *dev) { u32 i; msr_t msr; diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index a755e1c..c7fbd75 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> -static void model_15_init(device_t dev) +static void model_15_init(struct device *dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 64c78af..b888cf2 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -35,7 +35,7 @@ #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -static void model_15_init(device_t dev) +static void model_15_init(struct device *dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index ef31f96..07b92f5 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -34,7 +34,7 @@ #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -static void model_16_init(device_t dev) +static void model_16_init(struct device *dev) { printk(BIOS_DEBUG, "Model 16 Init.\n"); diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index d9942de..e2ad3a1 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -19,7 +19,7 @@ static int disable_siblings = !CONFIG_LOGICAL_CPUS; static int get_max_siblings(int nodes) { - device_t dev; + struct device *dev; int nodeid; int siblings=0; @@ -38,7 +38,7 @@ static int get_max_siblings(int nodes) static void enable_apic_ext_id(int nodes) { - device_t dev; + struct device *dev; int nodeid; //enable APIC_EXIT_ID all the nodes @@ -54,7 +54,7 @@ static void enable_apic_ext_id(int nodes) unsigned get_apicid_base(unsigned ioapic_num) { - device_t dev; + struct device *dev; int nodes; unsigned apicid_base; int siblings; diff --git a/src/cpu/amd/geode_gx1/geode_gx1_init.c b/src/cpu/amd/geode_gx1/geode_gx1_init.c index 8fbf507..4f08a1c 100644 --- a/src/cpu/amd/geode_gx1/geode_gx1_init.c +++ b/src/cpu/amd/geode_gx1/geode_gx1_init.c @@ -72,7 +72,7 @@ unsigned long addr; } #endif -static void geode_gx1_init(device_t dev) +static void geode_gx1_init(struct device *dev) { #if 0 gx1_cpu_setup(); diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c index b8f56db..43ac808 100644 --- a/src/cpu/amd/geode_gx2/geode_gx2_init.c +++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c @@ -15,7 +15,7 @@ static void vsm_end_post_smi(void) ); } -static void geode_gx2_init(device_t dev) +static void geode_gx2_init(struct device *dev) { printk(BIOS_DEBUG, "geode_gx2_init\n"); diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c index cd931a4..1024c00 100644 --- a/src/cpu/amd/geode_lx/geode_lx_init.c +++ b/src/cpu/amd/geode_lx/geode_lx_init.c @@ -37,7 +37,7 @@ static void vsm_end_post_smi(void) ".byte 0x0f, 0x38\n" "pop %ax\n"); } -static void geode_lx_init(device_t dev) +static void geode_lx_init(struct device *dev) { printk(BIOS_DEBUG, "geode_lx_init\n"); diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 4297c90..c0be3d0 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -134,7 +134,7 @@ static void enable_fid_change(u8 fid) { u32 dword; u32 nodes; - device_t dev; + struct device *dev; int i; nodes = get_nodes(); @@ -151,7 +151,7 @@ static void enable_fid_change(u8 fid) } } -static void applyBoostFIDOffset( device_t dev ) { +static void applyBoostFIDOffset( struct device *dev ) { // BKDG 2.4.2.8 // revision E only, but E is apparently not supported yet, therefore untested if ((cpuid_edx(0x80000007) & CPB_MASK) @@ -168,7 +168,7 @@ static void applyBoostFIDOffset( device_t dev ) { } } -static void enableNbPState1( device_t dev ) { +static void enableNbPState1( struct device *dev ) { u32 cpuRev = mctGetLogicalCPUID(0xFF); if (cpuRev & AMD_FAM10_C3) { u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); @@ -188,7 +188,7 @@ static void enableNbPState1( device_t dev ) { } } -static u8 setPStateMaxVal( device_t dev ) { +static u8 setPStateMaxVal( struct device *dev ) { u8 i,maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PS_REG_BASE + i); @@ -208,7 +208,7 @@ static u8 setPStateMaxVal( device_t dev ) { return maxpstate; } -static void dualPlaneOnly( device_t dev ) { +static void dualPlaneOnly( struct device *dev ) { // BKDG 2.4.2.7 u32 cpuRev = mctGetLogicalCPUID(0xFF); @@ -252,7 +252,7 @@ static int vidTo100uV(u8 vid) return voltage; } -static void setVSRamp(device_t dev) { +static void setVSRamp(struct device *dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] * If this field accepts 8 values between 10 and 500 us why * does page 324 say "BIOS should set this field to 001b." @@ -267,7 +267,7 @@ static void setVSRamp(device_t dev) { pci_write_config32(dev, 0xd8, dword); } -static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) +static void recalculateVsSlamTimeSettingOnCorePre(struct device *dev) { u8 pviModeFlag; u8 highVoltageVid, lowVoltageVid, bValue; @@ -443,7 +443,7 @@ static u32 power_up_down(int node, u8 procPkg) { } static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { - device_t dev = NODE_PCI(node, 3); + struct device *dev = NODE_PCI(node, 3); /* Program fields in Clock Power/Control register0 (F3xD4) */ @@ -467,7 +467,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { } -static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { +static void config_power_ctrl_misc_reg(struct device *dev,u32 cpuRev, u8 procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xA0); @@ -500,7 +500,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { pci_write_config32(dev, 0xA0, dword); } -static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { +static void config_nb_syn_ptr_adj(struct device *dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ @@ -522,7 +522,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { pci_write_config32(dev, 0xdc, dword); } -static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { +static void config_acpi_pwr_state_ctrl_regs(struct device *dev, u32 cpuRev, u8 procPkg) { /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ u32 dword; u32 c1= 1; @@ -582,7 +582,7 @@ static void prep_fid_change(void) { u32 dword; u32 nodes; - device_t dev; + struct device *dev; int i; /* This needs to be run before any Pstate changes are requested */ @@ -785,7 +785,7 @@ static u32 needs_NB_COF_VID_update(void) static u32 init_fidvid_core(u32 nodeid, u32 coreid) { - device_t dev; + struct device *dev; u32 vid_max; u32 fid_max = 0; u8 nb_cof_vid_update = needs_NB_COF_VID_update(); @@ -946,7 +946,7 @@ static void finalPstateChange(void) static void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; - device_t dev; + struct device *dev; u32 reg1fc; u32 dtemp; u32 nbvid; diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 10c0c8a..f6d2bd7 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -362,7 +362,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + struct device *device; device = NODE_PCI(nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_ColdR_Detect; diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c6cf64a..214b416 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -38,7 +38,7 @@ #define MCI_STATUS 0x401 -static void model_10xxx_init(device_t dev) +static void model_10xxx_init(struct device *dev) { u8 i; msr_t msr; diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 12d3a95..0dacc8d 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -310,7 +310,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + struct device *device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_INIT_Detect; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 260e83e..24e86dc 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -51,7 +51,7 @@ int is_e0_later_in_bsp(int nodeid) return !is_cpu_pre_e0(); } // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; + struct device *dev; dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 2)); if (!dev) return 0; @@ -73,7 +73,7 @@ int is_e0_later_in_bsp(int nodeid) int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + struct device *dev; dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 3)); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff00) == 0x40f00; @@ -228,7 +228,9 @@ static void init_ecc_memory(unsigned node_id) unsigned long basek; struct mtrr_state mtrr_state; - device_t f1_dev, f2_dev, f3_dev; + struct device *f1_dev; + struct device *f2_dev; + struct device *f3_dev; int enable_scrubbing; uint32_t dcl; @@ -456,7 +458,7 @@ static inline void k8_errata(void) } -static void model_fxx_init(device_t dev) +static void model_fxx_init(struct device *dev) { unsigned long i; msr_t msr; diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index d653a85..419af78 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -30,7 +30,7 @@ #include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/amdfam10_sysconf.h> -extern device_t get_node_pci(u32 nodeid, u32 fn); +extern struct device *get_node_pci(u32 nodeid, u32 fn); #if 0 static int first_time = 1; @@ -40,7 +40,7 @@ static int first_time = 1; static u32 get_max_siblings(u32 nodes) { - device_t dev; + struct device *dev; u32 nodeid; u32 siblings=0; @@ -60,7 +60,7 @@ static u32 get_max_siblings(u32 nodes) static void enable_apic_ext_id(u32 nodes) { - device_t dev; + struct device *dev; u32 nodeid; //enable APIC_EXIT_ID all the nodes diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index 808c33c..ac3ba4e 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -18,7 +18,7 @@ * set up basic things ... * PAR should NOT go here, as it might change with the mainboard. */ -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { unsigned long *l = (unsigned long *) 0xfffef088; int i; @@ -49,7 +49,7 @@ static void sc520_enable_resources(struct device *dev) { } -static void sc520_read_resources(device_t dev) +static void sc520_read_resources(struct device *dev) { struct resource* res; @@ -83,9 +83,9 @@ static const struct pci_driver cpu_driver __pci_driver = { .device = 0x3000 }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "%s\n", __func__); pci_tolm = find_pci_tolm(dev->link_list); @@ -130,7 +130,7 @@ static void pci_domain_set_resources(device_t dev) } #if 0 -void sc520_enable_resources(device_t dev) { +void sc520_enable_resources(struct device *dev) { printk(BIOS_SPEW, "%s\n", __func__); printk(BIOS_SPEW, "THIS IS FOR THE SC520 =============================\n"); @@ -165,12 +165,12 @@ static struct device_operations pci_domain_ops = { }; #if 0 -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, "cpu_bus_init\n"); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device *dev) { }

1 0

Patch set updated for coreboot: ab442ed NOTFORMERGE: fix reset.c
by Edward O'Callaghan 27 Oct '14

27 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7196 -gerrit commit ab442ed127799ee55e4bc5a84b5c0d9d31566b1a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:36:02 2014 +1100 NOTFORMERGE: fix reset.c Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/amdfam10/reset_test.c | 10 +++++----- src/northbridge/amd/amdk8/reset_test.c | 4 ++-- src/southbridge/amd/amd8111/reset.c | 14 ++++++-------- src/southbridge/broadcom/bcm5785/reset.c | 6 ++---- src/southbridge/nvidia/ck804/reset.c | 6 ++---- src/southbridge/nvidia/mcp55/reset.c | 6 ++---- src/southbridge/sis/sis966/reset.c | 6 ++---- 7 files changed, 21 insertions(+), 31 deletions(-) diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 24f5397..de7949e 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -32,7 +32,7 @@ u32 cpu_init_detected(u8 nodeid) { u32 htic; - device_t dev; + pci_devfn_t dev; dev = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(dev, HT_INIT_CONTROL); @@ -67,7 +67,7 @@ u32 other_reset_detected(void) // other warm reset not started by BIOS static void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; @@ -77,7 +77,7 @@ static void distinguish_cpu_resets(u8 nodeid) static u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -89,7 +89,7 @@ void __attribute__ ((weak)) set_bios_reset(void) u32 nodes; u32 htic; - device_t dev; + pci_devfn_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; @@ -134,7 +134,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b int i; int j; u32 cfg_map_dest; - device_t dev; + pci_devfn_t dev; cfg_map_dest = (1<<7)|(1<<6)|link; diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 6ef3ec0..8015290 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -10,7 +10,7 @@ static inline int cpu_init_detected(unsigned nodeid) { u32 htic; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); @@ -37,7 +37,7 @@ static inline int cold_reset_detected(void) static inline void distinguish_cpu_resets(unsigned nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index c96e898..8824550 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -10,9 +10,7 @@ #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -typedef unsigned device_t; - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) { unsigned addr; addr = (dev>>4) | where; @@ -20,7 +18,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value) outb(value, 0xCFC + (addr & 3)); } -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -28,7 +26,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; @@ -37,9 +35,9 @@ static unsigned pci_read_config32(device_t dev, unsigned where) } #define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); for(; dev <= last; dev += PCI_DEV(0,0,1)) { @@ -57,7 +55,7 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) void hard_reset(void) { - device_t dev; + pci_devfn_t dev; unsigned bus; unsigned node = 0; unsigned link = get_sblk(); diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 51ba6ec..b34cc86 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index a241966..53c0c40 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev >> 4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev >> 4) | where; diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/sis/sis966/reset.c +++ b/src/southbridge/sis/sis966/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where;

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Patch set updated for coreboot: 795e683 {arch, cpu, drivers, ec}: Don't hide pointers behind typedefs
by Edward O'Callaghan 27 Oct '14

27 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7146 -gerrit commit 795e68393eb66082f65fe7470f7c427f7c989981 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Oct 27 23:29:29 2014 +1100 {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/boot/acpi.c | 6 +++--- src/arch/x86/boot/mpspec.c | 6 ++++-- src/arch/x86/boot/smbios.c | 6 +++--- src/cpu/allwinner/a10/cpu.c | 8 ++++---- src/cpu/intel/ep80579/ep80579_init.c | 2 +- src/cpu/intel/fsp_model_206ax/acpi.c | 2 +- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 6 +++--- src/cpu/intel/fsp_model_406dx/acpi.c | 2 +- src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 6 +++--- src/cpu/intel/haswell/acpi.c | 2 +- src/cpu/intel/haswell/haswell_init.c | 4 ++-- src/cpu/intel/haswell/smmrelocate.c | 6 +++--- src/cpu/intel/hyperthreading/intel_sibling.c | 4 ++-- src/cpu/intel/model_1067x/model_1067x_init.c | 6 +++--- src/cpu/intel/model_106cx/model_106cx_init.c | 2 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_2065x/model_2065x_init.c | 8 ++++---- src/cpu/intel/model_206ax/acpi.c | 2 +- src/cpu/intel/model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/model_65x/model_65x_init.c | 2 +- src/cpu/intel/model_67x/model_67x_init.c | 2 +- src/cpu/intel/model_68x/model_68x_init.c | 2 +- src/cpu/intel/model_69x/model_69x_init.c | 2 +- src/cpu/intel/model_6bx/model_6bx_init.c | 2 +- src/cpu/intel/model_6dx/model_6dx_init.c | 2 +- src/cpu/intel/model_6ex/model_6ex_init.c | 2 +- src/cpu/intel/model_6fx/model_6fx_init.c | 2 +- src/cpu/intel/model_6xx/model_6xx_init.c | 2 +- src/cpu/intel/model_f0x/model_f0x_init.c | 2 +- src/cpu/intel/model_f1x/model_f1x_init.c | 2 +- src/cpu/intel/model_f2x/model_f2x_init.c | 2 +- src/cpu/intel/model_f3x/model_f3x_init.c | 2 +- src/cpu/intel/model_f4x/model_f4x_init.c | 2 +- src/cpu/intel/speedstep/acpi.c | 2 +- src/cpu/via/c3/c3_init.c | 2 +- src/cpu/via/c7/c7_init.c | 2 +- src/cpu/via/nano/nano_init.c | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 8 ++++---- src/cpu/x86/mp_init.c | 4 ++-- src/drivers/ati/ragexl/xlinit.c | 2 +- src/drivers/dec/21143/21143.c | 2 +- src/drivers/emulation/qemu/bochs.c | 2 +- src/drivers/emulation/qemu/cirrus.c | 2 +- src/drivers/generic/ioapic/ioapic.c | 8 ++++---- src/drivers/i2c/adm1026/adm1026.c | 6 +++--- src/drivers/i2c/adm1027/adm1027.c | 6 +++--- src/drivers/i2c/adt7463/adt7463.c | 4 ++-- src/drivers/i2c/at24rf08c/at24rf08c.c | 6 +++--- src/drivers/i2c/at24rf08c/lenovo_serials.c | 14 +++++++------- src/drivers/i2c/i2cmux/i2cmux.c | 4 ++-- src/drivers/i2c/i2cmux2/i2cmux2.c | 4 ++-- src/drivers/i2c/lm63/lm63.c | 4 ++-- src/drivers/i2c/rtd2132/rtd2132.c | 24 ++++++++++++------------ src/drivers/i2c/w83793/w83793.c | 18 +++++++++--------- src/drivers/i2c/w83795/w83795.c | 6 +++--- src/drivers/ics/954309/ics954309.c | 4 ++-- src/ec/compal/ene932/ec.c | 8 ++++---- src/ec/google/chromeec/ec_lpc.c | 8 ++++---- src/ec/kontron/it8516e/ec.c | 4 ++-- src/ec/lenovo/h8/h8.c | 4 ++-- src/ec/lenovo/pmh7/pmh7.c | 2 +- src/ec/quanta/ene_kb3940q/ec.c | 8 ++++---- src/ec/quanta/it8518/ec.c | 8 ++++---- src/ec/smsc/mec1308/ec.c | 2 +- src/superio/fintek/f71869ad/f71869ad_hwm.c | 2 +- src/superio/fintek/f71869ad/f71869ad_multifunc.c | 2 +- src/superio/fintek/f71869ad/fintek_internal.h | 4 ++-- src/superio/ite/it8728f/it8728f_hwm.c | 2 +- src/superio/ite/it8728f/it8728f_internal.h | 2 +- src/superio/smsc/fdc37n972/fdc37n972.c | 2 +- src/superio/smsc/sio10n268/sio10n268.c | 2 +- src/superio/via/vt1211/vt1211.c | 4 ++-- 72 files changed, 159 insertions(+), 157 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index c3c946d..b506cb4 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -141,7 +141,7 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) unsigned long acpi_create_madt_lapics(unsigned long current) { - device_t cpu; + struct device *cpu; int index = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { @@ -278,7 +278,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) acpigen_set_current((char *) current); { #if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) - device_t dev; + struct device *dev; for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_fill_ssdt_generator) { dev->ops->acpi_fill_ssdt_generator(); @@ -708,7 +708,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt; acpi_mcfg_t *mcfg; acpi_madt_t *madt; - device_t dev; + struct device *dev; current = start; diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index d079d08..8049be4 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -166,7 +166,7 @@ void smp_write_processors(struct mp_config_table *mc) unsigned cpu_features; unsigned cpu_feature_flags; struct cpuid_result result; - device_t cpu; + struct device *cpu; boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; @@ -493,7 +493,9 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) struct drivers_generic_ioapic_config *ioapic_config; struct mp_config_table *mc; int isa_bus, pin, parentpin; - device_t dev, parent, oldparent; + struct device *dev; + struct device *parent; + struct device *oldparent; void *tmp, *v; int isaioapic = -1, have_fixed_entries; diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 724def3..64889f7 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -303,7 +303,7 @@ static int smbios_write_type11(unsigned long *current, int *handle) { struct smbios_type11 *t = (struct smbios_type11 *)*current; int len; - device_t dev; + struct device *dev; memset(t, 0, sizeof *t); t->type = SMBIOS_OEM_STRINGS; @@ -379,9 +379,9 @@ static int smbios_write_type127(unsigned long *current, int handle) return len; } -static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *current) +static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current) { - device_t dev; + struct device *dev; int len = 0; for(dev = tree; dev; dev = dev->next) { diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c index e0d4cdf..fac5730 100644 --- a/src/cpu/allwinner/a10/cpu.c +++ b/src/cpu/allwinner/a10/cpu.c @@ -11,7 +11,7 @@ #include <cbmem.h> -static void cpu_enable_resources(device_t dev) +static void cpu_enable_resources(struct device *dev) { ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10, CONFIG_DRAM_SIZE_MB << 10); @@ -20,12 +20,12 @@ static void cpu_enable_resources(device_t dev) */ } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { /* TODO: Check if anything else needs to be explicitly initialized */ } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -37,7 +37,7 @@ static struct device_operations cpu_ops = { .scan_bus = NULL, }; -static void a1x_cpu_enable_dev(device_t dev) +static void a1x_cpu_enable_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c index 433636d..2e66700 100644 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ b/src/cpu/intel/ep80579/ep80579_init.c @@ -28,7 +28,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> -static void ep80579_init(device_t dev) +static void ep80579_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/fsp_model_206ax/acpi.c b/src/cpu/intel/fsp_model_206ax/acpi.c index bf4a3ac..28aeb43 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi.c +++ b/src/cpu/intel/fsp_model_206ax/acpi.c @@ -89,7 +89,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_fsp_model_206ax_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index ebb3675..f5ca3f7 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -290,7 +290,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -313,7 +313,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -344,7 +344,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_206ax_init(device_t cpu) +static void model_206ax_init(struct device *cpu) { char processor_name[49]; struct cpuid_result cpuid_regs; diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index a3108ac..24f63cd 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -55,7 +55,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_model_406dx_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 3a36281..d892277 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -112,7 +112,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -135,7 +135,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -166,7 +166,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_406dx_init(device_t cpu) +static void model_406dx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 768511c..544436f 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -91,7 +91,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_haswell_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 68c7643..03935a0 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -597,7 +597,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { struct cpu_intel_haswell_config *conf; - device_t lapic; + struct device *lapic; msr_t msr; /* Find pointer to CPU configuration */ @@ -735,7 +735,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) } /* All CPUs including BSP will run the following function. */ -static void haswell_init(device_t cpu) +static void haswell_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 56d435c..d780beb 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -227,7 +227,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -237,7 +237,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -static void fill_in_relocation_params(device_t dev, +static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { u32 tseg_size; @@ -387,7 +387,7 @@ static int install_permanent_handler(int num_cpus, static int cpu_smm_setup(void) { - device_t dev; + struct device *dev; int num_cpus; msr_t msr; diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 16d8959..32c5e01 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -38,7 +38,7 @@ int intel_ht_sibling(void) return !!(lapicid() & (threads-1)); } -void intel_sibling_init(device_t cpu) +void intel_sibling_init(struct device *cpu) { unsigned i, siblings; struct cpuid_result result; @@ -74,7 +74,7 @@ void intel_sibling_init(device_t cpu) /* I am the primary cpu start up my siblings */ for(i = 1; i < siblings; i++) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 8e44c78..8b20107 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -86,7 +86,7 @@ static void configure_c_states(const int quad) msr_t msr; /* Find pointer to CPU configuration. */ - const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); const struct cpu_intel_model_1067x_config *const conf = (lapic && lapic->chip_info) ? lapic->chip_info : NULL; @@ -144,7 +144,7 @@ static void configure_p_states(const char stepping, const char cores) msr_t msr; /* Find pointer to CPU configuration. */ - const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); struct cpu_intel_model_1067x_config *const conf = (lapic && lapic->chip_info) ? lapic->chip_info : NULL; @@ -285,7 +285,7 @@ static void configure_pic_thermal_sensors(const int tm2, const int quad) wrmsr(PIC_SENS_CFG, msr); } -static void model_1067x_init(device_t cpu) +static void model_1067x_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 73ee5cd..b201474 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -110,7 +110,7 @@ static void configure_misc(void) wrmsr(IA32_MISC_ENABLE, msr); } -static void model_106cx_init(device_t cpu) +static void model_106cx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index d0be502..870020f 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -89,7 +89,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_model_2065x_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 9a2afa4..f79aba5 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -182,7 +182,7 @@ int cpu_config_tdp_levels(void) static void configure_thermal_target(void) { struct cpu_intel_model_2065x_config *conf; - device_t lapic; + struct device *lapic; msr_t msr; /* Find pointer to CPU configuration */ @@ -286,7 +286,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -309,7 +309,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -337,7 +337,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_2065x_init(device_t cpu) +static void model_2065x_init(struct device *cpu) { char processor_name[49]; struct cpuid_result cpuid_regs; diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index f2cd6a9..21f9c3e 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -89,7 +89,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_model_206ax_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index dbde512..1c5d1af 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -364,7 +364,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { struct cpu_intel_model_206ax_config *conf; - device_t lapic; + struct device *lapic; msr_t msr; /* Find pointer to CPU configuration */ @@ -477,7 +477,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -500,7 +500,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -531,7 +531,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_206ax_init(device_t cpu) +static void model_206ax_init(struct device *cpu) { char processor_name[49]; struct cpuid_result cpuid_regs; diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index a9f1811..6b21939 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -28,7 +28,7 @@ #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> -static void model_65x_init(device_t dev) +static void model_65x_init(struct device *dev) { /* Update the microcode */ intel_update_microcode_from_cbfs(); diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 467d3db..c72dfae 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -29,7 +29,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/l2_cache.h> -static void model_67x_init(device_t cpu) +static void model_67x_init(struct device *cpu) { /* Update the microcode */ intel_update_microcode_from_cbfs(); diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index d1b4463..fc016d2 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static void model_68x_init(device_t cpu) +static void model_68x_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index 4339274..214673a 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_69x_init(device_t dev) +static void model_69x_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index d166bfa..013a6a5 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static void model_6bx_init(device_t cpu) +static void model_6bx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 18c2fa4..190edf0 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_6dx_init(device_t dev) +static void model_6dx_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 8f9fbf8..54e59eb 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -141,7 +141,7 @@ static void configure_pic_thermal_sensors(void) wrmsr(PIC_SENS_CFG, msr); } -static void model_6ex_init(device_t cpu) +static void model_6ex_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 93635d4..1b52781 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -161,7 +161,7 @@ static void configure_pic_thermal_sensors(void) wrmsr(PIC_SENS_CFG, msr); } -static void model_6fx_init(device_t cpu) +static void model_6fx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 9b92dcc..d8acd5e 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_6xx_init(device_t dev) +static void model_6xx_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index ca40515..fe9ea3b 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_f0x_init(device_t dev) +static void model_f0x_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index dbb5cd0..3678bfe 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_f1x_init(device_t dev) +static void model_f1x_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 53eb75e..cf0b827 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -9,7 +9,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static void model_f2x_init(device_t cpu) +static void model_f2x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index f8d9ca6..2d3bc73 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -9,7 +9,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static void model_f3x_init(device_t cpu) +static void model_f3x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 260b60a..cbc042e 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -9,7 +9,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static void model_f4x_init(device_t cpu) +static void model_f4x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 483e813..98d1ee7 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -44,7 +44,7 @@ int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries static int determine_total_number_of_cores(void) { - device_t cpu; + struct device *cpu; int count = 0; for(cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c index 7d94384..fc6001b 100644 --- a/src/cpu/via/c3/c3_init.c +++ b/src/cpu/via/c3/c3_init.c @@ -26,7 +26,7 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> -static void c3_init(device_t dev) +static void c3_init(struct device *dev) { x86_enable_cache(); x86_setup_mtrrs(); diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 510e66d..7f22e59 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -147,7 +147,7 @@ static void set_c7_speed(int model) { printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff)); } -static void c7_init(device_t dev) +static void c7_init(struct device *dev) { u8 brand; struct cpuinfo_x86 c; diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 417119f..acb5f95 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -139,7 +139,7 @@ static void nano_power(void) wrmsr(MSR_IA32_MISC_ENABLE, msr); } -static void nano_init(device_t dev) +static void nano_init(struct device *dev) { struct cpuinfo_x86 c; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 09b6b9e..018924f 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -253,7 +253,7 @@ static void *stacks[CONFIG_MAX_CPUS]; volatile unsigned long secondary_stack; volatile unsigned int secondary_cpu_index; -int start_cpu(device_t cpu) +int start_cpu(struct device *cpu) { struct cpu_info *info; unsigned long stack_end; @@ -430,9 +430,9 @@ void asmlinkage secondary_cpu_init(unsigned int index) stop_this_cpu(); } -static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) +static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) { - device_t cpu; + struct device *cpu; /* Loop through the cpus once getting them started */ for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { @@ -465,7 +465,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) static void wait_other_cpus_stop(struct bus *cpu_bus) { - device_t cpu; + struct device *cpu; int old_active_count, active_count; long loopcount = 0; int i; diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index e83c23d..a97a4c5 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -86,7 +86,7 @@ struct mp_flight_plan { static struct mp_flight_plan mp_info; struct cpu_map { - device_t dev; + struct device *dev; int apic_id; }; @@ -328,7 +328,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) info = cpu_info(); for (i = 1; i < max_cpus; i++) { struct device_path cpu_path; - device_t new; + struct device *new; int apic_id; /* Build the cpu device path */ diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index cdcb862..41cea72 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -489,7 +489,7 @@ static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) info->mem_refresh_rate = i; } #endif /*CONFIG_CONSOLE_BTEXT */ -static void ati_ragexl_init(device_t dev) +static void ati_ragexl_init(struct device *dev) { u32 chip_id; int j; diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index 7ce3d6b..b26b22c 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <console/console.h> -static void dec_21143_enable(device_t dev) +static void dec_21143_enable(struct device *dev) { printk(BIOS_DEBUG, "Initializing DECchip 21143\n"); diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index f2e4dfb..cb0075a 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -58,7 +58,7 @@ static int bochs_read(int index) } #endif -static void bochs_init(device_t dev) +static void bochs_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) struct edid edid; diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index c96e032..1c659eb 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -212,7 +212,7 @@ write_hidden_dac (uint8_t data) } #endif -static void cirrus_init(device_t dev) +static void cirrus_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) uint8_t cr_ext, cr_overlay; diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 42b2f07..3d62a7c 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -12,7 +12,7 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> -static void ioapic_init(device_t dev) +static void ioapic_init(struct device *dev) { struct drivers_generic_ioapic_config *config = dev->chip_info; u32 bsp_lapicid = lapicid(); @@ -86,15 +86,15 @@ static void ioapic_init(device_t dev) } } -static void ioapic_enable_resources(device_t dev) +static void ioapic_enable_resources(struct device *dev) { } -static void ioapic_nop(device_t dummy) +static void ioapic_nop(struct device * dummy) { } -static void ioapic_read_resources(device_t dev) +static void ioapic_read_resources(struct device *dev) { struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; struct resource *res; diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index ab85eb5..305972f 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -19,7 +19,7 @@ #define ADM1026_REG_CONFIG2 0x01 #define ADM1026_REG_CONFIG3 0x07 -static void adm1026_enable_monitoring(device_t dev) +static void adm1026_enable_monitoring(struct device *dev) { int result; result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); @@ -33,7 +33,7 @@ static void adm1026_enable_monitoring(device_t dev) } } -static void adm1026_init(device_t dev) +static void adm1026_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -44,7 +44,7 @@ static void adm1026_init(device_t dev) } } -static void adm1026_noop(device_t dummy) +static void adm1026_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index e83f2c4..1fc50de 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -18,7 +18,7 @@ #define ADM1027_REG_CONFIG2 0x73 #define ADM1027_REG_CONFIG3 0x78 -static void adm1027_enable_monitoring(device_t dev) +static void adm1027_enable_monitoring(struct device *dev) { int result; @@ -39,7 +39,7 @@ static void adm1027_enable_monitoring(device_t dev) printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n"); } -static void adm1027_init(device_t dev) +static void adm1027_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -50,7 +50,7 @@ static void adm1027_init(device_t dev) } } -static void adm1027_noop(device_t dummy) +static void adm1027_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 9ca9f37..3146dbb 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -32,7 +32,7 @@ * See Analog Devices ADT7463 datasheet, Rev C (2004): * http://www.analog.com/en/prod/0,,766_825_ADT7463,00.html */ -static void adt7463_init(device_t adt7463) +static void adt7463_init(struct device * adt7463) { int result; @@ -85,7 +85,7 @@ static void adt7463_init(device_t adt7463) printk(BIOS_DEBUG, "ADT7463 properly initialized\n"); } -static void adt7463_noop(device_t dummy) +static void adt7463_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index a9cf2c5..870c11a 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -25,7 +25,7 @@ #include <smbios.h> #include <console/console.h> -static void at24rf08c_init(device_t dev) +static void at24rf08c_init(struct device *dev) { int i, j; @@ -52,7 +52,7 @@ static void at24rf08c_init(device_t dev) printk (BIOS_DEBUG, "init EEPROM done\n"); } -static void at24rf08c_noop(device_t dummy) +static void at24rf08c_noop(struct device * dummy) { } @@ -63,7 +63,7 @@ static struct device_operations at24rf08c_operations = { .init = at24rf08c_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &at24rf08c_operations; } diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 53e76da..8cd1e1b 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -28,16 +28,16 @@ #define ERROR_STRING "*INVALID*" -static device_t at24rf08c_find_bank(u8 bank) +static struct device * at24rf08c_find_bank(u8 bank) { - device_t dev; + struct device *dev; dev = dev_find_slot_on_smbus(1, 0x54 | bank); if (!dev) printk(BIOS_WARNING, "EEPROM not found\n"); return dev; } -static int at24rf08c_read_byte(device_t dev, u8 addr) +static int at24rf08c_read_byte(struct device *dev, u8 addr) { int t = -1; int j; @@ -54,7 +54,7 @@ static int at24rf08c_read_byte(device_t dev, u8 addr) return t; } -static void at24rf08c_read_string_dev(device_t dev, u8 start, +static void at24rf08c_read_string_dev(struct device *dev, u8 start, u8 len, char *result) { int i; @@ -72,7 +72,7 @@ static void at24rf08c_read_string_dev(device_t dev, u8 start, static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) { - device_t dev; + struct device *dev; dev = at24rf08c_find_bank(bank); if (dev == 0) { @@ -124,7 +124,7 @@ void smbios_mainboard_set_uuid(u8 *uuid) static char result[16]; unsigned i; static int already_read; - device_t dev; + struct device *dev; const int remap[16] = { /* UUID byteswap. */ 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 @@ -173,7 +173,7 @@ const char *smbios_mainboard_version(void) { static char result[100]; static int already_read; - device_t dev; + struct device *dev; int len; if (already_read) diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index b318508..256569c 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void i2cmux_set_link(device_t dev, unsigned int link) +static void i2cmux_set_link(struct device *dev, unsigned int link) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -16,7 +16,7 @@ static void i2cmux_set_link(device_t dev, unsigned int link) } } -static void i2cmux_noop(device_t dummy) +static void i2cmux_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index a7d40e2..287784c 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void i2cmux2_set_link(device_t dev, unsigned int link) +static void i2cmux2_set_link(struct device *dev, unsigned int link) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -15,7 +15,7 @@ static void i2cmux2_set_link(device_t dev, unsigned int link) } } -static void i2cmux2_noop(device_t dummy) +static void i2cmux2_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index 47a5489..80835f3 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void lm63_init(device_t dev) +static void lm63_init(struct device *dev) { int result; if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { @@ -21,7 +21,7 @@ static void lm63_init(device_t dev) } } -static void lm63_noop(device_t dummy) +static void lm63_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 44333ac..9ccf3b0 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -75,7 +75,7 @@ #define RTD2132_DEBUG_REG 0 -static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) +static void rtd2132_write_reg(struct device *dev, u8 reg, u8 value) { if (RTD2132_DEBUG_REG) printk(BIOS_DEBUG, "RTD2132 0x%02x <- 0x%02x\n", reg, value); @@ -83,18 +83,18 @@ static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) smbus_write_byte(dev, RTD2132_DATA, value); } -static void rtd2132_firmware_stop(device_t dev) +static void rtd2132_firmware_stop(struct device *dev) { smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_STOP); mdelay(60); } -static void rtd2132_firmware_start(device_t dev) +static void rtd2132_firmware_start(struct device *dev) { smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_START); } -static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) +static void rtd2132_pps(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { /* T2, T5, and T7 register values are in units of 4ms. */ rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T1, cfg->t1); @@ -106,7 +106,7 @@ static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T7, cfg->t7 / 4); } -static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) +static void rtd2132_sscg_enable(struct device *dev, u8 sscg_percent) { /* SSCG_Config_0 */ rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, @@ -116,7 +116,7 @@ static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_1, sscg_percent); } -static void rtd2132_sscg_disable(device_t dev) +static void rtd2132_sscg_disable(struct device *dev) { /* SSCG_Config_0 */ rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, @@ -127,7 +127,7 @@ static void rtd2132_sscg_disable(device_t dev) RTD2132_SSCG_CONFIG_DISABLED); } -static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) +static void rtd2132_sscg(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { switch (cfg->sscg_percent) { case RTD2132_SSCG_PERCENT_0_0: @@ -152,7 +152,7 @@ static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) } } -static void rtd2132_lvds_swap(device_t dev, +static void rtd2132_lvds_swap(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { u8 swap_value = RTD2132_LVDS_SWAP_NORMAL; @@ -186,7 +186,7 @@ static void rtd2132_lvds_swap(device_t dev, rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); } -static void rtd2132_defaults(device_t dev) +static void rtd2132_defaults(struct device *dev) { static const struct def_setting { u8 reg; @@ -207,7 +207,7 @@ static void rtd2132_defaults(device_t dev) def_settings[i].value); } -static void rtd2132_setup(device_t dev) +static void rtd2132_setup(struct device *dev) { struct drivers_i2c_rtd2132_config *config = dev->chip_info; @@ -233,7 +233,7 @@ static void rtd2132_setup(device_t dev) rtd2132_firmware_start(dev); } -static void rtd2132_init(device_t dev) +static void rtd2132_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && ops_smbus_bus(get_pbus_smbus(dev))) { @@ -241,7 +241,7 @@ static void rtd2132_init(device_t dev) } } -static void rtd2132_noop(device_t dummy) +static void rtd2132_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c index 8dcfb28..6127085 100644 --- a/src/drivers/i2c/w83793/w83793.c +++ b/src/drivers/i2c/w83793/w83793.c @@ -25,18 +25,18 @@ #include <device/smbus.h> #include "chip.h" -static int w83793_fan_limit(device_t dev, int fan, uint16_t limit) +static int w83793_fan_limit(struct device *dev, int fan, uint16_t limit) { return smbus_write_byte(dev, 0x90 + fan * 2, limit >> 8) || smbus_write_byte(dev, 0x91 + fan * 2, limit & 0xff); } -static int w83793_bank(device_t dev, int bank) +static int w83793_bank(struct device *dev, int bank) { return smbus_write_byte(dev, 0, bank); } -static int w83793_td_level(device_t dev, int fan, const char *level) +static int w83793_td_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -50,7 +50,7 @@ static int w83793_td_level(device_t dev, int fan, const char *level) return 0; } -static int w83793_tr_level(device_t dev, int fan, const char *level) +static int w83793_tr_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -65,7 +65,7 @@ static int w83793_tr_level(device_t dev, int fan, const char *level) } -static int w83793_td_fan_level(device_t dev, int fan, const char *level) +static int w83793_td_fan_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -79,7 +79,7 @@ static int w83793_td_fan_level(device_t dev, int fan, const char *level) return 0; } -static int w83793_tr_fan_level(device_t dev, int fan, const char *level) +static int w83793_tr_fan_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -94,7 +94,7 @@ static int w83793_tr_fan_level(device_t dev, int fan, const char *level) } -static void w83793_init(device_t dev) +static void w83793_init(struct device *dev) { struct drivers_i2c_w83793_config *config = dev->chip_info; uint16_t id; @@ -220,7 +220,7 @@ static void w83793_init(device_t dev) } -static void w83793_noop(device_t dummy) +static void w83793_noop(struct device * dummy) { } @@ -231,7 +231,7 @@ static struct device_operations w83793_operations = { .init = w83793_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &w83793_operations; } diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 87aa7f5..b8a056e 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -221,7 +221,7 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) } } -static void w83795_hwm_init(device_t dev) +static void w83795_hwm_init(struct device *dev) { struct device *cpu; struct cpu_info *info; @@ -239,7 +239,7 @@ static void w83795_hwm_init(device_t dev) printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n"); } -static void w83795_noop(device_t dummy) +static void w83795_noop(struct device * dummy) { } @@ -250,7 +250,7 @@ static struct device_operations w83795_operations = { .init = w83795_hwm_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &w83795_operations; } diff --git a/src/drivers/ics/954309/ics954309.c b/src/drivers/ics/954309/ics954309.c index ef62879..9104d28 100644 --- a/src/drivers/ics/954309/ics954309.c +++ b/src/drivers/ics/954309/ics954309.c @@ -29,7 +29,7 @@ #include "chip.h" #include <string.h> -static void ics954309_init(device_t dev) +static void ics954309_init(struct device *dev) { struct drivers_ics_954309_config *config; u8 initdata[12]; @@ -55,7 +55,7 @@ static void ics954309_init(device_t dev) smbus_block_write(dev, 0, 12, initdata); } -static void ics954309_noop(device_t dummy) +static void ics954309_noop(struct device * dummy) { } diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 2e83b4c..4bf6727 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -132,7 +132,7 @@ static u8 ec_io_read(u16 addr) */ #ifndef __SMM__ -static void ene932_init(device_t dev) +static void ene932_init(struct device *dev) { if (!dev->enabled) return; @@ -143,13 +143,13 @@ static void ene932_init(device_t dev) } -static void ene932_read_resources(device_t dev) +static void ene932_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void ene932_enable_resources(device_t dev) +static void ene932_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -164,7 +164,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 4cd30f3..5344716 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -137,7 +137,7 @@ int google_chromeec_command(struct chromeec_command *cec_command) #ifndef __PRE_RAM__ #ifndef __SMM__ -static void lpc_ec_init(device_t dev) +static void lpc_ec_init(struct device *dev) { if (!dev->enabled) return; @@ -146,12 +146,12 @@ static void lpc_ec_init(device_t dev) google_chromeec_init(); } -static void lpc_ec_read_resources(device_t dev) +static void lpc_ec_read_resources(struct device *dev) { /* Nothing, but this function avoids an error on serial console. */ } -static void lpc_ec_enable_resources(device_t dev) +static void lpc_ec_enable_resources(struct device *dev) { /* Nothing, but this function avoids an error on serial console. */ } @@ -166,7 +166,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index 925b7ea..7827a1d 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -211,7 +211,7 @@ static void it8516e_set_fan_from_options(const config_t *const config, } } -static void it8516e_pm2_init(const device_t dev) +static void it8516e_pm2_init(struct device *dev) { const config_t *const config = dev->chip_info; @@ -251,7 +251,7 @@ static struct pnp_info it8516e_dev_infos[] = { { NULL, IT8516E_LDN_PM3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, }; -static void it8516e_enable(const device_t dev) +static void it8516e_enable(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(it8516e_dev_infos), it8516e_dev_infos); diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 79ef3cd..13b0483 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -167,7 +167,7 @@ u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) return i; } -static void h8_smbios_strings(device_t dev, struct smbios_type11 *t) +static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t) { char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; @@ -180,7 +180,7 @@ struct device_operations h8_dev_ops = { .get_smbios_strings = h8_smbios_strings }; -static void h8_enable(device_t dev) +static void h8_enable(struct device *dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; u8 val, tmp; diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index cb0e27b..f67fbda 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -102,7 +102,7 @@ void pmh7_register_write(int reg, int val) #ifndef __PRE_RAM__ #ifndef __SMM__ -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index f0a2308..dcd9c4a 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -141,7 +141,7 @@ static void ene_kb3940q_log_events(void) #endif } -static void ene_kb3940q_init(device_t dev) +static void ene_kb3940q_init(struct device *dev) { if (!dev->enabled) return; @@ -153,13 +153,13 @@ static void ene_kb3940q_init(device_t dev) } -static void ene_kb3940q_read_resources(device_t dev) +static void ene_kb3940q_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void ene_kb3940q_enable_resources(device_t dev) +static void ene_kb3940q_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -174,7 +174,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index b9cb68f..cd976e6 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -156,7 +156,7 @@ void ec_it8518_enable_wake_events(void) } #ifndef __SMM__ -static void it8518_init(device_t dev) +static void it8518_init(struct device *dev) { if (!dev->enabled) return; @@ -166,13 +166,13 @@ static void it8518_init(device_t dev) } -static void it8518_read_resources(device_t dev) +static void it8518_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void it8518_enable_resources(device_t dev) +static void it8518_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -187,7 +187,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index 4d3b30a..0a7c4ae 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -121,7 +121,7 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg) } #if !defined(__PRE_RAM__) && !defined(__SMM__) -static void mec1308_enable(device_t dev) +static void mec1308_enable(struct device *dev) { struct ec_smsc_mec1308_config *conf = dev->chip_info; diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c index 0475081..25bc1ff 100644 --- a/src/superio/fintek/f71869ad/f71869ad_hwm.c +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -62,7 +62,7 @@ static void pnp_write_index(u16 port, u8 reg, u8 value) } /* note: multifunc registers need to be tweaked before here */ -void f71869ad_hwm_init(device_t dev) +void f71869ad_hwm_init(struct device *dev) { const struct superio_fintek_f71869ad_config *conf = dev->chip_info; struct resource *res = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/fintek/f71869ad/f71869ad_multifunc.c b/src/superio/fintek/f71869ad/f71869ad_multifunc.c index e0182ed..3374ef1 100644 --- a/src/superio/fintek/f71869ad/f71869ad_multifunc.c +++ b/src/superio/fintek/f71869ad/f71869ad_multifunc.c @@ -30,7 +30,7 @@ #define MULTI_FUNC_SEL_REG4 0x2B #define MULTI_FUNC_SEL_REG5 0x2C -void f71869ad_multifunc_init(device_t dev) +void f71869ad_multifunc_init(struct device *dev) { const struct superio_fintek_f71869ad_config *conf = dev->chip_info; diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h index 6856c01..ac96a1e 100644 --- a/src/superio/fintek/f71869ad/fintek_internal.h +++ b/src/superio/fintek/f71869ad/fintek_internal.h @@ -24,7 +24,7 @@ #include <arch/io.h> #include <device/pnp.h> -void f71869ad_multifunc_init(device_t dev); -void f71869ad_hwm_init(device_t dev); +void f71869ad_multifunc_init(struct device *dev); +void f71869ad_hwm_init(struct device *dev); #endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */ diff --git a/src/superio/ite/it8728f/it8728f_hwm.c b/src/superio/ite/it8728f/it8728f_hwm.c index fd486a8..23fa9e8 100644 --- a/src/superio/ite/it8728f/it8728f_hwm.c +++ b/src/superio/ite/it8728f/it8728f_hwm.c @@ -41,7 +41,7 @@ static void pnp_write_index(u16 port, u8 reg, u8 value) outb(value, port + 1); } -void it8728f_hwm_ec_init(device_t dev) +void it8728f_hwm_ec_init(struct device *dev) { struct superio_ite_it8728f_config *conf = dev->chip_info; struct resource *res = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/ite/it8728f/it8728f_internal.h b/src/superio/ite/it8728f/it8728f_internal.h index 89aecb4..6eb16af 100644 --- a/src/superio/ite/it8728f/it8728f_internal.h +++ b/src/superio/ite/it8728f/it8728f_internal.h @@ -23,6 +23,6 @@ #include <device/device.h> -void it8728f_hwm_ec_init(device_t dev); +void it8728f_hwm_ec_init(struct device *dev); #endif /* SUPERIO_ITE_IT8728F_INTERNAL_H */ diff --git a/src/superio/smsc/fdc37n972/fdc37n972.c b/src/superio/smsc/fdc37n972/fdc37n972.c index 97dea9f..ff04526 100644 --- a/src/superio/smsc/fdc37n972/fdc37n972.c +++ b/src/superio/smsc/fdc37n972/fdc37n972.c @@ -24,7 +24,7 @@ #include "fdc37n972.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) return; diff --git a/src/superio/smsc/sio10n268/sio10n268.c b/src/superio/smsc/sio10n268/sio10n268.c index fab7c41..4635080 100644 --- a/src/superio/smsc/sio10n268/sio10n268.c +++ b/src/superio/smsc/sio10n268/sio10n268.c @@ -23,7 +23,7 @@ #include <pc80/keyboard.h> #include "sio10n268.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) return; diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index f7a5cd9..8e9904b 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -44,7 +44,7 @@ static u8 hwm_io_regs[] = { 0x5c,0x00, 0x5f,0x33, 0x40,0x01, }; -static void vt1211_set_iobase(device_t dev, u8 index, u16 iobase) +static void vt1211_set_iobase(struct device *dev, u8 index, u16 iobase) { switch (dev->path.pnp.device) { case VT1211_FDC: @@ -107,7 +107,7 @@ static void vt1211_init(struct device *dev) } } -static void vt1211_pnp_enable_resources(device_t dev) +static void vt1211_pnp_enable_resources(struct device *dev) { printk(BIOS_DEBUG, "%s - enabling\n", dev_path(dev)); pnp_enable_resources(dev);

1 0

Patch merged into coreboot/master: f21bdc3 superio/*/superio.c: Don't hide pointer types behind typedefs
by gerrit＠coreboot.org 27 Oct '14

27 Oct '14

the following patch was just integrated into master: commit f21bdc3020b24cce585c4df69b06913177c94182 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 21 07:43:41 2014 +1100 superio/*/superio.c: Don't hide pointer types behind typedefs Hiding pointer types behind 'typedef's is usually not a great idea at the best of times. Worse the typedef becomes an integer at different stages in Coreboot. Let us refrain from doing this at all. Change-Id: Ia2ca8c98bb489daaa58f379433875864f6efabc8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7136 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/7136 for details. -gerrit

1 0

Patch merged into coreboot/master: 85836c2 superio: Use 'pnp_devfn_t' over 'device_t' in romstage component
by gerrit＠coreboot.org 27 Oct '14

27 Oct '14

the following patch was just integrated into master: commit 85836c2215498ff18746b3a7e85ed684cf2e119e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 20:26:25 2014 +1000 superio: Use 'pnp_devfn_t' over 'device_t' in romstage component The romstage component of Super I/O support is in fact written around passing a lower and upper half packed integer. We currently have two typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of 'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the ramstage context and so is really a conflicting definition. This helps solve problems down the road to having the 'real' 'device_t' definition usable in romstage later. This follows on from the rational given in: c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6231 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6231 for details. -gerrit

1 0

Patch merged into coreboot/master: 377fd75 superio/common/conf_mode.c: Don't hide pointers with typedefs
by gerrit＠coreboot.org 27 Oct '14

27 Oct '14

the following patch was just integrated into master: commit 377fd754932922e8c907994ef3e4d8ab925c6132 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 21 07:51:24 2014 +1100 superio/common/conf_mode.c: Don't hide pointers with typedefs Change-Id: Ia1bbf2f885acf601b8a8360a7cd72819f70ef6a6 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7137 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7137 for details. -gerrit

1 0

Patch set updated for coreboot: ab62e20 bd82x6x: Move to common FADT.
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7200 -gerrit commit ab62e2062ca37f485a4b1235662993f052fd2540 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 25 15:20:55 2014 +0200 bd82x6x: Move to common FADT. Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/devicetree.cb | 3 + src/mainboard/google/butterfly/fadt.c | 169 ---------------------- src/mainboard/google/link/devicetree.cb | 3 + src/mainboard/google/link/fadt.c | 166 ---------------------- src/mainboard/google/parrot/devicetree.cb | 3 + src/mainboard/google/parrot/fadt.c | 166 ---------------------- src/mainboard/google/stout/devicetree.cb | 3 + src/mainboard/google/stout/fadt.c | 166 ---------------------- src/mainboard/intel/cougar_canyon2/devicetree.cb | 3 + src/mainboard/intel/cougar_canyon2/fadt.c | 171 ----------------------- src/mainboard/intel/emeraldlake2/devicetree.cb | 3 + src/mainboard/intel/emeraldlake2/fadt.c | 156 --------------------- src/mainboard/kontron/ktqm77/devicetree.cb | 3 + src/mainboard/kontron/ktqm77/fadt.c | 169 ---------------------- src/mainboard/lenovo/t520/devicetree.cb | 3 + src/mainboard/lenovo/t520/fadt.c | 160 --------------------- src/mainboard/lenovo/t530/devicetree.cb | 2 + src/mainboard/lenovo/t530/fadt.c | 160 --------------------- src/mainboard/lenovo/x220/devicetree.cb | 3 + src/mainboard/lenovo/x220/fadt.c | 160 --------------------- src/mainboard/lenovo/x230/devicetree.cb | 2 + src/mainboard/lenovo/x230/fadt.c | 160 --------------------- src/mainboard/samsung/lumpy/devicetree.cb | 3 + src/mainboard/samsung/lumpy/fadt.c | 156 --------------------- src/mainboard/samsung/stumpy/devicetree.cb | 3 + src/mainboard/samsung/stumpy/fadt.c | 156 --------------------- src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/chip.h | 4 + src/southbridge/intel/bd82x6x/lpc.c | 134 ++++++++++++++++++ src/southbridge/intel/fsp_bd82x6x/Kconfig | 1 + src/southbridge/intel/fsp_bd82x6x/chip.h | 3 + src/southbridge/intel/fsp_bd82x6x/lpc.c | 130 +++++++++++++++++ 32 files changed, 310 insertions(+), 2115 deletions(-) diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index e944639..ed0d8d1 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -61,6 +61,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported + register "p_cnt_throttling_supported" = "1" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/butterfly/fadt.c b/src/mainboard/google/butterfly/fadt.c deleted file mode 100644 index b8da1be..0000000 --- a/src/mainboard/google/butterfly/fadt.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 608bc84..5333dfc 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -63,6 +63,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/link/fadt.c b/src/mainboard/google/link/fadt.c deleted file mode 100644 index 5ce9ab1..0000000 --- a/src/mainboard/google/link/fadt.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 8496c9f..a4baafd 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -61,6 +61,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/parrot/fadt.c b/src/mainboard/google/parrot/fadt.c deleted file mode 100644 index b96ec32..0000000 --- a/src/mainboard/google/parrot/fadt.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 9f0be35..4ac89f6 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -64,6 +64,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/stout/fadt.c b/src/mainboard/google/stout/fadt.c deleted file mode 100644 index 5ce9ab1..0000000 --- a/src/mainboard/google/stout/fadt.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index 136a581..c386853 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -34,6 +34,9 @@ chip northbridge/intel/fsp_sandybridge chip southbridge/intel/fsp_bd82x6x # Intel Series 6 Cougar Point PCH register "sata_port_map" = "0x3f" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 14.0 on end # XHCI device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 on end # Management Engine Interface 2 diff --git a/src/mainboard/intel/cougar_canyon2/fadt.c b/src/mainboard/intel/cougar_canyon2/fadt.c deleted file mode 100644 index 5191674..0000000 --- a/src/mainboard/intel/cougar_canyon2/fadt.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; - fadt->model = 0x00; /* reserved, should be 0 ACPI 3.0 */ - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x00; - fadt->pstate_cnt = 0x00; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */ - fadt->pm2_cnt_len = 1; /* 8 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 16; /* 128 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0x00; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->duty_offset = 1; - fadt->duty_width = 0; /* not supported */ - fadt->day_alrm = 0x0D; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->res3 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - - fadt->x_firmware_ctl_l = 0x00; /* set to 0 if firmware_ctrl is used */ - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0; - fadt->x_pm1b_evt_blk.addrh = 0; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x04; - fadt->x_pm1a_cnt_blk.addrh = 0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0; - fadt->x_pm1b_cnt_blk.addrh = 0; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x08; - fadt->x_pm_tmr_blk.addrh = 0; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 128; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0; - - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 76c4ac9..e5a8ea0 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -46,6 +46,9 @@ chip northbridge/intel/sandybridge # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/intel/emeraldlake2/fadt.c b/src/mainboard/intel/emeraldlake2/fadt.c deleted file mode 100644 index 315cb58..0000000 --- a/src/mainboard/intel/emeraldlake2/fadt.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 5dfd6cc..855fd5c 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -41,6 +41,9 @@ chip northbridge/intel/sandybridge # Disable root port coalescing register "pcie_port_coalesce" = "0" + register "c2_latency" = "101" # c2 not supported + register "p_cnt_throttling_supported" = "1" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/kontron/ktqm77/fadt.c b/src/mainboard/kontron/ktqm77/fadt.c deleted file mode 100644 index b8da1be..0000000 --- a/src/mainboard/kontron/ktqm77/fadt.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 168e0e7..486e8d2 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -64,6 +64,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported + register "p_cnt_throttling_supported" = "1" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end device pci 16.2 off end diff --git a/src/mainboard/lenovo/t520/fadt.c b/src/mainboard/lenovo/t520/fadt.c deleted file mode 100644 index 27e6303..0000000 --- a/src/mainboard/lenovo/t520/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index ba33601..c1cbca2 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -63,6 +63,8 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported + register "p_cnt_throttling_supported" = "1" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 diff --git a/src/mainboard/lenovo/t530/fadt.c b/src/mainboard/lenovo/t530/fadt.c deleted file mode 100644 index 27e6303..0000000 --- a/src/mainboard/lenovo/t530/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 0ecec26..c3b8ad9 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -68,6 +68,9 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported + register "p_cnt_throttling_supported" = "1" + device pci 16.0 on subsystemid 0x17aa 0x21db end # Management Engine Interface 1 diff --git a/src/mainboard/lenovo/x220/fadt.c b/src/mainboard/lenovo/x220/fadt.c deleted file mode 100644 index 27e6303..0000000 --- a/src/mainboard/lenovo/x220/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 1560b0d..f2fed1f 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -67,6 +67,8 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported + register "p_cnt_throttling_supported" = "1" device pci 14.0 on subsystemid 0x17aa 0x21fa diff --git a/src/mainboard/lenovo/x230/fadt.c b/src/mainboard/lenovo/x230/fadt.c deleted file mode 100644 index 27e6303..0000000 --- a/src/mainboard/lenovo/x230/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 101; /* c2 not supported */ - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index a5b96e2..9b0fc40 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -56,6 +56,9 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x003c0a01" register "gen2_dec" = "0x003c0b01" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/samsung/lumpy/fadt.c b/src/mainboard/samsung/lumpy/fadt.c deleted file mode 100644 index 510b765..0000000 --- a/src/mainboard/samsung/lumpy/fadt.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 9769ca4..60b112b 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -42,6 +42,9 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3" + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/mainboard/samsung/stumpy/fadt.c b/src/mainboard/samsung/stumpy/fadt.c deleted file mode 100644 index 315cb58..0000000 --- a/src/mainboard/samsung/stumpy/fadt.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 4b1931f..767193e 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select PER_DEVICE_ACPI_TABLES + select COMMON_FADT config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index d1d6401..1256129 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -83,6 +83,10 @@ struct southbridge_intel_bd82x6x_config { uint8_t pcie_aspm_f5; uint8_t pcie_aspm_f6; uint8_t pcie_aspm_f7; + + int p_cnt_throttling_supported; + int c2_latency; + int docking_supported; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 521e847..20f20ae 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -32,8 +32,10 @@ #include <elog.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> +#include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> +#include <cpu/x86/smm.h> #include "pch.h" #include "nvs.h" @@ -705,6 +707,138 @@ static void southbridge_inject_dsdt(void) } } +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *chip = dev->chip_info; + u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + int c2_latency; + + fadt->model = 1; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + c2_latency = chip->c2_latency; + if (!c2_latency) { + c2_latency = 101; /* c2 unsupported */ + } + fadt->p_lvl2_lat = c2_latency; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + if (chip->p_cnt_throttling_supported) { + fadt->duty_width = 3; + } else { + fadt->duty_width = 0; + } + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + if (chip->docking_supported) { + fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + } + if (c2_latency < 100) { + fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; + } + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index f628270..97bfcb0 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select PER_DEVICE_ACPI_TABLES + select COMMON_FADT config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_bd82x6x/chip.h b/src/southbridge/intel/fsp_bd82x6x/chip.h index 2415224..7d7ee87 100644 --- a/src/southbridge/intel/fsp_bd82x6x/chip.h +++ b/src/southbridge/intel/fsp_bd82x6x/chip.h @@ -87,6 +87,9 @@ struct southbridge_intel_fsp_bd82x6x_config { uint8_t pcie_aspm_f5; uint8_t pcie_aspm_f6; uint8_t pcie_aspm_f7; + + int p_cnt_throttling_supported; + int c2_latency; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e5d63b6..86cce06 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -33,6 +33,7 @@ #include <elog.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> +#include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> #include "pch.h" @@ -656,6 +657,135 @@ static void southbridge_inject_dsdt(void) } } +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *chip = dev->chip_info; + u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + int c2_latency; + + fadt->model = 1; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + c2_latency = chip->c2_latency; + if (!c2_latency) { + c2_latency = 101; /* c2 unsupported */ + } + fadt->p_lvl2_lat = c2_latency; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + if (chip->p_cnt_throttling_supported) { + fadt->duty_width = 3; + } else { + fadt->duty_width = 0; + } + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + if (c2_latency < 100) { + fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; + } + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, };

1 0

Patch set updated for coreboot: 3b826a6 ibexpeak: Move to common FADT
by Vladimir Serbinenko 27 Oct '14

27 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7201 -gerrit commit 3b826a661e3f09b0e320e84cd829381f89958e79 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Oct 25 15:49:23 2014 +0200 ibexpeak: Move to common FADT Change-Id: Ibb4dcc4356876f6385e79c10d8296fb680937827 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/devicetree.cb | 4 + src/mainboard/lenovo/x201/fadt.c | 160 -------------------------------- src/mainboard/packardbell/ms2290/fadt.c | 160 -------------------------------- src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/ibexpeak/lpc.c | 132 ++++++++++++++++++++++++++ 5 files changed, 137 insertions(+), 320 deletions(-) diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6920d2a..d467e92 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -109,6 +109,10 @@ chip northbridge/intel/nehalem register "gen3_dec" = "0x1c1681" register "gen4_dec" = "0x040069" + register "p_cnt_throttling_supported" = "1" + register "c2_latency" = "1" + register "docking_supported" = "1" + device pci 16.2 on # IDE/SATA subsystemid 0x17aa 0x2161 end diff --git a/src/mainboard/lenovo/x201/fadt.c b/src/mainboard/lenovo/x201/fadt.c deleted file mode 100644 index 0639026..0000000 --- a/src/mainboard/lenovo/x201/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = - pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - 0x40) & 0xfffe; - - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 0; - - fadt->firmware_ctrl = (unsigned long)facs; - fadt->dsdt = (unsigned long)dsdt; - fadt->model = 0x00; - fadt->preferred_pm_profile = PM_MOBILE; - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 0x10; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = APM_CNT_CST_CONTROL; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 0x23; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x32; - fadt->iapc_boot_arch = 0x00; - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_DOCKING_SUPPORTED; - - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 0; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 0; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 32; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 0; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 0; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *)fadt, header->length); -} diff --git a/src/mainboard/packardbell/ms2290/fadt.c b/src/mainboard/packardbell/ms2290/fadt.c deleted file mode 100644 index 0639026..0000000 --- a/src/mainboard/packardbell/ms2290/fadt.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = - pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - 0x40) & 0xfffe; - - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 0; - - fadt->firmware_ctrl = (unsigned long)facs; - fadt->dsdt = (unsigned long)dsdt; - fadt->model = 0x00; - fadt->preferred_pm_profile = PM_MOBILE; - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 0x10; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = APM_CNT_CST_CONTROL; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 0x23; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x32; - fadt->iapc_boot_arch = 0x00; - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_DOCKING_SUPPORTED; - - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 0; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 0; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 32; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 0; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 0; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *)fadt, header->length); -} diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index dfd8276..07a5ac2 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select HAVE_USBDEBUG_OPTIONS select PER_DEVICE_ACPI_TABLES + select COMMON_FADT config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index db8f54f..da609da 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -35,6 +35,7 @@ #include <drivers/intel/gma/i915.h> #include <cbmem.h> #include <string.h> +#include <cpu/x86/smm.h> #include "pch.h" #include "nvs.h" @@ -690,6 +691,137 @@ static void southbridge_inject_dsdt(void) } } +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + config_t *chip = dev->chip_info; + u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + int c2_latency; + + fadt->model = 1; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + c2_latency = chip->c2_latency; + if (!c2_latency) { + c2_latency = 101; /* c2 unsupported */ + } + fadt->p_lvl2_lat = c2_latency; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + if (chip->p_cnt_throttling_supported) { + fadt->duty_width = 3; + } else { + fadt->duty_width = 0; + } + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + if (chip->docking_supported) { + fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + } + if (c2_latency < 100) { + fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; + } + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, };

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coreboot-gerrit October 2014