coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 7a94275 autoport: Experimental stuff
by Vladimir Serbinenko 26 Oct '14

26 Oct '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7131 -gerrit commit 7a942751fc6a95eb9dba085f8c49e7f4966fa0dc Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 21:51:47 2014 +0200 autoport: Experimental stuff Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/autoport/azalia.go | 54 +++++ util/autoport/bd82x6x.go | 181 ++++++++++++++++ util/autoport/hardcoded.go | 407 +++++++++++++++++++++++++++++++++++ util/autoport/i82801gx.go | 265 +++++++++++++++++++++++ util/autoport/i945.go | 82 +++++++ util/autoport/log_maker.go | 77 +++++++ util/autoport/log_reader.go | 264 +++++++++++++++++++++++ util/autoport/main.go | 500 +++++++++++++++++++++++++++++++++++++++++++ util/autoport/root.go | 28 +++ util/autoport/sandybridge.go | 112 ++++++++++ 10 files changed, 1970 insertions(+) diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go new file mode 100644 index 0000000..97e3449 --- /dev/null +++ b/util/autoport/azalia.go @@ -0,0 +1,54 @@ +package main + +import ( + "fmt" +) + +type azalia struct { +} + +func (i azalia) Scan(ctx Context, addr PCIDevData) { + az := Create(ctx, "hda_verb.c") + defer az.Close() + + az.WriteString( + `#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +`) + + for _, codec := range ctx.InfoSource.GetAzaliaCodecs() { + fmt.Fprintf(az, "\t0x%08x, /* Codec Vendor / Device ID: %s */\n", + codec.VendorID, codec.Name) + fmt.Fprintf(az, "\t0x%08x, /* Subsystem ID */\n", + codec.SubsystemID) + fmt.Fprintf(az, "\n\t0x%08x, /* Number of 4 dword sets */\n", + len(codec.PinConfig)+1) + fmt.Fprintf(az, "\t/* NID 0x01: Subsystem ID. */\n") + fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n", + codec.CodecNo, codec.SubsystemID) + + for nid, val := range codec.PinConfig { + fmt.Fprintf(az, "\n\t/* NID 0x%02x: Subsystem ID. */\n", nid) + fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n", + codec.CodecNo, nid, val) + } + } + + az.WriteString( + `}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; +`) + + PutPCIDev(addr, "Audio controller") +} + +func init() { + /* I82801GX/I945 */ + RegisterPCI(0x8086, 0x27d8, azalia{}) + /* C216/ivybridge */ + RegisterPCI(0x8086, 0x1e20, azalia{}) +} diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go new file mode 100644 index 0000000..e7c6e75 --- /dev/null +++ b/util/autoport/bd82x6x.go @@ -0,0 +1,181 @@ +package main + +import ( + "fmt" + "os" +) + +type bd82x6x struct { + variant string +} + +func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + { "GPIO_MODE_NATIVE", "GPIO_MODE_GPIO" }, + { "GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT" }, + { "GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH" }, + { "GPIO_RESET_PWROK", "GPIO_RESET_RSMRST" }, + { "GPIO_NO_INVERT", "GPIO_INVERT" }, + { "GPIO_NO_BLINK", "GPIO_BLINK" }, + } + + for i := uint(0); i < max; i++ { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set - 1) * 32 + i, + bits[partno][(val >> i) & 1]) + } +} + + +func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) { + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMstageFile("gpio.c", "") + + gpio.WriteString(`#include "southbridge/intel/bd82x6x/gpio.h" +`) + + adresses := [3][6]int{ + { 0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18 }, + { 0x30, 0x34, 0x38, 0x64, -1, -1 }, + { 0x40, 0x44, 0x48, 0x68, -1, -1 }, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := adresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`static const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} + +func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + b.GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_" + b.variant] = true + /* FIMXE: move */ + KconfigBool["HAVE_SMI_HANDLER"] = true + KconfigInt["IRQ_SLOT_COUNT"] = 18 + /* FIXME: hardcoded */ + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + /* FIXME: hardcoded */ + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + /* FIXME: hardcoded */ + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + cur := DevTreeNode{ + Chip: "southbridge/intel/bd82x6x", + Comment: "Intel Series 6 Cougar Point PCH", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "alt_gp_smi_en": "0x0000", + "gpi1_routing": "2", + "gpi8_routing": "2", + "sata_port_map": "0x7", + "sata_interface_speed_support": "0x3", + "gen1_dec": "0x7c1601", + "gen2_dec": "0x0c15e1", + "gen4_dec": "0x0c06a1", + "pcie_port_coalesce": "1", + + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c2_latency": FormatHexLE16(FADT[96:98]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr:PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + PutChip("pcibus0", cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/pch.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x1e55, bd82x6x{variant:"C216"}) + RegisterPCI(0x8086, 0x1e31, GenericPCI{}) + RegisterPCI(0x8086, 0x1e26, GenericPCI{}) + RegisterPCI(0x8086, 0x1e2d, GenericPCI{}) + RegisterPCI(0x8086, 0x1e3a, GenericPCI{}) + RegisterPCI(0x8086, 0x1502, GenericPCI{}) + RegisterPCI(0x8086, 0x1e10, GenericPCI{}) + RegisterPCI(0x8086, 0x1e12, GenericPCI{}) + RegisterPCI(0x8086, 0x1e14, GenericPCI{}) + RegisterPCI(0x8086, 0x1e03, GenericPCI{}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) +} diff --git a/util/autoport/hardcoded.go b/util/autoport/hardcoded.go new file mode 100644 index 0000000..584ddd8 --- /dev/null +++ b/util/autoport/hardcoded.go @@ -0,0 +1,407 @@ +package main + +func Hardcoded(ctx Context) { + ai := Create(ctx, "acpi/ich7_pci_irqs.asl") + defer ai.Close() + + /* FIXME: hardcoded. */ + ai.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} +`) + ap := Create(ctx, "acpi/platform.asl") + defer ap.Close() + + /* FIXME: hardcoded. */ + ap.WriteString( + `Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Scope(\_SB) +{ + Method(_INI, 0) + { + \GOS() + } +} +`) + sh := Create(ctx, "smihandler.c") + defer sh.Close() + + /* FIXME: hardcoded. */ + sh.WriteString( + ` +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include <pc80/mc146818rtc.h> +#include <delay.h> + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + case APM_CNT_ACPI_DISABLE: + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + default: + break; + } + return 0; +} +`) + mb := Create(ctx, "mainboard.c") + defer mb.Close() + + /* FIXME: hardcoded. */ + mb.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <northbridge/intel/i945/i945.h> +#include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> +#include <drivers/intel/gma/int15.h> +#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} + +static void mainboard_init(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; +`) + + em := Create(ctx, "early_mainboard.h") + defer em.Close() + + /* FIXME: hardcoded. */ + em.WriteString( + `void ich7_enable_lpc(void); +void rcba_config(void); +void early_ich7_init(void); +`) + + rs := Create(ctx, "romstage.c") + defer rs.Close() + + /* FIXME: hardcoded. */ + rs.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <cpu/x86/lapic.h> +#include <timestamp.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "early_mainboard.h" + +void main(unsigned long bist) +{ + int s3resume = 0; + const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + + ich7_enable_lpc(); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, + "Soft reset detected, rebooting properly.\n"); + outb(0x6, 0xcf9); + while (1) + asm("hlt"); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(s3resume ? 2 : 0, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); + + timestamp_add_now(TS_END_ROMSTAGE); +} +`) + + at := Create(ctx, "acpi_tables.c") + defer at.Close() + + /* FIXME: hardcoded. */ + at.WriteString( + `#include <stdint.h> +#include "southbridge/intel/i82801gx/nvs.h" +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} +`) + + av := Create(ctx, "acpi/video.asl") + defer av.Close() + + ec := Create(ctx, "acpi/ec.asl") + defer ec.Close() + + si := Create(ctx, "acpi/superio.asl") + defer si.Close() +} diff --git a/util/autoport/i82801gx.go b/util/autoport/i82801gx.go new file mode 100644 index 0000000..f82de8a --- /dev/null +++ b/util/autoport/i82801gx.go @@ -0,0 +1,265 @@ +package main + +import ( + "fmt" + "os" +) + +type i82801gx struct { +} + +func (i i82801gx) writeGPIO(ctx Context, sb *os.File, inteltool InteltoolData, addr uint16, name string) { + fmt.Fprintf(sb, " outl(0x%08x, DEFAULT_GPIOBASE + %s);\n", + inteltool.GPIO[addr], name) +} + +func (i i82801gx) Scan(ctx Context, addr PCIDevData) { + + /* FIXME: Move to southbbridge. */ + KconfigBool["HAVE_MP_TABLE"] = true + + KconfigBool["SOUTHBRIDGE_INTEL_I82801GX"] = true + KconfigInt["IRQ_SLOT_COUNT"] = 18 + + sb := Create(ctx, "early_southbridge.c") + defer sb.Close() + AddROMstageFile("early_southbridge.c", "") + sb.WriteString(`#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "northbridge/intel/i945/i945.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include "early_mainboard.h" + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + +`) + inteltool := ctx.InfoSource.GetInteltool() + i.writeGPIO(ctx, sb, inteltool, 0x0, "GPIO_USE_SEL") + i.writeGPIO(ctx, sb, inteltool, 0x4, "GP_IO_SEL") + i.writeGPIO(ctx, sb, inteltool, 0xc, "GP_LVL") + i.writeGPIO(ctx, sb, inteltool, 0x18, "GPO_BLINK") + i.writeGPIO(ctx, sb, inteltool, 0x2c, "GPI_INV") + i.writeGPIO(ctx, sb, inteltool, 0x30, "GPIO_USE_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x34, "GP_IO_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x38, "GP_LVL2") + + sb.WriteString(`} + +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // Enable address decodes + /* FIXME: Make sure that all regions are properly reserved. */ +`) + + /* FIXME: Make sure that all regions are properly reserved. */ + RestorePCI16Simple(sb, addr, 0x80) + RestorePCI16Simple(sb, addr, 0x82) + RestorePCI16Simple(sb, addr, 0x84) + RestorePCI16Simple(sb, addr, 0x86) + RestorePCI16Simple(sb, addr, 0x88) + RestorePCI16Simple(sb, addr, 0x8a) + RestorePCI16Simple(sb, addr, 0x8c) + RestorePCI16Simple(sb, addr, 0x8e) + RestorePCI16Simple(sb, addr, 0x90) + RestorePCI16Simple(sb, addr, 0x92) + + /* Just use the same interrupt map for all boards: just registers have to match ACPI. */ + sb.WriteString(`} + +void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Disable devices. */ +`) + + RestoreRCBA32(sb, inteltool, 0x3418) + + sb.WriteString(` + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} +`) + + /* FIXME: does this one need adjustments? */ + sb.WriteString(`void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} +`) + + Hardcoded(ctx) + + ioapic := DevTreeNode{ + Chip: "drivers/generic/ioapic", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "have_isa_interrupts": "1", + "irq_on_fsb": "1", + "enable_virtual_wire": "0", + "base": "0xfec00000", + }, + Children: []DevTreeNode{ + { + Chip: "ioapic", + Dev: 2, + }, + }, + } + + PutChip("pcibus0", ioapic) + + ideConfig := PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 1}].ConfigDump[0x54] + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + cur := DevTreeNode{ + Chip: "southbridge/intel/i82801gx", + Comment: "Southbridge", + MissingParent: "southbridge", + Registers: map[string]string{ + /* FIXME: should be a CMOS config */ + "sata_ahci": "0x1", + /* FIXME: hardcoded. */ + "gpi1_routing": "2", + "gpi7_routing": "2", + "gpe0_en": "0x11000006", + "alt_gp_smi_en": "0x1000", + + "sata_ports_implemented": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0xf), + "ide_enable_primary": fmt.Sprintf("%d", (ideConfig>>1)&1), + "ide_enable_secondary": fmt.Sprintf("%d", (ideConfig>>3)&1), + "c4onc3_enable": fmt.Sprintf("%d", ((addr.ConfigDump[0xa0] >> 7) & 1)), + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c3_latency": FormatHexLE16(FADT[98:100]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr:PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 1}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 2}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 3}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1d, Func: 7}, writeEmpty: true, additionalComment: "USB EHCI"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 1}, writeEmpty: true, additionalComment: "IDE Controller"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + }, + } + + PutChip("pcibus0", cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x00}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x07}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1b}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1c}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x11, 0x10, 0x12, 0x13}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1d}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x17, 0x13, 0x12, 0x10}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1e}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0x14, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1f}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x12, 0x13, 0, 0x10}} + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/ich7.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x27b9, i82801gx{}) + RegisterPCI(0x8086, 0x27c8, GenericPCI{}) + RegisterPCI(0x8086, 0x27c9, GenericPCI{}) + RegisterPCI(0x8086, 0x27ca, GenericPCI{}) + RegisterPCI(0x8086, 0x27cb, GenericPCI{}) + RegisterPCI(0x8086, 0x27cc, GenericPCI{}) + + RegisterPCI(0x8086, 0x27d0, GenericPCI{}) + RegisterPCI(0x8086, 0x27d2, GenericPCI{}) + RegisterPCI(0x8086, 0x27d4, GenericPCI{}) + RegisterPCI(0x8086, 0x27d6, GenericPCI{}) + + RegisterPCI(0x8086, 0x2448, GenericPCI{}) + + RegisterPCI(0x8086, 0x27c5, GenericPCI{}) + RegisterPCI(0x8086, 0x27c4, GenericPCI{}) + RegisterPCI(0x8086, 0x27df, GenericPCI{}) + RegisterPCI(0x8086, 0x27da, GenericPCI{MissingParent:"smbus"}) +} diff --git a/util/autoport/i945.go b/util/autoport/i945.go new file mode 100644 index 0000000..013197e --- /dev/null +++ b/util/autoport/i945.go @@ -0,0 +1,82 @@ +package main + +type i945mc struct { +} + +func (i i945mc) Scan(ctx Context, addr PCIDevData) { + DevTree = DevTreeNode{ + Chip: "northbridge/intel/i945", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "gpu_hotplug": "0x00000220", + "gpu_lvds_use_spread_spectrum_clock": "1", + "gpu_lvds_is_dual_channel": "0", + "gpu_backlight": "0x1280128", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_mFCPGA478", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + }, + }, + { + Chip: "domain", + Dev: 0, + MissingParent: "pcibus0", + PCIController: true, + ChildPCIBus: 0, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME: Move part to northbridge? */ + /* FIXME: some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool["VGA"] = true + KconfigBool["MAINBOARD_DO_EDID"] = true + KconfigBool["EARLY_CBMEM_INIT"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_MFCPGA478"] = true + KconfigBool["NORTHBRIDGE_INTEL_I945"] = true + KconfigBool["CHANNEL_XOR_RANDOMIZATION"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigHex["DCACHE_RAM_BASE"] = 0xffdf8000 + KconfigHex["DCACHE_RAM_SIZE"] = 0x8000 + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 2 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_6dx/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/i945/acpi/i945.asl", + }) + + /* FIXME: when adding new i945 variants change this. */ + KconfigBool["NORTHBRIDGE_INTEL_SUBTYPE_I945GM"] = true +} + +func init() { + RegisterPCI(0x8086, 0x27a0, i945mc{}) + RegisterPCI(0x8086, 0x27ac, i945mc{}) + RegisterPCI(0x8086, 0x27a2, GenericVGA{GenericPCI{Comment:"VGA controller"}}) + RegisterPCI(0x8086, 0x27ae, GenericVGA{GenericPCI{Comment:"VGA controller"}}) + RegisterPCI(0x8086, 0x27a6, GenericPCI{Comment:"display controller"}) +} diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go new file mode 100644 index 0000000..f172520 --- /dev/null +++ b/util/autoport/log_maker.go @@ -0,0 +1,77 @@ +package main + +import ( + "io" + "io/ioutil" + "log" + "os" + "os/exec" + "strings" +) + +func RunAndSave(output string, name string, arg ...string) { + cmd := exec.Command(name, arg...) + + f, err := os.Create(output) + if err != nil { + log.Fatal(err) + } + + cmd.Stdout = f + cmd.Stderr = f + + err = cmd.Start() + if err != nil { + log.Fatal(err) + } + cmd.Wait() +} + +func MakeLogs(outDir string) { + os.MkdirAll(outDir, 0700) + RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx") + RunAndSave(outDir+"/dmidecode.log", "dmidecode") + RunAndSave(outDir+"/acpidump.log", "acpidump") + /* FIXME */ + RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", "-a") + + SysDir := "/sys/class/sound/card0/" + files, _ := ioutil.ReadDir(SysDir) + for _, f := range files { + if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { + in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + ProcDir := "/proc/asound/card0/" + files, _ = ioutil.ReadDir(ProcDir) + for _, f := range files { + if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { + in, err := os.Open(ProcDir + f.Name()) + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/" + f.Name()) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + /* + l.InputDirectory + "/inteltool.log" + */ +} diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go new file mode 100644 index 0000000..4e89cf2 --- /dev/null +++ b/util/autoport/log_reader.go @@ -0,0 +1,264 @@ +package main + +import ( + "bufio" + "flag" + "fmt" + "log" + "os" + "strconv" + "strings" +) + +type LogDevReader struct { + InputDirectory string + ACPITables map[string][]byte +} + +func isXDigit(x uint8) bool { + if x >= '0' && x <= '9' { + return true + } + if x >= 'a' && x <= 'f' { + return true + } + if x >= 'A' && x <= 'F' { + return true + } + return false +} + +type HexLine struct { + length uint + values [16]byte + start uint +} + +func (l *LogDevReader) ReadHexLine(line string) (hex HexLine) { + hex.start = 0 + line = strings.Trim(line, " ") + fmt.Sscanf(line, "%x:", &hex.start) + ll, _ := fmt.Sscanf(line, "%x: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x", &hex.start, + &hex.values[0], &hex.values[1], &hex.values[2], + &hex.values[3], &hex.values[4], &hex.values[5], + &hex.values[6], &hex.values[7], &hex.values[8], + &hex.values[9], &hex.values[10], &hex.values[11], + &hex.values[12], &hex.values[13], &hex.values[14], + &hex.values[15]) + hex.length = uint(ll - 1) + return +} + +func (l *LogDevReader) AssignHexLine(inp string, target []byte) []byte { + hex := l.ReadHexLine(inp) + if hex.start+hex.length > uint(len(target)) { + target = target[0 : hex.start+hex.length] + } + copy(target[hex.start:hex.start+hex.length], hex.values[0:hex.length]) + return target +} + +func (l *LogDevReader) GetACPI() (Tables map[string][]byte) { + if l.ACPITables != nil { + return l.ACPITables + } + l.ACPITables = Tables + + file, err := os.Open(l.InputDirectory + "/acpidump.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + Tables = map[string][]byte{} + + curTable := "" + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) >= 6 && line[5] == '@': + curTable = line[0:4] + Tables[curTable] = make([]byte, 0, 100000) + case len(line) > 7 && line[0:2] == " " && isXDigit(line[2]) && isXDigit(line[3]) && isXDigit(line[4]) && isXDigit(line[5]) && line[6] == ':': + Tables[curTable] = l.AssignHexLine(line, Tables[curTable]) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetPCIList() (PCIList []PCIDevData) { + file, err := os.Open(l.InputDirectory + "/lspci.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + PCIList = []PCIDevData{} + + for scanner.Scan() { + line := scanner.Text() + switch { + case !(len(line) < 7 || !isXDigit(line[0]) || !isXDigit(line[1]) || line[2] != ':' || !isXDigit(line[3]) || !isXDigit(line[4]) || line[5] != '.' || !isXDigit(line[6])): + cur := PCIDevData{} + fmt.Sscanf(line, "%x:%x.%x", &cur.Bus, &cur.Dev, &cur.Func) + lc := strings.LastIndex(line, ":") + li := strings.LastIndex(line[0:lc], "[") + if li < 0 { + continue + } + ven := 0 + dev := 0 + fmt.Sscanf(line[li+1:], "%x:%x", &ven, &dev) + cur.PCIDevID = uint16(dev) + cur.PCIVenID = uint16(ven) + cur.ConfigDump = make([]byte, 0x100, 0x1000) + PCIList = append(PCIList, cur) + case len(line) > 7 && isXDigit(line[0]) && line[1] == '0' && line[2] == ':': + start := 0 + fmt.Sscanf(line, "%x:", &start) + cur := &PCIList[len(PCIList)-1] + cur.ConfigDump = l.AssignHexLine(line, cur.ConfigDump) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetInteltool() (ret InteltoolData) { + file, err := os.Open(l.InputDirectory + "/inteltool.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + ret.GPIO = map[uint16]uint32{} + ret.RCBA = map[uint16]uint32{} + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "RCBA": + addr, value := 0, 0 + fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value) + ret.RCBA[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "gpiobase"): + addr, value := 0, 0 + fmt.Sscanf(line, "gpiobase+0x%x: 0x%x", &addr, &value) + ret.GPIO[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "============="): + paragraph = strings.Trim(line, "= ") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetDMI() (ret DMIData) { + file, err := os.Open(l.InputDirectory + "/dmidecode.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + for scanner.Scan() { + line := scanner.Text() + if !strings.HasPrefix(line, "\t") { + paragraph = strings.TrimSpace(line) + continue + } + idx := strings.Index(line, ":") + if idx < 0 { + continue + } + name := strings.TrimSpace(line[0:idx]) + value := strings.TrimSpace(line[idx+1:]) + switch paragraph + ":" + name { + case "System Information:Manufacturer": + ret.Vendor = value + case "System Information:Product Name": + ret.Model = value + case "System Information:Version": + ret.Version = value + case "Chassis Information:Type": + ret.IsLaptop = (value == "Notebook" || value == "Laptop") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetAzaliaCodecs() (ret []AzaliaCodec) { + for codecno := 0; codecno < 10; codecno++ { + cur := AzaliaCodec{CodecNo: codecno, PinConfig: map[int]uint32{}} + codec, err := os.Open(l.InputDirectory + "/codec#" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer codec.Close() + pin, err := os.Open(l.InputDirectory + "/pin_hwC0D" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer pin.Close() + + scanner := bufio.NewScanner(codec) + for scanner.Scan() { + line := scanner.Text() + if strings.HasPrefix(line, "Codec:") { + fmt.Sscanf(line, "Codec: %s", &cur.Name) + continue + } + if strings.HasPrefix(line, "Vendor Id:") { + fmt.Sscanf(line, "Vendor Id: 0x%x", &cur.VendorID) + continue + } + if strings.HasPrefix(line, "Subsystem Id:") { + fmt.Sscanf(line, "Subsystem Id: 0x%x", &cur.SubsystemID) + continue + } + } + + scanner = bufio.NewScanner(pin) + for scanner.Scan() { + line := scanner.Text() + addr := 0 + val := uint32(0) + fmt.Sscanf(line, "0x%x 0x%x", &addr, &val) + cur.PinConfig[addr] = val + } + ret = append(ret, cur) + } + return +} + +var FlagLogInput = flag.String("input_log", ".", "Input log directory") +var FlagLogMkLogs = flag.Bool("make_logs", false, "Dump logs") + +func MakeLogReader() *LogDevReader { + if *FlagLogMkLogs { + MakeLogs(*FlagLogInput) + } + return &LogDevReader{InputDirectory: *FlagLogInput} +} diff --git a/util/autoport/main.go b/util/autoport/main.go new file mode 100644 index 0000000..d24952e --- /dev/null +++ b/util/autoport/main.go @@ -0,0 +1,500 @@ +/* This is just an experiment. Full automatic porting + is probably not possible but a lot can be automated. */ +package main + +import ( + "flag" + "fmt" + "log" + "os" + "strings" +) + +type PCIAddr struct { + Bus int + Dev int + Func int +} + +type PCIDevData struct { + PCIAddr + PCIVenID uint16 + PCIDevID uint16 + ConfigDump []uint8 +} + +type PCIDevice interface { + Scan(ctx Context, addr PCIDevData) +} + +type InteltoolData struct { + GPIO map[uint16]uint32 + RCBA map[uint16]uint32 +} + +type DMIData struct { + Vendor string + Model string + Version string + IsLaptop bool +} + +type AzaliaCodec struct { + Name string + VendorID uint32 + SubsystemID uint32 + CodecNo int + PinConfig map[int]uint32 +} + +type DevReader interface { + GetPCIList() []PCIDevData + GetDMI() DMIData + GetInteltool() InteltoolData + GetAzaliaCodecs() []AzaliaCodec + GetACPI() map[string][]byte +} + +var ROMStageFiles map[string]string = map[string]string{} +var RAMStageFiles map[string]string = map[string]string{} + +type Context struct { + MoboID string + KconfigName string + Vendor string + Model string + BaseDirectory string + InfoSource DevReader +} + +type IOAPICIRQ struct { + APICID int + IRQNO [4]int +} + +var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{} +var KconfigBool map[string]bool = map[string]bool{} +var KconfigString map[string]string = map[string]string{} +var KconfigStringUnquoted map[string]string = map[string]string{} +var KconfigHex map[string]uint32 = map[string]uint32{} +var KconfigInt map[string]int = map[string]int{} + +func FormatHexLE16(inp []byte) string { + return fmt.Sprintf ("0x%04x", uint16(inp[0]) | (uint16(inp[1]) << 8)) +} + +func FormatBool(inp bool) string { + if inp { + return "1" + } else { + return "0" + } +} + +func sanitize(inp string) string { + result := strings.ToLower(inp) + result = strings.Replace(result, " ", "_", -1) + result = strings.Replace(result, ",", "_", -1) + for strings.HasSuffix(result, ".") { + result = result[0 : len(result)-1] + } + return result +} + +func AddROMstageFile(Name string, Condition string) { + ROMStageFiles[Name] = Condition +} + +func AddRAMstageFile(Name string, Condition string) { + RAMStageFiles[Name] = Condition +} + +var FlagOutDir = flag.String("coreboot_dir", ".", "Resulting coreboot directory") + +func writeMF(mf *os.File, files map[string]string, category string) { + for file, condition := range files { + if condition == "" { + fmt.Fprintf(mf, "%s-y += %s\n", category, file) + } else { + fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, + condition, file) + } + } +} + +func Create(ctx Context, name string) *os.File { + li := strings.LastIndex(name, "/") + if li > 0 { + os.MkdirAll(ctx.BaseDirectory+"/"+name[0:li], 0700) + } + mf, err := os.Create(ctx.BaseDirectory + "/" + name) + if err != nil { + log.Fatal(err) + } + return mf +} + +func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestoreRCBA32(f *os.File, inteltool InteltoolData, addr uint16) { + fmt.Fprintf(f, "\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr]) +} + +type PCISlot struct { + PCIAddr + additionalComment string + writeEmpty bool +} + +type DevTreeNode struct { + Bus int + Dev int + Func int + Disabled bool + Registers map[string]string + Children []DevTreeNode + PCISlots []PCISlot + PCIController bool + ChildPCIBus int + MissingParent string + SubVendor uint16 + SubSystem uint16 + Chip string + Comment string +} + +var DevTree DevTreeNode +var MissingChildren map[string][]DevTreeNode = map[string][]DevTreeNode{} +var unmatchedPCIDevices map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} + +func Offset(dt *os.File, offset int) { + for i := 0; i < offset; i++ { + fmt.Fprintf(dt, "\t") + } +} + +func MatchDev(dev *DevTreeNode) { + for _, slot := range dev.PCISlots { + slotDev, ok := unmatchedPCIDevices[slot.PCIAddr] + if !ok { + if slot.writeEmpty { + dev.Children = append(dev.Children, + DevTreeNode{ + Registers: map[string]string{}, + Chip: "pci", + Bus: slot.Bus, + Dev: slot.Dev, + Func: slot.Func, + Comment: slot.additionalComment, + Disabled: true, + }, + ) + } + continue + } + + if slot.additionalComment != "" && slotDev.Comment != "" { + slotDev.Comment = slot.additionalComment + " " + slotDev.Comment + } else { + slotDev.Comment = slot.additionalComment + slotDev.Comment + } + + dev.Children = append(dev.Children, slotDev) + delete (unmatchedPCIDevices, slot.PCIAddr) + } + + for idx := range dev.Children { + MatchDev(&dev.Children[idx]) + } + + if dev.MissingParent != "" { + for _, child := range MissingChildren[dev.MissingParent] { + MatchDev(&child) + dev.Children = append(dev.Children, child) + } + delete (MissingChildren, dev.MissingParent) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIDevices { + if slot.Bus == dev.ChildPCIBus { + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete (unmatchedPCIDevices, slot) + } + } + } +} + +func writeOn(dt *os.File, dev DevTreeNode) { + if dev.Disabled { + fmt.Fprintf(dt, "off") + } else { + fmt.Fprintf(dt, "on") + } +} + +func WriteDev(dt *os.File, offset int, dev DevTreeNode) { + Offset(dt, offset) + switch dev.Chip { + case "cpu_cluster", "lapic", "domain", "ioapic": + fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev) + writeOn(dt, dev) + case "pci": + fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func) + writeOn(dt, dev) + default: + fmt.Fprintf(dt, "chip %s", dev.Chip) + } + if dev.Comment != "" { + fmt.Fprintf(dt, " # %s", dev.Comment) + } + fmt.Fprintf(dt, "\n") + if dev.Chip == "pci" && dev.SubSystem != 0 && dev.SubVendor != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem) + } + + ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}] + if dev.Chip == "pci" && ok { + for pin, irq := range ioapic.IRQNO { + if irq != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq) + } + } + } + + for reg, val := range dev.Registers { + Offset(dt, offset+1) + fmt.Fprintf(dt, "register \"%s\" = \"%s\"\n", reg, val) + } + + for _, child := range dev.Children { + WriteDev(dt, offset+1, child) + } + + Offset(dt, offset) + fmt.Fprintf(dt, "end\n") +} + +func PutChip(domain string, cur DevTreeNode) { + MissingChildren[domain] = append(MissingChildren[domain], cur) +} + +func PutPCIDevParent(addr PCIDevData, comment string, parent string) { + cur := DevTreeNode{ + Registers: map[string]string{}, + SubVendor: uint16(addr.ConfigDump[0x2c]) | (uint16(addr.ConfigDump[0x2d]) << 8), + SubSystem: uint16(addr.ConfigDump[0x2e]) | (uint16(addr.ConfigDump[0x2f]) << 8), + Chip: "pci", + Bus: addr.Bus, + Dev: addr.Dev, + Func: addr.Func, + MissingParent: parent, + Comment: comment, + } + unmatchedPCIDevices[addr.PCIAddr] = cur +} + +func PutPCIDev(addr PCIDevData, comment string) { + PutPCIDevParent(addr, comment, "") +} + +type GenericPCI struct { + Comment string + Bus0Subdiv string + MissingParent string +} + +type GenericVGA struct { + GenericPCI +} + + +type DSDTInclude struct { + Comment string + File string +} + +var DSDTIncludes []DSDTInclude +var DSDTPCI0Includes []DSDTInclude + +func (g GenericPCI) Scan(ctx Context, addr PCIDevData) { + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func (g GenericVGA) Scan(ctx Context, addr PCIDevData) { + KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x.%04x", + addr.PCIVenID, + addr.PCIDevID) + KconfigString["VGA_BIOS_FILE"] = fmt.Sprintf("pci%04x,%04x.rom", + addr.PCIVenID, + addr.PCIDevID) + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func main() { + flag.Parse() + + ctx := Context{} + + ctx.InfoSource = MakeLogReader() + + dmi := ctx.InfoSource.GetDMI() + + ctx.Vendor = dmi.Vendor + + if dmi.Vendor == "LENOVO" { + ctx.Model = dmi.Version + } else { + ctx.Model = dmi.Model + } + + if dmi.IsLaptop { + KconfigBool["SYSTEM_TYPE_LAPTOP"] = true + } + ctx.MoboID = sanitize(ctx.Vendor) + "/" + sanitize(ctx.Model) + ctx.KconfigName = "BOARD_" + strings.ToUpper(sanitize(ctx.Vendor)+"_"+sanitize(ctx.Model)) + ctx.BaseDirectory = *FlagOutDir + "/src/mainboard/" + ctx.MoboID + KconfigStringUnquoted["MAINBOARD_DIR"] = ctx.MoboID + KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model + + /* Only x86 currently. */ + KconfigBool["ARCH_X86"] = true + + /* FIXME: hardcoded. */ + KconfigBool["BOARD_ROMSIZE_KB_2048"] = true + + os.MkdirAll(ctx.BaseDirectory, 0700) + + ScanRoot(ctx) + + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 { + mf := Create(ctx, "Makefile.inc") + defer mf.Close() + writeMF(mf, ROMStageFiles, "romstage") + } + + devtree := Create(ctx, "devicetree.cb") + defer devtree.Close() + + MatchDev(&DevTree) + WriteDev(devtree, 0, DevTree) + + bi := Create(ctx, "board_info.txt") + defer bi.Close() + + if dmi.IsLaptop { + bi.WriteString("Category: laptop") + } else { + /* FIXME: other categories. */ + bi.WriteString("Category: desktop") + } + + /* FIXME: flash chip. */ + + kc := Create(ctx, "Kconfig") + defer kc.Close() + + fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName) + + fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS # dummy\n\tdef_bool y\n") + for name, val := range KconfigBool { + if val { + fmt.Fprintf(kc, "\tselect %s\n", name) + } + } + + for name, val := range KconfigBool { + if !val { + fmt.Fprintf(kc, ` +config %s + string + default n +`, name) + } + } + + for name, val := range KconfigStringUnquoted { + fmt.Fprintf(kc, ` +config %s + string + default %s +`, name, val) + } + + for name, val := range KconfigString { + fmt.Fprintf(kc, ` +config %s + string + default "%s" +`, name, val) + } + + for name, val := range KconfigHex { + fmt.Fprintf(kc, ` +config %s + hex + default 0x%x +`, name, val) + } + + for name, val := range KconfigInt { + fmt.Fprintf(kc, ` +config %s + int + default %d +`, name, val) + } + + fmt.Fprintf(kc, "endif\n") + + dsdt := Create(ctx, "dsdt.asl") + defer dsdt.Close() + + dsdt.WriteString( + `DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" +`) + + for _, x := range DSDTIncludes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t#include <%s>\n", x.File) + } + + dsdt.WriteString(` + Scope (\_SB) { + Device (PCI0) + { +`) + /* FIXME: use scoping at another level. */ + for _, x := range DSDTPCI0Includes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) + } + dsdt.WriteString( + ` } + } +} +`) + +} diff --git a/util/autoport/root.go b/util/autoport/root.go new file mode 100644 index 0000000..9a32427 --- /dev/null +++ b/util/autoport/root.go @@ -0,0 +1,28 @@ +package main + +import "fmt" + +var supportedPCIDevices map[uint32]PCIDevice = map[uint32]PCIDevice{} +var PCIMap map[PCIAddr]PCIDevData = map[PCIAddr]PCIDevData{} + +func ScanRoot(ctx Context) { + for _, pciDev := range ctx.InfoSource.GetPCIList() { + PCIMap[pciDev.PCIAddr] = pciDev + } + for _, pciDev := range ctx.InfoSource.GetPCIList() { + vendevid := (uint32(pciDev.PCIDevID) << 16) | uint32(pciDev.PCIVenID) + + dev, ok := supportedPCIDevices[vendevid] + if !ok { + fmt.Printf("Unsupported PCI device %04x:%04x\n", + pciDev.PCIVenID, pciDev.PCIDevID) + continue + } + dev.Scan(ctx, pciDev) + } +} + +func RegisterPCI(VenID uint16, DevID uint16, dev PCIDevice) { + vendevid := (uint32(DevID) << 16) | uint32(VenID) + supportedPCIDevices[vendevid] = dev +} diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go new file mode 100644 index 0000000..ba4ec04 --- /dev/null +++ b/util/autoport/sandybridge.go @@ -0,0 +1,112 @@ +package main + +type sandybridgemc struct { + variant string +} + +func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { + DevTree = DevTreeNode{ + Chip: "northbridge/intel/sandybridge", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "gpu_dp_d_hotplug": "0x06", + "gpu_panel_port_select": "0", + "gpu_panel_power_cycle_delay": "5", + "gpu_panel_power_up_delay": "300", + "gpu_panel_power_down_delay": "300", + "gpu_panel_power_backlight_on_delay": "2000", + "gpu_panel_power_backlight_off_delay": "2000", + "gfx.use_spread_spectrum_clock": "1", + "gfx.lvds_dual_channel": "0", + "gfx.link_frequency_270_mhz": "1", + "gfx.lvds_num_lanes": "4", + "gpu_cpu_backlight": "0x1155", + "gpu_pch_backlight": "0x06100610", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_rPGA989", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + + { + Chip: "cpu/intel/model_206ax", + Registers: map[string]string{ + /* FIXME: hardcoded. */ + "pstate_coord_type": "0xfe", + "c1_acpower": "1", + "c2_acpower": "3", + "c3_acpower": "5", + "c1_battery": "1", + "c2_battery": "3", + "c3_battery": "5", + }, + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0xacac, + Disabled: true, + }, + }, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + MissingParent: "pcibus0", + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr:PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr:PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME: Move part to northbridge? */ + /* FIXME: some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool[i.variant+"BRIDGE_LVDS"] = true + + KconfigBool["VGA"] = true + KconfigBool["EARLY_CBMEM_INIT"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true + KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE_NATIVE"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigBool["HAVE_IFD_BIN"] = false + KconfigBool["HAVE_ME_BIN"] = false + + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 8 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_206ax/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/sandybridge/acpi/sandybridge.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0154, sandybridgemc{variant:"IVY"}) + RegisterPCI(0x8086, 0x0166, GenericVGA{GenericPCI{Comment:"VGA controller"}}) +}

1 0

Patch set updated for coreboot: db68ea0 superio/common/conf_mode.c: Don't hide pointers with typedefs
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7137 -gerrit commit db68ea0d0e8207b18156109e6a140e7e34f8312a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 21 07:51:24 2014 +1100 superio/common/conf_mode.c: Don't hide pointers with typedefs Change-Id: Ia1bbf2f885acf601b8a8360a7cd72819f70ef6a6 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/superio/conf_mode.h | 10 +++++----- src/superio/common/conf_mode.c | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h index c49cae7..9f7e3e6 100644 --- a/src/include/superio/conf_mode.h +++ b/src/include/superio/conf_mode.h @@ -24,11 +24,11 @@ #include <device/pnp.h> /* Common enter/exit implementations */ -void pnp_enter_conf_mode_55(device_t dev); -void pnp_enter_conf_mode_8787(device_t dev); -void pnp_exit_conf_mode_aa(device_t dev); -void pnp_enter_conf_mode_870155aa(device_t dev); -void pnp_exit_conf_mode_0202(device_t dev); +void pnp_enter_conf_mode_55(struct device *dev); +void pnp_enter_conf_mode_8787(struct device *dev); +void pnp_exit_conf_mode_aa(struct device *dev); +void pnp_enter_conf_mode_870155aa(struct device *dev); +void pnp_exit_conf_mode_0202(struct device *dev); extern const struct pnp_mode_ops pnp_conf_mode_55_aa; extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index f3e6277..271d4ef 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -23,23 +23,23 @@ /* Common enter/exit implementations */ -void pnp_enter_conf_mode_55(device_t dev) +void pnp_enter_conf_mode_55(struct device *dev) { outb(0x55, dev->path.pnp.port); } -void pnp_enter_conf_mode_8787(device_t dev) +void pnp_enter_conf_mode_8787(struct device *dev) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } -void pnp_exit_conf_mode_aa(device_t dev) +void pnp_exit_conf_mode_aa(struct device *dev) { outb(0xaa, dev->path.pnp.port); } -void pnp_enter_conf_mode_870155aa(device_t dev) +void pnp_enter_conf_mode_870155aa(struct device *dev) { outb(0x87, dev->path.pnp.port); outb(0x01, dev->path.pnp.port); @@ -51,7 +51,7 @@ void pnp_enter_conf_mode_870155aa(device_t dev) outb(0x55, dev->path.pnp.port); } -void pnp_exit_conf_mode_0202(device_t dev) +void pnp_exit_conf_mode_0202(struct device *dev) { outb(0x02, dev->path.pnp.port); outb(0x02, dev->path.pnp.port + 1);

1 0

Patch set updated for coreboot: 5e38d77 superio: Use 'pnp_devfn_t' over 'device_t' in romstage component
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6231 -gerrit commit 5e38d777093dacdb43966ec0f6ee538d6d08a2f2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 20:26:25 2014 +1000 superio: Use 'pnp_devfn_t' over 'device_t' in romstage component The romstage component of Super I/O support is in fact written around passing a lower and upper half packed integer. We currently have two typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of 'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the ramstage context and so is really a conflicting definition. This helps solve problems down the road to having the 'real' 'device_t' definition usable in romstage later. This follows on from the rational given in: c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/common/early_serial.c | 6 +++--- src/superio/fintek/common/fintek.h | 2 +- src/superio/intel/i3100/early_serial.c | 8 ++++---- src/superio/ite/common/early_serial.c | 16 ++++++++-------- src/superio/ite/common/ite.h | 10 +++++----- src/superio/ite/it8661f/early_serial.c | 10 +++++----- src/superio/ite/it8661f/it8661f.h | 2 +- src/superio/ite/it8671f/early_serial.c | 2 +- src/superio/ite/it8671f/it8671f.h | 2 +- src/superio/ite/it8718f/early_serial.c | 2 +- src/superio/ite/it8718f/it8718f.h | 2 +- src/superio/ite/it8772f/early_init.c | 16 ++++++++-------- src/superio/ite/it8772f/it8772f.h | 12 ++++++------ src/superio/nsc/pc8374/early_init.c | 2 +- src/superio/nsc/pc87309/early_serial.c | 2 +- src/superio/nsc/pc87309/pc87309.h | 2 +- src/superio/nsc/pc87351/early_serial.c | 2 +- src/superio/nsc/pc87360/early_serial.c | 2 +- src/superio/nsc/pc87366/early_serial.c | 2 +- src/superio/nsc/pc87392/early_serial.c | 2 +- src/superio/nsc/pc87417/early_init.c | 6 +++--- src/superio/nsc/pc87417/early_serial.c | 4 ++-- src/superio/nsc/pc87417/pc87417.h | 4 ++-- src/superio/nsc/pc87427/early_init.c | 6 +++--- src/superio/nsc/pc97317/early_serial.c | 2 +- src/superio/nuvoton/common/early_serial.c | 6 +++--- src/superio/nuvoton/common/nuvoton.h | 2 +- src/superio/nuvoton/nct5104d/early_init.c | 6 +++--- src/superio/nuvoton/nct5104d/nct5104d.h | 2 +- src/superio/serverengines/pilot/early_init.c | 2 +- src/superio/serverengines/pilot/early_serial.c | 8 ++++---- src/superio/serverengines/pilot/pilot.h | 10 +++++----- src/superio/smsc/fdc37m60x/early_serial.c | 2 +- src/superio/smsc/kbc1100/early_init.c | 8 ++++---- src/superio/smsc/kbc1100/kbc1100.h | 2 +- src/superio/smsc/lpc47b272/early_serial.c | 6 +++--- src/superio/smsc/lpc47b397/early_serial.c | 6 +++--- src/superio/smsc/lpc47m10x/early_serial.c | 6 +++--- src/superio/smsc/lpc47m15x/early_serial.c | 6 +++--- src/superio/smsc/lpc47m15x/lpc47m15x.h | 2 +- src/superio/smsc/lpc47n217/early_serial.c | 10 +++++----- src/superio/smsc/lpc47n227/early_serial.c | 10 +++++----- src/superio/smsc/sch4037/sch4037_early_init.c | 6 +++--- src/superio/smsc/sio1036/sio1036.h | 2 +- src/superio/smsc/sio1036/sio1036_early_init.c | 8 ++++---- src/superio/smsc/smscsuperio/early_serial.c | 6 +++--- src/superio/smsc/smscsuperio/smscsuperio.h | 2 +- src/superio/winbond/common/early_serial.c | 6 +++--- src/superio/winbond/common/winbond.h | 2 +- src/superio/winbond/w83627dhg/early_serial.c | 8 ++++---- src/superio/winbond/w83627dhg/w83627dhg.h | 8 ++++---- src/superio/winbond/w83627ehg/early_serial.c | 4 ++-- src/superio/winbond/w83627ehg/w83627ehg.h | 4 ++-- src/superio/winbond/w83627hf/early_init.c | 6 +++--- src/superio/winbond/w83627hf/early_serial.c | 8 ++++---- src/superio/winbond/w83627hf/w83627hf.h | 4 ++-- src/superio/winbond/w83627thg/w83627thg.h | 6 +++--- src/superio/winbond/w83697hf/early_serial.c | 8 ++++---- src/superio/winbond/w83697hf/w83697hf.h | 4 ++-- src/superio/winbond/w83977f/early_serial.c | 6 +++--- src/superio/winbond/w83977tf/early_serial.c | 6 +++--- 61 files changed, 162 insertions(+), 162 deletions(-) diff --git a/src/superio/fintek/common/early_serial.c b/src/superio/fintek/common/early_serial.c index d74b786..4433d11 100644 --- a/src/superio/fintek/common/early_serial.c +++ b/src/superio/fintek/common/early_serial.c @@ -46,7 +46,7 @@ #define FINTEK_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_ENTRY_KEY, port); @@ -54,14 +54,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void fintek_enable_serial(device_t dev, u16 iobase) +void fintek_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h index a08cf92..1bc308b 100644 --- a/src/superio/fintek/common/fintek.h +++ b/src/superio/fintek/common/fintek.h @@ -24,6 +24,6 @@ #include <arch/io.h> #include <stdint.h> -void fintek_enable_serial(device_t dev, u16 iobase); +void fintek_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_FINTEK_COMMON_ROMSTAGE_H */ diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..96bb550 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include "i3100.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -29,7 +29,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb(0x86, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -38,14 +38,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +static void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +static void i3100_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index 73354d4..a57c047 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -33,14 +33,14 @@ #define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ /* Helper procedure */ -static void ite_sio_write(device_t dev, u8 reg, u8 value) +static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value) { pnp_set_logical_device(dev); pnp_write_config(dev, reg, value); } /* Enable configuration */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -51,12 +51,12 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02); } -void ite_reg_write(device_t dev, u8 reg, u8 value) +void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value) { pnp_enter_conf_state(dev); ite_sio_write(dev, reg, value); @@ -71,13 +71,13 @@ void ite_reg_write(device_t dev, u8 reg, u8 value) * ITE_UART_CLK_PREDIVIDE_24 * ITE_UART_CLK_PREDIVIDE_48 (default) */ -void ite_conf_clkin(device_t dev, u8 predivide) +void ite_conf_clkin(pnp_devfn_t dev, u8 predivide) { ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); } /* Bring up early serial debugging output before the RAM is initialized. */ -void ite_enable_serial(device_t dev, u16 iobase) +void ite_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); @@ -101,7 +101,7 @@ void ite_enable_serial(device_t dev, u16 iobase) * and pass: GPIO_DEV */ -void ite_enable_3vsbsw(device_t dev) +void ite_enable_3vsbsw(pnp_devfn_t dev) { u8 tmp; pnp_enter_conf_state(dev); @@ -118,7 +118,7 @@ void ite_enable_3vsbsw(device_t dev) * and pass: GPIO_DEV */ -void ite_kill_watchdog(device_t dev) +void ite_kill_watchdog(pnp_devfn_t dev) { pnp_enter_conf_state(dev); ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00); diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index 5389f14..c732664 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -27,12 +27,12 @@ #define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */ #define ITE_UART_CLK_PREDIVIDE_24 0x01 -void ite_conf_clkin(device_t dev, u8 predivide); -void ite_enable_serial(device_t dev, u16 iobase); +void ite_conf_clkin(pnp_devfn_t dev, u8 predivide); +void ite_enable_serial(pnp_devfn_t dev, u16 iobase); /* Some boards need to init wdt+gpio's very early */ -void ite_reg_write(device_t dev, u8 reg, u8 value); -void ite_enable_3vsbsw(device_t dev); -void ite_kill_watchdog(device_t dev); +void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); +void ite_enable_3vsbsw(pnp_devfn_t dev); +void ite_kill_watchdog(pnp_devfn_t dev); #endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */ diff --git a/src/superio/ite/it8661f/early_serial.c b/src/superio/ite/it8661f/early_serial.c index 7373f71..19d60b1 100644 --- a/src/superio/ite/it8661f/early_serial.c +++ b/src/superio/ite/it8661f/early_serial.c @@ -26,7 +26,7 @@ /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { int i; u16 port = dev >> 8; @@ -42,7 +42,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb(init_values[i], port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { pnp_write_config(dev, IT8661F_REG_CC, (1 << 1)); } @@ -55,21 +55,21 @@ static void pnp_exit_ext_func_mode(device_t dev) * * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved. */ -static void it8661f_enable_logical_devices(device_t dev) +static void it8661f_enable_logical_devices(pnp_devfn_t dev) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, IT8661F_REG_LDE, 0x1f); pnp_exit_ext_func_mode(dev); } -static void it8661f_set_clkin(device_t dev, u8 clkin) +static void it8661f_set_clkin(pnp_devfn_t dev, u8 clkin) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1)); pnp_exit_ext_func_mode(dev); } -void it8661f_enable_serial(device_t dev, u16 iobase) +void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/ite/it8661f/it8661f.h b/src/superio/ite/it8661f/it8661f.h index 045a54c..297dea3 100644 --- a/src/superio/ite/it8661f/it8661f.h +++ b/src/superio/ite/it8661f/it8661f.h @@ -52,6 +52,6 @@ static const u8 init_values[] = { 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -void it8661f_enable_serial(device_t dev, u16 iobase); +void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_ITE_IT8661F_H */ diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c index 9f35b8a..89feb5f 100644 --- a/src/superio/ite/it8671f/early_serial.c +++ b/src/superio/ite/it8671f/early_serial.c @@ -89,7 +89,7 @@ void it8671f_48mhz_clkin(void) } /* Enable the serial port(s). */ -void it8671f_enable_serial(device_t dev, u16 iobase) +void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase) { it8671f_enter_conf(); diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h index c3865ff..90f1481 100644 --- a/src/superio/ite/it8671f/it8671f.h +++ b/src/superio/ite/it8671f/it8671f.h @@ -34,6 +34,6 @@ #define IT8671F_KBCM 0x06 /* PS/2 mouse */ void it8671f_48mhz_clkin(void); -void it8671f_enable_serial(device_t dev, u16 iobase); +void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_ITE_IT8671F__H */ diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index 166c856..563132a 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -27,7 +27,7 @@ * mechanism. It lives in the GPIO LDN. However, register 0xEF is not * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. */ -void it8718f_disable_reboot(device_t dev) +void it8718f_disable_reboot(pnp_devfn_t dev) { ite_reg_write(dev, 0xEF, 0x7E); } diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 61c75cf..c0a79c2 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -35,6 +35,6 @@ #define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ -void it8718f_disable_reboot(device_t dev); +void it8718f_disable_reboot(pnp_devfn_t dev); #endif /* SUPERIO_ITE_IT8718F_H */ diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c index 1ae80c8..55e06f7 100644 --- a/src/superio/ite/it8772f/early_init.c +++ b/src/superio/ite/it8772f/early_init.c @@ -26,8 +26,8 @@ /* NOTICE: This file is deprecated, use ite/common instead */ /* RAMstage equiv */ -/* u8 pnp_read_config(device_t dev, u8 reg) */ -u8 it8772f_sio_read(device_t dev, u8 reg) +/* u8 pnp_read_config(pnp_devfn_t dev, u8 reg) */ +u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg) { u16 port = dev >> 8; @@ -36,8 +36,8 @@ u8 it8772f_sio_read(device_t dev, u8 reg) } /* RAMstage equiv */ -/* void pnp_write_config(device_t dev, u8 reg, u8 value) */ -void it8772f_sio_write(device_t dev, u8 reg, u8 value) +/* void pnp_write_config(pnp_devfn_t dev, u8 reg, u8 value) */ +void it8772f_sio_write(pnp_devfn_t dev, u8 reg, u8 value) { u16 port = dev >> 8; @@ -45,7 +45,7 @@ void it8772f_sio_write(device_t dev, u8 reg, u8 value) outb(value, port + 1); } -void it8772f_enter_conf(device_t dev) +void it8772f_enter_conf(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -55,13 +55,13 @@ void it8772f_enter_conf(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -void it8772f_exit_conf(device_t dev) +void it8772f_exit_conf(pnp_devfn_t dev) { it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02); } /* Set AC resume to be up to the Southbridge */ -void it8772f_ac_resume_southbridge(device_t dev) +void it8772f_ac_resume_southbridge(pnp_devfn_t dev) { it8772f_enter_conf(dev); it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); @@ -70,7 +70,7 @@ void it8772f_ac_resume_southbridge(device_t dev) } /* Configure a set of GPIOs */ -void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity, +void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable) { set--; /* Set 1 is offset 0 */ diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 09eeb8f..43e7d4c 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -106,10 +106,10 @@ #include <arch/io.h> #include <stdint.h> -u8 it8772f_sio_read(device_t dev, u8 reg); -void it8772f_sio_write(device_t dev, u8 reg, u8 value); -void it8772f_ac_resume_southbridge(device_t dev); -void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity, +u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg); +void it8772f_sio_write(pnp_devfn_t dev, u8 reg, u8 value); +void it8772f_ac_resume_southbridge(pnp_devfn_t dev); +void it8772f_gpio_setup(pnp_devfn_t dev, int set, u8 select, u8 polarity, u8 pullup, u8 output, u8 enable); /* FIXME: should be static so will be removed later.. */ @@ -117,7 +117,7 @@ void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity, #define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -void it8772f_enter_conf(device_t dev); -void it8772f_exit_conf(device_t dev); +void it8772f_enter_conf(pnp_devfn_t dev); +void it8772f_exit_conf(pnp_devfn_t dev); #endif /* SUPERIO_ITE_IT8772F_H */ diff --git a/src/superio/nsc/pc8374/early_init.c b/src/superio/nsc/pc8374/early_init.c index d3f601d..a5e9b95 100644 --- a/src/superio/nsc/pc8374/early_init.c +++ b/src/superio/nsc/pc8374/early_init.c @@ -46,7 +46,7 @@ static void pc8374_enable(u16 iobase, u8 *init) } } -static void pc8374_enable_dev(device_t dev, u16 iobase) +static void pc8374_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87309/early_serial.c b/src/superio/nsc/pc87309/early_serial.c index 6e48e0c..da0d5d7 100644 --- a/src/superio/nsc/pc87309/early_serial.c +++ b/src/superio/nsc/pc87309/early_serial.c @@ -22,7 +22,7 @@ #include <device/pnp_def.h> #include "pc87309.h" -void pc87309_enable_serial(device_t dev, u16 iobase) +void pc87309_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h index 5f39b6e..513576e 100644 --- a/src/superio/nsc/pc87309/pc87309.h +++ b/src/superio/nsc/pc87309/pc87309.h @@ -34,6 +34,6 @@ #include <arch/io.h> #include <stdint.h> -void pc87309_enable_serial(device_t dev, u16 iobase); +void pc87309_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87351/early_serial.c b/src/superio/nsc/pc87351/early_serial.c index c34538f..a31f79c 100644 --- a/src/superio/nsc/pc87351/early_serial.c +++ b/src/superio/nsc/pc87351/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87351.h" -static void pc87351_enable_serial(device_t dev, u16 iobase) +static void pc87351_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87360/early_serial.c b/src/superio/nsc/pc87360/early_serial.c index da4abdb..3deac3b 100644 --- a/src/superio/nsc/pc87360/early_serial.c +++ b/src/superio/nsc/pc87360/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87360.h" -static void pc87360_enable_serial(device_t dev, u16 iobase) +static void pc87360_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87366/early_serial.c b/src/superio/nsc/pc87366/early_serial.c index e173afd..e663df6 100644 --- a/src/superio/nsc/pc87366/early_serial.c +++ b/src/superio/nsc/pc87366/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87366.h" -static void pc87366_enable_serial(device_t dev, u16 iobase) +static void pc87366_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87392/early_serial.c b/src/superio/nsc/pc87392/early_serial.c index 6e85fb9..f1e5716 100644 --- a/src/superio/nsc/pc87392/early_serial.c +++ b/src/superio/nsc/pc87392/early_serial.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include "pc87392.h" -static void pc87392_enable_serial(device_t dev, u16 iobase) +static void pc87392_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index d1870f9..42f8cd1 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "pc87417.h" -static void pc87417_disable_dev(device_t dev) +static void pc87417_disable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87417_enable_dev(device_t dev, u16 iobase) +static void pc87417_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -37,7 +37,7 @@ static void pc87417_enable_dev(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -static void xbus_cfg(device_t dev) +static void xbus_cfg(pnp_devfn_t dev) { u8 i, data; u16 xbus_index; diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c index 33bae7e..42ba941 100644 --- a/src/superio/nsc/pc87417/early_serial.c +++ b/src/superio/nsc/pc87417/early_serial.c @@ -23,7 +23,7 @@ #include <arch/io.h> #include "pc87417.h" -void pc87417_enable_serial(device_t dev, u16 iobase) +void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -31,7 +31,7 @@ void pc87417_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -void pc87417_enable_dev(device_t dev) +void pc87417_enable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 1); diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index 73c1fbc..e7d5413 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -115,8 +115,8 @@ #define PC87417_XWBCNF 0x16 #if defined(__PRE_RAM__) -void pc87417_enable_serial(device_t dev, u16 iobase); -void pc87417_enable_dev(device_t dev); +void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase); +void pc87417_enable_dev(pnp_devfn_t dev); #endif #endif diff --git a/src/superio/nsc/pc87427/early_init.c b/src/superio/nsc/pc87427/early_init.c index 6df1b9f..adaa868 100644 --- a/src/superio/nsc/pc87427/early_init.c +++ b/src/superio/nsc/pc87427/early_init.c @@ -22,13 +22,13 @@ #include <arch/io.h> #include "pc87427.h" -static void pc87427_disable_dev(device_t dev) +static void pc87427_disable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87427_enable_dev(device_t dev, u16 iobase) +static void pc87427_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -36,7 +36,7 @@ static void pc87427_enable_dev(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -static void xbus_cfg(device_t dev) +static void xbus_cfg(pnp_devfn_t dev) { u8 i, data; u16 xbus_index; diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c index 0c21561..ad43010 100644 --- a/src/superio/nsc/pc97317/early_serial.c +++ b/src/superio/nsc/pc97317/early_serial.c @@ -25,7 +25,7 @@ #define PM_BASE 0xe8 /* The PC97317 needs clocks to be set up before the serial port will operate. */ -static void pc97317_enable_serial(device_t dev, u16 iobase) +static void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase) { /* Set base address of power management unit. */ pnp_set_logical_device(PM_DEV); diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 1cbcee8..dbb0d13 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -49,7 +49,7 @@ /* Enable configuration: pass entry key '0x87' into index port dev * two times. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_ENTRY_KEY, port); @@ -57,14 +57,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void nuvoton_enable_serial(device_t dev, u16 iobase) +void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h index e9e8d4b..43d80a9 100644 --- a/src/superio/nuvoton/common/nuvoton.h +++ b/src/superio/nuvoton/common/nuvoton.h @@ -25,6 +25,6 @@ #include <arch/io.h> #include <stdint.h> -void nuvoton_enable_serial(device_t dev, u16 iobase); +void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_NUVOTON_COMMON_ROMSTAGE_H */ diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c index c9a408e..96fac19 100644 --- a/src/superio/nuvoton/nct5104d/early_init.c +++ b/src/superio/nuvoton/nct5104d/early_init.c @@ -28,7 +28,7 @@ /* Enable configuration: pass entry key '0x87' into index port dev * two times. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_ENTRY_KEY, port); @@ -36,14 +36,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_EXIT_KEY, port); } /* Route UARTD to pins 41-48 */ -void nct5104d_enable_uartd(device_t dev) +void nct5104d_enable_uartd(pnp_devfn_t dev) { u8 tmp; u16 port = dev >> 8; diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index e4dcf38..5b12cc5 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -48,6 +48,6 @@ #define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V) #define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V) -void nct5104d_enable_uartd(device_t dev); +void nct5104d_enable_uartd(pnp_devfn_t dev); #endif /* SUPERIO_NUVOTON_NCT5104D_H */ diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 002210f..6635645 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -32,7 +32,7 @@ * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ -void pilot_early_init(device_t dev) +void pilot_early_init(pnp_devfn_t dev) { u16 port = dev >> 8; diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 82e124c..3e99ef4 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -26,20 +26,20 @@ #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x5A, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xA5, port); } /* Serial config is a fairly standard procedure. */ -void pilot_enable_serial(device_t dev, u16 iobase) +void pilot_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -48,7 +48,7 @@ void pilot_enable_serial(device_t dev, u16 iobase) pnp_exit_ext_func_mode(dev); } -void pilot_disable_serial(device_t dev) +void pilot_disable_serial(pnp_devfn_t dev) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index e19cf37..cffa258 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -31,12 +31,12 @@ #define PILOT_LD7 0x07 /* Logical device 7 */ /* should not expose these however early_init needs love */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); -void pilot_early_init(device_t dev); +void pilot_early_init(pnp_devfn_t dev); -void pilot_enable_serial(device_t dev, u16 iobase); -void pilot_disable_serial(device_t dev); +void pilot_enable_serial(pnp_devfn_t dev, u16 iobase); +void pilot_disable_serial(pnp_devfn_t dev); #endif /* SUPERIO_SERVERENGINES_PILOT_PILOT_H */ diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c index 38cb0f8..80258a9 100644 --- a/src/superio/smsc/fdc37m60x/early_serial.c +++ b/src/superio/smsc/fdc37m60x/early_serial.c @@ -46,7 +46,7 @@ static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) } /* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ -static void fdc37m60x_enable_serial(device_t dev, u16 iobase) +static void fdc37m60x_enable_serial(pnp_devfn_t dev, u16 iobase) { /* (1) Enter the configuration state. */ outb(0x55, FDC37M60X_CONFIGURATION_PORT); diff --git a/src/superio/smsc/kbc1100/early_init.c b/src/superio/smsc/kbc1100/early_init.c index d075f9c..bd42288 100644 --- a/src/superio/smsc/kbc1100/early_init.c +++ b/src/superio/smsc/kbc1100/early_init.c @@ -26,19 +26,19 @@ #include "kbc1100.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void kbc1100_early_serial(device_t dev, u16 iobase) +void kbc1100_early_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); @@ -50,7 +50,7 @@ void kbc1100_early_serial(device_t dev, u16 iobase) void kbc1100_early_init(u16 port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV (port, KBC1100_KBC); pnp_enter_conf_state(dev); diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h index 2b588f9..ec24dd3 100644 --- a/src/superio/smsc/kbc1100/kbc1100.h +++ b/src/superio/smsc/kbc1100/kbc1100.h @@ -36,7 +36,7 @@ #define KBC1100_EC1 0x0D /* EC Channel 1 */ #define KBC1100_EC2 0x0E /* EC Channel 2 */ -void kbc1100_early_serial(device_t dev, u16 iobase); +void kbc1100_early_serial(pnp_devfn_t dev, u16 iobase); void kbc1100_early_init(u16 port); #endif /* SUPERIO_SMSC_KBC1100_H */ diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c index b2f0d1b..3624df2 100644 --- a/src/superio/smsc/lpc47b272/early_serial.c +++ b/src/superio/smsc/lpc47b272/early_serial.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "lpc47b272.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47b272_enable_serial(device_t dev, u16 iobase) +static void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c index 31d515b..953cd4b 100644 --- a/src/superio/smsc/lpc47b397/early_serial.c +++ b/src/superio/smsc/lpc47b397/early_serial.c @@ -23,19 +23,19 @@ #include <arch/io.h> #include "lpc47b397.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void lpc47b397_enable_serial(device_t dev, u16 iobase) +static void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index fc6efb9..1174120 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -21,13 +21,13 @@ #include <arch/io.h> #include "lpc47m10x.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -40,7 +40,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47m10x_enable_serial(device_t dev, u16 iobase) +static void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c index 5686f52..0a42ad3 100644 --- a/src/superio/smsc/lpc47m15x/early_serial.c +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -25,19 +25,19 @@ #include "lpc47m15x.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void lpc47m15x_enable_serial(device_t dev, u16 iobase) +void lpc47m15x_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m15x/lpc47m15x.h b/src/superio/smsc/lpc47m15x/lpc47m15x.h index 32cff48..ee9e9c6 100644 --- a/src/superio/smsc/lpc47m15x/lpc47m15x.h +++ b/src/superio/smsc/lpc47m15x/lpc47m15x.h @@ -34,6 +34,6 @@ #include <arch/io.h> #include <stdint.h> -void lpc47m15x_enable_serial(device_t dev, u16 iobase); +void lpc47m15x_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_SMSC_LPC47M15X_H */ diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index 451628a..7405f32 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -24,13 +24,13 @@ #include <assert.h> #include "lpc47n217.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n217_pnp_set_iobase(pnp_devfn_t dev, u16 iobase) { /* LPC47N217 requires base ports to be a multiple of 4. */ ASSERT(!(iobase & 0x3)); @@ -74,7 +74,7 @@ static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -static void lpc47n217_pnp_set_enable(device_t dev, int enable) +static void lpc47n217_pnp_set_enable(pnp_devfn_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -109,7 +109,7 @@ static void lpc47n217_pnp_set_enable(device_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n217_enable_serial(device_t dev, u16 iobase) +static void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index 4aea7c5..64a6d84 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "lpc47n227.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -41,7 +41,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -static void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n227_pnp_set_iobase(pnp_devfn_t dev, u16 iobase) { /* LPC47N227 requires base ports to be a multiple of 4. */ /* it's not very useful to do an ASSERT here: if it trips, @@ -76,7 +76,7 @@ static void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -static void lpc47n227_pnp_set_enable(device_t dev, int enable) +static void lpc47n227_pnp_set_enable(pnp_devfn_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -111,7 +111,7 @@ static void lpc47n227_pnp_set_enable(device_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n227_enable_serial(device_t dev, u16 iobase) +static void lpc47n227_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c index 099e5f2..56af87a 100644 --- a/src/superio/smsc/sch4037/sch4037_early_init.c +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -24,13 +24,13 @@ #include "sch4037.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { unsigned port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { unsigned port = dev >> 8; outb(0xaa, port); @@ -38,7 +38,7 @@ static void pnp_exit_conf_state(device_t dev) void sch4037_early_init(unsigned port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV(port, SMSCSUPERIO_SP1); pnp_enter_conf_state(dev); diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index fa52a1a..ba7a932 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -29,6 +29,6 @@ #include <arch/io.h> #include <stdint.h> -void sio1036_enable_serial(device_t dev, u16 iobase); +void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_SMSC_1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 5f10230..b37e81b 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -24,13 +24,13 @@ #include "sio1036.h" -static inline void sio1036_enter_conf_state(device_t dev) +static inline void sio1036_enter_conf_state(pnp_devfn_t dev) { unsigned port = dev >> 8; outb(0x55, port); } -static inline void sio1036_exit_conf_state(device_t dev) +static inline void sio1036_exit_conf_state(pnp_devfn_t dev) { unsigned port = dev >> 8; outb(0xaa, port); @@ -39,7 +39,7 @@ static inline void sio1036_exit_conf_state(device_t dev) /* Detect SMSC SIO1036 LPC Debug Card status */ static u8 detect_sio1036_chip(unsigned port) { - device_t dev = PNP_DEV(port, SIO1036_SP1); + pnp_devfn_t dev = PNP_DEV(port, SIO1036_SP1); unsigned data; sio1036_enter_conf_state (dev); @@ -56,7 +56,7 @@ static u8 detect_sio1036_chip(unsigned port) }; } -void sio1036_enable_serial(device_t dev, u16 iobase) +void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase) { unsigned port = dev >> 8; diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index e2eea6d..c058ef5 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -29,14 +29,14 @@ #define SMSC_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(SMSC_ENTRY_KEY, port); } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(SMSC_EXIT_KEY, port); @@ -49,7 +49,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev The device to use. * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). */ -void smscsuperio_enable_serial(device_t dev, u16 iobase) +void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/smscsuperio/smscsuperio.h b/src/superio/smsc/smscsuperio/smscsuperio.h index 60a58e6..8a761ba 100644 --- a/src/superio/smsc/smscsuperio/smscsuperio.h +++ b/src/superio/smsc/smscsuperio/smscsuperio.h @@ -30,6 +30,6 @@ #define SMSCSUPERIO_SP1 4 /* Com1 */ #define SMSCSUPERIO_SP2 5 /* Com2 */ -void smscsuperio_enable_serial(device_t dev, u16 iobase); +void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_SMSC_SMSCSUPERIO_H */ diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_serial.c index 747cc45..fd51cd5 100644 --- a/src/superio/winbond/common/early_serial.c +++ b/src/superio/winbond/common/early_serial.c @@ -46,7 +46,7 @@ #define WINBOND_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(WINBOND_ENTRY_KEY, port); @@ -54,14 +54,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(WINBOND_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void winbond_enable_serial(device_t dev, u16 iobase) +void winbond_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 20eefc8..0f937c1 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -24,6 +24,6 @@ #include <arch/io.h> #include <stdint.h> -void winbond_enable_serial(device_t dev, u16 iobase); +void winbond_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_COMMON_ROMSTAGE_H */ diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index 67aaa93..83f8e34 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -24,14 +24,14 @@ #include <stdint.h> #include "w83627dhg.h" -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ void pnp_exit_ext_func_mode(device_t dev) * {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or * {RSTOUT3#, RSTOUT2#} or {SDA, SCL} */ -void w83627dhg_enable_i2c(device_t dev) +void w83627dhg_enable_i2c(pnp_devfn_t dev) { u8 val; @@ -56,7 +56,7 @@ void w83627dhg_enable_i2c(device_t dev) pnp_exit_ext_func_mode(dev); } -void w83627dhg_set_clksel_48(device_t dev) +void w83627dhg_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 08ea04f..c4ead34 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -52,9 +52,9 @@ /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); -void w83627dhg_enable_i2c(device_t dev); -void w83627dhg_set_clksel_48(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); +void w83627dhg_enable_i2c(pnp_devfn_t dev); +void w83627dhg_set_clksel_48(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627DHG_H */ diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 346d6cf..e052863 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -23,14 +23,14 @@ #include <device/pnp.h> #include "w83627ehg.h" -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 221de7b..3d6f56f 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,7 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627EHG_H */ diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c index db616ae..2e275e6 100644 --- a/src/superio/winbond/w83627hf/early_init.c +++ b/src/superio/winbond/w83627hf/early_init.c @@ -25,14 +25,14 @@ #include <device/pnp.h> #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -43,7 +43,7 @@ static void pnp_exit_ext_func_mode(device_t dev) * work around a limitation of ROMCC where we can no make early_serial.c into * link-time symbols and #include early_serial.c. */ -void w83627hf_set_clksel_48(device_t dev) +void w83627hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c index bc251a6..694a3fe 100644 --- a/src/superio/winbond/w83627hf/early_serial.c +++ b/src/superio/winbond/w83627hf/early_serial.c @@ -24,14 +24,14 @@ #include <arch/io.h> #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -49,7 +49,7 @@ static void pnp_exit_ext_func_mode(device_t dev) * XXX: ROMCC - everything is inlined, no forwarding function prototypes * declarations are accepted. */ -void w83627hf_enable_serial(device_t dev, u16 iobase) +void w83627hf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -59,7 +59,7 @@ void w83627hf_enable_serial(device_t dev, u16 iobase) pnp_exit_ext_func_mode(dev); } -void w83627hf_set_clksel_48(device_t dev) +void w83627hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index bf7186e..6eeb62b 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -115,7 +115,7 @@ #include <arch/io.h> -void w83627hf_set_clksel_48(device_t dev); -void w83627hf_enable_serial(device_t dev, u16 iobase); +void w83627hf_set_clksel_48(pnp_devfn_t dev); +void w83627hf_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83627HF_H */ diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index ec857d3..8d85379 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -34,9 +34,9 @@ #define W83627THG_ACPI 10 #define W83627THG_HWM 11 /* Hardware monitor */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); -void w83627thg_set_clksel_48(device_t dev); +void w83627thg_set_clksel_48(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627THG_W83627THG_H */ diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 6c00b27..515fee9 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -22,20 +22,20 @@ #include <device/pnp_def.h> #include "w83697hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void w83697hf_set_clksel_48(device_t dev) +void w83697hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; @@ -47,7 +47,7 @@ void w83697hf_set_clksel_48(device_t dev) } /* Depreciated, use winbond_enable_serial() */ -void w83697hf_enable_serial(device_t dev, u16 iobase) +void w83697hf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index f711786..3bd1f44 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -34,9 +34,9 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ -void w83697hf_set_clksel_48(device_t); +void w83697hf_set_clksel_48(pnp_devfn_t); /* Depreciated, use winbond_enable_serial() */ -void w83697hf_enable_serial(device_t dev, u16 iobase); +void w83697hf_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83697HF_H */ diff --git a/src/superio/winbond/w83977f/early_serial.c b/src/superio/winbond/w83977f/early_serial.c index c572dcb..9b5785d 100644 --- a/src/superio/winbond/w83977f/early_serial.c +++ b/src/superio/winbond/w83977f/early_serial.c @@ -21,20 +21,20 @@ #include <arch/io.h> #include "w83977f.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83977f_enable_serial(device_t dev, u16 iobase) +static void w83977f_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83977tf/early_serial.c b/src/superio/winbond/w83977tf/early_serial.c index c016515..866d9f2 100644 --- a/src/superio/winbond/w83977tf/early_serial.c +++ b/src/superio/winbond/w83977tf/early_serial.c @@ -23,20 +23,20 @@ #include <arch/io.h> #include "w83977tf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83977tf_enable_serial(device_t dev, u16 iobase) +static void w83977tf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev);

1 0

New patch to review for coreboot: f8b3fc1 TEST
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7198 -gerrit commit f8b3fc15680f91d7a2afe1cca7559a64465e9352 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 23:33:22 2014 +1100 TEST Change-Id: I6f29b198569eb4834328d36ca8f69d6550ded4cf Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/agesa/00730F01/model_16_init.c | 2 +- src/cpu/amd/agesa/amd_late_init.c | 2 +- src/cpu/amd/agesa/family10/model_10_init.c | 2 +- src/cpu/amd/agesa/family12/model_12_init.c | 2 +- src/cpu/amd/agesa/family14/model_14_init.c | 2 +- src/cpu/amd/agesa/family15/model_15_init.c | 2 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +- src/cpu/amd/dualcore/amd_sibling.c | 6 +++--- src/cpu/amd/geode_gx1/geode_gx1_init.c | 2 +- src/cpu/amd/geode_gx2/geode_gx2_init.c | 2 +- src/cpu/amd/geode_lx/geode_lx_init.c | 2 +- src/cpu/amd/model_10xxx/fidvid.c | 28 ++++++++++++++-------------- src/cpu/amd/model_10xxx/init_cpus.c | 2 +- src/cpu/amd/model_10xxx/model_10xxx_init.c | 2 +- src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/cpu/amd/model_fxx/model_fxx_init.c | 10 ++++++---- src/cpu/amd/quadcore/amd_sibling.c | 6 +++--- src/cpu/amd/sc520/sc520.c | 14 +++++++------- 19 files changed, 47 insertions(+), 45 deletions(-) diff --git a/src/cpu/amd/agesa/00730F01/model_16_init.c b/src/cpu/amd/agesa/00730F01/model_16_init.c index 8053fd1..78cfc06 100644 --- a/src/cpu/amd/agesa/00730F01/model_16_init.c +++ b/src/cpu/amd/agesa/00730F01/model_16_init.c @@ -37,7 +37,7 @@ #include <cpu/amd/agesa/s3_resume.h> #endif -static void model_16_init(device_t dev) +static void model_16_init(struct device *dev) { printk(BIOS_DEBUG, "Model 16 Init.\n"); diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index cab03a3..97f5425 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -42,7 +42,7 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdinitlate); #if (NORTHBRIDGE_00700F00) || (NORTHBRIDGE_00730F01) - device_t dev; + struct device *dev; u32 value; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 6fbfd1a..d00a105 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -34,7 +34,7 @@ #define MCI_STATUS 0x401 -static void model_10_init(device_t dev) +static void model_10_init(struct device *dev) { printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n"); diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 635bd81..a2061e7 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -35,7 +35,7 @@ #define MCI_STATUS 0x401 -static void model_12_init(device_t dev) +static void model_12_init(struct device *dev) { printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n"); diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 60a88c7..ca250b9 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -36,7 +36,7 @@ #define MCI_STATUS 0x401 -static void model_14_init(device_t dev) +static void model_14_init(struct device *dev) { u32 i; msr_t msr; diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index a755e1c..c7fbd75 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> -static void model_15_init(device_t dev) +static void model_15_init(struct device *dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 64c78af..b888cf2 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -35,7 +35,7 @@ #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -static void model_15_init(device_t dev) +static void model_15_init(struct device *dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index ef31f96..07b92f5 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -34,7 +34,7 @@ #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -static void model_16_init(device_t dev) +static void model_16_init(struct device *dev) { printk(BIOS_DEBUG, "Model 16 Init.\n"); diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index d9942de..e2ad3a1 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -19,7 +19,7 @@ static int disable_siblings = !CONFIG_LOGICAL_CPUS; static int get_max_siblings(int nodes) { - device_t dev; + struct device *dev; int nodeid; int siblings=0; @@ -38,7 +38,7 @@ static int get_max_siblings(int nodes) static void enable_apic_ext_id(int nodes) { - device_t dev; + struct device *dev; int nodeid; //enable APIC_EXIT_ID all the nodes @@ -54,7 +54,7 @@ static void enable_apic_ext_id(int nodes) unsigned get_apicid_base(unsigned ioapic_num) { - device_t dev; + struct device *dev; int nodes; unsigned apicid_base; int siblings; diff --git a/src/cpu/amd/geode_gx1/geode_gx1_init.c b/src/cpu/amd/geode_gx1/geode_gx1_init.c index 8fbf507..4f08a1c 100644 --- a/src/cpu/amd/geode_gx1/geode_gx1_init.c +++ b/src/cpu/amd/geode_gx1/geode_gx1_init.c @@ -72,7 +72,7 @@ unsigned long addr; } #endif -static void geode_gx1_init(device_t dev) +static void geode_gx1_init(struct device *dev) { #if 0 gx1_cpu_setup(); diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c index b8f56db..43ac808 100644 --- a/src/cpu/amd/geode_gx2/geode_gx2_init.c +++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c @@ -15,7 +15,7 @@ static void vsm_end_post_smi(void) ); } -static void geode_gx2_init(device_t dev) +static void geode_gx2_init(struct device *dev) { printk(BIOS_DEBUG, "geode_gx2_init\n"); diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c index cd931a4..1024c00 100644 --- a/src/cpu/amd/geode_lx/geode_lx_init.c +++ b/src/cpu/amd/geode_lx/geode_lx_init.c @@ -37,7 +37,7 @@ static void vsm_end_post_smi(void) ".byte 0x0f, 0x38\n" "pop %ax\n"); } -static void geode_lx_init(device_t dev) +static void geode_lx_init(struct device *dev) { printk(BIOS_DEBUG, "geode_lx_init\n"); diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 4297c90..c0be3d0 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -134,7 +134,7 @@ static void enable_fid_change(u8 fid) { u32 dword; u32 nodes; - device_t dev; + struct device *dev; int i; nodes = get_nodes(); @@ -151,7 +151,7 @@ static void enable_fid_change(u8 fid) } } -static void applyBoostFIDOffset( device_t dev ) { +static void applyBoostFIDOffset( struct device *dev ) { // BKDG 2.4.2.8 // revision E only, but E is apparently not supported yet, therefore untested if ((cpuid_edx(0x80000007) & CPB_MASK) @@ -168,7 +168,7 @@ static void applyBoostFIDOffset( device_t dev ) { } } -static void enableNbPState1( device_t dev ) { +static void enableNbPState1( struct device *dev ) { u32 cpuRev = mctGetLogicalCPUID(0xFF); if (cpuRev & AMD_FAM10_C3) { u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); @@ -188,7 +188,7 @@ static void enableNbPState1( device_t dev ) { } } -static u8 setPStateMaxVal( device_t dev ) { +static u8 setPStateMaxVal( struct device *dev ) { u8 i,maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PS_REG_BASE + i); @@ -208,7 +208,7 @@ static u8 setPStateMaxVal( device_t dev ) { return maxpstate; } -static void dualPlaneOnly( device_t dev ) { +static void dualPlaneOnly( struct device *dev ) { // BKDG 2.4.2.7 u32 cpuRev = mctGetLogicalCPUID(0xFF); @@ -252,7 +252,7 @@ static int vidTo100uV(u8 vid) return voltage; } -static void setVSRamp(device_t dev) { +static void setVSRamp(struct device *dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] * If this field accepts 8 values between 10 and 500 us why * does page 324 say "BIOS should set this field to 001b." @@ -267,7 +267,7 @@ static void setVSRamp(device_t dev) { pci_write_config32(dev, 0xd8, dword); } -static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) +static void recalculateVsSlamTimeSettingOnCorePre(struct device *dev) { u8 pviModeFlag; u8 highVoltageVid, lowVoltageVid, bValue; @@ -443,7 +443,7 @@ static u32 power_up_down(int node, u8 procPkg) { } static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { - device_t dev = NODE_PCI(node, 3); + struct device *dev = NODE_PCI(node, 3); /* Program fields in Clock Power/Control register0 (F3xD4) */ @@ -467,7 +467,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { } -static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { +static void config_power_ctrl_misc_reg(struct device *dev,u32 cpuRev, u8 procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xA0); @@ -500,7 +500,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { pci_write_config32(dev, 0xA0, dword); } -static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { +static void config_nb_syn_ptr_adj(struct device *dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ @@ -522,7 +522,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { pci_write_config32(dev, 0xdc, dword); } -static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { +static void config_acpi_pwr_state_ctrl_regs(struct device *dev, u32 cpuRev, u8 procPkg) { /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ u32 dword; u32 c1= 1; @@ -582,7 +582,7 @@ static void prep_fid_change(void) { u32 dword; u32 nodes; - device_t dev; + struct device *dev; int i; /* This needs to be run before any Pstate changes are requested */ @@ -785,7 +785,7 @@ static u32 needs_NB_COF_VID_update(void) static u32 init_fidvid_core(u32 nodeid, u32 coreid) { - device_t dev; + struct device *dev; u32 vid_max; u32 fid_max = 0; u8 nb_cof_vid_update = needs_NB_COF_VID_update(); @@ -946,7 +946,7 @@ static void finalPstateChange(void) static void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; - device_t dev; + struct device *dev; u32 reg1fc; u32 dtemp; u32 nbvid; diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 10c0c8a..f6d2bd7 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -362,7 +362,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + struct device *device; device = NODE_PCI(nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_ColdR_Detect; diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c6cf64a..214b416 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -38,7 +38,7 @@ #define MCI_STATUS 0x401 -static void model_10xxx_init(device_t dev) +static void model_10xxx_init(struct device *dev) { u8 i; msr_t msr; diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 12d3a95..0dacc8d 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -310,7 +310,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + struct device *device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_INIT_Detect; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 260e83e..24e86dc 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -51,7 +51,7 @@ int is_e0_later_in_bsp(int nodeid) return !is_cpu_pre_e0(); } // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; + struct device *dev; dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 2)); if (!dev) return 0; @@ -73,7 +73,7 @@ int is_e0_later_in_bsp(int nodeid) int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + struct device *dev; dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 3)); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff00) == 0x40f00; @@ -228,7 +228,9 @@ static void init_ecc_memory(unsigned node_id) unsigned long basek; struct mtrr_state mtrr_state; - device_t f1_dev, f2_dev, f3_dev; + struct device *f1_dev; + struct device *f2_dev; + struct device *f3_dev; int enable_scrubbing; uint32_t dcl; @@ -456,7 +458,7 @@ static inline void k8_errata(void) } -static void model_fxx_init(device_t dev) +static void model_fxx_init(struct device *dev) { unsigned long i; msr_t msr; diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index d653a85..419af78 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -30,7 +30,7 @@ #include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/amdfam10_sysconf.h> -extern device_t get_node_pci(u32 nodeid, u32 fn); +extern struct device *get_node_pci(u32 nodeid, u32 fn); #if 0 static int first_time = 1; @@ -40,7 +40,7 @@ static int first_time = 1; static u32 get_max_siblings(u32 nodes) { - device_t dev; + struct device *dev; u32 nodeid; u32 siblings=0; @@ -60,7 +60,7 @@ static u32 get_max_siblings(u32 nodes) static void enable_apic_ext_id(u32 nodes) { - device_t dev; + struct device *dev; u32 nodeid; //enable APIC_EXIT_ID all the nodes diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index 808c33c..ac3ba4e 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -18,7 +18,7 @@ * set up basic things ... * PAR should NOT go here, as it might change with the mainboard. */ -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { unsigned long *l = (unsigned long *) 0xfffef088; int i; @@ -49,7 +49,7 @@ static void sc520_enable_resources(struct device *dev) { } -static void sc520_read_resources(device_t dev) +static void sc520_read_resources(struct device *dev) { struct resource* res; @@ -83,9 +83,9 @@ static const struct pci_driver cpu_driver __pci_driver = { .device = 0x3000 }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "%s\n", __func__); pci_tolm = find_pci_tolm(dev->link_list); @@ -130,7 +130,7 @@ static void pci_domain_set_resources(device_t dev) } #if 0 -void sc520_enable_resources(device_t dev) { +void sc520_enable_resources(struct device *dev) { printk(BIOS_SPEW, "%s\n", __func__); printk(BIOS_SPEW, "THIS IS FOR THE SC520 =============================\n"); @@ -165,12 +165,12 @@ static struct device_operations pci_domain_ops = { }; #if 0 -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, "cpu_bus_init\n"); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device *dev) { }

1 0

Patch set updated for coreboot: 687d5ff {arch, cpu, drivers, ec}: Don't hide pointers behind typedefs
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7146 -gerrit commit 687d5ffe717026ca97db01625dfbad1cb30ffc02 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 22 13:39:12 2014 +1100 {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/boot/acpi.c | 6 +++--- src/arch/x86/boot/mpspec.c | 6 ++++-- src/arch/x86/boot/smbios.c | 6 +++--- src/cpu/allwinner/a10/cpu.c | 8 ++++---- src/cpu/intel/ep80579/ep80579_init.c | 2 +- src/cpu/intel/fsp_model_206ax/acpi.c | 2 +- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 6 +++--- src/cpu/intel/fsp_model_406dx/acpi.c | 2 +- src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 6 +++--- src/cpu/intel/haswell/acpi.c | 2 +- src/cpu/intel/haswell/haswell_init.c | 4 ++-- src/cpu/intel/haswell/smmrelocate.c | 6 +++--- src/cpu/intel/hyperthreading/intel_sibling.c | 4 ++-- src/cpu/intel/model_1067x/model_1067x_init.c | 6 +++--- src/cpu/intel/model_106cx/model_106cx_init.c | 2 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_2065x/model_2065x_init.c | 8 ++++---- src/cpu/intel/model_206ax/acpi.c | 2 +- src/cpu/intel/model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/model_65x/model_65x_init.c | 2 +- src/cpu/intel/model_67x/model_67x_init.c | 2 +- src/cpu/intel/model_68x/model_68x_init.c | 2 +- src/cpu/intel/model_69x/model_69x_init.c | 2 +- src/cpu/intel/model_6bx/model_6bx_init.c | 2 +- src/cpu/intel/model_6dx/model_6dx_init.c | 2 +- src/cpu/intel/model_6ex/model_6ex_init.c | 2 +- src/cpu/intel/model_6fx/model_6fx_init.c | 2 +- src/cpu/intel/model_6xx/model_6xx_init.c | 2 +- src/cpu/intel/model_f0x/model_f0x_init.c | 2 +- src/cpu/intel/model_f1x/model_f1x_init.c | 2 +- src/cpu/intel/model_f2x/model_f2x_init.c | 2 +- src/cpu/intel/model_f3x/model_f3x_init.c | 2 +- src/cpu/intel/model_f4x/model_f4x_init.c | 2 +- src/cpu/intel/speedstep/acpi.c | 2 +- src/cpu/via/c3/c3_init.c | 2 +- src/cpu/via/c7/c7_init.c | 2 +- src/cpu/via/nano/nano_init.c | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 8 ++++---- src/cpu/x86/mp_init.c | 4 ++-- src/drivers/ati/ragexl/xlinit.c | 2 +- src/drivers/dec/21143/21143.c | 2 +- src/drivers/emulation/qemu/bochs.c | 2 +- src/drivers/emulation/qemu/cirrus.c | 2 +- src/drivers/generic/ioapic/ioapic.c | 8 ++++---- src/drivers/i2c/adm1026/adm1026.c | 6 +++--- src/drivers/i2c/adm1027/adm1027.c | 6 +++--- src/drivers/i2c/adt7463/adt7463.c | 4 ++-- src/drivers/i2c/at24rf08c/at24rf08c.c | 6 +++--- src/drivers/i2c/at24rf08c/lenovo_serials.c | 14 +++++++------- src/drivers/i2c/i2cmux/i2cmux.c | 4 ++-- src/drivers/i2c/i2cmux2/i2cmux2.c | 4 ++-- src/drivers/i2c/lm63/lm63.c | 4 ++-- src/drivers/i2c/rtd2132/rtd2132.c | 24 ++++++++++++------------ src/drivers/i2c/w83793/w83793.c | 18 +++++++++--------- src/drivers/i2c/w83795/w83795.c | 6 +++--- src/drivers/ics/954309/ics954309.c | 4 ++-- src/ec/compal/ene932/ec.c | 8 ++++---- src/ec/google/chromeec/ec_lpc.c | 8 ++++---- src/ec/kontron/it8516e/ec.c | 4 ++-- src/ec/lenovo/h8/h8.c | 4 ++-- src/ec/lenovo/pmh7/pmh7.c | 2 +- src/ec/quanta/ene_kb3940q/ec.c | 8 ++++---- src/ec/quanta/it8518/ec.c | 8 ++++---- src/ec/smsc/mec1308/ec.c | 2 +- 64 files changed, 149 insertions(+), 147 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index c3c946d..b506cb4 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -141,7 +141,7 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) unsigned long acpi_create_madt_lapics(unsigned long current) { - device_t cpu; + struct device *cpu; int index = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { @@ -278,7 +278,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) acpigen_set_current((char *) current); { #if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) - device_t dev; + struct device *dev; for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_fill_ssdt_generator) { dev->ops->acpi_fill_ssdt_generator(); @@ -708,7 +708,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt; acpi_mcfg_t *mcfg; acpi_madt_t *madt; - device_t dev; + struct device *dev; current = start; diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index d079d08..8049be4 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -166,7 +166,7 @@ void smp_write_processors(struct mp_config_table *mc) unsigned cpu_features; unsigned cpu_feature_flags; struct cpuid_result result; - device_t cpu; + struct device *cpu; boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; @@ -493,7 +493,9 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) struct drivers_generic_ioapic_config *ioapic_config; struct mp_config_table *mc; int isa_bus, pin, parentpin; - device_t dev, parent, oldparent; + struct device *dev; + struct device *parent; + struct device *oldparent; void *tmp, *v; int isaioapic = -1, have_fixed_entries; diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 724def3..64889f7 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -303,7 +303,7 @@ static int smbios_write_type11(unsigned long *current, int *handle) { struct smbios_type11 *t = (struct smbios_type11 *)*current; int len; - device_t dev; + struct device *dev; memset(t, 0, sizeof *t); t->type = SMBIOS_OEM_STRINGS; @@ -379,9 +379,9 @@ static int smbios_write_type127(unsigned long *current, int handle) return len; } -static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *current) +static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current) { - device_t dev; + struct device *dev; int len = 0; for(dev = tree; dev; dev = dev->next) { diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c index e0d4cdf..fac5730 100644 --- a/src/cpu/allwinner/a10/cpu.c +++ b/src/cpu/allwinner/a10/cpu.c @@ -11,7 +11,7 @@ #include <cbmem.h> -static void cpu_enable_resources(device_t dev) +static void cpu_enable_resources(struct device *dev) { ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10, CONFIG_DRAM_SIZE_MB << 10); @@ -20,12 +20,12 @@ static void cpu_enable_resources(device_t dev) */ } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { /* TODO: Check if anything else needs to be explicitly initialized */ } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -37,7 +37,7 @@ static struct device_operations cpu_ops = { .scan_bus = NULL, }; -static void a1x_cpu_enable_dev(device_t dev) +static void a1x_cpu_enable_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c index 433636d..2e66700 100644 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ b/src/cpu/intel/ep80579/ep80579_init.c @@ -28,7 +28,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> -static void ep80579_init(device_t dev) +static void ep80579_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/fsp_model_206ax/acpi.c b/src/cpu/intel/fsp_model_206ax/acpi.c index bf4a3ac..28aeb43 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi.c +++ b/src/cpu/intel/fsp_model_206ax/acpi.c @@ -89,7 +89,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_fsp_model_206ax_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index ebb3675..f5ca3f7 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -290,7 +290,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -313,7 +313,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -344,7 +344,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_206ax_init(device_t cpu) +static void model_206ax_init(struct device *cpu) { char processor_name[49]; struct cpuid_result cpuid_regs; diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index a3108ac..24f63cd 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -55,7 +55,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_model_406dx_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 3a36281..d892277 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -112,7 +112,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -135,7 +135,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -166,7 +166,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_406dx_init(device_t cpu) +static void model_406dx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 768511c..544436f 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -91,7 +91,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_haswell_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 68c7643..03935a0 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -597,7 +597,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { struct cpu_intel_haswell_config *conf; - device_t lapic; + struct device *lapic; msr_t msr; /* Find pointer to CPU configuration */ @@ -735,7 +735,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) } /* All CPUs including BSP will run the following function. */ -static void haswell_init(device_t cpu) +static void haswell_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 56d435c..d780beb 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -227,7 +227,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -237,7 +237,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -static void fill_in_relocation_params(device_t dev, +static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { u32 tseg_size; @@ -387,7 +387,7 @@ static int install_permanent_handler(int num_cpus, static int cpu_smm_setup(void) { - device_t dev; + struct device *dev; int num_cpus; msr_t msr; diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 16d8959..32c5e01 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -38,7 +38,7 @@ int intel_ht_sibling(void) return !!(lapicid() & (threads-1)); } -void intel_sibling_init(device_t cpu) +void intel_sibling_init(struct device *cpu) { unsigned i, siblings; struct cpuid_result result; @@ -74,7 +74,7 @@ void intel_sibling_init(device_t cpu) /* I am the primary cpu start up my siblings */ for(i = 1; i < siblings; i++) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 8e44c78..8b20107 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -86,7 +86,7 @@ static void configure_c_states(const int quad) msr_t msr; /* Find pointer to CPU configuration. */ - const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); const struct cpu_intel_model_1067x_config *const conf = (lapic && lapic->chip_info) ? lapic->chip_info : NULL; @@ -144,7 +144,7 @@ static void configure_p_states(const char stepping, const char cores) msr_t msr; /* Find pointer to CPU configuration. */ - const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); struct cpu_intel_model_1067x_config *const conf = (lapic && lapic->chip_info) ? lapic->chip_info : NULL; @@ -285,7 +285,7 @@ static void configure_pic_thermal_sensors(const int tm2, const int quad) wrmsr(PIC_SENS_CFG, msr); } -static void model_1067x_init(device_t cpu) +static void model_1067x_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 73ee5cd..b201474 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -110,7 +110,7 @@ static void configure_misc(void) wrmsr(IA32_MISC_ENABLE, msr); } -static void model_106cx_init(device_t cpu) +static void model_106cx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index d0be502..870020f 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -89,7 +89,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_model_2065x_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 9a2afa4..f79aba5 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -182,7 +182,7 @@ int cpu_config_tdp_levels(void) static void configure_thermal_target(void) { struct cpu_intel_model_2065x_config *conf; - device_t lapic; + struct device *lapic; msr_t msr; /* Find pointer to CPU configuration */ @@ -286,7 +286,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -309,7 +309,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -337,7 +337,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_2065x_init(device_t cpu) +static void model_2065x_init(struct device *cpu) { char processor_name[49]; struct cpuid_result cpuid_regs; diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index f2cd6a9..21f9c3e 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -89,7 +89,7 @@ static int generate_C_state_entries(void) struct cpu_info *info; struct cpu_driver *cpu; int len, lenif; - device_t lapic; + struct device *lapic; struct cpu_intel_model_206ax_config *conf = NULL; /* Find the SpeedStep CPU in the device tree using magic APIC ID */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index dbde512..1c5d1af 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -364,7 +364,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { struct cpu_intel_model_206ax_config *conf; - device_t lapic; + struct device *lapic; msr_t msr; /* Find pointer to CPU configuration */ @@ -477,7 +477,7 @@ static void configure_mca(void) /* * Initialize any extra cores/threads in this package. */ -static void intel_cores_init(device_t cpu) +static void intel_cores_init(struct device *cpu) { struct cpuid_result result; unsigned threads_per_package, threads_per_core, i; @@ -500,7 +500,7 @@ static void intel_cores_init(device_t cpu) for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; - device_t new; + struct device *new; /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; @@ -531,7 +531,7 @@ static void intel_cores_init(device_t cpu) } } -static void model_206ax_init(device_t cpu) +static void model_206ax_init(struct device *cpu) { char processor_name[49]; struct cpuid_result cpuid_regs; diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index a9f1811..6b21939 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -28,7 +28,7 @@ #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> -static void model_65x_init(device_t dev) +static void model_65x_init(struct device *dev) { /* Update the microcode */ intel_update_microcode_from_cbfs(); diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 467d3db..c72dfae 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -29,7 +29,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/l2_cache.h> -static void model_67x_init(device_t cpu) +static void model_67x_init(struct device *cpu) { /* Update the microcode */ intel_update_microcode_from_cbfs(); diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index d1b4463..fc016d2 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static void model_68x_init(device_t cpu) +static void model_68x_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index 4339274..214673a 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_69x_init(device_t dev) +static void model_69x_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index d166bfa..013a6a5 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> -static void model_6bx_init(device_t cpu) +static void model_6bx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 18c2fa4..190edf0 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_6dx_init(device_t dev) +static void model_6dx_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 8f9fbf8..54e59eb 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -141,7 +141,7 @@ static void configure_pic_thermal_sensors(void) wrmsr(PIC_SENS_CFG, msr); } -static void model_6ex_init(device_t cpu) +static void model_6ex_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 93635d4..1b52781 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -161,7 +161,7 @@ static void configure_pic_thermal_sensors(void) wrmsr(PIC_SENS_CFG, msr); } -static void model_6fx_init(device_t cpu) +static void model_6fx_init(struct device *cpu) { char processor_name[49]; diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 9b92dcc..d8acd5e 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_6xx_init(device_t dev) +static void model_6xx_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index ca40515..fe9ea3b 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_f0x_init(device_t dev) +static void model_f0x_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index dbb5cd0..3678bfe 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -8,7 +8,7 @@ #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -static void model_f1x_init(device_t dev) +static void model_f1x_init(struct device *dev) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 53eb75e..cf0b827 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -9,7 +9,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static void model_f2x_init(device_t cpu) +static void model_f2x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index f8d9ca6..2d3bc73 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -9,7 +9,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static void model_f3x_init(device_t cpu) +static void model_f3x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 260b60a..cbc042e 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -9,7 +9,7 @@ #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -static void model_f4x_init(device_t cpu) +static void model_f4x_init(struct device *cpu) { /* Turn on caching if we haven't already */ x86_enable_cache(); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 483e813..98d1ee7 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -44,7 +44,7 @@ int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries static int determine_total_number_of_cores(void) { - device_t cpu; + struct device *cpu; int count = 0; for(cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c index 7d94384..fc6001b 100644 --- a/src/cpu/via/c3/c3_init.c +++ b/src/cpu/via/c3/c3_init.c @@ -26,7 +26,7 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> -static void c3_init(device_t dev) +static void c3_init(struct device *dev) { x86_enable_cache(); x86_setup_mtrrs(); diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 510e66d..7f22e59 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -147,7 +147,7 @@ static void set_c7_speed(int model) { printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff)); } -static void c7_init(device_t dev) +static void c7_init(struct device *dev) { u8 brand; struct cpuinfo_x86 c; diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 417119f..acb5f95 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -139,7 +139,7 @@ static void nano_power(void) wrmsr(MSR_IA32_MISC_ENABLE, msr); } -static void nano_init(device_t dev) +static void nano_init(struct device *dev) { struct cpuinfo_x86 c; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 09b6b9e..018924f 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -253,7 +253,7 @@ static void *stacks[CONFIG_MAX_CPUS]; volatile unsigned long secondary_stack; volatile unsigned int secondary_cpu_index; -int start_cpu(device_t cpu) +int start_cpu(struct device *cpu) { struct cpu_info *info; unsigned long stack_end; @@ -430,9 +430,9 @@ void asmlinkage secondary_cpu_init(unsigned int index) stop_this_cpu(); } -static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) +static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) { - device_t cpu; + struct device *cpu; /* Loop through the cpus once getting them started */ for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { @@ -465,7 +465,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) static void wait_other_cpus_stop(struct bus *cpu_bus) { - device_t cpu; + struct device *cpu; int old_active_count, active_count; long loopcount = 0; int i; diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index e83c23d..a97a4c5 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -86,7 +86,7 @@ struct mp_flight_plan { static struct mp_flight_plan mp_info; struct cpu_map { - device_t dev; + struct device *dev; int apic_id; }; @@ -328,7 +328,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) info = cpu_info(); for (i = 1; i < max_cpus; i++) { struct device_path cpu_path; - device_t new; + struct device *new; int apic_id; /* Build the cpu device path */ diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index cdcb862..41cea72 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -489,7 +489,7 @@ static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) info->mem_refresh_rate = i; } #endif /*CONFIG_CONSOLE_BTEXT */ -static void ati_ragexl_init(device_t dev) +static void ati_ragexl_init(struct device *dev) { u32 chip_id; int j; diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index 7ce3d6b..b26b22c 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <console/console.h> -static void dec_21143_enable(device_t dev) +static void dec_21143_enable(struct device *dev) { printk(BIOS_DEBUG, "Initializing DECchip 21143\n"); diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index f2e4dfb..cb0075a 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -58,7 +58,7 @@ static int bochs_read(int index) } #endif -static void bochs_init(device_t dev) +static void bochs_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) struct edid edid; diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index c96e032..1c659eb 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -212,7 +212,7 @@ write_hidden_dac (uint8_t data) } #endif -static void cirrus_init(device_t dev) +static void cirrus_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) uint8_t cr_ext, cr_overlay; diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 42b2f07..3d62a7c 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -12,7 +12,7 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> -static void ioapic_init(device_t dev) +static void ioapic_init(struct device *dev) { struct drivers_generic_ioapic_config *config = dev->chip_info; u32 bsp_lapicid = lapicid(); @@ -86,15 +86,15 @@ static void ioapic_init(device_t dev) } } -static void ioapic_enable_resources(device_t dev) +static void ioapic_enable_resources(struct device *dev) { } -static void ioapic_nop(device_t dummy) +static void ioapic_nop(struct device * dummy) { } -static void ioapic_read_resources(device_t dev) +static void ioapic_read_resources(struct device *dev) { struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; struct resource *res; diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index ab85eb5..305972f 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -19,7 +19,7 @@ #define ADM1026_REG_CONFIG2 0x01 #define ADM1026_REG_CONFIG3 0x07 -static void adm1026_enable_monitoring(device_t dev) +static void adm1026_enable_monitoring(struct device *dev) { int result; result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); @@ -33,7 +33,7 @@ static void adm1026_enable_monitoring(device_t dev) } } -static void adm1026_init(device_t dev) +static void adm1026_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -44,7 +44,7 @@ static void adm1026_init(device_t dev) } } -static void adm1026_noop(device_t dummy) +static void adm1026_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index e83f2c4..1fc50de 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -18,7 +18,7 @@ #define ADM1027_REG_CONFIG2 0x73 #define ADM1027_REG_CONFIG3 0x78 -static void adm1027_enable_monitoring(device_t dev) +static void adm1027_enable_monitoring(struct device *dev) { int result; @@ -39,7 +39,7 @@ static void adm1027_enable_monitoring(device_t dev) printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n"); } -static void adm1027_init(device_t dev) +static void adm1027_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -50,7 +50,7 @@ static void adm1027_init(device_t dev) } } -static void adm1027_noop(device_t dummy) +static void adm1027_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 9ca9f37..3146dbb 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -32,7 +32,7 @@ * See Analog Devices ADT7463 datasheet, Rev C (2004): * http://www.analog.com/en/prod/0,,766_825_ADT7463,00.html */ -static void adt7463_init(device_t adt7463) +static void adt7463_init(struct device * adt7463) { int result; @@ -85,7 +85,7 @@ static void adt7463_init(device_t adt7463) printk(BIOS_DEBUG, "ADT7463 properly initialized\n"); } -static void adt7463_noop(device_t dummy) +static void adt7463_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index a9cf2c5..870c11a 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -25,7 +25,7 @@ #include <smbios.h> #include <console/console.h> -static void at24rf08c_init(device_t dev) +static void at24rf08c_init(struct device *dev) { int i, j; @@ -52,7 +52,7 @@ static void at24rf08c_init(device_t dev) printk (BIOS_DEBUG, "init EEPROM done\n"); } -static void at24rf08c_noop(device_t dummy) +static void at24rf08c_noop(struct device * dummy) { } @@ -63,7 +63,7 @@ static struct device_operations at24rf08c_operations = { .init = at24rf08c_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &at24rf08c_operations; } diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 53e76da..8cd1e1b 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -28,16 +28,16 @@ #define ERROR_STRING "*INVALID*" -static device_t at24rf08c_find_bank(u8 bank) +static struct device * at24rf08c_find_bank(u8 bank) { - device_t dev; + struct device *dev; dev = dev_find_slot_on_smbus(1, 0x54 | bank); if (!dev) printk(BIOS_WARNING, "EEPROM not found\n"); return dev; } -static int at24rf08c_read_byte(device_t dev, u8 addr) +static int at24rf08c_read_byte(struct device *dev, u8 addr) { int t = -1; int j; @@ -54,7 +54,7 @@ static int at24rf08c_read_byte(device_t dev, u8 addr) return t; } -static void at24rf08c_read_string_dev(device_t dev, u8 start, +static void at24rf08c_read_string_dev(struct device *dev, u8 start, u8 len, char *result) { int i; @@ -72,7 +72,7 @@ static void at24rf08c_read_string_dev(device_t dev, u8 start, static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) { - device_t dev; + struct device *dev; dev = at24rf08c_find_bank(bank); if (dev == 0) { @@ -124,7 +124,7 @@ void smbios_mainboard_set_uuid(u8 *uuid) static char result[16]; unsigned i; static int already_read; - device_t dev; + struct device *dev; const int remap[16] = { /* UUID byteswap. */ 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 @@ -173,7 +173,7 @@ const char *smbios_mainboard_version(void) { static char result[100]; static int already_read; - device_t dev; + struct device *dev; int len; if (already_read) diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index b318508..256569c 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void i2cmux_set_link(device_t dev, unsigned int link) +static void i2cmux_set_link(struct device *dev, unsigned int link) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -16,7 +16,7 @@ static void i2cmux_set_link(device_t dev, unsigned int link) } } -static void i2cmux_noop(device_t dummy) +static void i2cmux_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index a7d40e2..287784c 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void i2cmux2_set_link(device_t dev, unsigned int link) +static void i2cmux2_set_link(struct device *dev, unsigned int link) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -15,7 +15,7 @@ static void i2cmux2_set_link(device_t dev, unsigned int link) } } -static void i2cmux2_noop(device_t dummy) +static void i2cmux2_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index 47a5489..80835f3 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void lm63_init(device_t dev) +static void lm63_init(struct device *dev) { int result; if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { @@ -21,7 +21,7 @@ static void lm63_init(device_t dev) } } -static void lm63_noop(device_t dummy) +static void lm63_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 44333ac..9ccf3b0 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -75,7 +75,7 @@ #define RTD2132_DEBUG_REG 0 -static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) +static void rtd2132_write_reg(struct device *dev, u8 reg, u8 value) { if (RTD2132_DEBUG_REG) printk(BIOS_DEBUG, "RTD2132 0x%02x <- 0x%02x\n", reg, value); @@ -83,18 +83,18 @@ static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) smbus_write_byte(dev, RTD2132_DATA, value); } -static void rtd2132_firmware_stop(device_t dev) +static void rtd2132_firmware_stop(struct device *dev) { smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_STOP); mdelay(60); } -static void rtd2132_firmware_start(device_t dev) +static void rtd2132_firmware_start(struct device *dev) { smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_START); } -static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) +static void rtd2132_pps(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { /* T2, T5, and T7 register values are in units of 4ms. */ rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T1, cfg->t1); @@ -106,7 +106,7 @@ static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T7, cfg->t7 / 4); } -static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) +static void rtd2132_sscg_enable(struct device *dev, u8 sscg_percent) { /* SSCG_Config_0 */ rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, @@ -116,7 +116,7 @@ static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_1, sscg_percent); } -static void rtd2132_sscg_disable(device_t dev) +static void rtd2132_sscg_disable(struct device *dev) { /* SSCG_Config_0 */ rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, @@ -127,7 +127,7 @@ static void rtd2132_sscg_disable(device_t dev) RTD2132_SSCG_CONFIG_DISABLED); } -static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) +static void rtd2132_sscg(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { switch (cfg->sscg_percent) { case RTD2132_SSCG_PERCENT_0_0: @@ -152,7 +152,7 @@ static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) } } -static void rtd2132_lvds_swap(device_t dev, +static void rtd2132_lvds_swap(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { u8 swap_value = RTD2132_LVDS_SWAP_NORMAL; @@ -186,7 +186,7 @@ static void rtd2132_lvds_swap(device_t dev, rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); } -static void rtd2132_defaults(device_t dev) +static void rtd2132_defaults(struct device *dev) { static const struct def_setting { u8 reg; @@ -207,7 +207,7 @@ static void rtd2132_defaults(device_t dev) def_settings[i].value); } -static void rtd2132_setup(device_t dev) +static void rtd2132_setup(struct device *dev) { struct drivers_i2c_rtd2132_config *config = dev->chip_info; @@ -233,7 +233,7 @@ static void rtd2132_setup(device_t dev) rtd2132_firmware_start(dev); } -static void rtd2132_init(device_t dev) +static void rtd2132_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && ops_smbus_bus(get_pbus_smbus(dev))) { @@ -241,7 +241,7 @@ static void rtd2132_init(device_t dev) } } -static void rtd2132_noop(device_t dummy) +static void rtd2132_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c index 8dcfb28..6127085 100644 --- a/src/drivers/i2c/w83793/w83793.c +++ b/src/drivers/i2c/w83793/w83793.c @@ -25,18 +25,18 @@ #include <device/smbus.h> #include "chip.h" -static int w83793_fan_limit(device_t dev, int fan, uint16_t limit) +static int w83793_fan_limit(struct device *dev, int fan, uint16_t limit) { return smbus_write_byte(dev, 0x90 + fan * 2, limit >> 8) || smbus_write_byte(dev, 0x91 + fan * 2, limit & 0xff); } -static int w83793_bank(device_t dev, int bank) +static int w83793_bank(struct device *dev, int bank) { return smbus_write_byte(dev, 0, bank); } -static int w83793_td_level(device_t dev, int fan, const char *level) +static int w83793_td_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -50,7 +50,7 @@ static int w83793_td_level(device_t dev, int fan, const char *level) return 0; } -static int w83793_tr_level(device_t dev, int fan, const char *level) +static int w83793_tr_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -65,7 +65,7 @@ static int w83793_tr_level(device_t dev, int fan, const char *level) } -static int w83793_td_fan_level(device_t dev, int fan, const char *level) +static int w83793_td_fan_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -79,7 +79,7 @@ static int w83793_td_fan_level(device_t dev, int fan, const char *level) return 0; } -static int w83793_tr_fan_level(device_t dev, int fan, const char *level) +static int w83793_tr_fan_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -94,7 +94,7 @@ static int w83793_tr_fan_level(device_t dev, int fan, const char *level) } -static void w83793_init(device_t dev) +static void w83793_init(struct device *dev) { struct drivers_i2c_w83793_config *config = dev->chip_info; uint16_t id; @@ -220,7 +220,7 @@ static void w83793_init(device_t dev) } -static void w83793_noop(device_t dummy) +static void w83793_noop(struct device * dummy) { } @@ -231,7 +231,7 @@ static struct device_operations w83793_operations = { .init = w83793_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &w83793_operations; } diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 87aa7f5..b8a056e 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -221,7 +221,7 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) } } -static void w83795_hwm_init(device_t dev) +static void w83795_hwm_init(struct device *dev) { struct device *cpu; struct cpu_info *info; @@ -239,7 +239,7 @@ static void w83795_hwm_init(device_t dev) printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n"); } -static void w83795_noop(device_t dummy) +static void w83795_noop(struct device * dummy) { } @@ -250,7 +250,7 @@ static struct device_operations w83795_operations = { .init = w83795_hwm_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &w83795_operations; } diff --git a/src/drivers/ics/954309/ics954309.c b/src/drivers/ics/954309/ics954309.c index ef62879..9104d28 100644 --- a/src/drivers/ics/954309/ics954309.c +++ b/src/drivers/ics/954309/ics954309.c @@ -29,7 +29,7 @@ #include "chip.h" #include <string.h> -static void ics954309_init(device_t dev) +static void ics954309_init(struct device *dev) { struct drivers_ics_954309_config *config; u8 initdata[12]; @@ -55,7 +55,7 @@ static void ics954309_init(device_t dev) smbus_block_write(dev, 0, 12, initdata); } -static void ics954309_noop(device_t dummy) +static void ics954309_noop(struct device * dummy) { } diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 2e83b4c..4bf6727 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -132,7 +132,7 @@ static u8 ec_io_read(u16 addr) */ #ifndef __SMM__ -static void ene932_init(device_t dev) +static void ene932_init(struct device *dev) { if (!dev->enabled) return; @@ -143,13 +143,13 @@ static void ene932_init(device_t dev) } -static void ene932_read_resources(device_t dev) +static void ene932_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void ene932_enable_resources(device_t dev) +static void ene932_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -164,7 +164,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 4cd30f3..5344716 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -137,7 +137,7 @@ int google_chromeec_command(struct chromeec_command *cec_command) #ifndef __PRE_RAM__ #ifndef __SMM__ -static void lpc_ec_init(device_t dev) +static void lpc_ec_init(struct device *dev) { if (!dev->enabled) return; @@ -146,12 +146,12 @@ static void lpc_ec_init(device_t dev) google_chromeec_init(); } -static void lpc_ec_read_resources(device_t dev) +static void lpc_ec_read_resources(struct device *dev) { /* Nothing, but this function avoids an error on serial console. */ } -static void lpc_ec_enable_resources(device_t dev) +static void lpc_ec_enable_resources(struct device *dev) { /* Nothing, but this function avoids an error on serial console. */ } @@ -166,7 +166,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index 925b7ea..7827a1d 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -211,7 +211,7 @@ static void it8516e_set_fan_from_options(const config_t *const config, } } -static void it8516e_pm2_init(const device_t dev) +static void it8516e_pm2_init(struct device *dev) { const config_t *const config = dev->chip_info; @@ -251,7 +251,7 @@ static struct pnp_info it8516e_dev_infos[] = { { NULL, IT8516E_LDN_PM3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, }; -static void it8516e_enable(const device_t dev) +static void it8516e_enable(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(it8516e_dev_infos), it8516e_dev_infos); diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 79ef3cd..13b0483 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -167,7 +167,7 @@ u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) return i; } -static void h8_smbios_strings(device_t dev, struct smbios_type11 *t) +static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t) { char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; @@ -180,7 +180,7 @@ struct device_operations h8_dev_ops = { .get_smbios_strings = h8_smbios_strings }; -static void h8_enable(device_t dev) +static void h8_enable(struct device *dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; u8 val, tmp; diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index cb0e27b..f67fbda 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -102,7 +102,7 @@ void pmh7_register_write(int reg, int val) #ifndef __PRE_RAM__ #ifndef __SMM__ -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index f0a2308..dcd9c4a 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -141,7 +141,7 @@ static void ene_kb3940q_log_events(void) #endif } -static void ene_kb3940q_init(device_t dev) +static void ene_kb3940q_init(struct device *dev) { if (!dev->enabled) return; @@ -153,13 +153,13 @@ static void ene_kb3940q_init(device_t dev) } -static void ene_kb3940q_read_resources(device_t dev) +static void ene_kb3940q_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void ene_kb3940q_enable_resources(device_t dev) +static void ene_kb3940q_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -174,7 +174,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index b9cb68f..cd976e6 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -156,7 +156,7 @@ void ec_it8518_enable_wake_events(void) } #ifndef __SMM__ -static void it8518_init(device_t dev) +static void it8518_init(struct device *dev) { if (!dev->enabled) return; @@ -166,13 +166,13 @@ static void it8518_init(device_t dev) } -static void it8518_read_resources(device_t dev) +static void it8518_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void it8518_enable_resources(device_t dev) +static void it8518_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -187,7 +187,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index 4d3b30a..0a7c4ae 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -121,7 +121,7 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg) } #if !defined(__PRE_RAM__) && !defined(__SMM__) -static void mec1308_enable(device_t dev) +static void mec1308_enable(struct device *dev) { struct ec_smsc_mec1308_config *conf = dev->chip_info;

1 0

Patch set updated for coreboot: d8b507d NOTFORMERGE: fix reset.c
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7196 -gerrit commit d8b507d63e21f30a3abc1ca9dcf672e2fd82d1c1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:36:02 2014 +1100 NOTFORMERGE: fix reset.c Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/amdfam10/reset_test.c | 10 +++++----- src/northbridge/amd/amdk8/reset_test.c | 4 ++-- src/southbridge/amd/amd8111/reset.c | 14 ++++++-------- src/southbridge/broadcom/bcm5785/reset.c | 6 ++---- src/southbridge/nvidia/ck804/reset.c | 6 ++---- src/southbridge/nvidia/mcp55/reset.c | 6 ++---- src/southbridge/sis/sis966/reset.c | 6 ++---- 7 files changed, 21 insertions(+), 31 deletions(-) diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 24f5397..de7949e 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -32,7 +32,7 @@ u32 cpu_init_detected(u8 nodeid) { u32 htic; - device_t dev; + pci_devfn_t dev; dev = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(dev, HT_INIT_CONTROL); @@ -67,7 +67,7 @@ u32 other_reset_detected(void) // other warm reset not started by BIOS static void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; @@ -77,7 +77,7 @@ static void distinguish_cpu_resets(u8 nodeid) static u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -89,7 +89,7 @@ void __attribute__ ((weak)) set_bios_reset(void) u32 nodes; u32 htic; - device_t dev; + pci_devfn_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; @@ -134,7 +134,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b int i; int j; u32 cfg_map_dest; - device_t dev; + pci_devfn_t dev; cfg_map_dest = (1<<7)|(1<<6)|link; diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 6ef3ec0..8015290 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -10,7 +10,7 @@ static inline int cpu_init_detected(unsigned nodeid) { u32 htic; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); @@ -37,7 +37,7 @@ static inline int cold_reset_detected(void) static inline void distinguish_cpu_resets(unsigned nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index c96e898..8824550 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -10,9 +10,7 @@ #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -typedef unsigned device_t; - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) { unsigned addr; addr = (dev>>4) | where; @@ -20,7 +18,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value) outb(value, 0xCFC + (addr & 3)); } -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -28,7 +26,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; @@ -37,9 +35,9 @@ static unsigned pci_read_config32(device_t dev, unsigned where) } #define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); for(; dev <= last; dev += PCI_DEV(0,0,1)) { @@ -57,7 +55,7 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) void hard_reset(void) { - device_t dev; + pci_devfn_t dev; unsigned bus; unsigned node = 0; unsigned link = get_sblk(); diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 51ba6ec..b34cc86 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index a241966..53c0c40 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev >> 4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev >> 4) | where; diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/sis/sis966/reset.c +++ b/src/southbridge/sis/sis966/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where;

1 0

New patch to review for coreboot: a030e6d cpu/intel: Add configuration for socket LGA1155
by Damien Zammit 26 Oct '14

26 Oct '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7197 -gerrit commit a030e6d6c80d27cccba7cb6e3fa48c57d3d35e36 Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Oct 23 21:57:48 2014 +1100 cpu/intel: Add configuration for socket LGA1155 This allows mainboards to explicitly select LGA1155. Change-Id: Id33679b27c89038588347cb4f1a6a0e66aae3e6e Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/socket_LGA1155/Kconfig | 15 +++++++++++++++ src/cpu/intel/socket_LGA1155/Makefile.inc | 7 +++++++ src/cpu/intel/socket_LGA1155/socket_LGA1155.c | 5 +++++ 5 files changed, 29 insertions(+) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index aa3dd5b..de76e3e 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -33,6 +33,7 @@ source src/cpu/intel/socket_mPGA603/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig +source src/cpu/intel/socket_LGA1155/Kconfig source src/cpu/intel/socket_LGA771/Kconfig source src/cpu/intel/socket_LGA775/Kconfig source src/cpu/intel/socket_rPGA988B/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index b6e7268..51451e9 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -27,6 +27,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 diff --git a/src/cpu/intel/socket_LGA1155/Kconfig b/src/cpu/intel/socket_LGA1155/Kconfig new file mode 100644 index 0000000..d409f22 --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/Kconfig @@ -0,0 +1,15 @@ +config CPU_INTEL_SOCKET_LGA1155 + bool + +if CPU_INTEL_SOCKET_LGA1155 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select MMX + select SSE + +config CACHE_MRC_BIN + bool + default n + +endif # CPU_INTEL_SOCKET_LGA1155 diff --git a/src/cpu/intel/socket_LGA1155/Makefile.inc b/src/cpu/intel/socket_LGA1155/Makefile.inc new file mode 100644 index 0000000..cbf6f06 --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/Makefile.inc @@ -0,0 +1,7 @@ +ramstage-y += socket_LGA1155.c +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo diff --git a/src/cpu/intel/socket_LGA1155/socket_LGA1155.c b/src/cpu/intel/socket_LGA1155/socket_LGA1155.c new file mode 100644 index 0000000..63c925d --- /dev/null +++ b/src/cpu/intel/socket_LGA1155/socket_LGA1155.c @@ -0,0 +1,5 @@ +#include <device/device.h> + +struct chip_operations cpu_intel_socket_LGA1155_ops = { + CHIP_NAME("Socket LGA1155 CPU") +};

1 0

Patch set updated for coreboot: f87bf3f gigabyte/ga-b75m-d3h: Add new Intel mainboard
by Damien Zammit 26 Oct '14

26 Oct '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7020 -gerrit commit f87bf3f812130fc012bdd6461060490c53ff893e Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Oct 23 22:06:38 2014 +1100 gigabyte/ga-b75m-d3h: Add new Intel mainboard This is based on LENOVO X230 port. Board boots to payload. Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM hangs when run in SeaBIOS 3. SATA does not work. SeaBIOS does not detect devices connected to SATA ports Change-Id: Ib465a4824ef1a71ab6aa17bd40fc281215c6d44f Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/Kconfig | 3 + src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 75 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 21 ++ src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl | 1 + .../gigabyte/ga-b75m-d3h/acpi/mainboard.asl | 28 ++ .../gigabyte/ga-b75m-d3h/acpi/platform.asl | 73 ++++++ .../gigabyte/ga-b75m-d3h/acpi/superio.asl | 24 ++ .../gigabyte/ga-b75m-d3h/acpi/thermal.asl | 65 +++++ src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl | 43 ++++ src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 83 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt | 6 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.default | 18 ++ src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout | 167 ++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 87 +++++++ src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 54 ++++ src/mainboard/gigabyte/ga-b75m-d3h/fadt.c | 167 ++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/gpio.c | 283 +++++++++++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c | 252 ++++++++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 83 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c | 109 ++++++++ src/mainboard/gigabyte/ga-b75m-d3h/onboard.h | 33 +++ src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 194 ++++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/thermal.h | 30 +++ src/southbridge/intel/bd82x6x/early_usb_native.c | 2 +- 24 files changed, 1900 insertions(+), 1 deletion(-) diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index ff96a17..c46b979 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -27,6 +27,8 @@ config BOARD_GIGABYTE_GA_6BXC bool "GA-6BXC" config BOARD_GIGABYTE_GA_6BXE bool "GA-6BXE" +config BOARD_GIGABYTE_GA_B75M_D3H + bool "GA-B75M-D3H" config BOARD_GIGABYTE_M57SLI bool "GA-M57SLI-S4" config BOARD_GIGABYTE_MA785GMT @@ -41,6 +43,7 @@ endchoice source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig" source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/ga-6bxe/Kconfig" +source "src/mainboard/gigabyte/ga-b75m-d3h/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" source "src/mainboard/gigabyte/ma785gmt/Kconfig" source "src/mainboard/gigabyte/ma785gm/Kconfig" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig new file mode 100644 index 0000000..85e9ec2 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -0,0 +1,75 @@ +if BOARD_GIGABYTE_GA_B75M_D3H + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA1155 + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select INTEL_INT15 + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS + select UDELAY_TSC + select EARLY_CBMEM_INIT + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAINBOARD_DIR + string + default gigabyte/ga-b75m-d3h + +config MAINBOARD_PART_NUMBER + string + default "GA-B75M-D3H" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +# No need to override the chipset VGA_BIOS_ID. +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config IFD_BIOS_SECTION + string + default "0x00600000:0x007fffff" + +config IFD_ME_SECTION + string + default "0x00001000:0x004fffff" + +# UNCOMMENT BELOW WHEN YOU BUILD WITH REAL ME IMAGE +#config IFD_GBE_SECTION +# string +# default "0x00fff000:0x00000fff" + +endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc new file mode 100644 index 0000000..a2efadd --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl new file mode 100644 index 0000000..09cff9a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl new file mode 100644 index 0000000..1448aeb --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl new file mode 100644 index 0000000..753fc29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ + +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // Enable PS/2 Mouse + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl new file mode 100644 index 0000000..f71611a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 10 seconds + Name (_TSP, 100) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c new file mode 100644 index 0000000..73b1c11 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt new file mode 100644 index 0000000..312f6ef --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default new file mode 100644 index 0000000..137f482 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +hyper_threading=Enable +backlight=Both \ No newline at end of file diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout new file mode 100644 index 0000000..7a2eb01 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -0,0 +1,167 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +#419 2 r 0 unused +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb new file mode 100644 index 0000000..bd9cdf6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -0,0 +1,87 @@ +chip northbridge/intel/sandybridge + + # Enable DVI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + device cpu_cluster 0 on + chip cpu/intel/socket_LGA1155 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + end + end + + device domain 0 on + subsystemid 0x1458 0x5000 inherit + device pci 00.0 on end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + + # GPI routing + register "alt_gp_smi_en" = "0x0000" + + # Set max SATA speed to 6.0 Gb/s + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + register "gen1_dec" = "0x003c0a01" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + device pci 14.0 off end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 on end # PCI bridge (ethernet here) + device pci 1f.0 on # ISA/LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 9 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x0 + io 0x62 = 0xa00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.a off end # IR + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl new file mode 100644 index 0000000..3209963 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include "acpi/thermal.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/fadt.c b/src/mainboard/gigabyte/ga-b75m-d3h/fadt.c new file mode 100644 index 0000000..8104d22 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/fadt.c @@ -0,0 +1,167 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ +#define APM_CNT 0xb2 +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x80 +#define ACPI_DISABLE 0x1e +#define ACPI_ENABLE 0xe1 +#define GNVS_UPDATE 0xea + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), + 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_DESKTOP; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = ACPI_ENABLE; + fadt->acpi_disable = ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c new file mode 100644 index 0000000..9b93c9a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c @@ -0,0 +1,283 @@ +#include "southbridge/intel/bd82x6x/gpio.h" +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /*1GPIO0 */ + .gpio1 = GPIO_MODE_GPIO, /*0SIO_EXT_SMI# */ + .gpio2 = GPIO_MODE_GPIO, /*1NOT USED */ + .gpio3 = GPIO_MODE_GPIO, /*1NOT USED */ + .gpio4 = GPIO_MODE_GPIO, /*1NOT USED */ + .gpio5 = GPIO_MODE_GPIO, /*0INTH# */ + .gpio6 = GPIO_MODE_GPIO, /*0SIO_EXT_SCI# */ + .gpio7 = GPIO_MODE_GPIO, /*1GE_SCR_WP# */ + .gpio8 = GPIO_MODE_GPIO, /*0NOT USED */ + .gpio9 = GPIO_MODE_NATIVE, /*1USB_OC5# */ + .gpio10 = GPIO_MODE_NATIVE, /*1USB_OC6# */ + .gpio11 = GPIO_MODE_NATIVE, /*0SMBALERT# */ + .gpio12 = GPIO_MODE_GPIO, /*1GPIO12 */ + .gpio13 = GPIO_MODE_GPIO, /*0GPIO13 */ + .gpio14 = GPIO_MODE_NATIVE, /*1USB_OC7# */ + .gpio15 = GPIO_MODE_GPIO, /*1GPIO15 */ + .gpio16 = GPIO_MODE_GPIO, /*1WWAN_LED_ON */ + .gpio17 = GPIO_MODE_GPIO, /*0WLAN_LED_ON */ + .gpio18 = GPIO_MODE_NATIVE, /*1PCIE_CLKREQ_WLAN# */ + .gpio19 = GPIO_MODE_GPIO, /*1BBS_BIT0 */ + .gpio20 = GPIO_MODE_NATIVE, /*0PCIE_CLKREQ_CARD# */ + .gpio21 = GPIO_MODE_GPIO, /*0BT_DET# / TP29 */ + .gpio22 = GPIO_MODE_GPIO, /*0MODEL_ID0 */ + .gpio23 = GPIO_MODE_NATIVE, /*1LCD_BK_OFF */ + .gpio24 = GPIO_MODE_GPIO, /*1GPIO24 */ + .gpio25 = GPIO_MODE_NATIVE, /*1PCIE_REQ_WWAN# / TP89 */ + .gpio26 = GPIO_MODE_NATIVE, /*1CLK_PCIE_REQ4# / TP59 */ + .gpio27 = GPIO_MODE_GPIO, /*1MSATA_DTCT# */ + .gpio28 = GPIO_MODE_GPIO, /*1PLL_ODVR_EN */ + .gpio29 = GPIO_MODE_GPIO, /*1WLAN_AOAC_ON */ + .gpio30 = GPIO_MODE_NATIVE, /*1SUS_PWR_ACK */ + .gpio31 = GPIO_MODE_GPIO, /*1AC_PRESENT */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, /* PCI_CLKRUN# */ + .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ + .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ + .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ + .gpio36 = GPIO_MODE_GPIO, /* NOT USED */ + .gpio37 = GPIO_MODE_GPIO, /* NOT USED */ + .gpio38 = GPIO_MODE_GPIO, /* NOT USED */ + .gpio39 = GPIO_MODE_GPIO, /* NOT USED */ + .gpio40 = GPIO_MODE_NATIVE, /* USB_OC1# */ + .gpio41 = GPIO_MODE_NATIVE, /* USB_OC2# */ + .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ + .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ + .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ + .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ + .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ + .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ + .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ + .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ + .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ + .gpio51 = GPIO_MODE_NATIVE, /* BBS_BIT1 */ + .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ + .gpio53 = GPIO_MODE_NATIVE, /* PWM_SELECT# / TP44 */ + .gpio54 = GPIO_MODE_NATIVE, /* PCI_REQ3# */ + .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ + .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ + .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ + .gpio59 = GPIO_MODE_NATIVE, /* USB_OC0_1# */ + .gpio60 = GPIO_MODE_NATIVE, /* DRAMRST_CNTRL_PCH */ + .gpio61 = GPIO_MODE_NATIVE, /* LPCPD# */ + .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ + .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, /* CLK_FLEX0 / TP38 */ + .gpio65 = GPIO_MODE_NATIVE, /* CLK_FLEX1 / TP45 */ + .gpio66 = GPIO_MODE_NATIVE, /* CLK_FLEX2 / TP83 */ + .gpio67 = GPIO_MODE_NATIVE, /* CLK_FLEX3 / TP82 */ + .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ + .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ + .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ + .gpio71 = GPIO_MODE_NATIVE, /* WWAN_OFF# */ + .gpio72 = GPIO_MODE_NATIVE, /* PM_BATLOW# */ + .gpio73 = GPIO_MODE_GPIO, /* PCIECLKRQ0# / TP39 */ + .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ + .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c new file mode 100644 index 0000000..29f8a45 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c @@ -0,0 +1,252 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Vendor Name : IDT + * Vendor ID : 0x10ec0269 + * Subsystem ID : 0x17aa21fa + * Revision ID : 0x100303 + */ + + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC + 0x17aa21fa, // Subsystem ID + 0x0000007d, // Number of 4 dword sets + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +/* NID 0x01 - NodeInfo */ + AZALIA_SUBVENDOR(0x0, 0x17AA21FA), + +/* NID 0x0A - External Microphone Connector + * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), + +/* NID 0x0B - Headphone Connector + * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), + +/* NID 0x0C - Not connected + * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), + +/* NID 0x0D - Internal Speakers + * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), + +/* NID 0x0F - Not connected + * Config=0x40F000F0 + */ + AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), + +/* NID 0x11 - Internal Microphone + * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + */ + AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), + AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0), + + 0x01970804, + 0x01870803, + 0x01470740, + 0x00970600, + + 0x00370600, + 0x00270600, + 0x00270600, + 0x00270600, + + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205), + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), + + /* + * Hardware EQ Parameters + * Sample Rate 88200 + */ + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, + 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, + 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, + 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, + 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, + 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, + 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, + 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, + 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, + 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, + 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, + 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, + 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, + 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, + 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, + 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, + 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, + 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, + 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, + 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, + 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, + 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, + 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, + 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, + 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, + 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, + 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, + 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, + 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, + 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, + 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, + 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, + 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, + 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, + 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, + 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, + 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, + 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, + 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, + 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, + 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, + 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, + 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, + 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, + 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, + 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, + 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, + + /* + * Hardware EQ Parameters + * Sample Rate 96000 + */ + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, + 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, + 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, + 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, + 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, + 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, + 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, + 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, + 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, + 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, + 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, + 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, + 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, + 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, + 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, + 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, + 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, + 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, + 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, + 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, + 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, + 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, + 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, + 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, + 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, + 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, + 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, + 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, + 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, + 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, + 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, + 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, + 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, + 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, + 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, + 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, + 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, + 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, + 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, + 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, + 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, + 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, + 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, + 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, + 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, + 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, + 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, + + /* SAFEDSP Parameters */ + 0x022782C1, 0x02277127, 0x02277227, 0x02278801, + 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, + 0x02278B0F, 0x0017B008, + + /* Misc entries */ + 0x00B707C0, /* Enable PortB as Output with HP amp */ + 0x00D70740, /* Enable PortD as Output */ + 0x0017A200, /* Disable ClkEn of PortSenseTst */ + 0x0017C621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + + /* --- Next Codec --- */ + +/* Vendor Name : Intel + * Vendor ID : 0x80862806 + * Subsystem ID : 0x80860101 + * Revision ID : 0x100000 + */ + /* coreboot specific header */ + 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of IDs + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c new file mode 100644 index 0000000..62b437b --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> +#include <pc80/keyboard.h> +#include <ec/lenovo/h8/h8.h> +#include <build.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + + + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + + /* This sneaked in here, because X201 SuperIO chip isn't really + connected to anything and hence we don't init it. + */ + pc_keyboard_init(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c new file mode 100644 index 0000000..9f8a29f --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <pc80/mc146818rtc.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h new file mode 100644 index 0000000..0580945 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GAB75MD3V_ONBOARD_H +#define GAB75MD3V_ONBOARD_H + +#include <arch/smp/mpspec.h> + +#define GAB75MD3V_NIC_VENDOR_ID 0x10EC +#define GAB75MD3V_NIC_DEVICE_ID 0x8168 + +#define XHCI_MODE 2 // Auto +#define XHCI_PORTS 3 // Port 0 & 1 +#define XHCI_PREBOOT 0 // No PreOS boot support +#define XHCI_STREAMS 1 // Sure, lets have streams + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c new file mode 100644 index 0000000..d3ba6cc --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SUPERIO_BASE 0x2e +#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <superio/ite/it8728f/it8728f.h> +#include <superio/ite/common/ite.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +static void it8728f_b75md3h_disable_reboot(device_t dev) +{ + ite_reg_write(dev, 0xEF, 0x7E); + + ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 + ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 + ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port + ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 + ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! + ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in + ite_reg_write(dev, 0xe9, 0x21); // bus select disable + ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12) +} + +void rcba_config(void) +{ +/* + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); + + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x3500) = 0x2000035f; + RCBA32(0x3504) = 0x2000035f; + RCBA32(0x3508) = 0x2000035f; + RCBA32(0x350c) = 0x2000035f; + RCBA32(0x3510) = 0x2000035f; + RCBA32(0x3514) = 0x2000035f; + RCBA32(0x3518) = 0x2000035f; + RCBA32(0x351c) = 0x2000035f; + RCBA32(0x3520) = 0x2000035f; + RCBA32(0x3524) = 0x2000035f; + RCBA32(0x3528) = 0x2000035f; + RCBA32(0x352c) = 0x2000035f; + RCBA32(0x3530) = 0x2000035f; + RCBA32(0x3534) = 0x2000035f; + RCBA32(0x3560) = 0x024c8001; + RCBA32(0x3564) = 0x000024a3; + RCBA32(0x3568) = 0x00040002; + RCBA32(0x356c) = 0x01000050; + RCBA32(0x3570) = 0x02000662; + RCBA32(0x3574) = 0x18000f9f; + RCBA32(0x3578) = 0x1800ff4f; + RCBA32(0x357c) = 0x0001d530; + RCBA32(0x35a0) = 0xc0300c03; + RCBA32(0x35a4) = 0x00241803; + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + outw (0x0000, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3418) = 0x1fee1fe1; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; +*/ + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17ee1fe1; +} + +void pch_enable_lpc(void) +{ + /* + * Enable: + * EC Decode Range PortA30/A20 + * SuperIO Port2E/2F + * PS/2 Keyboard/Mouse Port60/64 + * FDD Port3F0h-3F5h and Port3F7h + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + + /* Initialize SuperIO */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8728f_b75md3h_disable_reboot(SUPERIO_GPIO); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd (&spd[0], 0x50); + read_spd (&spd[1], 0x51); + read_spd (&spd[2], 0x52); + read_spd (&spd[3], 0x53); +} + +#if 0 +static void dmi_config(void) +{ + DMIBAR32(0x0218) = 0x06aa0b0c; + DMIBAR32(0x021c) = 0x0b0d0b0d; + DMIBAR32(0x0300) = 0x0011028d; + DMIBAR32(0x0304) = 0x002102cd; + DMIBAR32(0x030c) = 0x007d004b; + DMIBAR32(0x0310) = 0x007e004c; + DMIBAR32(0x0318) = 0x002304ad; + DMIBAR32(0x031c) = 0x003304ed; + DMIBAR32(0x03b8) = 0x005c05a4; + DMIBAR32(0x03bc) = 0x006c05e4; + DMIBAR32(0x0530) = 0x41d3b000; + DMIBAR32(0x0534) = 0x00019f80; + DMIBAR32(0x0ba4) = 0x0000000d; + DMIBAR32(0x0d80) = 0x1c9cfc0b; + DMIBAR32(0x0e1c) = 0x20000000; + DMIBAR32(0x0e2c) = 0x20000000; +} +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h new file mode 100644 index 0000000..ab24bb1 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef X230_THERMAL_H +#define X230_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c index 7ce5574..b1f8447 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_native.c +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -33,7 +33,7 @@ early_usb_init (const struct southbridge_usb_port *portmap) /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 , 0x2000094a }; + const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 , 0x2000094a, 0x2000035f }; int i; /* Activate PMBAR. */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);

1 0

Patch set updated for coreboot: 6215009 {arch, cpu, drivers, ec}: Don't hide pointers behind typedefs
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7146 -gerrit commit 6215009df928d40cf8c5ff9d102a33f631241827 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 22 13:39:12 2014 +1100 {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/boot/acpi.c | 6 +++--- src/arch/x86/boot/mpspec.c | 6 ++++-- src/arch/x86/boot/smbios.c | 6 +++--- src/cpu/allwinner/a10/cpu.c | 8 ++++---- src/drivers/ati/ragexl/xlinit.c | 2 +- src/drivers/dec/21143/21143.c | 2 +- src/drivers/emulation/qemu/bochs.c | 2 +- src/drivers/emulation/qemu/cirrus.c | 2 +- src/drivers/generic/ioapic/ioapic.c | 8 ++++---- src/drivers/i2c/adm1026/adm1026.c | 6 +++--- src/drivers/i2c/adm1027/adm1027.c | 6 +++--- src/drivers/i2c/adt7463/adt7463.c | 4 ++-- src/drivers/i2c/at24rf08c/at24rf08c.c | 6 +++--- src/drivers/i2c/at24rf08c/lenovo_serials.c | 14 +++++++------- src/drivers/i2c/i2cmux/i2cmux.c | 4 ++-- src/drivers/i2c/i2cmux2/i2cmux2.c | 4 ++-- src/drivers/i2c/lm63/lm63.c | 4 ++-- src/drivers/i2c/rtd2132/rtd2132.c | 24 ++++++++++++------------ src/drivers/i2c/w83793/w83793.c | 18 +++++++++--------- src/drivers/i2c/w83795/w83795.c | 6 +++--- src/drivers/ics/954309/ics954309.c | 4 ++-- src/ec/compal/ene932/ec.c | 8 ++++---- src/ec/google/chromeec/ec_lpc.c | 8 ++++---- src/ec/kontron/it8516e/ec.c | 4 ++-- src/ec/lenovo/h8/h8.c | 4 ++-- src/ec/lenovo/pmh7/pmh7.c | 2 +- src/ec/quanta/ene_kb3940q/ec.c | 8 ++++---- src/ec/quanta/it8518/ec.c | 8 ++++---- src/ec/smsc/mec1308/ec.c | 2 +- 29 files changed, 94 insertions(+), 92 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index c3c946d..b506cb4 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -141,7 +141,7 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) unsigned long acpi_create_madt_lapics(unsigned long current) { - device_t cpu; + struct device *cpu; int index = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { @@ -278,7 +278,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) acpigen_set_current((char *) current); { #if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) - device_t dev; + struct device *dev; for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_fill_ssdt_generator) { dev->ops->acpi_fill_ssdt_generator(); @@ -708,7 +708,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt; acpi_mcfg_t *mcfg; acpi_madt_t *madt; - device_t dev; + struct device *dev; current = start; diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index d079d08..8049be4 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -166,7 +166,7 @@ void smp_write_processors(struct mp_config_table *mc) unsigned cpu_features; unsigned cpu_feature_flags; struct cpuid_result result; - device_t cpu; + struct device *cpu; boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; @@ -493,7 +493,9 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) struct drivers_generic_ioapic_config *ioapic_config; struct mp_config_table *mc; int isa_bus, pin, parentpin; - device_t dev, parent, oldparent; + struct device *dev; + struct device *parent; + struct device *oldparent; void *tmp, *v; int isaioapic = -1, have_fixed_entries; diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 724def3..64889f7 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -303,7 +303,7 @@ static int smbios_write_type11(unsigned long *current, int *handle) { struct smbios_type11 *t = (struct smbios_type11 *)*current; int len; - device_t dev; + struct device *dev; memset(t, 0, sizeof *t); t->type = SMBIOS_OEM_STRINGS; @@ -379,9 +379,9 @@ static int smbios_write_type127(unsigned long *current, int handle) return len; } -static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *current) +static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current) { - device_t dev; + struct device *dev; int len = 0; for(dev = tree; dev; dev = dev->next) { diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c index e0d4cdf..fac5730 100644 --- a/src/cpu/allwinner/a10/cpu.c +++ b/src/cpu/allwinner/a10/cpu.c @@ -11,7 +11,7 @@ #include <cbmem.h> -static void cpu_enable_resources(device_t dev) +static void cpu_enable_resources(struct device *dev) { ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10, CONFIG_DRAM_SIZE_MB << 10); @@ -20,12 +20,12 @@ static void cpu_enable_resources(device_t dev) */ } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { /* TODO: Check if anything else needs to be explicitly initialized */ } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -37,7 +37,7 @@ static struct device_operations cpu_ops = { .scan_bus = NULL, }; -static void a1x_cpu_enable_dev(device_t dev) +static void a1x_cpu_enable_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index cdcb862..41cea72 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -489,7 +489,7 @@ static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) info->mem_refresh_rate = i; } #endif /*CONFIG_CONSOLE_BTEXT */ -static void ati_ragexl_init(device_t dev) +static void ati_ragexl_init(struct device *dev) { u32 chip_id; int j; diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index 7ce3d6b..b26b22c 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <console/console.h> -static void dec_21143_enable(device_t dev) +static void dec_21143_enable(struct device *dev) { printk(BIOS_DEBUG, "Initializing DECchip 21143\n"); diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index f2e4dfb..cb0075a 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -58,7 +58,7 @@ static int bochs_read(int index) } #endif -static void bochs_init(device_t dev) +static void bochs_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) struct edid edid; diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index c96e032..1c659eb 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -212,7 +212,7 @@ write_hidden_dac (uint8_t data) } #endif -static void cirrus_init(device_t dev) +static void cirrus_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) uint8_t cr_ext, cr_overlay; diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 42b2f07..3d62a7c 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -12,7 +12,7 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> -static void ioapic_init(device_t dev) +static void ioapic_init(struct device *dev) { struct drivers_generic_ioapic_config *config = dev->chip_info; u32 bsp_lapicid = lapicid(); @@ -86,15 +86,15 @@ static void ioapic_init(device_t dev) } } -static void ioapic_enable_resources(device_t dev) +static void ioapic_enable_resources(struct device *dev) { } -static void ioapic_nop(device_t dummy) +static void ioapic_nop(struct device * dummy) { } -static void ioapic_read_resources(device_t dev) +static void ioapic_read_resources(struct device *dev) { struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; struct resource *res; diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index ab85eb5..305972f 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -19,7 +19,7 @@ #define ADM1026_REG_CONFIG2 0x01 #define ADM1026_REG_CONFIG3 0x07 -static void adm1026_enable_monitoring(device_t dev) +static void adm1026_enable_monitoring(struct device *dev) { int result; result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); @@ -33,7 +33,7 @@ static void adm1026_enable_monitoring(device_t dev) } } -static void adm1026_init(device_t dev) +static void adm1026_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -44,7 +44,7 @@ static void adm1026_init(device_t dev) } } -static void adm1026_noop(device_t dummy) +static void adm1026_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index e83f2c4..1fc50de 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -18,7 +18,7 @@ #define ADM1027_REG_CONFIG2 0x73 #define ADM1027_REG_CONFIG3 0x78 -static void adm1027_enable_monitoring(device_t dev) +static void adm1027_enable_monitoring(struct device *dev) { int result; @@ -39,7 +39,7 @@ static void adm1027_enable_monitoring(device_t dev) printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n"); } -static void adm1027_init(device_t dev) +static void adm1027_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -50,7 +50,7 @@ static void adm1027_init(device_t dev) } } -static void adm1027_noop(device_t dummy) +static void adm1027_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 9ca9f37..3146dbb 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -32,7 +32,7 @@ * See Analog Devices ADT7463 datasheet, Rev C (2004): * http://www.analog.com/en/prod/0,,766_825_ADT7463,00.html */ -static void adt7463_init(device_t adt7463) +static void adt7463_init(struct device * adt7463) { int result; @@ -85,7 +85,7 @@ static void adt7463_init(device_t adt7463) printk(BIOS_DEBUG, "ADT7463 properly initialized\n"); } -static void adt7463_noop(device_t dummy) +static void adt7463_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index a9cf2c5..870c11a 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -25,7 +25,7 @@ #include <smbios.h> #include <console/console.h> -static void at24rf08c_init(device_t dev) +static void at24rf08c_init(struct device *dev) { int i, j; @@ -52,7 +52,7 @@ static void at24rf08c_init(device_t dev) printk (BIOS_DEBUG, "init EEPROM done\n"); } -static void at24rf08c_noop(device_t dummy) +static void at24rf08c_noop(struct device * dummy) { } @@ -63,7 +63,7 @@ static struct device_operations at24rf08c_operations = { .init = at24rf08c_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &at24rf08c_operations; } diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 53e76da..8cd1e1b 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -28,16 +28,16 @@ #define ERROR_STRING "*INVALID*" -static device_t at24rf08c_find_bank(u8 bank) +static struct device * at24rf08c_find_bank(u8 bank) { - device_t dev; + struct device *dev; dev = dev_find_slot_on_smbus(1, 0x54 | bank); if (!dev) printk(BIOS_WARNING, "EEPROM not found\n"); return dev; } -static int at24rf08c_read_byte(device_t dev, u8 addr) +static int at24rf08c_read_byte(struct device *dev, u8 addr) { int t = -1; int j; @@ -54,7 +54,7 @@ static int at24rf08c_read_byte(device_t dev, u8 addr) return t; } -static void at24rf08c_read_string_dev(device_t dev, u8 start, +static void at24rf08c_read_string_dev(struct device *dev, u8 start, u8 len, char *result) { int i; @@ -72,7 +72,7 @@ static void at24rf08c_read_string_dev(device_t dev, u8 start, static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) { - device_t dev; + struct device *dev; dev = at24rf08c_find_bank(bank); if (dev == 0) { @@ -124,7 +124,7 @@ void smbios_mainboard_set_uuid(u8 *uuid) static char result[16]; unsigned i; static int already_read; - device_t dev; + struct device *dev; const int remap[16] = { /* UUID byteswap. */ 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 @@ -173,7 +173,7 @@ const char *smbios_mainboard_version(void) { static char result[100]; static int already_read; - device_t dev; + struct device *dev; int len; if (already_read) diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index b318508..256569c 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void i2cmux_set_link(device_t dev, unsigned int link) +static void i2cmux_set_link(struct device *dev, unsigned int link) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -16,7 +16,7 @@ static void i2cmux_set_link(device_t dev, unsigned int link) } } -static void i2cmux_noop(device_t dummy) +static void i2cmux_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index a7d40e2..287784c 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void i2cmux2_set_link(device_t dev, unsigned int link) +static void i2cmux2_set_link(struct device *dev, unsigned int link) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -15,7 +15,7 @@ static void i2cmux2_set_link(device_t dev, unsigned int link) } } -static void i2cmux2_noop(device_t dummy) +static void i2cmux2_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index 47a5489..80835f3 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void lm63_init(device_t dev) +static void lm63_init(struct device *dev) { int result; if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { @@ -21,7 +21,7 @@ static void lm63_init(device_t dev) } } -static void lm63_noop(device_t dummy) +static void lm63_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 44333ac..9ccf3b0 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -75,7 +75,7 @@ #define RTD2132_DEBUG_REG 0 -static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) +static void rtd2132_write_reg(struct device *dev, u8 reg, u8 value) { if (RTD2132_DEBUG_REG) printk(BIOS_DEBUG, "RTD2132 0x%02x <- 0x%02x\n", reg, value); @@ -83,18 +83,18 @@ static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) smbus_write_byte(dev, RTD2132_DATA, value); } -static void rtd2132_firmware_stop(device_t dev) +static void rtd2132_firmware_stop(struct device *dev) { smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_STOP); mdelay(60); } -static void rtd2132_firmware_start(device_t dev) +static void rtd2132_firmware_start(struct device *dev) { smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_START); } -static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) +static void rtd2132_pps(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { /* T2, T5, and T7 register values are in units of 4ms. */ rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T1, cfg->t1); @@ -106,7 +106,7 @@ static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T7, cfg->t7 / 4); } -static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) +static void rtd2132_sscg_enable(struct device *dev, u8 sscg_percent) { /* SSCG_Config_0 */ rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, @@ -116,7 +116,7 @@ static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_1, sscg_percent); } -static void rtd2132_sscg_disable(device_t dev) +static void rtd2132_sscg_disable(struct device *dev) { /* SSCG_Config_0 */ rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, @@ -127,7 +127,7 @@ static void rtd2132_sscg_disable(device_t dev) RTD2132_SSCG_CONFIG_DISABLED); } -static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) +static void rtd2132_sscg(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { switch (cfg->sscg_percent) { case RTD2132_SSCG_PERCENT_0_0: @@ -152,7 +152,7 @@ static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) } } -static void rtd2132_lvds_swap(device_t dev, +static void rtd2132_lvds_swap(struct device *dev, struct drivers_i2c_rtd2132_config *cfg) { u8 swap_value = RTD2132_LVDS_SWAP_NORMAL; @@ -186,7 +186,7 @@ static void rtd2132_lvds_swap(device_t dev, rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); } -static void rtd2132_defaults(device_t dev) +static void rtd2132_defaults(struct device *dev) { static const struct def_setting { u8 reg; @@ -207,7 +207,7 @@ static void rtd2132_defaults(device_t dev) def_settings[i].value); } -static void rtd2132_setup(device_t dev) +static void rtd2132_setup(struct device *dev) { struct drivers_i2c_rtd2132_config *config = dev->chip_info; @@ -233,7 +233,7 @@ static void rtd2132_setup(device_t dev) rtd2132_firmware_start(dev); } -static void rtd2132_init(device_t dev) +static void rtd2132_init(struct device *dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && ops_smbus_bus(get_pbus_smbus(dev))) { @@ -241,7 +241,7 @@ static void rtd2132_init(device_t dev) } } -static void rtd2132_noop(device_t dummy) +static void rtd2132_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c index 8dcfb28..6127085 100644 --- a/src/drivers/i2c/w83793/w83793.c +++ b/src/drivers/i2c/w83793/w83793.c @@ -25,18 +25,18 @@ #include <device/smbus.h> #include "chip.h" -static int w83793_fan_limit(device_t dev, int fan, uint16_t limit) +static int w83793_fan_limit(struct device *dev, int fan, uint16_t limit) { return smbus_write_byte(dev, 0x90 + fan * 2, limit >> 8) || smbus_write_byte(dev, 0x91 + fan * 2, limit & 0xff); } -static int w83793_bank(device_t dev, int bank) +static int w83793_bank(struct device *dev, int bank) { return smbus_write_byte(dev, 0, bank); } -static int w83793_td_level(device_t dev, int fan, const char *level) +static int w83793_td_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -50,7 +50,7 @@ static int w83793_td_level(device_t dev, int fan, const char *level) return 0; } -static int w83793_tr_level(device_t dev, int fan, const char *level) +static int w83793_tr_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -65,7 +65,7 @@ static int w83793_tr_level(device_t dev, int fan, const char *level) } -static int w83793_td_fan_level(device_t dev, int fan, const char *level) +static int w83793_td_fan_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -79,7 +79,7 @@ static int w83793_td_fan_level(device_t dev, int fan, const char *level) return 0; } -static int w83793_tr_fan_level(device_t dev, int fan, const char *level) +static int w83793_tr_fan_level(struct device *dev, int fan, const char *level) { fan *= 0x10; @@ -94,7 +94,7 @@ static int w83793_tr_fan_level(device_t dev, int fan, const char *level) } -static void w83793_init(device_t dev) +static void w83793_init(struct device *dev) { struct drivers_i2c_w83793_config *config = dev->chip_info; uint16_t id; @@ -220,7 +220,7 @@ static void w83793_init(device_t dev) } -static void w83793_noop(device_t dummy) +static void w83793_noop(struct device * dummy) { } @@ -231,7 +231,7 @@ static struct device_operations w83793_operations = { .init = w83793_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &w83793_operations; } diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 87aa7f5..b8a056e 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -221,7 +221,7 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) } } -static void w83795_hwm_init(device_t dev) +static void w83795_hwm_init(struct device *dev) { struct device *cpu; struct cpu_info *info; @@ -239,7 +239,7 @@ static void w83795_hwm_init(device_t dev) printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n"); } -static void w83795_noop(device_t dummy) +static void w83795_noop(struct device * dummy) { } @@ -250,7 +250,7 @@ static struct device_operations w83795_operations = { .init = w83795_hwm_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { dev->ops = &w83795_operations; } diff --git a/src/drivers/ics/954309/ics954309.c b/src/drivers/ics/954309/ics954309.c index ef62879..9104d28 100644 --- a/src/drivers/ics/954309/ics954309.c +++ b/src/drivers/ics/954309/ics954309.c @@ -29,7 +29,7 @@ #include "chip.h" #include <string.h> -static void ics954309_init(device_t dev) +static void ics954309_init(struct device *dev) { struct drivers_ics_954309_config *config; u8 initdata[12]; @@ -55,7 +55,7 @@ static void ics954309_init(device_t dev) smbus_block_write(dev, 0, 12, initdata); } -static void ics954309_noop(device_t dummy) +static void ics954309_noop(struct device * dummy) { } diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 2e83b4c..4bf6727 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -132,7 +132,7 @@ static u8 ec_io_read(u16 addr) */ #ifndef __SMM__ -static void ene932_init(device_t dev) +static void ene932_init(struct device *dev) { if (!dev->enabled) return; @@ -143,13 +143,13 @@ static void ene932_init(device_t dev) } -static void ene932_read_resources(device_t dev) +static void ene932_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void ene932_enable_resources(device_t dev) +static void ene932_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -164,7 +164,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 4cd30f3..5344716 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -137,7 +137,7 @@ int google_chromeec_command(struct chromeec_command *cec_command) #ifndef __PRE_RAM__ #ifndef __SMM__ -static void lpc_ec_init(device_t dev) +static void lpc_ec_init(struct device *dev) { if (!dev->enabled) return; @@ -146,12 +146,12 @@ static void lpc_ec_init(device_t dev) google_chromeec_init(); } -static void lpc_ec_read_resources(device_t dev) +static void lpc_ec_read_resources(struct device *dev) { /* Nothing, but this function avoids an error on serial console. */ } -static void lpc_ec_enable_resources(device_t dev) +static void lpc_ec_enable_resources(struct device *dev) { /* Nothing, but this function avoids an error on serial console. */ } @@ -166,7 +166,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index 925b7ea..7827a1d 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -211,7 +211,7 @@ static void it8516e_set_fan_from_options(const config_t *const config, } } -static void it8516e_pm2_init(const device_t dev) +static void it8516e_pm2_init(struct device *dev) { const config_t *const config = dev->chip_info; @@ -251,7 +251,7 @@ static struct pnp_info it8516e_dev_infos[] = { { NULL, IT8516E_LDN_PM3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, }; -static void it8516e_enable(const device_t dev) +static void it8516e_enable(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(it8516e_dev_infos), it8516e_dev_infos); diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 79ef3cd..13b0483 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -167,7 +167,7 @@ u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) return i; } -static void h8_smbios_strings(device_t dev, struct smbios_type11 *t) +static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t) { char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; @@ -180,7 +180,7 @@ struct device_operations h8_dev_ops = { .get_smbios_strings = h8_smbios_strings }; -static void h8_enable(device_t dev) +static void h8_enable(struct device *dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; u8 val, tmp; diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index cb0e27b..f67fbda 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -102,7 +102,7 @@ void pmh7_register_write(int reg, int val) #ifndef __PRE_RAM__ #ifndef __SMM__ -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index f0a2308..dcd9c4a 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -141,7 +141,7 @@ static void ene_kb3940q_log_events(void) #endif } -static void ene_kb3940q_init(device_t dev) +static void ene_kb3940q_init(struct device *dev) { if (!dev->enabled) return; @@ -153,13 +153,13 @@ static void ene_kb3940q_init(device_t dev) } -static void ene_kb3940q_read_resources(device_t dev) +static void ene_kb3940q_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void ene_kb3940q_enable_resources(device_t dev) +static void ene_kb3940q_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -174,7 +174,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index b9cb68f..cd976e6 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -156,7 +156,7 @@ void ec_it8518_enable_wake_events(void) } #ifndef __SMM__ -static void it8518_init(device_t dev) +static void it8518_init(struct device *dev) { if (!dev->enabled) return; @@ -166,13 +166,13 @@ static void it8518_init(device_t dev) } -static void it8518_read_resources(device_t dev) +static void it8518_read_resources(struct device *dev) { /* This function avoids an error on serial console. */ } -static void it8518_enable_resources(device_t dev) +static void it8518_enable_resources(struct device *dev) { /* This function avoids an error on serial console. */ } @@ -187,7 +187,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index 4d3b30a..0a7c4ae 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -121,7 +121,7 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg) } #if !defined(__PRE_RAM__) && !defined(__SMM__) -static void mec1308_enable(device_t dev) +static void mec1308_enable(struct device *dev) { struct ec_smsc_mec1308_config *conf = dev->chip_info;

1 0

Patch set updated for coreboot: 853ac40 superio/common/conf_mode.c: Don't hiding pointers with typedefs
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7137 -gerrit commit 853ac402a6ed5119236dccf28fbd782262c41902 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 21 07:51:24 2014 +1100 superio/common/conf_mode.c: Don't hiding pointers with typedefs Change-Id: Ia1bbf2f885acf601b8a8360a7cd72819f70ef6a6 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/superio/conf_mode.h | 10 +++++----- src/superio/common/conf_mode.c | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h index c49cae7..f69dc07 100644 --- a/src/include/superio/conf_mode.h +++ b/src/include/superio/conf_mode.h @@ -24,11 +24,11 @@ #include <device/pnp.h> /* Common enter/exit implementations */ -void pnp_enter_conf_mode_55(device_t dev); -void pnp_enter_conf_mode_8787(device_t dev); -void pnp_exit_conf_mode_aa(device_t dev); -void pnp_enter_conf_mode_870155aa(device_t dev); -void pnp_exit_conf_mode_0202(device_t dev); +void pnp_enter_conf_mode_55(struct device * dev); +void pnp_enter_conf_mode_8787(struct device * dev); +void pnp_exit_conf_mode_aa(struct device * dev); +void pnp_enter_conf_mode_870155aa(struct device * dev); +void pnp_exit_conf_mode_0202(struct device * dev); extern const struct pnp_mode_ops pnp_conf_mode_55_aa; extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index f3e6277..271d4ef 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -23,23 +23,23 @@ /* Common enter/exit implementations */ -void pnp_enter_conf_mode_55(device_t dev) +void pnp_enter_conf_mode_55(struct device *dev) { outb(0x55, dev->path.pnp.port); } -void pnp_enter_conf_mode_8787(device_t dev) +void pnp_enter_conf_mode_8787(struct device *dev) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } -void pnp_exit_conf_mode_aa(device_t dev) +void pnp_exit_conf_mode_aa(struct device *dev) { outb(0xaa, dev->path.pnp.port); } -void pnp_enter_conf_mode_870155aa(device_t dev) +void pnp_enter_conf_mode_870155aa(struct device *dev) { outb(0x87, dev->path.pnp.port); outb(0x01, dev->path.pnp.port); @@ -51,7 +51,7 @@ void pnp_enter_conf_mode_870155aa(device_t dev) outb(0x55, dev->path.pnp.port); } -void pnp_exit_conf_mode_0202(device_t dev) +void pnp_exit_conf_mode_0202(struct device *dev) { outb(0x02, dev->path.pnp.port); outb(0x02, dev->path.pnp.port + 1);

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coreboot-gerrit October 2014