coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 8dfa839 superio/*/superio.c: Don't hide pointer types behind typedefs
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7136 -gerrit commit 8dfa8397481b6c32d2418d1b49b2502a53d12f55 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 21 07:43:41 2014 +1100 superio/*/superio.c: Don't hide pointer types behind typedefs Hiding pointer types behind 'typedef's is usually not a great idea at the best of times. Worse the typedef becomes an integer at different stages in Coreboot. Let us refrain from doing this at all. Change-Id: Ia2ca8c98bb489daaa58f379433875864f6efabc8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71805f/superio.c | 4 +-- src/superio/fintek/f71859/superio.c | 4 +-- src/superio/fintek/f71863fg/superio.c | 4 +-- src/superio/fintek/f71869ad/superio.c | 4 +-- src/superio/fintek/f71872/superio.c | 4 +-- src/superio/fintek/f71889/superio.c | 4 +-- src/superio/fintek/f81865f/superio.c | 4 +-- src/superio/intel/i3100/superio.c | 6 ++-- src/superio/ite/it8661f/superio.c | 2 +- src/superio/ite/it8671f/superio.c | 2 +- src/superio/ite/it8712f/superio.c | 6 ++-- src/superio/ite/it8716f/superio.c | 6 ++-- src/superio/ite/it8718f/superio.c | 2 +- src/superio/ite/it8721f/superio.c | 2 +- src/superio/ite/it8728f/superio.c | 4 +-- src/superio/ite/it8772f/superio.c | 6 ++-- src/superio/nsc/pc8374/superio.c | 2 +- src/superio/nsc/pc87309/superio.c | 2 +- src/superio/nsc/pc87351/superio.c | 2 +- src/superio/nsc/pc87360/superio.c | 2 +- src/superio/nsc/pc87366/superio.c | 2 +- src/superio/nsc/pc87382/superio.c | 2 +- src/superio/nsc/pc87392/superio.c | 2 +- src/superio/nsc/pc87417/superio.c | 2 +- src/superio/nsc/pc87427/superio.c | 2 +- src/superio/nsc/pc97307/superio.c | 2 +- src/superio/nsc/pc97317/superio.c | 2 +- src/superio/nuvoton/nct5104d/superio.c | 2 +- src/superio/nuvoton/wpcm450/superio.c | 2 +- src/superio/renesas/m3885x/superio.c | 8 +++--- src/superio/smsc/fdc37m60x/superio.c | 2 +- src/superio/smsc/kbc1100/superio.c | 8 +++--- src/superio/smsc/lpc47b272/superio.c | 12 ++++---- src/superio/smsc/lpc47b397/superio.c | 10 +++---- src/superio/smsc/lpc47m10x/superio.c | 12 ++++---- src/superio/smsc/lpc47m15x/superio.c | 8 +++--- src/superio/smsc/lpc47n217/superio.c | 50 ++++++++++++++++----------------- src/superio/smsc/lpc47n227/superio.c | 48 +++++++++++++++---------------- src/superio/smsc/mec1308/superio.c | 4 +-- src/superio/smsc/sch4037/superio.c | 4 +-- src/superio/smsc/sio1036/superio.c | 4 +-- src/superio/smsc/smscsuperio/superio.c | 4 +-- src/superio/winbond/w83627dhg/superio.c | 4 +-- src/superio/winbond/w83627ehg/superio.c | 8 +++--- src/superio/winbond/w83627hf/superio.c | 8 +++--- src/superio/winbond/w83627thg/superio.c | 4 +-- src/superio/winbond/w83627uhg/superio.c | 6 ++-- src/superio/winbond/w83697hf/superio.c | 2 +- src/superio/winbond/w83977f/superio.c | 4 +-- src/superio/winbond/w83977tf/superio.c | 4 +-- 50 files changed, 152 insertions(+), 152 deletions(-) diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index fa9608f..158e0cc 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -26,7 +26,7 @@ #include <stdlib.h> #include "f71805f.h" -static void f71805f_init(device_t dev) +static void f71805f_init(struct device *dev) { if (!dev->enabled) return; @@ -54,7 +54,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71805F_PME, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 8eca710..02c2572 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include "f71859.h" -static void f71859_init(device_t dev) +static void f71859_init(struct device *dev) { if (!dev->enabled) return; @@ -49,7 +49,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71859_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 83ccd38..8a543e8 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -27,7 +27,7 @@ #include <pc80/keyboard.h> #include "f71863fg.h" -static void f71863fg_init(device_t dev) +static void f71863fg_init(struct device *dev) { struct resource *res0; @@ -66,7 +66,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71863FG_PME, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 173713b..b05e73e 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -30,7 +30,7 @@ #include "chip.h" #include "f71869ad.h" -static void f71869ad_init(device_t dev) +static void f71869ad_init(struct device *dev) { if (!dev->enabled) return; @@ -122,7 +122,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71869AD_PME, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index c6fa7d0..cfccdef 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -27,7 +27,7 @@ #include <pc80/keyboard.h> #include "f71872.h" -static void f71872_init(device_t dev) +static void f71872_init(struct device *dev) { if (!dev->enabled) @@ -63,7 +63,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71872_PM, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f71889/superio.c b/src/superio/fintek/f71889/superio.c index 14bdd07..f962ad8 100644 --- a/src/superio/fintek/f71889/superio.c +++ b/src/superio/fintek/f71889/superio.c @@ -27,7 +27,7 @@ #include <pc80/keyboard.h> #include "f71889.h" -static void f71889_init(device_t dev) +static void f71889_init(struct device *dev) { if (!dev->enabled) @@ -65,7 +65,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71889_VREF, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index bfb53b4..530f260 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -27,7 +27,7 @@ #include <pc80/keyboard.h> #include "f81865f.h" -static void f81865f_init(device_t dev) +static void f81865f_init(struct device *dev) { if (!dev->enabled) @@ -62,7 +62,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F81865F_PME, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c index d0c5066..50c9de1 100644 --- a/src/superio/intel/i3100/superio.c +++ b/src/superio/intel/i3100/superio.c @@ -24,19 +24,19 @@ #include "i3100.h" #include <arch/io.h> -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(struct device *dev) { outb(0x80, dev->path.pnp.port); outb(0x86, dev->path.pnp.port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(struct device *dev) { outb(0x68, dev->path.pnp.port); outb(0x08, dev->path.pnp.port); } -static void i3100_init(device_t dev) +static void i3100_init(struct device *dev) { if (!dev->enabled) return; diff --git a/src/superio/ite/it8661f/superio.c b/src/superio/ite/it8661f/superio.c index 4b7aa00..e0d9f8d 100644 --- a/src/superio/ite/it8661f/superio.c +++ b/src/superio/ite/it8661f/superio.c @@ -25,7 +25,7 @@ /* TODO: Add pnp_enter_ext_func_mode() etc. and wrap functions. */ -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) return; diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c index 9da8f1d..b84d620 100644 --- a/src/superio/ite/it8671f/superio.c +++ b/src/superio/ite/it8671f/superio.c @@ -24,7 +24,7 @@ #include <stdlib.h> #include "it8671f.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 769afe3..9dd9f85 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -26,7 +26,7 @@ #include <stdlib.h> #include "it8712f.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(struct device *dev) { u16 port = dev->path.pnp.port; @@ -36,12 +36,12 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(struct device *dev) { pnp_write_config(dev, 0x02, 0x02); } -static void it8712f_init(device_t dev) +static void it8712f_init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index bd89a32..874061f 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -29,7 +29,7 @@ #include <stdlib.h> #include "it8716f.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(struct device *dev) { u16 port = dev->path.pnp.port; @@ -39,7 +39,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(struct device *dev) { pnp_write_config(dev, 0x02, 0x02); } @@ -73,7 +73,7 @@ static void init_ec(u16 base) } #endif -static void it8716f_init(device_t dev) +static void it8716f_init(struct device *dev) { struct resource *res0; diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index d40407a..ced4508 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -24,7 +24,7 @@ #include <stdlib.h> #include "it8718f.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index 66e6ef7..baf1f1b 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -25,7 +25,7 @@ #include <stdlib.h> #include "it8721f.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index e689b4c..ad644c6 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -30,7 +30,7 @@ #include "it8728f.h" #include "it8728f_internal.h" -static void it8728f_init(device_t dev) +static void it8728f_init(struct device *dev) { if (!dev->enabled) return; @@ -68,7 +68,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, IT8728F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 38f31c0..143cc30 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -26,7 +26,7 @@ #include "chip.h" /* FIXME */ #include "it8772f.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(struct device *dev) { u16 port = dev->path.pnp.port; @@ -36,7 +36,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(struct device *dev) { pnp_write_config(dev, 0x02, 0x02); } @@ -131,7 +131,7 @@ static void it8772f_enable_fan(struct resource *res, int fan) } } -static void it8772f_init(device_t dev) +static void it8772f_init(struct device *dev) { struct superio_ite_it8772f_config *conf = dev->chip_info; struct resource *res; diff --git a/src/superio/nsc/pc8374/superio.c b/src/superio/nsc/pc8374/superio.c index 8b6f1ca..7769a86 100644 --- a/src/superio/nsc/pc8374/superio.c +++ b/src/superio/nsc/pc8374/superio.c @@ -28,7 +28,7 @@ #include <stdlib.h> #include "pc8374.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index f374e6a..2c8fd71 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -25,7 +25,7 @@ #include <stdlib.h> #include "pc87309.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87351/superio.c b/src/superio/nsc/pc87351/superio.c index 7f395b4..bee9ebe 100644 --- a/src/superio/nsc/pc87351/superio.c +++ b/src/superio/nsc/pc87351/superio.c @@ -28,7 +28,7 @@ #include <stdlib.h> #include "pc87351.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index a53cc35..58e0802 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -28,7 +28,7 @@ #include <stdlib.h> #include "pc87360.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index 27bdd6e..9cfba04 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -28,7 +28,7 @@ #include <stdlib.h> #include "pc87366.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 3c0cda0..c6513b7 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include "pc87382.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) return; diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index d67539f..7eb6392 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -26,7 +26,7 @@ #include <stdlib.h> #include "pc87392.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) return; diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index 99882a5..2295f29 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc87417.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87427/superio.c b/src/superio/nsc/pc87427/superio.c index 170fd85..f23f97c 100644 --- a/src/superio/nsc/pc87427/superio.c +++ b/src/superio/nsc/pc87427/superio.c @@ -28,7 +28,7 @@ #include <pc80/keyboard.h> #include "pc87427.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc97307/superio.c b/src/superio/nsc/pc97307/superio.c index 6b15901..7c0faf4 100644 --- a/src/superio/nsc/pc97307/superio.c +++ b/src/superio/nsc/pc97307/superio.c @@ -26,7 +26,7 @@ #include <pc80/keyboard.h> #include "pc97307.h" -static void init(device_t dev) +static void init(struct device *dev) { u8 reg8; diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index 09c3b5e..b73dc7b 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -26,7 +26,7 @@ #include <pc80/keyboard.h> #include "pc97317.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index c2a744f..af1d4aa 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -25,7 +25,7 @@ #include "nct5104d.h" #include "chip.h" -static void nct5104d_init(device_t dev) +static void nct5104d_init(struct device *dev) { struct superio_nuvoton_nct5104d_config *conf = dev->chip_info; u8 reg10, reg11, reg26; diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index ff815cf..5322ace 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include "wpcm450.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 17bdadf..237cc26 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -29,7 +29,7 @@ void m3885_configure_multikey(void); -static void m3885x_init(device_t dev) +static void m3885x_init(struct device *dev) { if (!dev->enabled) @@ -41,12 +41,12 @@ static void m3885x_init(device_t dev) m3885_configure_multikey(); } -static void m3885x_read_resources(device_t dev) +static void m3885x_read_resources(struct device *dev) { /* Nothing, but this function avoids an error on serial console. */ } -static void m3885x_enable_resources(device_t dev) +static void m3885x_enable_resources(struct device *dev) { /* Nothing, but this function avoids an error on serial console. */ } @@ -61,7 +61,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/smsc/fdc37m60x/superio.c b/src/superio/smsc/fdc37m60x/superio.c index f5626ee..3822acd 100644 --- a/src/superio/smsc/fdc37m60x/superio.c +++ b/src/superio/smsc/fdc37m60x/superio.c @@ -24,7 +24,7 @@ #include <stdlib.h> #include "fdc37m60x.h" -static void init(device_t dev) +static void init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index 77777d0..9c0a196 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -31,8 +31,8 @@ #include "kbc1100.h" /* Forward declarations */ -static void enable_dev(device_t dev); -static void kbc1100_init(device_t dev); +static void enable_dev(struct device *dev); +static void kbc1100_init(struct device *dev); struct chip_operations superio_smsc_kbc1100_ops = { CHIP_NAME("SMSC KBC1100 Super I/O") @@ -52,12 +52,12 @@ static struct pnp_info pnp_dev_info[] = { { &ops, KBC1100_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -static void kbc1100_init(device_t dev) +static void kbc1100_init(struct device *dev) { struct resource *res0, *res1; diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 30e89a8..4fac022 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -35,9 +35,9 @@ #include "lpc47b272.h" /* Forward declarations */ -static void enable_dev(device_t dev); -static void lpc47b272_init(device_t dev); -// static void dump_pnp_device(device_t dev); +static void enable_dev(struct device *dev); +static void lpc47b272_init(struct device *dev); +// static void dump_pnp_device(struct device *dev); struct chip_operations superio_smsc_lpc47b272_ops = { CHIP_NAME("SMSC LPC47B272 Super I/O") @@ -68,7 +68,7 @@ static struct pnp_info pnp_dev_info[] = { * * @param dev Pointer to structure describing a Super I/O device. */ -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); @@ -82,7 +82,7 @@ static void enable_dev(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void lpc47b272_init(device_t dev) +static void lpc47b272_init(struct device *dev) { if (!dev->enabled) @@ -103,7 +103,7 @@ static void lpc47b272_init(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void dump_pnp_device(device_t dev) +static void dump_pnp_device(struct device *dev) { int i; print_debug("\n"); diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 8a6c03e..9c4a3b6 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -43,7 +43,7 @@ static u8 pnp_read_index(u16 port, u8 reg) return inb(port + 1); } -static void enable_hwm_smbus(device_t dev) +static void enable_hwm_smbus(struct device *dev) { /* Enable SensorBus register access. */ u8 reg8; @@ -53,7 +53,7 @@ static void enable_hwm_smbus(device_t dev) pnp_write_config(dev, 0xf0, reg8); } -static void lpc47b397_init(device_t dev) +static void lpc47b397_init(struct device *dev) { if (!dev->enabled) @@ -66,7 +66,7 @@ static void lpc47b397_init(device_t dev) } } -static void lpc47b397_pnp_enable_resources(device_t dev) +static void lpc47b397_pnp_enable_resources(struct device *dev) { pnp_enable_resources(dev); @@ -99,7 +99,7 @@ static struct device_operations ops = { #define SB_DATA2 0x0e #define SB_DATA3 0x0f -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { unsigned int device; struct resource *res; @@ -117,7 +117,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return result; } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) { unsigned int device; struct resource *res; diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index a9583e4..8530056 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -34,9 +34,9 @@ #include "lpc47m10x.h" /* Forward declarations */ -static void enable_dev(device_t dev); -static void lpc47m10x_init(device_t dev); -// static void dump_pnp_device(device_t dev); +static void enable_dev(struct device *dev); +static void lpc47m10x_init(struct device *dev); +// static void dump_pnp_device(struct device *dev); struct chip_operations superio_smsc_lpc47m10x_ops = { CHIP_NAME("SMSC LPC47M10x Super I/O") @@ -67,7 +67,7 @@ static struct pnp_info pnp_dev_info[] = { * * @param dev Pointer to structure describing a Super I/O device. */ -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); @@ -81,7 +81,7 @@ static void enable_dev(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void lpc47m10x_init(device_t dev) +static void lpc47m10x_init(struct device *dev) { if (!dev->enabled) @@ -102,7 +102,7 @@ static void lpc47m10x_init(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void dump_pnp_device(device_t dev) +static void dump_pnp_device(struct device *dev) { int i; print_debug("\n"); diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 91e77ba..3cb601b 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -31,8 +31,8 @@ #include "lpc47m15x.h" /* Forward declarations */ -static void enable_dev(device_t dev); -static void lpc47m15x_init(device_t dev); +static void enable_dev(struct device *dev); +static void lpc47m15x_init(struct device *dev); struct chip_operations superio_smsc_lpc47m15x_ops = { CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O") @@ -56,13 +56,13 @@ static struct pnp_info pnp_dev_info[] = { { &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -static void lpc47m15x_init(device_t dev) +static void lpc47m15x_init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index 0b470f6..96dd4e2 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -34,18 +34,18 @@ #include "lpc47n217.h" /* Forward declarations */ -static void enable_dev(device_t dev); -static void lpc47n217_pnp_set_resources(device_t dev); -static void lpc47n217_pnp_enable_resources(device_t dev); -static void lpc47n217_pnp_enable(device_t dev); -static void lpc47n217_init(device_t dev); -static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource); -static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase); -static void lpc47n217_pnp_set_drq(device_t dev, u8 drq); -static void lpc47n217_pnp_set_irq(device_t dev, u8 irq); -static void lpc47n217_pnp_set_enable(device_t dev, int enable); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); +static void enable_dev(struct device *dev); +static void lpc47n217_pnp_set_resources(struct device *dev); +static void lpc47n217_pnp_enable_resources(struct device *dev); +static void lpc47n217_pnp_enable(struct device *dev); +static void lpc47n217_init(struct device *dev); +static void lpc47n217_pnp_set_resource(struct device *dev, struct resource *resource); +static void lpc47n217_pnp_set_iobase(struct device *dev, u16 iobase); +static void lpc47n217_pnp_set_drq(struct device *dev, u8 drq); +static void lpc47n217_pnp_set_irq(struct device *dev, u8 irq); +static void lpc47n217_pnp_set_enable(struct device *dev, int enable); +static void pnp_enter_conf_state(struct device *dev); +static void pnp_exit_conf_state(struct device *dev); struct chip_operations superio_smsc_lpc47n217_ops = { CHIP_NAME("SMSC LPC47N217 Super I/O") @@ -72,7 +72,7 @@ static struct pnp_info pnp_dev_info[] = { * * @param dev Pointer to structure describing a Super I/O device. */ -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); @@ -87,7 +87,7 @@ static void enable_dev(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void lpc47n217_pnp_set_resources(device_t dev) +static void lpc47n217_pnp_set_resources(struct device *dev) { struct resource *res; @@ -102,7 +102,7 @@ static void lpc47n217_pnp_set_resources(device_t dev) * NOTE: Cannot use pnp_enable_resources() here because it assumes chip * support for logical devices, which the LPC47N217 doesn't have. */ -static void lpc47n217_pnp_enable_resources(device_t dev) +static void lpc47n217_pnp_enable_resources(struct device *dev) { pnp_enter_conf_state(dev); lpc47n217_pnp_set_enable(dev, 1); @@ -113,7 +113,7 @@ static void lpc47n217_pnp_enable_resources(device_t dev) * NOTE: Cannot use pnp_set_enable() here because it assumes chip * support for logical devices, which the LPC47N217 doesn't have. */ -static void lpc47n217_pnp_enable(device_t dev) +static void lpc47n217_pnp_enable(struct device *dev) { pnp_enter_conf_state(dev); lpc47n217_pnp_set_enable(dev, !!dev->enabled); @@ -128,13 +128,13 @@ static void lpc47n217_pnp_enable(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void lpc47n217_init(device_t dev) +static void lpc47n217_init(struct device *dev) { if (!dev->enabled) return; } -static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) +static void lpc47n217_pnp_set_resource(struct device *dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", @@ -164,7 +164,7 @@ static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) report_resource_stored(dev, resource, ""); } -static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n217_pnp_set_iobase(struct device *dev, u16 iobase) { ASSERT(!(iobase & 0x3)); @@ -184,7 +184,7 @@ static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) } } -static void lpc47n217_pnp_set_drq(device_t dev, u8 drq) +static void lpc47n217_pnp_set_drq(struct device *dev, u8 drq) { const u8 PP_DMA_MASK = 0x0F; const u8 PP_DMA_SELECTION_REGISTER = 0x26; @@ -201,7 +201,7 @@ static void lpc47n217_pnp_set_drq(device_t dev, u8 drq) } } -static void lpc47n217_pnp_set_irq(device_t dev, u8 irq) +static void lpc47n217_pnp_set_irq(struct device *dev, u8 irq) { u8 irq_config_register = 0, irq_config_mask = 0; u8 current_config, new_config; @@ -232,7 +232,7 @@ static void lpc47n217_pnp_set_irq(device_t dev, u8 irq) pnp_write_config(dev, irq_config_register, new_config); } -static void lpc47n217_pnp_set_enable(device_t dev, int enable) +static void lpc47n217_pnp_set_enable(struct device *dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -267,12 +267,12 @@ static void lpc47n217_pnp_set_enable(device_t dev, int enable) pnp_write_config(dev, power_register, new_power); } -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(struct device *dev) { outb(0x55, dev->path.pnp.port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(struct device *dev) { outb(0xaa, dev->path.pnp.port); } @@ -285,7 +285,7 @@ static void pnp_exit_conf_state(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void dump_pnp_device(device_t dev) +static void dump_pnp_device(struct device *dev) { int i; print_debug("\n"); diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index b1ef18a..dced0f3 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -32,18 +32,18 @@ #include "lpc47n227.h" /* Forward declarations. */ -static void enable_dev(device_t dev); -void lpc47n227_pnp_set_resources(device_t dev); -void lpc47n227_pnp_enable_resources(device_t dev); -void lpc47n227_pnp_enable(device_t dev); -static void lpc47n227_init(device_t dev); -static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource); -void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase); -void lpc47n227_pnp_set_drq(device_t dev, u8 drq); -void lpc47n227_pnp_set_irq(device_t dev, u8 irq); -void lpc47n227_pnp_set_enable(device_t dev, int enable); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); +static void enable_dev(struct device *dev); +void lpc47n227_pnp_set_resources(struct device *dev); +void lpc47n227_pnp_enable_resources(struct device *dev); +void lpc47n227_pnp_enable(struct device *dev); +static void lpc47n227_init(struct device *dev); +static void lpc47n227_pnp_set_resource(struct device *dev, struct resource *resource); +void lpc47n227_pnp_set_iobase(struct device *dev, u16 iobase); +void lpc47n227_pnp_set_drq(struct device *dev, u8 drq); +void lpc47n227_pnp_set_irq(struct device *dev, u8 irq); +void lpc47n227_pnp_set_enable(struct device *dev, int enable); +static void pnp_enter_conf_state(struct device *dev); +static void pnp_exit_conf_state(struct device *dev); struct chip_operations superio_smsc_lpc47n227_ops = { CHIP_NAME("SMSC LPC47N227 Super I/O") @@ -71,7 +71,7 @@ static struct pnp_info pnp_dev_info[] = { * * @param dev Pointer to structure describing a Super I/O device. */ -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); @@ -86,7 +86,7 @@ static void enable_dev(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -void lpc47n227_pnp_set_resources(device_t dev) +void lpc47n227_pnp_set_resources(struct device *dev) { struct resource *res; @@ -100,7 +100,7 @@ void lpc47n227_pnp_set_resources(device_t dev) * NOTE: Cannot use pnp_enable_resources() here because it assumes chip * support for logical devices, which the LPC47N227 doesn't have. */ -void lpc47n227_pnp_enable_resources(device_t dev) +void lpc47n227_pnp_enable_resources(struct device *dev) { pnp_enter_conf_state(dev); lpc47n227_pnp_set_enable(dev, 1); @@ -111,7 +111,7 @@ void lpc47n227_pnp_enable_resources(device_t dev) * NOTE: Cannot use pnp_set_enable() here because it assumes chip * support for logical devices, which the LPC47N227 doesn't have. */ -void lpc47n227_pnp_enable(device_t dev) +void lpc47n227_pnp_enable(struct device *dev) { pnp_enter_conf_state(dev); lpc47n227_pnp_set_enable(dev, !!dev->enabled); @@ -126,7 +126,7 @@ void lpc47n227_pnp_enable(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void lpc47n227_init(device_t dev) +static void lpc47n227_init(struct device *dev) { if (!dev->enabled) @@ -140,7 +140,7 @@ static void lpc47n227_init(device_t dev) } } -static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource) +static void lpc47n227_pnp_set_resource(struct device *dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", @@ -169,7 +169,7 @@ static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource) report_resource_stored(dev, resource, ""); } -void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) +void lpc47n227_pnp_set_iobase(struct device *dev, u16 iobase) { ASSERT(!(iobase & 0x3)); @@ -191,7 +191,7 @@ void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) } } -void lpc47n227_pnp_set_drq(device_t dev, u8 drq) +void lpc47n227_pnp_set_drq(struct device *dev, u8 drq) { const u8 PP_DMA_MASK = 0x0F; const u8 PP_DMA_SELECTION_REGISTER = 0x26; @@ -208,7 +208,7 @@ void lpc47n227_pnp_set_drq(device_t dev, u8 drq) } } -void lpc47n227_pnp_set_irq(device_t dev, u8 irq) +void lpc47n227_pnp_set_irq(struct device *dev, u8 irq) { u8 irq_config_register = 0, irq_config_mask = 0; u8 current_config, new_config; @@ -239,7 +239,7 @@ void lpc47n227_pnp_set_irq(device_t dev, u8 irq) pnp_write_config(dev, irq_config_register, new_config); } -void lpc47n227_pnp_set_enable(device_t dev, int enable) +void lpc47n227_pnp_set_enable(struct device *dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -276,12 +276,12 @@ void lpc47n227_pnp_set_enable(device_t dev, int enable) pnp_write_config(dev, power_register, new_power); } -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(struct device *dev) { outb(0x55, dev->path.pnp.port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(struct device *dev) { outb(0xaa, dev->path.pnp.port); } diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index bc20ed5..5e64d6d 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -30,7 +30,7 @@ #include <stdlib.h> #include "mec1308.h" -static void mec1308_init(device_t dev) +static void mec1308_init(struct device *dev) { if (!dev->enabled) @@ -62,7 +62,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, MEC1308_MBX, PNP_IO0, { 0x7ff, 0 } }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index ad8d8b4..e74c2e0 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -29,7 +29,7 @@ #include "sch4037.h" -static void sch4037_init(device_t dev) +static void sch4037_init(struct device *dev) { if (!dev->enabled) { return; @@ -55,7 +55,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index e9ed6c3..b40ec4d 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -28,7 +28,7 @@ #include "sio1036.h" -static void sio1036_init(device_t dev) +static void sio1036_init(struct device *dev) { if (!dev->enabled) { return; @@ -48,7 +48,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, SIO1036_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 92cae86..5f5b361 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -147,7 +147,7 @@ static const struct logical_devices { * * @param dev The device to use. */ -static void smsc_init(device_t dev) +static void smsc_init(struct device *dev) { int i, ld; @@ -224,7 +224,7 @@ static struct pnp_info pnp_dev_info[] = { * * @param dev The device to use. */ -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { int i, j, fn; int tmp[MAX_LOGICAL_DEVICES]; diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index fdab974..ee01cfd 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -25,7 +25,7 @@ #include <stdlib.h> #include "w83627dhg.h" -static void w83627dhg_enable_UR2(device_t dev) +static void w83627dhg_enable_UR2(struct device *dev) { u8 reg8; @@ -36,7 +36,7 @@ static void w83627dhg_enable_UR2(device_t dev) pnp_exit_conf_mode(dev); } -static void w83627dhg_init(device_t dev) +static void w83627dhg_init(struct device *dev) { if (!dev->enabled) diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index aae0ac4..73ab022 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -44,7 +44,7 @@ static u8 pnp_read_index(u16 port, u8 reg) return inb(port + 1); } -static void enable_hwm_smbus(device_t dev) +static void enable_hwm_smbus(struct device *dev) { u8 reg8; @@ -54,7 +54,7 @@ static void enable_hwm_smbus(device_t dev) pnp_write_config(dev, 0x2a, reg8); } -static void init_acpi(device_t dev) +static void init_acpi(struct device *dev) { u8 value = 0x20; /* TODO: 0x20 value here never used? */ int power_on = 1; @@ -92,7 +92,7 @@ static void init_hwm(u16 base) } } -static void w83627ehg_init(device_t dev) +static void w83627ehg_init(struct device *dev) { struct resource *res0; @@ -114,7 +114,7 @@ static void w83627ehg_init(device_t dev) } } -static void w83627ehg_pnp_enable_resources(device_t dev) +static void w83627ehg_pnp_enable_resources(struct device *dev) { pnp_enable_resources(dev); diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 5445b47..2d69fad 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -44,7 +44,7 @@ static u8 pnp_read_index(u16 port, u8 reg) return inb(port + 1); } -static void enable_hwm_smbus(device_t dev) +static void enable_hwm_smbus(struct device *dev) { u8 reg8; @@ -54,7 +54,7 @@ static void enable_hwm_smbus(device_t dev) pnp_write_config(dev, 0x2b, reg8); } -static void init_acpi(device_t dev) +static void init_acpi(struct device *dev) { u8 value = 0x20; /* FIXME: The 0x20 value here is never used? */ int power_on = 1; @@ -99,7 +99,7 @@ static void init_hwm(u16 base) } } -static void w83627hf_init(device_t dev) +static void w83627hf_init(struct device *dev) { struct resource *res0; @@ -121,7 +121,7 @@ static void w83627hf_init(device_t dev) } } -static void w83627hf_pnp_enable_resources(device_t dev) +static void w83627hf_pnp_enable_resources(struct device *dev) { pnp_enable_resources(dev); diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index 75186fa..d731933 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -29,7 +29,7 @@ #include <pc80/keyboard.h> #include "w83627thg.h" -static void w83627thg_init(device_t dev) +static void w83627thg_init(struct device *dev) { if (!dev->enabled) @@ -64,7 +64,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index f0d9aef..7e3ebdb 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -44,7 +44,7 @@ * Warning: The kernel will need to be adjusted since it assumes * a 1.8462 MHz clock. */ -static void set_uart_clock_source(device_t dev, u8 uart_clock) +static void set_uart_clock_source(struct device *dev, u8 uart_clock) { u8 value; @@ -57,7 +57,7 @@ static void set_uart_clock_source(device_t dev, u8 uart_clock) pnp_exit_conf_mode(dev); } -static void w83627uhg_init(device_t dev) +static void w83627uhg_init(struct device *dev) { if (!dev->enabled) @@ -115,7 +115,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index 9d9742c..195f941 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -50,7 +50,7 @@ static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divis } } -static void w83697hf_init(device_t dev) +static void w83697hf_init(struct device *dev) { struct resource *res0; struct superio_winbond_w83697hf_config *cfg; diff --git a/src/superio/winbond/w83977f/superio.c b/src/superio/winbond/w83977f/superio.c index 232f46a..5cc9732 100644 --- a/src/superio/winbond/w83977f/superio.c +++ b/src/superio/winbond/w83977f/superio.c @@ -28,7 +28,7 @@ #include <stdlib.h> #include "w83977f.h" -static void w83977f_init(device_t dev) +static void w83977f_init(struct device *dev) { if (!dev->enabled) @@ -62,7 +62,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83977F_GPIO2, PNP_IO0, {0x07f8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index a61770a..62be15a 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -30,7 +30,7 @@ #include <stdlib.h> #include "w83977tf.h" -static void w83977tf_init(device_t dev) +static void w83977tf_init(struct device *dev) { if (!dev->enabled) @@ -63,7 +63,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83977TF_ACPI, PNP_IRQ0, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); }

1 0

Patch merged into coreboot/master: dc878b4 include/device/device.h: Deduplicate '*_pnp_devfn_t' typedefs
by gerrit＠coreboot.org 26 Oct '14

26 Oct '14

the following patch was just integrated into master: commit dc878b45adff2f21bb209d8abdf3ccecc2dc32d8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 18:41:12 2014 +1000 include/device/device.h: Deduplicate '*_pnp_devfn_t' typedefs 'pci_devfn_t' and 'pnp_devfn_t' are already defined in arch/io.h Change-Id: I006182bf6933fae21fe6671659b76e7031e74b71 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6230 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6230 for details. -gerrit

1 0

Patch set updated for coreboot: 6eaa9ff superio/*/superio.c: Don't hide pointer types behind typedefs
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7136 -gerrit commit 6eaa9ff2fb885767a038632e6870eb913598d1f5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 21 07:43:41 2014 +1100 superio/*/superio.c: Don't hide pointer types behind typedefs Hiding pointer types behind 'typedef's is usually not a great idea at the best of times. Worse the typedef becomes an integer at different stages in Coreboot. Let us refrain from doing this at all. Change-Id: Ia2ca8c98bb489daaa58f379433875864f6efabc8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71805f/superio.c | 4 +-- src/superio/fintek/f71859/superio.c | 4 +-- src/superio/fintek/f71863fg/superio.c | 4 +-- src/superio/fintek/f71869ad/superio.c | 4 +-- src/superio/fintek/f71872/superio.c | 4 +-- src/superio/fintek/f71889/superio.c | 4 +-- src/superio/fintek/f81865f/superio.c | 4 +-- src/superio/intel/i3100/superio.c | 6 ++-- src/superio/ite/it8661f/superio.c | 2 +- src/superio/ite/it8671f/superio.c | 2 +- src/superio/ite/it8712f/superio.c | 6 ++-- src/superio/ite/it8716f/superio.c | 6 ++-- src/superio/ite/it8718f/superio.c | 2 +- src/superio/ite/it8721f/superio.c | 2 +- src/superio/ite/it8728f/superio.c | 4 +-- src/superio/ite/it8772f/superio.c | 6 ++-- src/superio/nsc/pc8374/superio.c | 2 +- src/superio/nsc/pc87309/superio.c | 2 +- src/superio/nsc/pc87351/superio.c | 2 +- src/superio/nsc/pc87360/superio.c | 2 +- src/superio/nsc/pc87366/superio.c | 2 +- src/superio/nsc/pc87382/superio.c | 2 +- src/superio/nsc/pc87392/superio.c | 2 +- src/superio/nsc/pc87417/superio.c | 2 +- src/superio/nsc/pc87427/superio.c | 2 +- src/superio/nsc/pc97307/superio.c | 2 +- src/superio/nsc/pc97317/superio.c | 2 +- src/superio/nuvoton/nct5104d/superio.c | 2 +- src/superio/nuvoton/wpcm450/superio.c | 2 +- src/superio/renesas/m3885x/superio.c | 8 +++--- src/superio/smsc/fdc37m60x/superio.c | 2 +- src/superio/smsc/kbc1100/superio.c | 8 +++--- src/superio/smsc/lpc47b272/superio.c | 12 ++++---- src/superio/smsc/lpc47b397/superio.c | 10 +++---- src/superio/smsc/lpc47m10x/superio.c | 12 ++++---- src/superio/smsc/lpc47m15x/superio.c | 8 +++--- src/superio/smsc/lpc47n217/superio.c | 50 ++++++++++++++++----------------- src/superio/smsc/lpc47n227/superio.c | 48 +++++++++++++++---------------- src/superio/smsc/mec1308/superio.c | 4 +-- src/superio/smsc/sch4037/superio.c | 4 +-- src/superio/smsc/sio1036/superio.c | 4 +-- src/superio/smsc/smscsuperio/superio.c | 4 +-- src/superio/winbond/w83627dhg/superio.c | 4 +-- src/superio/winbond/w83627ehg/superio.c | 8 +++--- src/superio/winbond/w83627hf/superio.c | 8 +++--- src/superio/winbond/w83627thg/superio.c | 4 +-- src/superio/winbond/w83627uhg/superio.c | 6 ++-- src/superio/winbond/w83697hf/superio.c | 2 +- src/superio/winbond/w83977f/superio.c | 4 +-- src/superio/winbond/w83977tf/superio.c | 4 +-- 50 files changed, 152 insertions(+), 152 deletions(-) diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index fa9608f..dc170ca 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -26,7 +26,7 @@ #include <stdlib.h> #include "f71805f.h" -static void f71805f_init(device_t dev) +static void f71805f_init(struct device * dev) { if (!dev->enabled) return; @@ -54,7 +54,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71805F_PME, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 8eca710..d1867b9 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include "f71859.h" -static void f71859_init(device_t dev) +static void f71859_init(struct device * dev) { if (!dev->enabled) return; @@ -49,7 +49,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71859_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 83ccd38..02862b1 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -27,7 +27,7 @@ #include <pc80/keyboard.h> #include "f71863fg.h" -static void f71863fg_init(device_t dev) +static void f71863fg_init(struct device * dev) { struct resource *res0; @@ -66,7 +66,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71863FG_PME, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 173713b..e4cc228 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -30,7 +30,7 @@ #include "chip.h" #include "f71869ad.h" -static void f71869ad_init(device_t dev) +static void f71869ad_init(struct device * dev) { if (!dev->enabled) return; @@ -122,7 +122,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71869AD_PME, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index c6fa7d0..505fd8f 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -27,7 +27,7 @@ #include <pc80/keyboard.h> #include "f71872.h" -static void f71872_init(device_t dev) +static void f71872_init(struct device * dev) { if (!dev->enabled) @@ -63,7 +63,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71872_PM, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f71889/superio.c b/src/superio/fintek/f71889/superio.c index 14bdd07..c782080 100644 --- a/src/superio/fintek/f71889/superio.c +++ b/src/superio/fintek/f71889/superio.c @@ -27,7 +27,7 @@ #include <pc80/keyboard.h> #include "f71889.h" -static void f71889_init(device_t dev) +static void f71889_init(struct device * dev) { if (!dev->enabled) @@ -65,7 +65,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71889_VREF, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index bfb53b4..cb341e1 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -27,7 +27,7 @@ #include <pc80/keyboard.h> #include "f81865f.h" -static void f81865f_init(device_t dev) +static void f81865f_init(struct device * dev) { if (!dev->enabled) @@ -62,7 +62,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F81865F_PME, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c index d0c5066..02fbbbf 100644 --- a/src/superio/intel/i3100/superio.c +++ b/src/superio/intel/i3100/superio.c @@ -24,19 +24,19 @@ #include "i3100.h" #include <arch/io.h> -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(struct device * dev) { outb(0x80, dev->path.pnp.port); outb(0x86, dev->path.pnp.port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(struct device * dev) { outb(0x68, dev->path.pnp.port); outb(0x08, dev->path.pnp.port); } -static void i3100_init(device_t dev) +static void i3100_init(struct device * dev) { if (!dev->enabled) return; diff --git a/src/superio/ite/it8661f/superio.c b/src/superio/ite/it8661f/superio.c index 4b7aa00..d84b37a 100644 --- a/src/superio/ite/it8661f/superio.c +++ b/src/superio/ite/it8661f/superio.c @@ -25,7 +25,7 @@ /* TODO: Add pnp_enter_ext_func_mode() etc. and wrap functions. */ -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) return; diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c index 9da8f1d..0e5fdd1 100644 --- a/src/superio/ite/it8671f/superio.c +++ b/src/superio/ite/it8671f/superio.c @@ -24,7 +24,7 @@ #include <stdlib.h> #include "it8671f.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 769afe3..ed37a2e 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -26,7 +26,7 @@ #include <stdlib.h> #include "it8712f.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(struct device * dev) { u16 port = dev->path.pnp.port; @@ -36,12 +36,12 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(struct device * dev) { pnp_write_config(dev, 0x02, 0x02); } -static void it8712f_init(device_t dev) +static void it8712f_init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index bd89a32..40764cb 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -29,7 +29,7 @@ #include <stdlib.h> #include "it8716f.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(struct device * dev) { u16 port = dev->path.pnp.port; @@ -39,7 +39,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(struct device * dev) { pnp_write_config(dev, 0x02, 0x02); } @@ -73,7 +73,7 @@ static void init_ec(u16 base) } #endif -static void it8716f_init(device_t dev) +static void it8716f_init(struct device * dev) { struct resource *res0; diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index d40407a..c0dfe19 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -24,7 +24,7 @@ #include <stdlib.h> #include "it8718f.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index 66e6ef7..56a2209 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -25,7 +25,7 @@ #include <stdlib.h> #include "it8721f.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index e689b4c..032928a 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -30,7 +30,7 @@ #include "it8728f.h" #include "it8728f_internal.h" -static void it8728f_init(device_t dev) +static void it8728f_init(struct device * dev) { if (!dev->enabled) return; @@ -68,7 +68,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, IT8728F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 38f31c0..b80e509 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -26,7 +26,7 @@ #include "chip.h" /* FIXME */ #include "it8772f.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(struct device * dev) { u16 port = dev->path.pnp.port; @@ -36,7 +36,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(struct device * dev) { pnp_write_config(dev, 0x02, 0x02); } @@ -131,7 +131,7 @@ static void it8772f_enable_fan(struct resource *res, int fan) } } -static void it8772f_init(device_t dev) +static void it8772f_init(struct device * dev) { struct superio_ite_it8772f_config *conf = dev->chip_info; struct resource *res; diff --git a/src/superio/nsc/pc8374/superio.c b/src/superio/nsc/pc8374/superio.c index 8b6f1ca..9a6c70b 100644 --- a/src/superio/nsc/pc8374/superio.c +++ b/src/superio/nsc/pc8374/superio.c @@ -28,7 +28,7 @@ #include <stdlib.h> #include "pc8374.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index f374e6a..13e00f0 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -25,7 +25,7 @@ #include <stdlib.h> #include "pc87309.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87351/superio.c b/src/superio/nsc/pc87351/superio.c index 7f395b4..67bd4b3 100644 --- a/src/superio/nsc/pc87351/superio.c +++ b/src/superio/nsc/pc87351/superio.c @@ -28,7 +28,7 @@ #include <stdlib.h> #include "pc87351.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index a53cc35..9834af1 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -28,7 +28,7 @@ #include <stdlib.h> #include "pc87360.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index 27bdd6e..b6a2dbd 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -28,7 +28,7 @@ #include <stdlib.h> #include "pc87366.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 3c0cda0..290d572 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include "pc87382.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) return; diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index d67539f..718088f 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -26,7 +26,7 @@ #include <stdlib.h> #include "pc87392.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) return; diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index 99882a5..16c2343 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -29,7 +29,7 @@ #include <stdlib.h> #include "pc87417.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc87427/superio.c b/src/superio/nsc/pc87427/superio.c index 170fd85..ce1e7ab 100644 --- a/src/superio/nsc/pc87427/superio.c +++ b/src/superio/nsc/pc87427/superio.c @@ -28,7 +28,7 @@ #include <pc80/keyboard.h> #include "pc87427.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/nsc/pc97307/superio.c b/src/superio/nsc/pc97307/superio.c index 6b15901..aa072da 100644 --- a/src/superio/nsc/pc97307/superio.c +++ b/src/superio/nsc/pc97307/superio.c @@ -26,7 +26,7 @@ #include <pc80/keyboard.h> #include "pc97307.h" -static void init(device_t dev) +static void init(struct device * dev) { u8 reg8; diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index 09c3b5e..3882b00 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -26,7 +26,7 @@ #include <pc80/keyboard.h> #include "pc97317.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index c2a744f..d47631f 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -25,7 +25,7 @@ #include "nct5104d.h" #include "chip.h" -static void nct5104d_init(device_t dev) +static void nct5104d_init(struct device * dev) { struct superio_nuvoton_nct5104d_config *conf = dev->chip_info; u8 reg10, reg11, reg26; diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index ff815cf..9f4bbdc 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include "wpcm450.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 17bdadf..8a10801 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -29,7 +29,7 @@ void m3885_configure_multikey(void); -static void m3885x_init(device_t dev) +static void m3885x_init(struct device * dev) { if (!dev->enabled) @@ -41,12 +41,12 @@ static void m3885x_init(device_t dev) m3885_configure_multikey(); } -static void m3885x_read_resources(device_t dev) +static void m3885x_read_resources(struct device * dev) { /* Nothing, but this function avoids an error on serial console. */ } -static void m3885x_enable_resources(device_t dev) +static void m3885x_enable_resources(struct device * dev) { /* Nothing, but this function avoids an error on serial console. */ } @@ -61,7 +61,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/smsc/fdc37m60x/superio.c b/src/superio/smsc/fdc37m60x/superio.c index f5626ee..9b018e6 100644 --- a/src/superio/smsc/fdc37m60x/superio.c +++ b/src/superio/smsc/fdc37m60x/superio.c @@ -24,7 +24,7 @@ #include <stdlib.h> #include "fdc37m60x.h" -static void init(device_t dev) +static void init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index 77777d0..f0e3583 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -31,8 +31,8 @@ #include "kbc1100.h" /* Forward declarations */ -static void enable_dev(device_t dev); -static void kbc1100_init(device_t dev); +static void enable_dev(struct device * dev); +static void kbc1100_init(struct device * dev); struct chip_operations superio_smsc_kbc1100_ops = { CHIP_NAME("SMSC KBC1100 Super I/O") @@ -52,12 +52,12 @@ static struct pnp_info pnp_dev_info[] = { { &ops, KBC1100_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -static void kbc1100_init(device_t dev) +static void kbc1100_init(struct device * dev) { struct resource *res0, *res1; diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 30e89a8..1233a6d 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -35,9 +35,9 @@ #include "lpc47b272.h" /* Forward declarations */ -static void enable_dev(device_t dev); -static void lpc47b272_init(device_t dev); -// static void dump_pnp_device(device_t dev); +static void enable_dev(struct device * dev); +static void lpc47b272_init(struct device * dev); +// static void dump_pnp_device(struct device * dev); struct chip_operations superio_smsc_lpc47b272_ops = { CHIP_NAME("SMSC LPC47B272 Super I/O") @@ -68,7 +68,7 @@ static struct pnp_info pnp_dev_info[] = { * * @param dev Pointer to structure describing a Super I/O device. */ -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); @@ -82,7 +82,7 @@ static void enable_dev(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void lpc47b272_init(device_t dev) +static void lpc47b272_init(struct device * dev) { if (!dev->enabled) @@ -103,7 +103,7 @@ static void lpc47b272_init(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void dump_pnp_device(device_t dev) +static void dump_pnp_device(struct device * dev) { int i; print_debug("\n"); diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 8a6c03e..7f9c9f5 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -43,7 +43,7 @@ static u8 pnp_read_index(u16 port, u8 reg) return inb(port + 1); } -static void enable_hwm_smbus(device_t dev) +static void enable_hwm_smbus(struct device * dev) { /* Enable SensorBus register access. */ u8 reg8; @@ -53,7 +53,7 @@ static void enable_hwm_smbus(device_t dev) pnp_write_config(dev, 0xf0, reg8); } -static void lpc47b397_init(device_t dev) +static void lpc47b397_init(struct device * dev) { if (!dev->enabled) @@ -66,7 +66,7 @@ static void lpc47b397_init(device_t dev) } } -static void lpc47b397_pnp_enable_resources(device_t dev) +static void lpc47b397_pnp_enable_resources(struct device * dev) { pnp_enable_resources(dev); @@ -99,7 +99,7 @@ static struct device_operations ops = { #define SB_DATA2 0x0e #define SB_DATA3 0x0f -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned int device; struct resource *res; @@ -117,7 +117,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return result; } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned int device; struct resource *res; diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index a9583e4..4bd8587 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -34,9 +34,9 @@ #include "lpc47m10x.h" /* Forward declarations */ -static void enable_dev(device_t dev); -static void lpc47m10x_init(device_t dev); -// static void dump_pnp_device(device_t dev); +static void enable_dev(struct device * dev); +static void lpc47m10x_init(struct device * dev); +// static void dump_pnp_device(struct device * dev); struct chip_operations superio_smsc_lpc47m10x_ops = { CHIP_NAME("SMSC LPC47M10x Super I/O") @@ -67,7 +67,7 @@ static struct pnp_info pnp_dev_info[] = { * * @param dev Pointer to structure describing a Super I/O device. */ -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); @@ -81,7 +81,7 @@ static void enable_dev(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void lpc47m10x_init(device_t dev) +static void lpc47m10x_init(struct device * dev) { if (!dev->enabled) @@ -102,7 +102,7 @@ static void lpc47m10x_init(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void dump_pnp_device(device_t dev) +static void dump_pnp_device(struct device * dev) { int i; print_debug("\n"); diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 91e77ba..cec839f 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -31,8 +31,8 @@ #include "lpc47m15x.h" /* Forward declarations */ -static void enable_dev(device_t dev); -static void lpc47m15x_init(device_t dev); +static void enable_dev(struct device * dev); +static void lpc47m15x_init(struct device * dev); struct chip_operations superio_smsc_lpc47m15x_ops = { CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O") @@ -56,13 +56,13 @@ static struct pnp_info pnp_dev_info[] = { { &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -static void lpc47m15x_init(device_t dev) +static void lpc47m15x_init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index 0b470f6..554a107 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -34,18 +34,18 @@ #include "lpc47n217.h" /* Forward declarations */ -static void enable_dev(device_t dev); -static void lpc47n217_pnp_set_resources(device_t dev); -static void lpc47n217_pnp_enable_resources(device_t dev); -static void lpc47n217_pnp_enable(device_t dev); -static void lpc47n217_init(device_t dev); -static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource); -static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase); -static void lpc47n217_pnp_set_drq(device_t dev, u8 drq); -static void lpc47n217_pnp_set_irq(device_t dev, u8 irq); -static void lpc47n217_pnp_set_enable(device_t dev, int enable); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); +static void enable_dev(struct device * dev); +static void lpc47n217_pnp_set_resources(struct device * dev); +static void lpc47n217_pnp_enable_resources(struct device * dev); +static void lpc47n217_pnp_enable(struct device * dev); +static void lpc47n217_init(struct device * dev); +static void lpc47n217_pnp_set_resource(struct device * dev, struct resource *resource); +static void lpc47n217_pnp_set_iobase(struct device * dev, u16 iobase); +static void lpc47n217_pnp_set_drq(struct device * dev, u8 drq); +static void lpc47n217_pnp_set_irq(struct device * dev, u8 irq); +static void lpc47n217_pnp_set_enable(struct device * dev, int enable); +static void pnp_enter_conf_state(struct device * dev); +static void pnp_exit_conf_state(struct device * dev); struct chip_operations superio_smsc_lpc47n217_ops = { CHIP_NAME("SMSC LPC47N217 Super I/O") @@ -72,7 +72,7 @@ static struct pnp_info pnp_dev_info[] = { * * @param dev Pointer to structure describing a Super I/O device. */ -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); @@ -87,7 +87,7 @@ static void enable_dev(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void lpc47n217_pnp_set_resources(device_t dev) +static void lpc47n217_pnp_set_resources(struct device * dev) { struct resource *res; @@ -102,7 +102,7 @@ static void lpc47n217_pnp_set_resources(device_t dev) * NOTE: Cannot use pnp_enable_resources() here because it assumes chip * support for logical devices, which the LPC47N217 doesn't have. */ -static void lpc47n217_pnp_enable_resources(device_t dev) +static void lpc47n217_pnp_enable_resources(struct device * dev) { pnp_enter_conf_state(dev); lpc47n217_pnp_set_enable(dev, 1); @@ -113,7 +113,7 @@ static void lpc47n217_pnp_enable_resources(device_t dev) * NOTE: Cannot use pnp_set_enable() here because it assumes chip * support for logical devices, which the LPC47N217 doesn't have. */ -static void lpc47n217_pnp_enable(device_t dev) +static void lpc47n217_pnp_enable(struct device * dev) { pnp_enter_conf_state(dev); lpc47n217_pnp_set_enable(dev, !!dev->enabled); @@ -128,13 +128,13 @@ static void lpc47n217_pnp_enable(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void lpc47n217_init(device_t dev) +static void lpc47n217_init(struct device * dev) { if (!dev->enabled) return; } -static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) +static void lpc47n217_pnp_set_resource(struct device * dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", @@ -164,7 +164,7 @@ static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) report_resource_stored(dev, resource, ""); } -static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n217_pnp_set_iobase(struct device * dev, u16 iobase) { ASSERT(!(iobase & 0x3)); @@ -184,7 +184,7 @@ static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) } } -static void lpc47n217_pnp_set_drq(device_t dev, u8 drq) +static void lpc47n217_pnp_set_drq(struct device * dev, u8 drq) { const u8 PP_DMA_MASK = 0x0F; const u8 PP_DMA_SELECTION_REGISTER = 0x26; @@ -201,7 +201,7 @@ static void lpc47n217_pnp_set_drq(device_t dev, u8 drq) } } -static void lpc47n217_pnp_set_irq(device_t dev, u8 irq) +static void lpc47n217_pnp_set_irq(struct device * dev, u8 irq) { u8 irq_config_register = 0, irq_config_mask = 0; u8 current_config, new_config; @@ -232,7 +232,7 @@ static void lpc47n217_pnp_set_irq(device_t dev, u8 irq) pnp_write_config(dev, irq_config_register, new_config); } -static void lpc47n217_pnp_set_enable(device_t dev, int enable) +static void lpc47n217_pnp_set_enable(struct device * dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -267,12 +267,12 @@ static void lpc47n217_pnp_set_enable(device_t dev, int enable) pnp_write_config(dev, power_register, new_power); } -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(struct device * dev) { outb(0x55, dev->path.pnp.port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(struct device * dev) { outb(0xaa, dev->path.pnp.port); } @@ -285,7 +285,7 @@ static void pnp_exit_conf_state(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void dump_pnp_device(device_t dev) +static void dump_pnp_device(struct device * dev) { int i; print_debug("\n"); diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index b1ef18a..beb6314 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -32,18 +32,18 @@ #include "lpc47n227.h" /* Forward declarations. */ -static void enable_dev(device_t dev); -void lpc47n227_pnp_set_resources(device_t dev); -void lpc47n227_pnp_enable_resources(device_t dev); -void lpc47n227_pnp_enable(device_t dev); -static void lpc47n227_init(device_t dev); -static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource); -void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase); -void lpc47n227_pnp_set_drq(device_t dev, u8 drq); -void lpc47n227_pnp_set_irq(device_t dev, u8 irq); -void lpc47n227_pnp_set_enable(device_t dev, int enable); -static void pnp_enter_conf_state(device_t dev); -static void pnp_exit_conf_state(device_t dev); +static void enable_dev(struct device * dev); +void lpc47n227_pnp_set_resources(struct device * dev); +void lpc47n227_pnp_enable_resources(struct device * dev); +void lpc47n227_pnp_enable(struct device * dev); +static void lpc47n227_init(struct device * dev); +static void lpc47n227_pnp_set_resource(struct device * dev, struct resource *resource); +void lpc47n227_pnp_set_iobase(struct device * dev, u16 iobase); +void lpc47n227_pnp_set_drq(struct device * dev, u8 drq); +void lpc47n227_pnp_set_irq(struct device * dev, u8 irq); +void lpc47n227_pnp_set_enable(struct device * dev, int enable); +static void pnp_enter_conf_state(struct device * dev); +static void pnp_exit_conf_state(struct device * dev); struct chip_operations superio_smsc_lpc47n227_ops = { CHIP_NAME("SMSC LPC47N227 Super I/O") @@ -71,7 +71,7 @@ static struct pnp_info pnp_dev_info[] = { * * @param dev Pointer to structure describing a Super I/O device. */ -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); @@ -86,7 +86,7 @@ static void enable_dev(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -void lpc47n227_pnp_set_resources(device_t dev) +void lpc47n227_pnp_set_resources(struct device * dev) { struct resource *res; @@ -100,7 +100,7 @@ void lpc47n227_pnp_set_resources(device_t dev) * NOTE: Cannot use pnp_enable_resources() here because it assumes chip * support for logical devices, which the LPC47N227 doesn't have. */ -void lpc47n227_pnp_enable_resources(device_t dev) +void lpc47n227_pnp_enable_resources(struct device * dev) { pnp_enter_conf_state(dev); lpc47n227_pnp_set_enable(dev, 1); @@ -111,7 +111,7 @@ void lpc47n227_pnp_enable_resources(device_t dev) * NOTE: Cannot use pnp_set_enable() here because it assumes chip * support for logical devices, which the LPC47N227 doesn't have. */ -void lpc47n227_pnp_enable(device_t dev) +void lpc47n227_pnp_enable(struct device * dev) { pnp_enter_conf_state(dev); lpc47n227_pnp_set_enable(dev, !!dev->enabled); @@ -126,7 +126,7 @@ void lpc47n227_pnp_enable(device_t dev) * * @param dev Pointer to structure describing a Super I/O device. */ -static void lpc47n227_init(device_t dev) +static void lpc47n227_init(struct device * dev) { if (!dev->enabled) @@ -140,7 +140,7 @@ static void lpc47n227_init(device_t dev) } } -static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource) +static void lpc47n227_pnp_set_resource(struct device * dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", @@ -169,7 +169,7 @@ static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource) report_resource_stored(dev, resource, ""); } -void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) +void lpc47n227_pnp_set_iobase(struct device * dev, u16 iobase) { ASSERT(!(iobase & 0x3)); @@ -191,7 +191,7 @@ void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) } } -void lpc47n227_pnp_set_drq(device_t dev, u8 drq) +void lpc47n227_pnp_set_drq(struct device * dev, u8 drq) { const u8 PP_DMA_MASK = 0x0F; const u8 PP_DMA_SELECTION_REGISTER = 0x26; @@ -208,7 +208,7 @@ void lpc47n227_pnp_set_drq(device_t dev, u8 drq) } } -void lpc47n227_pnp_set_irq(device_t dev, u8 irq) +void lpc47n227_pnp_set_irq(struct device * dev, u8 irq) { u8 irq_config_register = 0, irq_config_mask = 0; u8 current_config, new_config; @@ -239,7 +239,7 @@ void lpc47n227_pnp_set_irq(device_t dev, u8 irq) pnp_write_config(dev, irq_config_register, new_config); } -void lpc47n227_pnp_set_enable(device_t dev, int enable) +void lpc47n227_pnp_set_enable(struct device * dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -276,12 +276,12 @@ void lpc47n227_pnp_set_enable(device_t dev, int enable) pnp_write_config(dev, power_register, new_power); } -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(struct device * dev) { outb(0x55, dev->path.pnp.port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(struct device * dev) { outb(0xaa, dev->path.pnp.port); } diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index bc20ed5..2854735 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -30,7 +30,7 @@ #include <stdlib.h> #include "mec1308.h" -static void mec1308_init(device_t dev) +static void mec1308_init(struct device * dev) { if (!dev->enabled) @@ -62,7 +62,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, MEC1308_MBX, PNP_IO0, { 0x7ff, 0 } }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index ad8d8b4..819fd8b 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -29,7 +29,7 @@ #include "sch4037.h" -static void sch4037_init(device_t dev) +static void sch4037_init(struct device * dev) { if (!dev->enabled) { return; @@ -55,7 +55,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index e9ed6c3..4688c49 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -28,7 +28,7 @@ #include "sio1036.h" -static void sio1036_init(device_t dev) +static void sio1036_init(struct device * dev) { if (!dev->enabled) { return; @@ -48,7 +48,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, SIO1036_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 92cae86..13f0cbb 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -147,7 +147,7 @@ static const struct logical_devices { * * @param dev The device to use. */ -static void smsc_init(device_t dev) +static void smsc_init(struct device * dev) { int i, ld; @@ -224,7 +224,7 @@ static struct pnp_info pnp_dev_info[] = { * * @param dev The device to use. */ -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { int i, j, fn; int tmp[MAX_LOGICAL_DEVICES]; diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index fdab974..cb61c49 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -25,7 +25,7 @@ #include <stdlib.h> #include "w83627dhg.h" -static void w83627dhg_enable_UR2(device_t dev) +static void w83627dhg_enable_UR2(struct device * dev) { u8 reg8; @@ -36,7 +36,7 @@ static void w83627dhg_enable_UR2(device_t dev) pnp_exit_conf_mode(dev); } -static void w83627dhg_init(device_t dev) +static void w83627dhg_init(struct device * dev) { if (!dev->enabled) diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index aae0ac4..6f4f13e 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -44,7 +44,7 @@ static u8 pnp_read_index(u16 port, u8 reg) return inb(port + 1); } -static void enable_hwm_smbus(device_t dev) +static void enable_hwm_smbus(struct device * dev) { u8 reg8; @@ -54,7 +54,7 @@ static void enable_hwm_smbus(device_t dev) pnp_write_config(dev, 0x2a, reg8); } -static void init_acpi(device_t dev) +static void init_acpi(struct device * dev) { u8 value = 0x20; /* TODO: 0x20 value here never used? */ int power_on = 1; @@ -92,7 +92,7 @@ static void init_hwm(u16 base) } } -static void w83627ehg_init(device_t dev) +static void w83627ehg_init(struct device * dev) { struct resource *res0; @@ -114,7 +114,7 @@ static void w83627ehg_init(device_t dev) } } -static void w83627ehg_pnp_enable_resources(device_t dev) +static void w83627ehg_pnp_enable_resources(struct device * dev) { pnp_enable_resources(dev); diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 5445b47..37fbb32 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -44,7 +44,7 @@ static u8 pnp_read_index(u16 port, u8 reg) return inb(port + 1); } -static void enable_hwm_smbus(device_t dev) +static void enable_hwm_smbus(struct device * dev) { u8 reg8; @@ -54,7 +54,7 @@ static void enable_hwm_smbus(device_t dev) pnp_write_config(dev, 0x2b, reg8); } -static void init_acpi(device_t dev) +static void init_acpi(struct device * dev) { u8 value = 0x20; /* FIXME: The 0x20 value here is never used? */ int power_on = 1; @@ -99,7 +99,7 @@ static void init_hwm(u16 base) } } -static void w83627hf_init(device_t dev) +static void w83627hf_init(struct device * dev) { struct resource *res0; @@ -121,7 +121,7 @@ static void w83627hf_init(device_t dev) } } -static void w83627hf_pnp_enable_resources(device_t dev) +static void w83627hf_pnp_enable_resources(struct device * dev) { pnp_enable_resources(dev); diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index 75186fa..f94a4d4 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -29,7 +29,7 @@ #include <pc80/keyboard.h> #include "w83627thg.h" -static void w83627thg_init(device_t dev) +static void w83627thg_init(struct device * dev) { if (!dev->enabled) @@ -64,7 +64,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index f0d9aef..ed8f38f 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -44,7 +44,7 @@ * Warning: The kernel will need to be adjusted since it assumes * a 1.8462 MHz clock. */ -static void set_uart_clock_source(device_t dev, u8 uart_clock) +static void set_uart_clock_source(struct device * dev, u8 uart_clock) { u8 value; @@ -57,7 +57,7 @@ static void set_uart_clock_source(device_t dev, u8 uart_clock) pnp_exit_conf_mode(dev); } -static void w83627uhg_init(device_t dev) +static void w83627uhg_init(struct device * dev) { if (!dev->enabled) @@ -115,7 +115,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index 9d9742c..b8c50f8 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -50,7 +50,7 @@ static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divis } } -static void w83697hf_init(device_t dev) +static void w83697hf_init(struct device * dev) { struct resource *res0; struct superio_winbond_w83697hf_config *cfg; diff --git a/src/superio/winbond/w83977f/superio.c b/src/superio/winbond/w83977f/superio.c index 232f46a..562098a 100644 --- a/src/superio/winbond/w83977f/superio.c +++ b/src/superio/winbond/w83977f/superio.c @@ -28,7 +28,7 @@ #include <stdlib.h> #include "w83977f.h" -static void w83977f_init(device_t dev) +static void w83977f_init(struct device * dev) { if (!dev->enabled) @@ -62,7 +62,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83977F_GPIO2, PNP_IO0, {0x07f8, 0}, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index a61770a..06e7765 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -30,7 +30,7 @@ #include <stdlib.h> #include "w83977tf.h" -static void w83977tf_init(device_t dev) +static void w83977tf_init(struct device * dev) { if (!dev->enabled) @@ -63,7 +63,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83977TF_ACPI, PNP_IRQ0, }, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); }

1 0

Patch set updated for coreboot: 9a83f01 southbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7169 -gerrit commit 9a83f01d67bdd92db44db1df7ff5161df3ffa9ad Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Oct 23 02:09:00 2014 +1100 southbridge: Don't hide pointers behind typedefs Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively. Change-Id: Id6c221cc36a2b89db7b11796d947136bac76e565 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/spi.c | 2 +- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 14 +++++++------- src/southbridge/amd/sb700/early_setup.c | 18 +++++++++--------- src/southbridge/broadcom/bcm5780/nic.c | 2 +- src/southbridge/broadcom/bcm5780/pcix.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/bcm5785.h | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/broadcom/bcm5785/ide.c | 4 ++-- src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------ src/southbridge/broadcom/bcm5785/sata.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 14 +++++++------- src/southbridge/broadcom/bcm5785/usb.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 10 +++++----- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- src/southbridge/nvidia/ck804/ck804.c | 10 +++++----- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/ck804/smbus.c | 8 ++++---- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55.h | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------ src/southbridge/sis/sis966/early_ctrl.c | 2 +- src/southbridge/via/vt8231/early_serial.c | 2 +- src/southbridge/via/vt82c686/early_serial.c | 4 ++-- 31 files changed, 96 insertions(+), 96 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index bbf6dd3..ce22d34 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -86,7 +86,7 @@ static void execute_command(void) void spi_init(void) { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..b606352 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -69,7 +69,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648ed..0341567 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -33,7 +33,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index f38e691..86e4f89 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -53,7 +53,7 @@ static void execute_command(void) void spi_init() { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b6611f6..e412217 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg) /* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { @@ -67,7 +67,7 @@ static void sb600_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -196,7 +196,7 @@ void soft_reset(void) void sb600_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -241,7 +241,7 @@ void sb600_pci_port80(void) void sb600_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -260,7 +260,7 @@ void sb600_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; printk(BIOS_INFO, "sb600_devices_por_init()\n"); @@ -520,7 +520,7 @@ static void sb600_pmio_por_init(void) */ static void sb600_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index b7a5e77..90dbfa8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -79,7 +79,7 @@ static void sb700_acpi_init(void) /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id, enable_14Mhz, byte; u8 rev = 0; @@ -136,7 +136,7 @@ void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -195,7 +195,7 @@ void sb7xx_51xx_lpc_init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -208,7 +208,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 __attribute__ ((weak)) get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -290,7 +290,7 @@ void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) void sb7xx_51xx_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -335,7 +335,7 @@ void sb7xx_51xx_pci_port80(void) void sb7xx_51xx_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -354,7 +354,7 @@ void sb7xx_51xx_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb700_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; @@ -607,7 +607,7 @@ static void sb700_pmio_por_init(void) */ static void sb700_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index df59fdc..5fd56dd 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 92a3547..96d0ace 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 1675097..822b3ba 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -24,10 +24,10 @@ #include <device/pci_ids.h> #include "bcm5785.h" -void bcm5785_enable(device_t dev) +void bcm5785_enable(struct device * dev) { - device_t sb_pci_main_dev; - device_t bus_dev; + struct device * sb_pci_main_dev; + struct device * bus_dev; // unsigned index; /* See if we are on the behind the pcix bridge */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index bc3280f..5eb2f05 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -24,7 +24,7 @@ #include "chip.h" #ifndef __PRE_RAM__ -void bcm5785_enable(device_t dev); +void bcm5785_enable(struct device * dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..fe0fded 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -24,7 +24,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); @@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void) static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; @@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -134,7 +134,7 @@ void soft_reset(void) static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -162,7 +162,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev; //F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..200da09 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -24,7 +24,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 3426a2c..948fef0 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> #include "bcm5785.h" -static void bcm5785_ide_read_resources(device_t dev) +static void bcm5785_ide_read_resources(struct device * dev) { /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -40,7 +40,7 @@ static void ide_init(struct device *dev) { } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index af79892..5cf1376 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -30,7 +30,7 @@ #include <arch/ioapic.h> #include "bcm5785.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { /* Initialize the real time clock */ cmos_init(0); @@ -39,7 +39,7 @@ static void lpc_init(device_t dev) isa_dma_init(); } -static void bcm5785_lpc_read_resources(device_t dev) +static void bcm5785_lpc_read_resources(struct device * dev) { struct resource *res; @@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void bcm5785_lpc_enable_childrens_resources(device_t dev) +static void bcm5785_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; uint32_t reg; @@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } -static void bcm5785_lpc_enable_resources(device_t dev) +static void bcm5785_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); bcm5785_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..ddcb44c 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -73,7 +73,7 @@ static void sata_init(struct device *dev) } } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..0e42863 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -33,7 +33,7 @@ #define NMI_OFF 0 -static void sb_init(device_t dev) +static void sb_init(struct device * dev) { uint8_t byte; uint8_t byte_old; @@ -56,7 +56,7 @@ static void sb_init(device_t dev) } -static void bcm5785_sb_read_resources(device_t dev) +static void bcm5785_sb_read_resources(struct device * dev) { struct resource *res; @@ -76,7 +76,7 @@ static void bcm5785_sb_read_resources(device_t dev) } -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(struct device * dev, uint8_t val) { unsigned device; struct resource *res; @@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(struct device * dev, uint8_t address) { unsigned device; struct resource *res; @@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(struct device * dev, uint8_t address, uint8_t val) { unsigned device; struct resource *res; @@ -139,7 +139,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..b9c2452 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -37,7 +37,7 @@ static void usb_init(struct device *dev) } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d4f263b..b65fd11 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -95,7 +95,7 @@ static const unsigned char irq_to_int_routing[16] = { /* keyboard controller system flag timeout : 400 ms */ #define KBC_TIMEOUT_SYS_FLAG 400 -static u8 get_pci_dev_func(device_t dev) +static u8 get_pci_dev_func(struct device * dev) { return PCI_FUNC(dev->path.pci.devfn); } @@ -182,7 +182,7 @@ static void pci_routing_fixup(struct device *dev) /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */ for (i = 0; i < slot_num; i++) { unsigned int funct; - device_t pdev; + struct device * pdev; u8 irq; /* Each slot may contain up to eight functions. */ @@ -515,7 +515,7 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) +static void vortex86_sb_set_io_resv(struct device * dev, unsigned index, u32 base, u32 size) { struct resource *res; res = new_resource(dev, index); @@ -525,7 +525,7 @@ static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(struct device * dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; @@ -536,7 +536,7 @@ static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 fla res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void vortex86_sb_read_resources(device_t dev) +static void vortex86_sb_read_resources(struct device * dev) { u32 flash_size = 8 * 1024 * 1024; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 2ea9a24..e5783e7 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -322,7 +322,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev; + struct device * dev; ich9_spi_regs *ich9_spi; uint16_t hsfs; diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 6df99fd..c4e8a1c 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -370,7 +370,7 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - device_t dev; + struct device * dev; uint32_t ids; uint16_t vendor_id, device_id; diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..a285938 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -28,9 +28,9 @@ static u32 final_reg; -static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); if (!lpc_dev) @@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; } -void ck804_enable(device_t dev) +void ck804_enable(struct device * dev) { - device_t lpc_dev; + struct device * lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -188,7 +188,7 @@ void ck804_enable(device_t dev) } } -static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 9b6049c..a48401f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device * dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev) #endif } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev); } -static void rom_dummy_write(device_t dev) +static void rom_dummy_write(struct device * dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev) unsigned pm_base = 0; -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(device_t dev) rom_dummy_write(dev); } -static void ck804_lpc_read_resources(device_t dev) +static void ck804_lpc_read_resources(struct device * dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev) } } -static void ck804_lpc_set_resources(device_t dev) +static void ck804_lpc_set_resources(struct device * dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(device_t dev) +static void ck804_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void ck804_lpc_enable_resources(device_t dev) +static void ck804_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..62967bf 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -28,7 +28,7 @@ #include "ck804.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..954e305 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,7 +254,7 @@ static void azalia_init(struct device *dev) } } -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 11c2c4f..ebf2a01 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev, int master) +static void lpc_common_init(struct device * dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master) clear_ioapic(ioapic_base); } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(device_t dev) enable_hpet(dev); } -static void mcp55_lpc_read_resources(device_t dev) +static void mcp55_lpc_read_resources(struct device * dev) { struct resource *res; @@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(device_t dev) +static void mcp55_lpc_enable_childrens_resources(struct device * dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void mcp55_lpc_enable_resources(device_t dev) +static void mcp55_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 4fb3391..20b33b4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,7 +30,7 @@ #ifndef __PRE_RAM__ #include "chip.h" -void mcp55_enable(device_t dev); +void mcp55_enable(struct device * dev); extern struct pci_operations mcp55_pci_ops; #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3e0b87e..e28a896 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -31,7 +31,7 @@ #include "mcp55.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = { unsigned pm_base; #endif -static void mcp55_sm_read_resources(device_t dev) +static void mcp55_sm_read_resources(struct device * dev) { unsigned long index; @@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev) compact_resources(dev); } -static void mcp55_sm_init(device_t dev) +static void mcp55_sm_init(struct device * dev) { #if CONFIG_HAVE_ACPI_TABLES struct resource *res; diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus( diff --git a/src/southbridge/via/vt8231/early_serial.c b/src/southbridge/via/vt8231/early_serial.c index a0aec65..8c500b9 100644 --- a/src/southbridge/via/vt8231/early_serial.c +++ b/src/southbridge/via/vt8231/early_serial.c @@ -33,7 +33,7 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val) static void enable_vt8231_serial(void) { uint8_t c; - device_t dev; + pnp_devfn_t dev; post_code(0x06); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c index 55742a7..9cdf943 100644 --- a/src/southbridge/via/vt82c686/early_serial.c +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -48,10 +48,10 @@ static void vt82c686_sio_write(uint8_t index, uint8_t value) * @param dev TODO * @param iobase TODO */ -static void vt82c686_enable_serial(device_t dev, unsigned iobase) +static void vt82c686_enable_serial(pnp_devfn_t dev, unsigned iobase) { uint8_t reg; - device_t sbdev; + pnp_devfn_t sbdev; /* TODO: Use info from 'dev' and 'iobase'. */ /* TODO: Only enable one serial port (depending on config) or both? */

1 0

Patch set updated for coreboot: 58dd1f2 NOTFORMERGE: fix reset.c
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7196 -gerrit commit 58dd1f25ebc38bef8f16366aa69e9d42797c26c0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:36:02 2014 +1100 NOTFORMERGE: fix reset.c Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/amd8111/reset.c | 14 ++++++-------- src/southbridge/broadcom/bcm5785/reset.c | 6 ++---- src/southbridge/nvidia/ck804/reset.c | 6 ++---- src/southbridge/nvidia/mcp55/reset.c | 6 ++---- src/southbridge/sis/sis966/reset.c | 6 ++---- 5 files changed, 14 insertions(+), 24 deletions(-) diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index c96e898..8824550 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -10,9 +10,7 @@ #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -typedef unsigned device_t; - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) { unsigned addr; addr = (dev>>4) | where; @@ -20,7 +18,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value) outb(value, 0xCFC + (addr & 3)); } -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -28,7 +26,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; @@ -37,9 +35,9 @@ static unsigned pci_read_config32(device_t dev, unsigned where) } #define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); for(; dev <= last; dev += PCI_DEV(0,0,1)) { @@ -57,7 +55,7 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) void hard_reset(void) { - device_t dev; + pci_devfn_t dev; unsigned bus; unsigned node = 0; unsigned link = get_sblk(); diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 51ba6ec..b34cc86 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index a241966..53c0c40 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev >> 4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev >> 4) | where; diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/sis/sis966/reset.c +++ b/src/southbridge/sis/sis966/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where;

1 0

Patch set updated for coreboot: b479d28 soutbridge/*/bootblock: Use pci_dev_t over device_t typedef
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7193 -gerrit commit b479d28df4523fb445f0e8a21457698da2b9cff8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:12:15 2014 +1100 soutbridge/*/bootblock: Use pci_dev_t over device_t typedef Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/bootblock.c | 2 +- src/southbridge/amd/amd8111/bootblock.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/bootblock.c | 6 +++--- src/southbridge/amd/cimx/sb900/bootblock.c | 2 +- src/southbridge/amd/sb600/bootblock.c | 2 +- src/southbridge/amd/sb700/bootblock.c | 2 +- src/southbridge/amd/sb800/bootblock.c | 2 +- src/southbridge/broadcom/bcm5785/bootblock.c | 2 +- src/southbridge/intel/bd82x6x/bootblock.c | 4 ++-- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 4 ++-- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82801gx/bootblock.c | 2 +- src/southbridge/intel/i82801ix/bootblock.c | 2 +- src/southbridge/intel/lynxpoint/bootblock.c | 4 ++-- src/southbridge/nvidia/ck804/bootblock.c | 2 +- src/southbridge/nvidia/mcp55/bootblock.c | 2 +- src/southbridge/sis/sis966/bootblock.c | 2 +- src/southbridge/via/vt8237r/bootblock.c | 2 +- 19 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 65810fa..3cdba8b 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -33,7 +33,7 @@ static void hudson_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index ba3dc43..4c00989 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -26,7 +26,7 @@ static void amd8111_enable_rom(void) { u8 byte; - device_t dev; + pci_devfn_t dev; dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), 0); diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 1027659..4ddfb92 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -24,7 +24,7 @@ static void sb700_enable_rom(void) { u32 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB700 LPC Bridge 0:20:3:44h. diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 4fd2739..188ba29 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -23,7 +23,7 @@ static void enable_rom(void) { u16 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB800 LPC Bridge 0:20:3:44h. @@ -57,7 +57,7 @@ static void enable_rom(void) static void enable_prefetch(void) { u32 dword; - device_t dev = PCI_DEV(0, 0x14, 0x03); + pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* Enable PrefetchEnSPIFromHost */ dword = pci_io_read_config32(dev, 0xb8); @@ -67,7 +67,7 @@ static void enable_prefetch(void) static void enable_spi_fast_mode(void) { u32 dword; - device_t dev = PCI_DEV(0, 0x14, 0x03); + pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 9108a8b..561904e 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -23,7 +23,7 @@ static void sb900_enable_rom(void) { u32 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB900 LPC Bridge 0:20:3:44h. diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index e31a96c..94f5e6e 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -34,7 +34,7 @@ static void sb600_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_LPC), 0); diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index c290806..67da3fa 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -35,7 +35,7 @@ static void sb700_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 9311b97..61ff284 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -33,7 +33,7 @@ static void sb800_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 166464c..3c1d39c 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -26,7 +26,7 @@ static void bcm5785_enable_rom(void) { u8 byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 85a940e..b1b53af 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -38,7 +38,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); @@ -50,7 +50,7 @@ static void enable_spi_prefetch(void) static void enable_port80_on_lpc(void) { - device_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); /* Enable port 80 POST on LPC */ pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 7564442..61ff301 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -43,7 +43,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); @@ -55,7 +55,7 @@ static void enable_spi_prefetch(void) static void enable_port80_on_lpc(void) { - device_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); /* Enable port 80 POST on LPC */ pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index b350bde..67afc1c 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -26,7 +26,7 @@ static void i82371eb_enable_rom(void) { u16 reg16; - device_t dev; + pci_devfn_t dev; /* * Note: The Intel 82371AB/EB/MB ISA device can be on different diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index ca0aa92..7b4cd7d 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -34,7 +34,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 80b200e..fa056a8 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -22,7 +22,7 @@ static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 9629118..40c6bb8 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -38,7 +38,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); @@ -51,7 +51,7 @@ static void enable_spi_prefetch(void) static void map_rcba(void) { - device_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); } diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index e2f6bc0..6e68404 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -29,7 +29,7 @@ static void ck804_enable_rom(void) { unsigned char byte; - device_t addr; + pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ /* Locate the ck804 LPC. */ diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index 431c426..807c5a0 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -29,7 +29,7 @@ static void mcp55_enable_rom(void) { u8 byte; u16 word; - device_t addr; + pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ #if 0 diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index ac4919a..dbaf127 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -30,7 +30,7 @@ static void sis966_enable_rom(void) { - device_t addr; + pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 0d92073..41a224f 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -22,7 +22,7 @@ static void bootblock_southbridge_init(void) { - device_t dev; + pci_devfn_t dev; /* don't walk other busses, HT is not enabled */ /* ROM decode last 8MB FF800000 - FFFFFFFF on VT8237S/VT8237A */

1 0

Patch set updated for coreboot: e0dcd06 include/device/device.h: Deduplicate '*_pnp_devfn_t' typedefs
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6230 -gerrit commit e0dcd06565912d16e0c96fa89ea3e34c7c1c4213 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 18:41:12 2014 +1000 include/device/device.h: Deduplicate '*_pnp_devfn_t' typedefs 'pci_devfn_t' and 'pnp_devfn_t' are already defined in arch/io.h Change-Id: I006182bf6933fae21fe6671659b76e7031e74b71 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/include/arch/io.h | 9 ++++++--- src/include/device/device.h | 2 -- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index b6d82f9..d5cdf35 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -4,6 +4,11 @@ #include <stdint.h> #include <rules.h> +/* FIXME: Sources for romstage still use device_t. */ +/* Use pci_devfn_t or pnp_devfn_t instead */ +typedef u32 pci_devfn_t; +typedef u32 pnp_devfn_t; + /* * This file contains the definitions for the x86 IO instructions * inb/inw/inl/outb/outw/outl and the "string versions" of the same @@ -218,11 +223,9 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) /* FIXME: Sources for romstage still use device_t. */ +/* Use pci_devfn_t or pnp_devfn_t instead */ typedef u32 device_t; -typedef u32 pci_devfn_t; -typedef u32 pnp_devfn_t; - /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access diff --git a/src/include/device/device.h b/src/include/device/device.h index cf4cb8c..3810716 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -18,8 +18,6 @@ struct device; #ifndef __SIMPLE_DEVICE__ typedef struct device * device_t; -typedef u32 pci_devfn_t; -typedef u32 pnp_devfn_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations;

1 0

Patch set updated for coreboot: 0f54563 southbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7169 -gerrit commit 0f54563502154cd2f235e8aa9c92e4118d2fbbd8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Oct 23 02:09:00 2014 +1100 southbridge: Don't hide pointers behind typedefs Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively. Change-Id: Id6c221cc36a2b89db7b11796d947136bac76e565 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/spi.c | 2 +- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 14 +++++++------- src/southbridge/amd/sb700/early_setup.c | 18 +++++++++--------- src/southbridge/broadcom/bcm5780/nic.c | 2 +- src/southbridge/broadcom/bcm5780/pcix.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/bcm5785.h | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/broadcom/bcm5785/ide.c | 4 ++-- src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------ src/southbridge/broadcom/bcm5785/sata.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 14 +++++++------- src/southbridge/broadcom/bcm5785/usb.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 10 +++++----- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- src/southbridge/nvidia/ck804/ck804.c | 10 +++++----- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/ck804/smbus.c | 8 ++++---- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55.h | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------ src/southbridge/sis/sis966/early_ctrl.c | 2 +- 29 files changed, 93 insertions(+), 93 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index bbf6dd3..ce22d34 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -86,7 +86,7 @@ static void execute_command(void) void spi_init(void) { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..b606352 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -69,7 +69,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648ed..0341567 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -33,7 +33,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index f38e691..86e4f89 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -53,7 +53,7 @@ static void execute_command(void) void spi_init() { - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b6611f6..e412217 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg) /* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { @@ -67,7 +67,7 @@ static void sb600_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -196,7 +196,7 @@ void soft_reset(void) void sb600_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -241,7 +241,7 @@ void sb600_pci_port80(void) void sb600_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -260,7 +260,7 @@ void sb600_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; printk(BIOS_INFO, "sb600_devices_por_init()\n"); @@ -520,7 +520,7 @@ static void sb600_pmio_por_init(void) */ static void sb600_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index b7a5e77..90dbfa8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -79,7 +79,7 @@ static void sb700_acpi_init(void) /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id, enable_14Mhz, byte; u8 rev = 0; @@ -136,7 +136,7 @@ void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -195,7 +195,7 @@ void sb7xx_51xx_lpc_init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -208,7 +208,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 __attribute__ ((weak)) get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -290,7 +290,7 @@ void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) void sb7xx_51xx_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -335,7 +335,7 @@ void sb7xx_51xx_pci_port80(void) void sb7xx_51xx_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -354,7 +354,7 @@ void sb7xx_51xx_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb700_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; @@ -607,7 +607,7 @@ static void sb700_pmio_por_init(void) */ static void sb700_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index df59fdc..5fd56dd 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 92a3547..96d0ace 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 1675097..822b3ba 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -24,10 +24,10 @@ #include <device/pci_ids.h> #include "bcm5785.h" -void bcm5785_enable(device_t dev) +void bcm5785_enable(struct device * dev) { - device_t sb_pci_main_dev; - device_t bus_dev; + struct device * sb_pci_main_dev; + struct device * bus_dev; // unsigned index; /* See if we are on the behind the pcix bridge */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index bc3280f..5eb2f05 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -24,7 +24,7 @@ #include "chip.h" #ifndef __PRE_RAM__ -void bcm5785_enable(device_t dev); +void bcm5785_enable(struct device * dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..fe0fded 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -24,7 +24,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); @@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void) static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; @@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -134,7 +134,7 @@ void soft_reset(void) static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -162,7 +162,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev; //F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..200da09 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -24,7 +24,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 3426a2c..948fef0 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> #include "bcm5785.h" -static void bcm5785_ide_read_resources(device_t dev) +static void bcm5785_ide_read_resources(struct device * dev) { /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -40,7 +40,7 @@ static void ide_init(struct device *dev) { } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index af79892..5cf1376 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -30,7 +30,7 @@ #include <arch/ioapic.h> #include "bcm5785.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { /* Initialize the real time clock */ cmos_init(0); @@ -39,7 +39,7 @@ static void lpc_init(device_t dev) isa_dma_init(); } -static void bcm5785_lpc_read_resources(device_t dev) +static void bcm5785_lpc_read_resources(struct device * dev) { struct resource *res; @@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void bcm5785_lpc_enable_childrens_resources(device_t dev) +static void bcm5785_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; uint32_t reg; @@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } -static void bcm5785_lpc_enable_resources(device_t dev) +static void bcm5785_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); bcm5785_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..ddcb44c 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -73,7 +73,7 @@ static void sata_init(struct device *dev) } } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..0e42863 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -33,7 +33,7 @@ #define NMI_OFF 0 -static void sb_init(device_t dev) +static void sb_init(struct device * dev) { uint8_t byte; uint8_t byte_old; @@ -56,7 +56,7 @@ static void sb_init(device_t dev) } -static void bcm5785_sb_read_resources(device_t dev) +static void bcm5785_sb_read_resources(struct device * dev) { struct resource *res; @@ -76,7 +76,7 @@ static void bcm5785_sb_read_resources(device_t dev) } -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(struct device * dev, uint8_t val) { unsigned device; struct resource *res; @@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(struct device * dev, uint8_t address) { unsigned device; struct resource *res; @@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(struct device * dev, uint8_t address, uint8_t val) { unsigned device; struct resource *res; @@ -139,7 +139,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..b9c2452 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -37,7 +37,7 @@ static void usb_init(struct device *dev) } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d4f263b..b65fd11 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -95,7 +95,7 @@ static const unsigned char irq_to_int_routing[16] = { /* keyboard controller system flag timeout : 400 ms */ #define KBC_TIMEOUT_SYS_FLAG 400 -static u8 get_pci_dev_func(device_t dev) +static u8 get_pci_dev_func(struct device * dev) { return PCI_FUNC(dev->path.pci.devfn); } @@ -182,7 +182,7 @@ static void pci_routing_fixup(struct device *dev) /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */ for (i = 0; i < slot_num; i++) { unsigned int funct; - device_t pdev; + struct device * pdev; u8 irq; /* Each slot may contain up to eight functions. */ @@ -515,7 +515,7 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) +static void vortex86_sb_set_io_resv(struct device * dev, unsigned index, u32 base, u32 size) { struct resource *res; res = new_resource(dev, index); @@ -525,7 +525,7 @@ static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(struct device * dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; @@ -536,7 +536,7 @@ static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 fla res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void vortex86_sb_read_resources(device_t dev) +static void vortex86_sb_read_resources(struct device * dev) { u32 flash_size = 8 * 1024 * 1024; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 2ea9a24..e5783e7 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -322,7 +322,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev; + struct device * dev; ich9_spi_regs *ich9_spi; uint16_t hsfs; diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 6df99fd..c4e8a1c 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -370,7 +370,7 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - device_t dev; + struct device * dev; uint32_t ids; uint16_t vendor_id, device_id; diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..a285938 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -28,9 +28,9 @@ static u32 final_reg; -static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); if (!lpc_dev) @@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; } -void ck804_enable(device_t dev) +void ck804_enable(struct device * dev) { - device_t lpc_dev; + struct device * lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -188,7 +188,7 @@ void ck804_enable(device_t dev) } } -static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 9b6049c..a48401f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device * dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev) #endif } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev); } -static void rom_dummy_write(device_t dev) +static void rom_dummy_write(struct device * dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev) unsigned pm_base = 0; -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(device_t dev) rom_dummy_write(dev); } -static void ck804_lpc_read_resources(device_t dev) +static void ck804_lpc_read_resources(struct device * dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev) } } -static void ck804_lpc_set_resources(device_t dev) +static void ck804_lpc_set_resources(struct device * dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(device_t dev) +static void ck804_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void ck804_lpc_enable_resources(device_t dev) +static void ck804_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..62967bf 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -28,7 +28,7 @@ #include "ck804.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..954e305 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,7 +254,7 @@ static void azalia_init(struct device *dev) } } -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 11c2c4f..ebf2a01 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev, int master) +static void lpc_common_init(struct device * dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master) clear_ioapic(ioapic_base); } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(device_t dev) enable_hpet(dev); } -static void mcp55_lpc_read_resources(device_t dev) +static void mcp55_lpc_read_resources(struct device * dev) { struct resource *res; @@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(device_t dev) +static void mcp55_lpc_enable_childrens_resources(struct device * dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void mcp55_lpc_enable_resources(device_t dev) +static void mcp55_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 4fb3391..20b33b4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,7 +30,7 @@ #ifndef __PRE_RAM__ #include "chip.h" -void mcp55_enable(device_t dev); +void mcp55_enable(struct device * dev); extern struct pci_operations mcp55_pci_ops; #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3e0b87e..e28a896 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -31,7 +31,7 @@ #include "mcp55.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = { unsigned pm_base; #endif -static void mcp55_sm_read_resources(device_t dev) +static void mcp55_sm_read_resources(struct device * dev) { unsigned long index; @@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev) compact_resources(dev); } -static void mcp55_sm_init(device_t dev) +static void mcp55_sm_init(struct device * dev) { #if CONFIG_HAVE_ACPI_TABLES struct resource *res; diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(

1 0

Patch set updated for coreboot: 50e8544 NOTFORMERGE: fix reset.c
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7196 -gerrit commit 50e8544bc6a5b9da78787f42104bdb14a3c93ef8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:36:02 2014 +1100 NOTFORMERGE: fix reset.c Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/amd8111/reset.c | 14 ++++++-------- src/southbridge/broadcom/bcm5785/reset.c | 6 ++---- src/southbridge/nvidia/ck804/reset.c | 6 ++---- src/southbridge/nvidia/mcp55/reset.c | 6 ++---- src/southbridge/sis/sis966/reset.c | 6 ++---- 5 files changed, 14 insertions(+), 24 deletions(-) diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index c96e898..8824550 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -10,9 +10,7 @@ #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -typedef unsigned device_t; - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) { unsigned addr; addr = (dev>>4) | where; @@ -20,7 +18,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value) outb(value, 0xCFC + (addr & 3)); } -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -28,7 +26,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; @@ -37,9 +35,9 @@ static unsigned pci_read_config32(device_t dev, unsigned where) } #define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); for(; dev <= last; dev += PCI_DEV(0,0,1)) { @@ -57,7 +55,7 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) void hard_reset(void) { - device_t dev; + pci_devfn_t dev; unsigned bus; unsigned node = 0; unsigned link = get_sblk(); diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 51ba6ec..b34cc86 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index a241966..53c0c40 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev >> 4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev >> 4) | where; diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/sis/sis966/reset.c +++ b/src/southbridge/sis/sis966/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where;

1 0

Patch set updated for coreboot: 02848ee soutbridge/*/bootblock: Use pci_dev_t over device_t typedef
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7193 -gerrit commit 02848ee826f682299395cd8abd6fe11ffa056130 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:12:15 2014 +1100 soutbridge/*/bootblock: Use pci_dev_t over device_t typedef Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/bootblock.c | 2 +- src/southbridge/amd/amd8111/bootblock.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/bootblock.c | 6 +++--- src/southbridge/amd/cimx/sb900/bootblock.c | 2 +- src/southbridge/amd/sb600/bootblock.c | 2 +- src/southbridge/amd/sb700/bootblock.c | 2 +- src/southbridge/amd/sb800/bootblock.c | 2 +- src/southbridge/broadcom/bcm5785/bootblock.c | 2 +- src/southbridge/intel/bd82x6x/bootblock.c | 4 ++-- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 4 ++-- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82801gx/bootblock.c | 2 +- src/southbridge/intel/i82801ix/bootblock.c | 2 +- src/southbridge/intel/lynxpoint/bootblock.c | 4 ++-- src/southbridge/nvidia/ck804/bootblock.c | 2 +- src/southbridge/nvidia/mcp55/bootblock.c | 2 +- src/southbridge/sis/sis966/bootblock.c | 2 +- src/southbridge/via/vt8237r/bootblock.c | 2 +- 19 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 65810fa..3cdba8b 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -33,7 +33,7 @@ static void hudson_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index ba3dc43..4c00989 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -26,7 +26,7 @@ static void amd8111_enable_rom(void) { u8 byte; - device_t dev; + pci_devfn_t dev; dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), 0); diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 1027659..4ddfb92 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -24,7 +24,7 @@ static void sb700_enable_rom(void) { u32 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB700 LPC Bridge 0:20:3:44h. diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 4fd2739..188ba29 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -23,7 +23,7 @@ static void enable_rom(void) { u16 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB800 LPC Bridge 0:20:3:44h. @@ -57,7 +57,7 @@ static void enable_rom(void) static void enable_prefetch(void) { u32 dword; - device_t dev = PCI_DEV(0, 0x14, 0x03); + pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* Enable PrefetchEnSPIFromHost */ dword = pci_io_read_config32(dev, 0xb8); @@ -67,7 +67,7 @@ static void enable_prefetch(void) static void enable_spi_fast_mode(void) { u32 dword; - device_t dev = PCI_DEV(0, 0x14, 0x03); + pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 9108a8b..561904e 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -23,7 +23,7 @@ static void sb900_enable_rom(void) { u32 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB900 LPC Bridge 0:20:3:44h. diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index e31a96c..94f5e6e 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -34,7 +34,7 @@ static void sb600_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_LPC), 0); diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index c290806..67da3fa 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -35,7 +35,7 @@ static void sb700_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 9311b97..61ff284 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -33,7 +33,7 @@ static void sb800_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 166464c..3c1d39c 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -26,7 +26,7 @@ static void bcm5785_enable_rom(void) { u8 byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 85a940e..b1b53af 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -38,7 +38,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); @@ -50,7 +50,7 @@ static void enable_spi_prefetch(void) static void enable_port80_on_lpc(void) { - device_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); /* Enable port 80 POST on LPC */ pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 7564442..61ff301 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -43,7 +43,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); @@ -55,7 +55,7 @@ static void enable_spi_prefetch(void) static void enable_port80_on_lpc(void) { - device_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); /* Enable port 80 POST on LPC */ pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index b350bde..67afc1c 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -26,7 +26,7 @@ static void i82371eb_enable_rom(void) { u16 reg16; - device_t dev; + pci_devfn_t dev; /* * Note: The Intel 82371AB/EB/MB ISA device can be on different diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index ca0aa92..7b4cd7d 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -34,7 +34,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 80b200e..fa056a8 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -22,7 +22,7 @@ static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 9629118..40c6bb8 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -38,7 +38,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); @@ -51,7 +51,7 @@ static void enable_spi_prefetch(void) static void map_rcba(void) { - device_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); } diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index e2f6bc0..6e68404 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -29,7 +29,7 @@ static void ck804_enable_rom(void) { unsigned char byte; - device_t addr; + pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ /* Locate the ck804 LPC. */ diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index 431c426..807c5a0 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -29,7 +29,7 @@ static void mcp55_enable_rom(void) { u8 byte; u16 word; - device_t addr; + pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ #if 0 diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index ac4919a..dbaf127 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -30,7 +30,7 @@ static void sis966_enable_rom(void) { - device_t addr; + pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 0d92073..41a224f 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -22,7 +22,7 @@ static void bootblock_southbridge_init(void) { - device_t dev; + pci_devfn_t dev; /* don't walk other busses, HT is not enabled */ /* ROM decode last 8MB FF800000 - FFFFFFFF on VT8237S/VT8237A */

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coreboot-gerrit October 2014