coreboot-gerrit October 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: ece114c NOTFORMERGE: fix reset.c
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7196 -gerrit commit ece114c6d6768e9bb26324a48dcf8ab84790ea0f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:36:02 2014 +1100 NOTFORMERGE: fix reset.c Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/amd8111/reset.c | 14 ++++++-------- src/southbridge/broadcom/bcm5785/reset.c | 6 ++---- src/southbridge/nvidia/ck804/reset.c | 6 ++---- src/southbridge/nvidia/mcp55/reset.c | 6 ++---- src/southbridge/sis/sis966/reset.c | 6 ++---- 5 files changed, 14 insertions(+), 24 deletions(-) diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index c96e898..8824550 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -10,9 +10,7 @@ #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -typedef unsigned device_t; - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) { unsigned addr; addr = (dev>>4) | where; @@ -20,7 +18,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value) outb(value, 0xCFC + (addr & 3)); } -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -28,7 +26,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; @@ -37,9 +35,9 @@ static unsigned pci_read_config32(device_t dev, unsigned where) } #define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); for(; dev <= last; dev += PCI_DEV(0,0,1)) { @@ -57,7 +55,7 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) void hard_reset(void) { - device_t dev; + pci_devfn_t dev; unsigned bus; unsigned node = 0; unsigned link = get_sblk(); diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 51ba6ec..b34cc86 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index a241966..53c0c40 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev >> 4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev >> 4) | where; diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/sis/sis966/reset.c +++ b/src/southbridge/sis/sis966/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where;

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New patch to review for coreboot: 73819c6 NOTFORMERGE
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7195 -gerrit commit 73819c6e381bf4533935f09038e4ddf0c17f836a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:19:15 2014 +1100 NOTFORMERGE Change-Id: I84ff779d300360a8f726d7707a89a7e419f04655 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/spi.c | 2 +- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index bbf6dd3..295c7bb 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -86,7 +86,7 @@ static void execute_command(void) void spi_init(void) { - device_t dev; + pci_devfn_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index f38e691..66eaddf 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -53,7 +53,7 @@ static void execute_command(void) void spi_init() { - device_t dev; + pci_devfn_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 2ea9a24..8cdbc37 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -322,7 +322,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev; + pci_devfn_t dev; ich9_spi_regs *ich9_spi; uint16_t hsfs; diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 6df99fd..883eec4 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -370,7 +370,7 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - device_t dev; + pci_devfn_t dev; uint32_t ids; uint16_t vendor_id, device_id;

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New patch to review for coreboot: ad8552f drivers/spi: add Macronix MX25U6435F and MX25L6495F support
by Idwer Vollering 26 Oct '14

26 Oct '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7194 -gerrit commit ad8552ff009bbc7aa2093505f130dbc36a674bde Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Oct 26 01:20:20 2014 +0200 drivers/spi: add Macronix MX25U6435F and MX25L6495F support Contributed by MXIC: http://www.coreboot.org/pipermail/coreboot/2014-October/078835.html Change-Id: I07f872a5cbb2b0ea63794edb8fbca40d7856ce10 Author: Alex Lu <alexlu6(a)mxic.com.tw> Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/drivers/spi/macronix.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 8a6601b..c9338ed 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -119,6 +119,22 @@ static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { .nr_blocks = 256, .name = "MX25L12855E", }, + { + .idcode = 0x2537, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "MX25U6435F", + }, + { + .idcode = 0x9517, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "MX25L6495F", + }, }; static int macronix_write(struct spi_flash *flash,

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New patch to review for coreboot: 09ceccd NOTFORMERGE: fix bootblock
by Edward O'Callaghan 26 Oct '14

26 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7193 -gerrit commit 09ceccdbc5743941f5db7f68ed84c627fdb024a7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:12:15 2014 +1100 NOTFORMERGE: fix bootblock Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/bootblock.c | 2 +- src/southbridge/amd/amd8111/bootblock.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/bootblock.c | 6 +++--- src/southbridge/amd/cimx/sb900/bootblock.c | 2 +- src/southbridge/amd/sb600/bootblock.c | 2 +- src/southbridge/amd/sb700/bootblock.c | 2 +- src/southbridge/amd/sb800/bootblock.c | 2 +- src/southbridge/broadcom/bcm5785/bootblock.c | 2 +- src/southbridge/intel/bd82x6x/bootblock.c | 4 ++-- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 4 ++-- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82801gx/bootblock.c | 2 +- src/southbridge/intel/i82801ix/bootblock.c | 2 +- src/southbridge/intel/lynxpoint/bootblock.c | 4 ++-- src/southbridge/nvidia/ck804/bootblock.c | 2 +- src/southbridge/nvidia/mcp55/bootblock.c | 2 +- src/southbridge/sis/sis966/bootblock.c | 2 +- src/southbridge/via/vt8237r/bootblock.c | 2 +- 19 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 65810fa..3cdba8b 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -33,7 +33,7 @@ static void hudson_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index ba3dc43..4c00989 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -26,7 +26,7 @@ static void amd8111_enable_rom(void) { u8 byte; - device_t dev; + pci_devfn_t dev; dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), 0); diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 1027659..4ddfb92 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -24,7 +24,7 @@ static void sb700_enable_rom(void) { u32 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB700 LPC Bridge 0:20:3:44h. diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 4fd2739..188ba29 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -23,7 +23,7 @@ static void enable_rom(void) { u16 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB800 LPC Bridge 0:20:3:44h. @@ -57,7 +57,7 @@ static void enable_rom(void) static void enable_prefetch(void) { u32 dword; - device_t dev = PCI_DEV(0, 0x14, 0x03); + pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* Enable PrefetchEnSPIFromHost */ dword = pci_io_read_config32(dev, 0xb8); @@ -67,7 +67,7 @@ static void enable_prefetch(void) static void enable_spi_fast_mode(void) { u32 dword; - device_t dev = PCI_DEV(0, 0x14, 0x03); + pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 9108a8b..561904e 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -23,7 +23,7 @@ static void sb900_enable_rom(void) { u32 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB900 LPC Bridge 0:20:3:44h. diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index e31a96c..94f5e6e 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -34,7 +34,7 @@ static void sb600_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_LPC), 0); diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index c290806..67da3fa 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -35,7 +35,7 @@ static void sb700_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 9311b97..61ff284 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -33,7 +33,7 @@ static void sb800_enable_rom(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 166464c..3c1d39c 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -26,7 +26,7 @@ static void bcm5785_enable_rom(void) { u8 byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 85a940e..b1b53af 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -38,7 +38,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); @@ -50,7 +50,7 @@ static void enable_spi_prefetch(void) static void enable_port80_on_lpc(void) { - device_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); /* Enable port 80 POST on LPC */ pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 7564442..61ff301 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -43,7 +43,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); @@ -55,7 +55,7 @@ static void enable_spi_prefetch(void) static void enable_port80_on_lpc(void) { - device_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); /* Enable port 80 POST on LPC */ pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index b350bde..67afc1c 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -26,7 +26,7 @@ static void i82371eb_enable_rom(void) { u16 reg16; - device_t dev; + pci_devfn_t dev; /* * Note: The Intel 82371AB/EB/MB ISA device can be on different diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index ca0aa92..7b4cd7d 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -34,7 +34,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 80b200e..fa056a8 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -22,7 +22,7 @@ static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 9629118..40c6bb8 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -38,7 +38,7 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { u8 reg8; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); @@ -51,7 +51,7 @@ static void enable_spi_prefetch(void) static void map_rcba(void) { - device_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); } diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index e2f6bc0..6e68404 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -29,7 +29,7 @@ static void ck804_enable_rom(void) { unsigned char byte; - device_t addr; + pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ /* Locate the ck804 LPC. */ diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index 431c426..807c5a0 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -29,7 +29,7 @@ static void mcp55_enable_rom(void) { u8 byte; u16 word; - device_t addr; + pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ #if 0 diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index ac4919a..dbaf127 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -30,7 +30,7 @@ static void sis966_enable_rom(void) { - device_t addr; + pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 0d92073..41a224f 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -22,7 +22,7 @@ static void bootblock_southbridge_init(void) { - device_t dev; + pci_devfn_t dev; /* don't walk other busses, HT is not enabled */ /* ROM decode last 8MB FF800000 - FFFFFFFF on VT8237S/VT8237A */

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Patch set updated for coreboot: 1382790 southbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 25 Oct '14

25 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7169 -gerrit commit 13827905d0c9e128b98f385d1f5afa44ac638417 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Oct 23 02:09:00 2014 +1100 southbridge: Don't hide pointers behind typedefs Unfortunately coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer type exclusively. Change-Id: Id6c221cc36a2b89db7b11796d947136bac76e565 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 14 +++++++------- src/southbridge/amd/sb700/early_setup.c | 18 +++++++++--------- src/southbridge/broadcom/bcm5780/nic.c | 2 +- src/southbridge/broadcom/bcm5780/pcix.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/bcm5785.h | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/broadcom/bcm5785/ide.c | 4 ++-- src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------ src/southbridge/broadcom/bcm5785/sata.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 14 +++++++------- src/southbridge/broadcom/bcm5785/usb.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 10 +++++----- src/southbridge/nvidia/ck804/ck804.c | 10 +++++----- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/ck804/smbus.c | 8 ++++---- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55.h | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------ src/southbridge/sis/sis966/early_ctrl.c | 2 +- 25 files changed, 89 insertions(+), 89 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..b606352 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -69,7 +69,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648ed..0341567 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -33,7 +33,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b6611f6..e412217 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg) /* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { @@ -67,7 +67,7 @@ static void sb600_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -196,7 +196,7 @@ void soft_reset(void) void sb600_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -241,7 +241,7 @@ void sb600_pci_port80(void) void sb600_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -260,7 +260,7 @@ void sb600_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; printk(BIOS_INFO, "sb600_devices_por_init()\n"); @@ -520,7 +520,7 @@ static void sb600_pmio_por_init(void) */ static void sb600_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index b7a5e77..90dbfa8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -79,7 +79,7 @@ static void sb700_acpi_init(void) /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id, enable_14Mhz, byte; u8 rev = 0; @@ -136,7 +136,7 @@ void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -195,7 +195,7 @@ void sb7xx_51xx_lpc_init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -208,7 +208,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 __attribute__ ((weak)) get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -290,7 +290,7 @@ void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) void sb7xx_51xx_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -335,7 +335,7 @@ void sb7xx_51xx_pci_port80(void) void sb7xx_51xx_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32; /* Enable LPC controller */ @@ -354,7 +354,7 @@ void sb7xx_51xx_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb700_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; @@ -607,7 +607,7 @@ static void sb700_pmio_por_init(void) */ static void sb700_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte; /* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index df59fdc..5fd56dd 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 92a3547..96d0ace 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 1675097..822b3ba 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -24,10 +24,10 @@ #include <device/pci_ids.h> #include "bcm5785.h" -void bcm5785_enable(device_t dev) +void bcm5785_enable(struct device * dev) { - device_t sb_pci_main_dev; - device_t bus_dev; + struct device * sb_pci_main_dev; + struct device * bus_dev; // unsigned index; /* See if we are on the behind the pcix bridge */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index bc3280f..5eb2f05 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -24,7 +24,7 @@ #include "chip.h" #ifndef __PRE_RAM__ -void bcm5785_enable(device_t dev); +void bcm5785_enable(struct device * dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..fe0fded 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -24,7 +24,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); @@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void) static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; @@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -134,7 +134,7 @@ void soft_reset(void) static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -162,7 +162,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev; //F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..200da09 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -24,7 +24,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 3426a2c..948fef0 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> #include "bcm5785.h" -static void bcm5785_ide_read_resources(device_t dev) +static void bcm5785_ide_read_resources(struct device * dev) { /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -40,7 +40,7 @@ static void ide_init(struct device *dev) { } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index af79892..5cf1376 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -30,7 +30,7 @@ #include <arch/ioapic.h> #include "bcm5785.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { /* Initialize the real time clock */ cmos_init(0); @@ -39,7 +39,7 @@ static void lpc_init(device_t dev) isa_dma_init(); } -static void bcm5785_lpc_read_resources(device_t dev) +static void bcm5785_lpc_read_resources(struct device * dev) { struct resource *res; @@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void bcm5785_lpc_enable_childrens_resources(device_t dev) +static void bcm5785_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; uint32_t reg; @@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } -static void bcm5785_lpc_enable_resources(device_t dev) +static void bcm5785_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); bcm5785_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..ddcb44c 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -73,7 +73,7 @@ static void sata_init(struct device *dev) } } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..0e42863 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -33,7 +33,7 @@ #define NMI_OFF 0 -static void sb_init(device_t dev) +static void sb_init(struct device * dev) { uint8_t byte; uint8_t byte_old; @@ -56,7 +56,7 @@ static void sb_init(device_t dev) } -static void bcm5785_sb_read_resources(device_t dev) +static void bcm5785_sb_read_resources(struct device * dev) { struct resource *res; @@ -76,7 +76,7 @@ static void bcm5785_sb_read_resources(device_t dev) } -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(struct device * dev, uint8_t val) { unsigned device; struct resource *res; @@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(struct device * dev, uint8_t address) { unsigned device; struct resource *res; @@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(struct device * dev, uint8_t address, uint8_t val) { unsigned device; struct resource *res; @@ -139,7 +139,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..b9c2452 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -37,7 +37,7 @@ static void usb_init(struct device *dev) } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d4f263b..b65fd11 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -95,7 +95,7 @@ static const unsigned char irq_to_int_routing[16] = { /* keyboard controller system flag timeout : 400 ms */ #define KBC_TIMEOUT_SYS_FLAG 400 -static u8 get_pci_dev_func(device_t dev) +static u8 get_pci_dev_func(struct device * dev) { return PCI_FUNC(dev->path.pci.devfn); } @@ -182,7 +182,7 @@ static void pci_routing_fixup(struct device *dev) /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */ for (i = 0; i < slot_num; i++) { unsigned int funct; - device_t pdev; + struct device * pdev; u8 irq; /* Each slot may contain up to eight functions. */ @@ -515,7 +515,7 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) +static void vortex86_sb_set_io_resv(struct device * dev, unsigned index, u32 base, u32 size) { struct resource *res; res = new_resource(dev, index); @@ -525,7 +525,7 @@ static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(struct device * dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; @@ -536,7 +536,7 @@ static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 fla res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void vortex86_sb_read_resources(device_t dev) +static void vortex86_sb_read_resources(struct device * dev) { u32 flash_size = 8 * 1024 * 1024; diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..a285938 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -28,9 +28,9 @@ static u32 final_reg; -static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); if (!lpc_dev) @@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; } -void ck804_enable(device_t dev) +void ck804_enable(struct device * dev) { - device_t lpc_dev; + struct device * lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -188,7 +188,7 @@ void ck804_enable(device_t dev) } } -static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 9b6049c..a48401f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device * dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev) #endif } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev); } -static void rom_dummy_write(device_t dev) +static void rom_dummy_write(struct device * dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev) unsigned pm_base = 0; -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(device_t dev) rom_dummy_write(dev); } -static void ck804_lpc_read_resources(device_t dev) +static void ck804_lpc_read_resources(struct device * dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev) } } -static void ck804_lpc_set_resources(device_t dev) +static void ck804_lpc_set_resources(struct device * dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(device_t dev) +static void ck804_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void ck804_lpc_enable_resources(device_t dev) +static void ck804_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..62967bf 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -28,7 +28,7 @@ #include "ck804.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..954e305 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,7 +254,7 @@ static void azalia_init(struct device *dev) } } -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 11c2c4f..ebf2a01 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev, int master) +static void lpc_common_init(struct device * dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master) clear_ioapic(ioapic_base); } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(device_t dev) enable_hpet(dev); } -static void mcp55_lpc_read_resources(device_t dev) +static void mcp55_lpc_read_resources(struct device * dev) { struct resource *res; @@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(device_t dev) +static void mcp55_lpc_enable_childrens_resources(struct device * dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void mcp55_lpc_enable_resources(device_t dev) +static void mcp55_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 4fb3391..20b33b4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,7 +30,7 @@ #ifndef __PRE_RAM__ #include "chip.h" -void mcp55_enable(device_t dev); +void mcp55_enable(struct device * dev); extern struct pci_operations mcp55_pci_ops; #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3e0b87e..e28a896 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -31,7 +31,7 @@ #include "mcp55.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = { unsigned pm_base; #endif -static void mcp55_sm_read_resources(device_t dev) +static void mcp55_sm_read_resources(struct device * dev) { unsigned long index; @@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev) compact_resources(dev); } -static void mcp55_sm_init(device_t dev) +static void mcp55_sm_init(struct device * dev) { #if CONFIG_HAVE_ACPI_TABLES struct resource *res; diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(

1 0

Patch set updated for coreboot: 901a447 southbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 25 Oct '14

25 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7169 -gerrit commit 901a44726ce660da2604039e4b02e349470f7afe Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Oct 23 02:09:00 2014 +1100 southbridge: Don't hide pointers behind typedefs Change-Id: Id6c221cc36a2b89db7b11796d947136bac76e565 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/broadcom/bcm5780/nic.c | 2 +- src/southbridge/broadcom/bcm5780/pcix.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/bcm5785.h | 2 +- src/southbridge/broadcom/bcm5785/bootblock.c | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/broadcom/bcm5785/ide.c | 4 ++-- src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------ src/southbridge/broadcom/bcm5785/sata.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 14 +++++++------- src/southbridge/broadcom/bcm5785/usb.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 10 +++++----- src/southbridge/nvidia/ck804/ck804.c | 10 +++++----- src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++--------- src/southbridge/nvidia/ck804/smbus.c | 8 ++++---- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55.h | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------ 20 files changed, 68 insertions(+), 68 deletions(-) diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index df59fdc..5fd56dd 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 92a3547..96d0ace 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 1675097..822b3ba 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -24,10 +24,10 @@ #include <device/pci_ids.h> #include "bcm5785.h" -void bcm5785_enable(device_t dev) +void bcm5785_enable(struct device * dev) { - device_t sb_pci_main_dev; - device_t bus_dev; + struct device * sb_pci_main_dev; + struct device * bus_dev; // unsigned index; /* See if we are on the behind the pcix bridge */ diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h index bc3280f..5eb2f05 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.h +++ b/src/southbridge/broadcom/bcm5785/bcm5785.h @@ -24,7 +24,7 @@ #include "chip.h" #ifndef __PRE_RAM__ -void bcm5785_enable(device_t dev); +void bcm5785_enable(struct device * dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 166464c..23833a0 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -26,7 +26,7 @@ static void bcm5785_enable_rom(void) { u8 byte; - device_t dev; + struct device * dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..fe0fded 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -24,7 +24,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); @@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void) static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; @@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -134,7 +134,7 @@ void soft_reset(void) static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -162,7 +162,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev; //F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..200da09 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -24,7 +24,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 3426a2c..948fef0 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> #include "bcm5785.h" -static void bcm5785_ide_read_resources(device_t dev) +static void bcm5785_ide_read_resources(struct device * dev) { /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -40,7 +40,7 @@ static void ide_init(struct device *dev) { } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index af79892..5cf1376 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -30,7 +30,7 @@ #include <arch/ioapic.h> #include "bcm5785.h" -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { /* Initialize the real time clock */ cmos_init(0); @@ -39,7 +39,7 @@ static void lpc_init(device_t dev) isa_dma_init(); } -static void bcm5785_lpc_read_resources(device_t dev) +static void bcm5785_lpc_read_resources(struct device * dev) { struct resource *res; @@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(device_t dev) * * @param dev The device whos children's resources are to be enabled. */ -static void bcm5785_lpc_enable_childrens_resources(device_t dev) +static void bcm5785_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; uint32_t reg; @@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } -static void bcm5785_lpc_enable_resources(device_t dev) +static void bcm5785_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); bcm5785_lpc_enable_childrens_resources(dev); } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..ddcb44c 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -73,7 +73,7 @@ static void sata_init(struct device *dev) } } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..0e42863 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -33,7 +33,7 @@ #define NMI_OFF 0 -static void sb_init(device_t dev) +static void sb_init(struct device * dev) { uint8_t byte; uint8_t byte_old; @@ -56,7 +56,7 @@ static void sb_init(device_t dev) } -static void bcm5785_sb_read_resources(device_t dev) +static void bcm5785_sb_read_resources(struct device * dev) { struct resource *res; @@ -76,7 +76,7 @@ static void bcm5785_sb_read_resources(device_t dev) } -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(struct device * dev, uint8_t val) { unsigned device; struct resource *res; @@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(struct device * dev, uint8_t address) { unsigned device; struct resource *res; @@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(struct device * dev, uint8_t address, uint8_t val) { unsigned device; struct resource *res; @@ -139,7 +139,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..b9c2452 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -37,7 +37,7 @@ static void usb_init(struct device *dev) } -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index d4f263b..b65fd11 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -95,7 +95,7 @@ static const unsigned char irq_to_int_routing[16] = { /* keyboard controller system flag timeout : 400 ms */ #define KBC_TIMEOUT_SYS_FLAG 400 -static u8 get_pci_dev_func(device_t dev) +static u8 get_pci_dev_func(struct device * dev) { return PCI_FUNC(dev->path.pci.devfn); } @@ -182,7 +182,7 @@ static void pci_routing_fixup(struct device *dev) /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */ for (i = 0; i < slot_num; i++) { unsigned int funct; - device_t pdev; + struct device * pdev; u8 irq; /* Each slot may contain up to eight functions. */ @@ -515,7 +515,7 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) +static void vortex86_sb_set_io_resv(struct device * dev, unsigned index, u32 base, u32 size) { struct resource *res; res = new_resource(dev, index); @@ -525,7 +525,7 @@ static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(struct device * dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; @@ -536,7 +536,7 @@ static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 fla res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void vortex86_sb_read_resources(device_t dev) +static void vortex86_sb_read_resources(struct device * dev) { u32 flash_size = 8 * 1024 * 1024; diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..a285938 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -28,9 +28,9 @@ static u32 final_reg; -static device_t find_lpc_dev(device_t dev, unsigned devfn) +static struct device * find_lpc_dev(struct device * dev, unsigned devfn) { - device_t lpc_dev; + struct device * lpc_dev; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); if (!lpc_dev) @@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) return lpc_dev; } -void ck804_enable(device_t dev) +void ck804_enable(struct device * dev) { - device_t lpc_dev; + struct device * lpc_dev; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; u32 reg_old, reg; u8 byte; @@ -188,7 +188,7 @@ void ck804_enable(device_t dev) } } -static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 9b6049c..a48401f 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -52,7 +52,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev) +static void lpc_common_init(struct device * dev) { u32 dword; struct resource *res; @@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev) #endif } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev); } -static void rom_dummy_write(device_t dev) +static void rom_dummy_write(struct device * dev) { u8 old, new; u8 *p; @@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev) unsigned pm_base = 0; -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -170,7 +170,7 @@ static void lpc_init(device_t dev) rom_dummy_write(dev); } -static void ck804_lpc_read_resources(device_t dev) +static void ck804_lpc_read_resources(struct device * dev) { struct resource *res; unsigned long index; @@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev) } } -static void ck804_lpc_set_resources(device_t dev) +static void ck804_lpc_set_resources(struct device * dev) { u8 byte; struct resource *res; @@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev) * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. */ -static void ck804_lpc_enable_childrens_resources(device_t dev) +static void ck804_lpc_enable_childrens_resources(struct device * dev) { struct bus *link; u32 reg, reg_var[4]; @@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void ck804_lpc_enable_resources(device_t dev) +static void ck804_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); ck804_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..62967bf 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -28,7 +28,7 @@ #include "ck804.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..954e305 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -254,7 +254,7 @@ static void azalia_init(struct device *dev) } } -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 11c2c4f..ebf2a01 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -57,7 +57,7 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -static void lpc_common_init(device_t dev, int master) +static void lpc_common_init(struct device * dev, int master) { u8 byte; u32 ioapic_base; @@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master) clear_ioapic(ioapic_base); } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(struct device * dev) { lpc_common_init(dev, 0); } @@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev) printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } -static void lpc_init(device_t dev) +static void lpc_init(struct device * dev) { u8 byte, byte_old; int on, nmi_option; @@ -161,7 +161,7 @@ static void lpc_init(device_t dev) enable_hpet(dev); } -static void mcp55_lpc_read_resources(device_t dev) +static void mcp55_lpc_read_resources(struct device * dev) { struct resource *res; @@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev The device whose children's resources are to be enabled. */ -static void mcp55_lpc_enable_childrens_resources(device_t dev) +static void mcp55_lpc_enable_childrens_resources(struct device * dev) { u32 reg, reg_var[4]; int i, var_num = 0; @@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config32(dev, 0xa0); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device * child; for (child = link->children; child; child = child->sibling) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; @@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]); } -static void mcp55_lpc_enable_resources(device_t dev) +static void mcp55_lpc_enable_resources(struct device * dev) { pci_dev_enable_resources(dev); mcp55_lpc_enable_childrens_resources(dev); diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 4fb3391..20b33b4 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -30,7 +30,7 @@ #ifndef __PRE_RAM__ #include "chip.h" -void mcp55_enable(device_t dev); +void mcp55_enable(struct device * dev); extern struct pci_operations mcp55_pci_ops; #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 3e0b87e..e28a896 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -31,7 +31,7 @@ #include "mcp55.h" #include "smbus.h" -static int lsmbus_recv_byte(device_t dev) +static int lsmbus_recv_byte(struct device * dev) { unsigned device; struct resource *res; @@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); } -static int lsmbus_send_byte(device_t dev, u8 val) +static int lsmbus_send_byte(struct device * dev, u8 val) { unsigned device; struct resource *res; @@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val) return do_smbus_send_byte(res->base, device, val); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device * dev, u8 address) { unsigned device; struct resource *res; @@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = { unsigned pm_base; #endif -static void mcp55_sm_read_resources(device_t dev) +static void mcp55_sm_read_resources(struct device * dev) { unsigned long index; @@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev) compact_resources(dev); } -static void mcp55_sm_init(device_t dev) +static void mcp55_sm_init(struct device * dev) { #if CONFIG_HAVE_ACPI_TABLES struct resource *res;

1 0

Patch set updated for coreboot: 355f6bc northbridge: Don't hide pointers behind typedefs
by Edward O'Callaghan 25 Oct '14

25 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7166 -gerrit commit 355f6bcc9b25df44c8d46b32116464c04937f550 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 22 22:03:49 2014 +1100 northbridge: Don't hide pointers behind typedefs Change-Id: Ib2c373695820e71a6e41e4f173d2615ee5838f28 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/device/pci_ops.h | 12 ++-- src/mainboard/emulation/qemu-i440fx/northbridge.c | 12 ++-- src/northbridge/amd/agesa/00730F01/northbridge.c | 72 +++++++++---------- src/northbridge/amd/agesa/family10/northbridge.c | 82 +++++++++++----------- src/northbridge/amd/agesa/family10/reset_test.h | 4 +- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 12 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 50 ++++++------- src/northbridge/amd/agesa/family12/northbridge.h | 2 +- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 12 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 54 +++++++------- src/northbridge/amd/agesa/family14/northbridge.h | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 74 +++++++++---------- src/northbridge/amd/agesa/family15/northbridge.h | 2 +- src/northbridge/amd/agesa/family15tn/iommu.c | 4 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 68 +++++++++--------- src/northbridge/amd/agesa/family16kb/northbridge.c | 72 +++++++++---------- src/northbridge/amd/amdfam10/northbridge.c | 74 +++++++++---------- src/northbridge/amd/amdk8/northbridge.c | 66 ++++++++--------- src/northbridge/amd/cimx/rd890/late.c | 2 +- src/northbridge/amd/gx1/northbridge.c | 14 ++-- src/northbridge/amd/gx2/northbridge.c | 14 ++-- src/northbridge/amd/lx/northbridge.c | 14 ++-- src/northbridge/dmp/vortex86ex/northbridge.c | 6 +- src/northbridge/intel/e7501/northbridge.c | 8 +-- src/northbridge/intel/e7505/northbridge.c | 10 +-- src/northbridge/intel/e7520/northbridge.c | 18 ++--- src/northbridge/intel/e7525/northbridge.c | 18 ++--- src/northbridge/intel/fsp_rangeley/northbridge.c | 22 +++--- .../intel/fsp_sandybridge/northbridge.c | 18 ++--- src/northbridge/intel/gm45/northbridge.c | 14 ++-- src/northbridge/intel/haswell/northbridge.c | 32 ++++----- src/northbridge/intel/i3100/northbridge.c | 20 +++--- src/northbridge/intel/i440bx/northbridge.c | 10 +-- src/northbridge/intel/i440lx/northbridge.c | 10 +-- src/northbridge/intel/i5000/northbridge.c | 16 ++--- src/northbridge/intel/i82810/northbridge.c | 10 +-- src/northbridge/intel/i82830/northbridge.c | 10 +-- src/northbridge/intel/i855/northbridge.c | 10 +-- src/northbridge/intel/i945/northbridge.c | 16 ++--- src/northbridge/intel/nehalem/northbridge.c | 16 ++--- src/northbridge/intel/sandybridge/northbridge.c | 18 ++--- src/northbridge/intel/sch/northbridge.c | 16 ++--- src/northbridge/rdc/r8610/northbridge.c | 6 +- src/northbridge/via/cn400/northbridge.c | 18 ++--- src/northbridge/via/cn700/northbridge.c | 12 ++-- src/northbridge/via/cx700/northbridge.c | 10 +-- src/northbridge/via/vt8601/northbridge.c | 10 +-- src/northbridge/via/vt8623/northbridge.c | 16 ++--- src/northbridge/via/vx800/northbridge.c | 10 +-- src/northbridge/via/vx900/northbridge.c | 16 ++--- 50 files changed, 557 insertions(+), 557 deletions(-) diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index ae58a01..c8ef149 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -6,12 +6,12 @@ #include <arch/pci_ops.h> #ifndef __SIMPLE_DEVICE__ -u8 pci_read_config8(device_t dev, unsigned int where); -u16 pci_read_config16(device_t dev, unsigned int where); -u32 pci_read_config32(device_t dev, unsigned int where); -void pci_write_config8(device_t dev, unsigned int where, u8 val); -void pci_write_config16(device_t dev, unsigned int where, u16 val); -void pci_write_config32(device_t dev, unsigned int where, u32 val); +u8 pci_read_config8(struct device * dev, unsigned int where); +u16 pci_read_config16(struct device * dev, unsigned int where); +u32 pci_read_config32(struct device * dev, unsigned int where); +void pci_write_config8(struct device * dev, unsigned int where, u8 val); +void pci_write_config16(struct device * dev, unsigned int where, u16 val); +void pci_write_config32(struct device * dev, unsigned int where, u32 val); #if CONFIG_MMCONF_SUPPORT u8 pci_mmio_read_config8(device_t dev, unsigned int where); diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 0f8c0c2..ad95a48 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -46,7 +46,7 @@ static void qemu_reserve_ports(struct device *dev, unsigned int idx, IORESOURCE_ASSIGNED; } -static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -213,7 +213,7 @@ static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long * return len; } -static int qemu_get_smbios_data(device_t dev, int *handle, unsigned long *current) +static int qemu_get_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len; len = qemu_get_smbios_data16(*handle, current); @@ -234,15 +234,15 @@ static struct device_operations pci_domain_ops = { #endif }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static unsigned int cpu_bus_scan(device_t bus, unsigned int max) +static unsigned int cpu_bus_scan(struct device * bus, unsigned int max) { int max_cpus = fw_cfg_max_cpus(); - device_t cpu; + struct device * cpu; int i; if (max_cpus < 0) @@ -262,7 +262,7 @@ static unsigned int cpu_bus_scan(device_t bus, unsigned int max) return max_cpus; } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.c b/src/northbridge/amd/agesa/00730F01/northbridge.c index 2689569..74fa46c 100644 --- a/src/northbridge/amd/agesa/00730F01/northbridge.c +++ b/src/northbridge/amd/agesa/00730F01/northbridge.c @@ -58,15 +58,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -287,7 +287,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -329,7 +329,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -342,7 +342,7 @@ static void read_resources(device_t dev) } } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -393,7 +393,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -402,7 +402,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -422,7 +422,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -449,11 +449,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -499,7 +499,7 @@ struct chip_operations northbridge_amd_agesa_00730F01_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -512,7 +512,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -559,7 +559,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -663,7 +663,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -840,13 +840,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -882,12 +882,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -983,7 +983,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1068,7 +1068,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1076,16 +1076,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1096,7 +1096,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index d3d6479..ce3bfad 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -52,10 +52,10 @@ typedef struct dram_base_mask { struct amdfam10_sysconf_t sysconf; -static device_t __f0_dev[NODE_NUMS]; -static device_t __f1_dev[NODE_NUMS]; -static device_t __f2_dev[NODE_NUMS]; -static device_t __f4_dev[NODE_NUMS]; +static struct device * __f0_dev[NODE_NUMS]; +static struct device * __f1_dev[NODE_NUMS]; +static struct device * __f2_dev[NODE_NUMS]; +static struct device * __f4_dev[NODE_NUMS]; static unsigned fx_devs = 0; #if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 @@ -64,7 +64,7 @@ static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; @@ -96,7 +96,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -149,7 +149,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, #endif #if CONFIG_PCI_BUS_SEGN_BITS -static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, +static u32 check_segn(struct device * dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) { //check segbusn here, We need every node have the same segn @@ -249,7 +249,7 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, sysconf.mmio_addr_num = index+1; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -318,7 +318,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first @@ -357,7 +357,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi #endif } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -407,7 +407,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -415,7 +415,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +static u32 amdfam10_nodeid(struct device * dev) { #if NODE_NUMS == 64 unsigned busn; @@ -442,7 +442,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -450,7 +450,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -470,7 +470,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -505,7 +505,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -541,7 +541,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -600,7 +600,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(device_t dev) +static void amdfam10_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -612,7 +612,7 @@ static void amdfam10_read_resources(device_t dev) } } -static void amdfam10_set_resource(device_t dev, struct resource *resource, +static void amdfam10_set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -667,7 +667,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -676,7 +676,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -696,7 +696,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(device_t dev) +static void amdfam10_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -723,12 +723,12 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0xff; nodeid = amdfam10_nodeid(dev); @@ -770,7 +770,7 @@ struct chip_operations northbridge_amd_agesa_family10_ops = { }; -static void amdfam10_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(struct device * dev) { unsigned reg; @@ -783,7 +783,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -829,7 +829,7 @@ static void amdfam10_domain_read_resources(device_t dev) #endif } -static void amdfam10_domain_enable_resources(device_t dev) +static void amdfam10_domain_enable_resources(struct device * dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); @@ -904,7 +904,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void amdfam10_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1071,7 +1071,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1102,7 +1102,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1132,7 +1132,7 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1150,7 +1150,7 @@ static void sysconf_init(device_t dev) // first node sysconf.bsp_apicid = lapicid(); } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1186,12 +1186,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int nodes; @@ -1282,7 +1282,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < nodes; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1363,7 +1363,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1371,16 +1371,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1391,7 +1391,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h index 8c8d9a0..a38cde8 100644 --- a/src/northbridge/amd/agesa/family10/reset_test.h +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -33,7 +33,7 @@ static inline u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -42,7 +42,7 @@ static inline u32 warm_reset_detect(u8 nodeid) static inline void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 00ff641..116a466 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 94de010..7d1b118 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -41,14 +41,14 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs=0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -89,7 +89,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -98,7 +98,7 @@ static void f1_write_config32(unsigned reg, u32 value) } -static u32 amdfam12_nodeid(device_t dev) +static u32 amdfam12_nodeid(struct device * dev) { printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); return (dev->path.pci.devfn >> 3) - CONFIG_CDB; @@ -108,7 +108,7 @@ static u32 amdfam12_nodeid(device_t dev) #include "amdfam12_conf.c" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -128,7 +128,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -137,7 +137,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -158,7 +158,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam12_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 result, reg; @@ -182,7 +182,7 @@ static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam12_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -218,7 +218,7 @@ static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam12_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -343,7 +343,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void read_resources(device_t dev) } -static void set_resource(device_t dev, struct resource *resource, +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -412,10 +412,10 @@ static void set_resource(device_t dev, struct resource *resource, #if CONFIG_CONSOLE_VGA_MULTI -extern device_t vga_pri; // the primary vga device, defined in device.c +extern struct device * vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -447,7 +447,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) } -static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -503,7 +503,7 @@ static void setup_uma_memory(void) /* Domain/Root Complex related code */ -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -518,7 +518,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -581,7 +581,7 @@ static void domain_read_resources(device_t dev) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -765,7 +765,7 @@ printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -783,7 +783,7 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -797,7 +797,7 @@ static void cpu_bus_read_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); @@ -809,7 +809,7 @@ static void cpu_bus_set_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h index 4edb525..c3fc171 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.h +++ b/src/northbridge/amd/agesa/family12/northbridge.h @@ -23,6 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -device_t get_node_pci(u32 nodeid, u32 fn); +struct device * get_node_pci(u32 nodeid, u32 fn); #endif /* NORTHBRIDGE_AMD_AGESA_FAM12H_H */ diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index c255213..b72b21b 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t { static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; } - device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 57502e9..de1465b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -44,13 +44,13 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs = 0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -88,7 +88,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -96,14 +96,14 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam14_nodeid(device_t dev) +static u32 amdfam14_nodeid(struct device * dev) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } #include "amdfam14_conf.c" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -119,7 +119,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -127,7 +127,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -146,7 +146,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, +static struct resource *amdfam14_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -173,7 +173,7 @@ static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, return resource; } -static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, +static struct resource *amdfam14_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -208,7 +208,7 @@ static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, return resource; } -static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam14_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(device_t dev) #endif } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -409,10 +409,10 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) } #if CONFIG_CONSOLE_VGA_MULTI -extern device_t vga_pri; // the primary vga device, defined in device.c +extern struct device * vga_pri; // the primary vga device, defined in device.c #endif -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -444,7 +444,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -477,7 +477,7 @@ static void nb_set_resources(device_t dev) /* Domain/Root Complex related code */ -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -492,7 +492,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base & 0x30); } else { // io @@ -566,7 +566,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -757,7 +757,7 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { #if CONFIG_AMD_SB_CIMX if (!acpi_is_wakeup_s3()) { @@ -779,18 +779,18 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus = dev->link_list; - device_t cpu; + struct device * cpu; int apic_id, cores_found; /* There is only one node for fam14, but there may be multiple cores. */ @@ -809,7 +809,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.h b/src/northbridge/amd/agesa/family14/northbridge.h index 474e74c..6046137 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.h +++ b/src/northbridge/amd/agesa/family14/northbridge.h @@ -23,6 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -device_t get_node_pci(u32 nodeid, u32 fn); +struct device * get_node_pci(u32 nodeid, u32 fn); #endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */ diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 34d7ea3..4a44598 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -57,16 +57,16 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -288,7 +288,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -332,7 +332,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(device_t dev) } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -412,7 +412,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -422,7 +422,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -443,7 +443,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -476,11 +476,11 @@ static void northbridge_init(struct device *dev) { } -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { @@ -526,7 +526,7 @@ struct chip_operations northbridge_amd_agesa_family15_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -540,7 +540,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -588,7 +588,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); @@ -681,7 +681,7 @@ static void setup_uma_memory(void) #endif } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -860,13 +860,13 @@ static struct device_operations pci_domain_ops = { }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -902,12 +902,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -987,7 +987,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1079,7 +1079,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1087,20 +1087,20 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { } @@ -1140,7 +1140,7 @@ struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { }; /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max) { max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); return max; diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h index 99fdcae..3a90964 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.h +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -22,6 +22,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max); +static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max); #endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */ diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 3765f20..5b3529b 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -23,7 +23,7 @@ #include <device/pci_ops.h> #include <lib.h> -static void iommu_read_resources(device_t dev) +static void iommu_read_resources(struct device * dev) { struct resource *res; @@ -39,7 +39,7 @@ static void iommu_read_resources(device_t dev) res->flags = IORESOURCE_MEM; } -static void iommu_set_resources(device_t dev) +static void iommu_set_resources(struct device * dev) { struct resource *res; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 3e2c635..d5cef28 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -354,7 +354,7 @@ static void nb_read_resources(device_t dev) #endif } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -405,7 +405,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -414,7 +414,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -434,7 +434,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -494,7 +494,7 @@ struct chip_operations northbridge_amd_agesa_family15tn_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -507,7 +507,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -554,7 +554,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -647,7 +647,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -824,13 +824,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -866,12 +866,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -951,7 +951,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1041,7 +1041,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1049,20 +1049,20 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 5572282..9a0de72 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask { static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0; static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); } -static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; } -static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -328,7 +328,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -341,7 +341,7 @@ static void read_resources(device_t dev) } } -static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -392,7 +392,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */ -static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -401,7 +401,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -421,7 +421,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); } -static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -448,11 +448,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -498,7 +498,7 @@ struct chip_operations northbridge_amd_agesa_family16kb_ops = { .enable_dev = 0, }; -static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg; @@ -511,7 +511,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -558,7 +558,7 @@ static void domain_read_resources(device_t dev) #endif } -static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -653,7 +653,7 @@ static void setup_uma_memory(void) } -static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -830,13 +830,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -872,12 +872,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -957,7 +957,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1047,7 +1047,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id); - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1055,16 +1055,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1075,7 +1075,7 @@ static void cpu_bus_read_resources(device_t dev) #endif } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 529dc0a..3173442 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -53,13 +53,13 @@ struct amdfam10_sysconf_t sysconf; #define FX_DEVS NODE_NUMS -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs=0; -device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if((CONFIG_CDB + nodeid) < 32) { @@ -102,7 +102,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -110,7 +110,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +static u32 amdfam10_nodeid(struct device * dev) { #if NODE_NUMS == 64 unsigned busn; @@ -139,7 +139,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdfam10_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { // I want to put sb chain in bus 0 can I? @@ -152,7 +152,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l u32 max_bus; u32 min_bus; u32 is_sublink1 = (link_num>3); - device_t devx; + struct device * devx; u32 busses; u32 segn = max>>8; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -284,7 +284,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l return max; } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -327,7 +327,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -335,7 +335,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -355,7 +355,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -389,7 +389,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi return resource; } -static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -425,7 +425,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link } -static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -484,7 +484,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) } } -static void amdfam10_read_resources(device_t dev) +static void amdfam10_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -496,7 +496,7 @@ static void amdfam10_read_resources(device_t dev) } } -static void amdfam10_set_resource(device_t dev, struct resource *resource, +static void amdfam10_set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -551,7 +551,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */ -static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link; @@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -580,7 +580,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); } -static void amdfam10_set_resources(device_t dev) +static void amdfam10_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -629,7 +629,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = { .enable_dev = 0, }; -static void amdfam10_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(struct device * dev) { unsigned reg; @@ -642,7 +642,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -767,7 +767,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - device_t dev; + struct device * dev; struct dram_base_mask_t d; u32 sel_m; u32 sel_hi_en; @@ -871,7 +871,7 @@ static void setup_uma_memory(void) #endif } -static void amdfam10_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1087,7 +1087,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1118,7 +1118,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1146,7 +1146,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1188,7 +1188,7 @@ static void sysconf_init(device_t dev) // first node #endif } -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1224,12 +1224,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int nodes; @@ -1324,7 +1324,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < nodes; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus; @@ -1394,7 +1394,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } } #endif - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1402,7 +1402,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX @@ -1411,15 +1411,15 @@ static void cpu_bus_init(device_t dev) #endif } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } -static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { } -static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 7d12dbd..eecb106 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -40,8 +40,8 @@ struct amdk8_sysconf_t sysconf; #define MAX_FX_DEVS 8 -static device_t __f0_dev[MAX_FX_DEVS]; -static device_t __f1_dev[MAX_FX_DEVS]; +static struct device * __f0_dev[MAX_FX_DEVS]; +static struct device * __f1_dev[MAX_FX_DEVS]; static unsigned fx_devs=0; static void get_fx_devs(void) @@ -71,7 +71,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -79,12 +79,12 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdk8_nodeid(device_t dev) +static u32 amdk8_nodeid(struct device * dev) { return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdk8_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { @@ -232,7 +232,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link return max; } -static unsigned amdk8_scan_chains(device_t dev, unsigned max) +static unsigned amdk8_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -271,7 +271,7 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) } -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -279,7 +279,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -299,7 +299,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; } -static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, +static unsigned amdk8_find_reg(struct device * dev, unsigned nodeid, unsigned link, unsigned min, unsigned max) { unsigned resource; @@ -327,17 +327,17 @@ static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, return resource; } -static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8); } -static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8); } -static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) +static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -376,9 +376,9 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) } } -static void amdk8_create_vga_resource(device_t dev, unsigned nodeid); +static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid); -static void amdk8_read_resources(device_t dev) +static void amdk8_read_resources(struct device * dev) { unsigned nodeid; struct bus *link; @@ -391,7 +391,7 @@ static void amdk8_read_resources(device_t dev) amdk8_create_vga_resource(dev, nodeid); } -static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid) +static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) { struct bus *link; resource_t rbase, rend; @@ -488,7 +488,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned report_resource_stored(dev, resource, buf); } -static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) +static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) { struct resource *resource; struct bus *link; @@ -498,7 +498,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -529,7 +529,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) IORESOURCE_ASSIGNED; } -static void amdk8_set_resources(device_t dev) +static void amdk8_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -638,7 +638,7 @@ struct chip_operations northbridge_amd_amdk8_ops = { .enable_dev = 0, }; -static void amdk8_domain_read_resources(device_t dev) +static void amdk8_domain_read_resources(struct device * dev) { unsigned reg; @@ -651,7 +651,7 @@ static void amdk8_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; nodeid = limit & 7; reg_link = (limit >> 4) & 3; reg_dev = __f0_dev[nodeid]; @@ -765,7 +765,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - device_t dev; + struct device * dev; u32 base, limit; u32 hoist; u32 hole_sizek; @@ -810,7 +810,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) { int i; u32 carry_over; - device_t dev; + struct device * dev; u32 base, limit; u32 basek; u32 hoist; @@ -904,7 +904,7 @@ static void setup_uma_memory(void) #endif } -static void amdk8_domain_set_resources(device_t dev) +static void amdk8_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1121,7 +1121,7 @@ static void amdk8_domain_set_resources(device_t dev) } -static u32 amdk8_domain_scan_bus(device_t dev, u32 max) +static u32 amdk8_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1136,7 +1136,7 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1164,7 +1164,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1200,10 +1200,10 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; int bsp_apicid; int i,j; unsigned nb_cfg_54; @@ -1258,7 +1258,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) remap_bsp_lapic(cpu_bus); for(i = 0; i < sysconf.nodes; i++) { - device_t cpu_dev; + struct device * cpu_dev; /* Find the cpu's pci device */ cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); @@ -1267,7 +1267,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * ensure all of the cpu's pci devices are found. */ int local_j; - device_t dev_f0; + struct device * dev_f0; for(local_j = 0; local_j <= 3; local_j++) { cpu_dev = pci_probe_dev(NULL, dev_mc->bus, PCI_DEVFN(0x18 + i, local_j)); @@ -1334,7 +1334,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } } - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1342,7 +1342,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; } -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { #if CONFIG_WAIT_BEFORE_CPUS_INIT cpus_ready_for_init(); @@ -1350,7 +1350,7 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index fa23344..09cdce5 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -66,7 +66,7 @@ void nb_Late_Post_Init(void) LibSystemApiCall(AmdLatePostInit, &gConfig); } -static void rd890_enable(device_t dev) +static void rd890_enable(struct device * dev) { u32 address = 0; u32 devfn; diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index c8f7f94..84afcfb 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -14,7 +14,7 @@ /* */ -static void optimize_xbus(device_t dev) +static void optimize_xbus(struct device * dev) { /* Optimise X-Bus performance */ pci_write_config8(dev, 0x40, 0x1e); @@ -31,13 +31,13 @@ static void optimize_xbus(device_t dev) * this region? **/ -static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { write32(GX_BASE+BC_XMAP_2, 0x77777777); write32(GX_BASE+BC_XMAP_3, 0x77777777); } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); @@ -65,9 +65,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -126,13 +126,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index e2f4d11..3b0e8a8 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -213,12 +213,12 @@ int sizeram(void) return sizem; } -static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__); @@ -273,11 +273,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { int idx; u32 tomk; - device_t mc_dev; + struct device * mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -296,7 +296,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void pci_domain_enable(device_t dev) +static void pci_domain_enable(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -318,14 +318,14 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index df69b51..c309e1b 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -291,11 +291,11 @@ int sizeram(void) return sizem; } -static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { } -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { //msr_t msr; @@ -372,11 +372,11 @@ static const struct pci_driver northbridge_driver __pci_driver = { #include <cbmem.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { int idx; u32 tomk; - device_t mc_dev; + struct device * mc_dev; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -395,7 +395,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void pci_domain_enable(device_t dev) +static void pci_domain_enable(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); @@ -422,14 +422,14 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index fcebed8..e193168 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -30,7 +30,7 @@ #define SPI_BASE 0xfc00 -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n"); // enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable. @@ -75,9 +75,9 @@ static void set_cmos_memory_size(unsigned long sizek) * don't touch it. */ } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n"); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 2efa787..cf1bc45 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -20,9 +20,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) #endif -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -110,12 +110,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 54c700b..37202ce 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -16,9 +16,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -97,7 +97,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -117,12 +117,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index c632b2d..652981a 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 e7520_domain_scan_bus(device_t dev, u32 max) +static u32 e7520_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -122,7 +122,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -134,7 +134,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -145,7 +145,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -170,12 +170,12 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x3590, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -188,7 +188,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 7625596..5d7db0b 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -15,9 +15,9 @@ static unsigned int max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -106,7 +106,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 e7525_domain_scan_bus(device_t dev, u32 max) +static u32 e7525_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -121,7 +121,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -133,7 +133,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -144,7 +144,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -169,12 +169,12 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x359e, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -187,7 +187,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 98c0b9c..5050078 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -63,7 +63,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -112,7 +112,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device * dev) { /* * Notify FSP for PostPciEnumeration. @@ -123,7 +123,7 @@ static void finalize_dev (device_t dev) printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device * dev) { u32 tomlow, bmbound, bsmmrrl, bsmmrrh; u64 bmbound_hi; @@ -168,7 +168,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -177,7 +177,7 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* * Assign memory resources for PCI devices @@ -187,13 +187,13 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { /* Call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -208,7 +208,7 @@ static void northbridge_init(struct device *dev) { } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { } @@ -258,13 +258,13 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = pci_device_ids, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -276,7 +276,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index a164536..86b3a78 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -68,7 +68,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -121,7 +121,7 @@ static void add_fixed_resources(struct device *dev, int index) mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -261,7 +261,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -283,7 +283,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -297,7 +297,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -322,7 +322,7 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -375,13 +375,13 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -393,7 +393,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index e93d036..9be19e5 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -46,7 +46,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) *base = 0; *len = 0; - const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; @@ -73,7 +73,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) return 0; } -static void mch_domain_read_resources(device_t dev) +static void mch_domain_read_resources(struct device * dev) { u64 tom, touud; u32 tomk, tolud, uma_sizek = 0, usable_tomk; @@ -170,7 +170,7 @@ static void mch_domain_read_resources(device_t dev) } } -static void mch_domain_set_resources(device_t dev) +static void mch_domain_set_resources(struct device * dev) { struct resource *resource; int i; @@ -185,7 +185,7 @@ static void mch_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void mch_domain_init(device_t dev) +static void mch_domain_init(struct device * dev) { u32 reg32; @@ -207,12 +207,12 @@ static struct device_operations pci_domain_ops = { }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -225,7 +225,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 1b4658a..5246e50 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -39,7 +39,7 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -69,7 +69,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -87,7 +87,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -106,7 +106,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -126,7 +126,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device * dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -146,7 +146,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device * dev) { int i; @@ -203,7 +203,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device * dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -272,7 +272,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device * dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -280,7 +280,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device * dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -291,7 +291,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device * dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -383,7 +383,7 @@ static void mc_add_dram_resources(device_t dev) #endif } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -395,7 +395,7 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -433,7 +433,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; @@ -480,12 +480,12 @@ static const struct pci_driver mc_driver_hsw_ult __pci_driver = { .device = PCI_DEVICE_ID_HSW_ULT, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { bsp_init_and_start_aps(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -497,7 +497,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 589c9c5..107826d 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -39,9 +39,9 @@ static u32 max_bus; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -132,7 +132,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static u32 i3100_domain_scan_bus(device_t dev, u32 max) +static u32 i3100_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -147,7 +147,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -159,7 +159,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -170,7 +170,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -180,7 +180,7 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device * dev; u64 mmcfg; dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_MC, 0); // 0:0x13.0 @@ -219,12 +219,12 @@ static const struct pci_driver mc_driver __pci_driver = { .device = PCI_DEVICE_ID_INTEL_3100_MC, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -237,7 +237,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 1e6b58e..e50c159 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -12,7 +12,7 @@ #include "northbridge.h" #include "i440bx.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -32,9 +32,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, }; -static void i440bx_domain_set_resources(device_t dev) +static void i440bx_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -81,12 +81,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index ca4ec6e..ef92d88 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -38,7 +38,7 @@ * Maciej */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -58,9 +58,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7180, }; -static void i440lx_domain_set_resources(device_t dev) +static void i440lx_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -107,12 +107,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index c28b0c1..034c4a5 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <cbmem.h> -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -40,15 +40,15 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; uint32_t hecbase, amsize, tolm; uint64_t ambase, memsize; int idx = 0; - device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); - device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + struct device * dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + struct device * dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); pci_dev_read_resources(dev); @@ -139,12 +139,12 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = nb_ids, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } static struct device_operations cpu_bus_ops = { @@ -154,7 +154,7 @@ static struct device_operations cpu_bus_ops = { .init = cpu_bus_init, .scan_bus = 0, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -168,7 +168,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 9d10f1d..fea30b3 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -32,7 +32,7 @@ #include "northbridge.h" #include "i82810.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -69,9 +69,9 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -136,12 +136,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index c78bdf1..8ab0a33 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -30,7 +30,7 @@ #include <string.h> #include "i82830.h" -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -50,9 +50,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3575, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0; @@ -103,12 +103,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 5c0379c..c2d1267 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -32,7 +32,7 @@ #include <cpu/x86/cache.h> #include <cpu/cpu.h> -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -52,9 +52,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3580, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); @@ -119,12 +119,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 815d4bf..eabee33 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -81,7 +81,7 @@ static void add_fixed_resources(struct device *dev, int index) } } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint32_t pci_tolm; uint8_t tolud, reg8; @@ -185,7 +185,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -207,7 +207,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -221,7 +221,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -274,12 +274,12 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x27a0, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -291,7 +291,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index a31e85c..7253736 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -96,7 +96,7 @@ static void add_fixed_resources(struct device *dev, int index) #endif } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -114,7 +114,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { uint32_t tseg_base; uint64_t TOUUD; @@ -165,13 +165,13 @@ static void mc_read_resources(device_t dev) add_fixed_resources(dev, 10); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { /* And call the normal set_resources */ pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -283,7 +283,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -324,12 +324,12 @@ static const struct pci_driver mc_driver_44 __pci_driver = { .device = 0x0044, /* Nehalem */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -341,7 +341,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 9331afa..48ed011 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -66,7 +66,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; *base = 0; @@ -132,7 +132,7 @@ static void add_fixed_resources(struct device *dev, int index) bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -266,7 +266,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -288,7 +288,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -302,7 +302,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -412,7 +412,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -465,12 +465,12 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -482,7 +482,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 1f327c6..0186fda 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -33,7 +33,7 @@ static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); @@ -93,7 +93,7 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { u32 pci_tolm; u8 reg8; @@ -200,7 +200,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; @@ -226,7 +226,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base + resource->size)); } -static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource; @@ -239,7 +239,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -292,12 +292,12 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x8100, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -309,7 +309,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index d69c4f6..5ca0ab3 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -33,7 +33,7 @@ static unsigned long get_memory_size(void) { - device_t nb_dev; + struct device * nb_dev; u8 size; nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, @@ -42,7 +42,7 @@ static unsigned long get_memory_size(void) return (2 * 1024) << size; } -static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(struct device * dev) { u32 pci_tolm = find_pci_tolm(dev->link_list); unsigned long tomk = 0, tolmk; @@ -92,7 +92,7 @@ static int rdc_get_smbios_data16(int handle, unsigned long *current) return len; } -static int rdc_get_smbios_data(device_t dev, int *handle, unsigned long *current) +static int rdc_get_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len; len = rdc_get_smbios_data16(*handle, current); diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 149eab3..e154e08 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn400.h" -static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { - device_t vlink_dev; + struct device * vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8; int i, j; @@ -140,7 +140,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, }; -static void cn400_domain_read_resources(device_t dev) +static void cn400_domain_read_resources(struct device * dev) { struct resource *resource; @@ -162,7 +162,7 @@ static void cn400_domain_read_resources(device_t dev) } #ifdef UNUSED_CODE -static void ram_reservation(device_t dev, unsigned long index, +static void ram_reservation(struct device * dev, unsigned long index, unsigned long base, unsigned long size) { struct resource *res; @@ -177,9 +177,9 @@ static void ram_reservation(device_t dev, unsigned long index, } #endif -static void cn400_domain_set_resources(device_t dev) +static void cn400_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering %s.\n", __func__); @@ -219,7 +219,7 @@ static void cn400_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Leaving %s.\n", __func__); } -static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int cn400_domain_scan_bus(struct device * dev, unsigned int max) { printk(BIOS_DEBUG, "Entering %s.\n", __func__); @@ -236,12 +236,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index a326baf..8591aab 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn700.h" -static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { - device_t vlink_dev; + struct device * vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg; @@ -97,11 +97,11 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* The order is important to find the correct RAM size. */ static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); @@ -156,12 +156,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index e3314ff..7b3e1f3 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -31,9 +31,9 @@ #include <cbmem.h> #include <arch/acpi.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; unsigned char reg; unsigned long tomk, tolmk; @@ -82,7 +82,7 @@ static void pci_domain_set_resources(device_t dev) unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device * dev; u64 mmcfg; dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 @@ -112,12 +112,12 @@ static struct device_operations pci_domain_ops = { .write_acpi_tables = acpi_write_hpet, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index bed434d..4c5cc2b 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -17,7 +17,7 @@ * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "VT8601 random fixup ...\n"); pci_write_config8(dev, 0x70, 0xc0); @@ -44,12 +44,12 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { static const uint8_t ramregs[] = { 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 }; - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; pci_tolm = find_pci_tolm(dev->link_list); @@ -102,12 +102,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 6e0f4ea..70934ba 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -19,9 +19,9 @@ * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { - device_t fb_dev; + struct device * fb_dev; unsigned long fb; unsigned char c; @@ -58,7 +58,7 @@ static void northbridge_init(device_t dev) } } -static void nullfunc(device_t dev) +static void nullfunc(struct device * dev) { /* Nothing to do */ } @@ -76,7 +76,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8623, }; -static void agp_init(device_t dev) +static void agp_init(struct device * dev) { printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n"); @@ -103,10 +103,10 @@ static const struct pci_driver agp_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8633_1, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n"); @@ -162,12 +162,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 214ca8b..d2b5c1e 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -37,7 +37,7 @@ /* !!FIXME!! I declared this to fix the build. */ u8 acpi_sleep_type = 0; -static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { /* set VGA in uma_ram_setting.c, not in this function. @@ -71,13 +71,13 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* * the order is important to find the correct ram size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; u8 reg; @@ -145,12 +145,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 53cada3..6ba42c9 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -60,7 +60,7 @@ uint64_t get_uma_memory_base(void) return uma_memory_base; } -static u64 vx900_get_top_of_ram(device_t mcu) +static u64 vx900_get_top_of_ram(struct device * mcu) { u16 reg16; /* The last valid DRAM address is computed by the MCU @@ -97,7 +97,7 @@ static void killme_debug_4g_remap_reg(u32 reg32) * * @return The new top of memory. */ -static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) +static u64 vx900_remap_above_4g(struct device * mcu, u32 tolm) { size_t i; u8 reg8, start8, end8, start, end; @@ -216,7 +216,7 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) return newtor; } -static void vx900_set_resources(device_t dev) +static void vx900_set_resources(struct device * dev) { u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk; @@ -228,7 +228,7 @@ static void vx900_set_resources(device_t dev) "========================================\n"); int idx = 10; - const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + struct device * mcu = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); if (!mcu) { @@ -286,7 +286,7 @@ static void vx900_set_resources(device_t dev) assign_resources(dev->link_list); } -static void vx900_read_resources(device_t dev) +static void vx900_read_resources(struct device * dev) { /* Our fixed resources start at 0 */ int idx = 0; @@ -317,12 +317,12 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device * dev) { } @@ -334,7 +334,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) {

1 0

Patch set updated for coreboot: ba7a1a8 {arch, cpu, drivers, ec}: Don't hide pointers behind typedefs
by Edward O'Callaghan 25 Oct '14

25 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7146 -gerrit commit ba7a1a82d2522cb0efe4bed98c0ca5ae953b73f5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Oct 22 13:39:12 2014 +1100 {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/boot/acpi.c | 6 +++--- src/arch/x86/boot/mpspec.c | 6 ++++-- src/arch/x86/boot/smbios.c | 6 +++--- src/cpu/allwinner/a10/cpu.c | 8 ++++---- src/drivers/ati/ragexl/xlinit.c | 2 +- src/drivers/dec/21143/21143.c | 2 +- src/drivers/emulation/qemu/bochs.c | 2 +- src/drivers/emulation/qemu/cirrus.c | 2 +- src/drivers/generic/ioapic/ioapic.c | 8 ++++---- src/drivers/i2c/adm1026/adm1026.c | 6 +++--- src/drivers/i2c/adm1027/adm1027.c | 6 +++--- src/drivers/i2c/adt7463/adt7463.c | 4 ++-- src/drivers/i2c/at24rf08c/at24rf08c.c | 6 +++--- src/drivers/i2c/at24rf08c/lenovo_serials.c | 14 +++++++------- src/drivers/i2c/i2cmux/i2cmux.c | 4 ++-- src/drivers/i2c/i2cmux2/i2cmux2.c | 4 ++-- src/drivers/i2c/lm63/lm63.c | 4 ++-- src/drivers/i2c/rtd2132/rtd2132.c | 24 ++++++++++++------------ src/drivers/i2c/w83793/w83793.c | 18 +++++++++--------- src/drivers/i2c/w83795/w83795.c | 6 +++--- src/drivers/ics/954309/ics954309.c | 4 ++-- src/ec/compal/ene932/ec.c | 8 ++++---- src/ec/google/chromeec/ec_lpc.c | 8 ++++---- src/ec/kontron/it8516e/ec.c | 4 ++-- src/ec/lenovo/h8/h8.c | 4 ++-- src/ec/lenovo/pmh7/pmh7.c | 2 +- src/ec/quanta/ene_kb3940q/ec.c | 8 ++++---- src/ec/quanta/it8518/ec.c | 8 ++++---- src/ec/smsc/mec1308/ec.c | 2 +- 29 files changed, 94 insertions(+), 92 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index c3c946d..b506cb4 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -141,7 +141,7 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic) unsigned long acpi_create_madt_lapics(unsigned long current) { - device_t cpu; + struct device *cpu; int index = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { @@ -278,7 +278,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) acpigen_set_current((char *) current); { #if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) - device_t dev; + struct device *dev; for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_fill_ssdt_generator) { dev->ops->acpi_fill_ssdt_generator(); @@ -708,7 +708,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt; acpi_mcfg_t *mcfg; acpi_madt_t *madt; - device_t dev; + struct device *dev; current = start; diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index d079d08..8049be4 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -166,7 +166,7 @@ void smp_write_processors(struct mp_config_table *mc) unsigned cpu_features; unsigned cpu_feature_flags; struct cpuid_result result; - device_t cpu; + struct device *cpu; boot_apic_id = lapicid(); apic_version = lapic_read(LAPIC_LVR) & 0xff; @@ -493,7 +493,9 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) struct drivers_generic_ioapic_config *ioapic_config; struct mp_config_table *mc; int isa_bus, pin, parentpin; - device_t dev, parent, oldparent; + struct device *dev; + struct device *parent; + struct device *oldparent; void *tmp, *v; int isaioapic = -1, have_fixed_entries; diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 724def3..64889f7 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -303,7 +303,7 @@ static int smbios_write_type11(unsigned long *current, int *handle) { struct smbios_type11 *t = (struct smbios_type11 *)*current; int len; - device_t dev; + struct device *dev; memset(t, 0, sizeof *t); t->type = SMBIOS_OEM_STRINGS; @@ -379,9 +379,9 @@ static int smbios_write_type127(unsigned long *current, int handle) return len; } -static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *current) +static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current) { - device_t dev; + struct device *dev; int len = 0; for(dev = tree; dev; dev = dev->next) { diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c index e0d4cdf..fac5730 100644 --- a/src/cpu/allwinner/a10/cpu.c +++ b/src/cpu/allwinner/a10/cpu.c @@ -11,7 +11,7 @@ #include <cbmem.h> -static void cpu_enable_resources(device_t dev) +static void cpu_enable_resources(struct device *dev) { ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10, CONFIG_DRAM_SIZE_MB << 10); @@ -20,12 +20,12 @@ static void cpu_enable_resources(device_t dev) */ } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { /* TODO: Check if anything else needs to be explicitly initialized */ } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -37,7 +37,7 @@ static struct device_operations cpu_ops = { .scan_bus = NULL, }; -static void a1x_cpu_enable_dev(device_t dev) +static void a1x_cpu_enable_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index cdcb862..41cea72 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -489,7 +489,7 @@ static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) info->mem_refresh_rate = i; } #endif /*CONFIG_CONSOLE_BTEXT */ -static void ati_ragexl_init(device_t dev) +static void ati_ragexl_init(struct device *dev) { u32 chip_id; int j; diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index 7ce3d6b..b26b22c 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <console/console.h> -static void dec_21143_enable(device_t dev) +static void dec_21143_enable(struct device *dev) { printk(BIOS_DEBUG, "Initializing DECchip 21143\n"); diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index f2e4dfb..cb0075a 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -58,7 +58,7 @@ static int bochs_read(int index) } #endif -static void bochs_init(device_t dev) +static void bochs_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) struct edid edid; diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index c96e032..1c659eb 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -212,7 +212,7 @@ write_hidden_dac (uint8_t data) } #endif -static void cirrus_init(device_t dev) +static void cirrus_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) uint8_t cr_ext, cr_overlay; diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 42b2f07..aa043a0 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -12,7 +12,7 @@ #include <arch/io.h> #include <cpu/x86/lapic.h> -static void ioapic_init(device_t dev) +static void ioapic_init(struct device * dev) { struct drivers_generic_ioapic_config *config = dev->chip_info; u32 bsp_lapicid = lapicid(); @@ -86,15 +86,15 @@ static void ioapic_init(device_t dev) } } -static void ioapic_enable_resources(device_t dev) +static void ioapic_enable_resources(struct device * dev) { } -static void ioapic_nop(device_t dummy) +static void ioapic_nop(struct device * dummy) { } -static void ioapic_read_resources(device_t dev) +static void ioapic_read_resources(struct device * dev) { struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; struct resource *res; diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index ab85eb5..7d37ec4 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -19,7 +19,7 @@ #define ADM1026_REG_CONFIG2 0x01 #define ADM1026_REG_CONFIG3 0x07 -static void adm1026_enable_monitoring(device_t dev) +static void adm1026_enable_monitoring(struct device * dev) { int result; result = smbus_read_byte(dev, ADM1026_REG_CONFIG1); @@ -33,7 +33,7 @@ static void adm1026_enable_monitoring(device_t dev) } } -static void adm1026_init(device_t dev) +static void adm1026_init(struct device * dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -44,7 +44,7 @@ static void adm1026_init(device_t dev) } } -static void adm1026_noop(device_t dummy) +static void adm1026_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c index e83f2c4..12b48a5 100644 --- a/src/drivers/i2c/adm1027/adm1027.c +++ b/src/drivers/i2c/adm1027/adm1027.c @@ -18,7 +18,7 @@ #define ADM1027_REG_CONFIG2 0x73 #define ADM1027_REG_CONFIG3 0x78 -static void adm1027_enable_monitoring(device_t dev) +static void adm1027_enable_monitoring(struct device * dev) { int result; @@ -39,7 +39,7 @@ static void adm1027_enable_monitoring(device_t dev) printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n"); } -static void adm1027_init(device_t dev) +static void adm1027_init(struct device * dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -50,7 +50,7 @@ static void adm1027_init(device_t dev) } } -static void adm1027_noop(device_t dummy) +static void adm1027_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/adt7463/adt7463.c b/src/drivers/i2c/adt7463/adt7463.c index 9ca9f37..3146dbb 100644 --- a/src/drivers/i2c/adt7463/adt7463.c +++ b/src/drivers/i2c/adt7463/adt7463.c @@ -32,7 +32,7 @@ * See Analog Devices ADT7463 datasheet, Rev C (2004): * http://www.analog.com/en/prod/0,,766_825_ADT7463,00.html */ -static void adt7463_init(device_t adt7463) +static void adt7463_init(struct device * adt7463) { int result; @@ -85,7 +85,7 @@ static void adt7463_init(device_t adt7463) printk(BIOS_DEBUG, "ADT7463 properly initialized\n"); } -static void adt7463_noop(device_t dummy) +static void adt7463_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index a9cf2c5..1faebed 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -25,7 +25,7 @@ #include <smbios.h> #include <console/console.h> -static void at24rf08c_init(device_t dev) +static void at24rf08c_init(struct device * dev) { int i, j; @@ -52,7 +52,7 @@ static void at24rf08c_init(device_t dev) printk (BIOS_DEBUG, "init EEPROM done\n"); } -static void at24rf08c_noop(device_t dummy) +static void at24rf08c_noop(struct device * dummy) { } @@ -63,7 +63,7 @@ static struct device_operations at24rf08c_operations = { .init = at24rf08c_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { dev->ops = &at24rf08c_operations; } diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 53e76da..091e687 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -28,16 +28,16 @@ #define ERROR_STRING "*INVALID*" -static device_t at24rf08c_find_bank(u8 bank) +static struct device * at24rf08c_find_bank(u8 bank) { - device_t dev; + struct device * dev; dev = dev_find_slot_on_smbus(1, 0x54 | bank); if (!dev) printk(BIOS_WARNING, "EEPROM not found\n"); return dev; } -static int at24rf08c_read_byte(device_t dev, u8 addr) +static int at24rf08c_read_byte(struct device * dev, u8 addr) { int t = -1; int j; @@ -54,7 +54,7 @@ static int at24rf08c_read_byte(device_t dev, u8 addr) return t; } -static void at24rf08c_read_string_dev(device_t dev, u8 start, +static void at24rf08c_read_string_dev(struct device * dev, u8 start, u8 len, char *result) { int i; @@ -72,7 +72,7 @@ static void at24rf08c_read_string_dev(device_t dev, u8 start, static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) { - device_t dev; + struct device * dev; dev = at24rf08c_find_bank(bank); if (dev == 0) { @@ -124,7 +124,7 @@ void smbios_mainboard_set_uuid(u8 *uuid) static char result[16]; unsigned i; static int already_read; - device_t dev; + struct device * dev; const int remap[16] = { /* UUID byteswap. */ 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 @@ -173,7 +173,7 @@ const char *smbios_mainboard_version(void) { static char result[100]; static int already_read; - device_t dev; + struct device * dev; int len; if (already_read) diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index b318508..7cb560b 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void i2cmux_set_link(device_t dev, unsigned int link) +static void i2cmux_set_link(struct device * dev, unsigned int link) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -16,7 +16,7 @@ static void i2cmux_set_link(device_t dev, unsigned int link) } } -static void i2cmux_noop(device_t dummy) +static void i2cmux_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index a7d40e2..459fca2 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void i2cmux2_set_link(device_t dev, unsigned int link) +static void i2cmux2_set_link(struct device * dev, unsigned int link) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { if (ops_smbus_bus(get_pbus_smbus(dev))) { @@ -15,7 +15,7 @@ static void i2cmux2_set_link(device_t dev, unsigned int link) } } -static void i2cmux2_noop(device_t dummy) +static void i2cmux2_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index 47a5489..052b524 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -6,7 +6,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> -static void lm63_init(device_t dev) +static void lm63_init(struct device * dev) { int result; if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { @@ -21,7 +21,7 @@ static void lm63_init(device_t dev) } } -static void lm63_noop(device_t dummy) +static void lm63_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/rtd2132/rtd2132.c b/src/drivers/i2c/rtd2132/rtd2132.c index 44333ac..107fd21 100644 --- a/src/drivers/i2c/rtd2132/rtd2132.c +++ b/src/drivers/i2c/rtd2132/rtd2132.c @@ -75,7 +75,7 @@ #define RTD2132_DEBUG_REG 0 -static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) +static void rtd2132_write_reg(struct device * dev, u8 reg, u8 value) { if (RTD2132_DEBUG_REG) printk(BIOS_DEBUG, "RTD2132 0x%02x <- 0x%02x\n", reg, value); @@ -83,18 +83,18 @@ static void rtd2132_write_reg(device_t dev, u8 reg, u8 value) smbus_write_byte(dev, RTD2132_DATA, value); } -static void rtd2132_firmware_stop(device_t dev) +static void rtd2132_firmware_stop(struct device * dev) { smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_STOP); mdelay(60); } -static void rtd2132_firmware_start(device_t dev) +static void rtd2132_firmware_start(struct device * dev) { smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_START); } -static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) +static void rtd2132_pps(struct device * dev, struct drivers_i2c_rtd2132_config *cfg) { /* T2, T5, and T7 register values are in units of 4ms. */ rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T1, cfg->t1); @@ -106,7 +106,7 @@ static void rtd2132_pps(device_t dev, struct drivers_i2c_rtd2132_config *cfg) rtd2132_write_reg(dev, RTD2132_COMMAND_PWR_SEQ_T7, cfg->t7 / 4); } -static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) +static void rtd2132_sscg_enable(struct device * dev, u8 sscg_percent) { /* SSCG_Config_0 */ rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, @@ -116,7 +116,7 @@ static void rtd2132_sscg_enable(device_t dev, u8 sscg_percent) rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_1, sscg_percent); } -static void rtd2132_sscg_disable(device_t dev) +static void rtd2132_sscg_disable(struct device * dev) { /* SSCG_Config_0 */ rtd2132_write_reg(dev, RTD2132_COMMAND_SSCG_CONFIG_0, @@ -127,7 +127,7 @@ static void rtd2132_sscg_disable(device_t dev) RTD2132_SSCG_CONFIG_DISABLED); } -static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) +static void rtd2132_sscg(struct device * dev, struct drivers_i2c_rtd2132_config *cfg) { switch (cfg->sscg_percent) { case RTD2132_SSCG_PERCENT_0_0: @@ -152,7 +152,7 @@ static void rtd2132_sscg(device_t dev, struct drivers_i2c_rtd2132_config *cfg) } } -static void rtd2132_lvds_swap(device_t dev, +static void rtd2132_lvds_swap(struct device * dev, struct drivers_i2c_rtd2132_config *cfg) { u8 swap_value = RTD2132_LVDS_SWAP_NORMAL; @@ -186,7 +186,7 @@ static void rtd2132_lvds_swap(device_t dev, rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value); } -static void rtd2132_defaults(device_t dev) +static void rtd2132_defaults(struct device * dev) { static const struct def_setting { u8 reg; @@ -207,7 +207,7 @@ static void rtd2132_defaults(device_t dev) def_settings[i].value); } -static void rtd2132_setup(device_t dev) +static void rtd2132_setup(struct device * dev) { struct drivers_i2c_rtd2132_config *config = dev->chip_info; @@ -233,7 +233,7 @@ static void rtd2132_setup(device_t dev) rtd2132_firmware_start(dev); } -static void rtd2132_init(device_t dev) +static void rtd2132_init(struct device * dev) { if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && ops_smbus_bus(get_pbus_smbus(dev))) { @@ -241,7 +241,7 @@ static void rtd2132_init(device_t dev) } } -static void rtd2132_noop(device_t dummy) +static void rtd2132_noop(struct device * dummy) { } diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c index 8dcfb28..e49600c 100644 --- a/src/drivers/i2c/w83793/w83793.c +++ b/src/drivers/i2c/w83793/w83793.c @@ -25,18 +25,18 @@ #include <device/smbus.h> #include "chip.h" -static int w83793_fan_limit(device_t dev, int fan, uint16_t limit) +static int w83793_fan_limit(struct device * dev, int fan, uint16_t limit) { return smbus_write_byte(dev, 0x90 + fan * 2, limit >> 8) || smbus_write_byte(dev, 0x91 + fan * 2, limit & 0xff); } -static int w83793_bank(device_t dev, int bank) +static int w83793_bank(struct device * dev, int bank) { return smbus_write_byte(dev, 0, bank); } -static int w83793_td_level(device_t dev, int fan, const char *level) +static int w83793_td_level(struct device * dev, int fan, const char *level) { fan *= 0x10; @@ -50,7 +50,7 @@ static int w83793_td_level(device_t dev, int fan, const char *level) return 0; } -static int w83793_tr_level(device_t dev, int fan, const char *level) +static int w83793_tr_level(struct device * dev, int fan, const char *level) { fan *= 0x10; @@ -65,7 +65,7 @@ static int w83793_tr_level(device_t dev, int fan, const char *level) } -static int w83793_td_fan_level(device_t dev, int fan, const char *level) +static int w83793_td_fan_level(struct device * dev, int fan, const char *level) { fan *= 0x10; @@ -79,7 +79,7 @@ static int w83793_td_fan_level(device_t dev, int fan, const char *level) return 0; } -static int w83793_tr_fan_level(device_t dev, int fan, const char *level) +static int w83793_tr_fan_level(struct device * dev, int fan, const char *level) { fan *= 0x10; @@ -94,7 +94,7 @@ static int w83793_tr_fan_level(device_t dev, int fan, const char *level) } -static void w83793_init(device_t dev) +static void w83793_init(struct device * dev) { struct drivers_i2c_w83793_config *config = dev->chip_info; uint16_t id; @@ -220,7 +220,7 @@ static void w83793_init(device_t dev) } -static void w83793_noop(device_t dummy) +static void w83793_noop(struct device * dummy) { } @@ -231,7 +231,7 @@ static struct device_operations w83793_operations = { .init = w83793_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { dev->ops = &w83793_operations; } diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 87aa7f5..0959fa3 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -221,7 +221,7 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) } } -static void w83795_hwm_init(device_t dev) +static void w83795_hwm_init(struct device * dev) { struct device *cpu; struct cpu_info *info; @@ -239,7 +239,7 @@ static void w83795_hwm_init(device_t dev) printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n"); } -static void w83795_noop(device_t dummy) +static void w83795_noop(struct device * dummy) { } @@ -250,7 +250,7 @@ static struct device_operations w83795_operations = { .init = w83795_hwm_init, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { dev->ops = &w83795_operations; } diff --git a/src/drivers/ics/954309/ics954309.c b/src/drivers/ics/954309/ics954309.c index ef62879..adafb60 100644 --- a/src/drivers/ics/954309/ics954309.c +++ b/src/drivers/ics/954309/ics954309.c @@ -29,7 +29,7 @@ #include "chip.h" #include <string.h> -static void ics954309_init(device_t dev) +static void ics954309_init(struct device * dev) { struct drivers_ics_954309_config *config; u8 initdata[12]; @@ -55,7 +55,7 @@ static void ics954309_init(device_t dev) smbus_block_write(dev, 0, 12, initdata); } -static void ics954309_noop(device_t dummy) +static void ics954309_noop(struct device * dummy) { } diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 2e83b4c..ab19696 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -132,7 +132,7 @@ static u8 ec_io_read(u16 addr) */ #ifndef __SMM__ -static void ene932_init(device_t dev) +static void ene932_init(struct device * dev) { if (!dev->enabled) return; @@ -143,13 +143,13 @@ static void ene932_init(device_t dev) } -static void ene932_read_resources(device_t dev) +static void ene932_read_resources(struct device * dev) { /* This function avoids an error on serial console. */ } -static void ene932_enable_resources(device_t dev) +static void ene932_enable_resources(struct device * dev) { /* This function avoids an error on serial console. */ } @@ -164,7 +164,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 4cd30f3..27d5e51 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -137,7 +137,7 @@ int google_chromeec_command(struct chromeec_command *cec_command) #ifndef __PRE_RAM__ #ifndef __SMM__ -static void lpc_ec_init(device_t dev) +static void lpc_ec_init(struct device * dev) { if (!dev->enabled) return; @@ -146,12 +146,12 @@ static void lpc_ec_init(device_t dev) google_chromeec_init(); } -static void lpc_ec_read_resources(device_t dev) +static void lpc_ec_read_resources(struct device * dev) { /* Nothing, but this function avoids an error on serial console. */ } -static void lpc_ec_enable_resources(device_t dev) +static void lpc_ec_enable_resources(struct device * dev) { /* Nothing, but this function avoids an error on serial console. */ } @@ -166,7 +166,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index 925b7ea..fbb2d2a 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -211,7 +211,7 @@ static void it8516e_set_fan_from_options(const config_t *const config, } } -static void it8516e_pm2_init(const device_t dev) +static void it8516e_pm2_init(struct device * dev) { const config_t *const config = dev->chip_info; @@ -251,7 +251,7 @@ static struct pnp_info it8516e_dev_infos[] = { { NULL, IT8516E_LDN_PM3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, }; -static void it8516e_enable(const device_t dev) +static void it8516e_enable(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(it8516e_dev_infos), it8516e_dev_infos); diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 79ef3cd..b16902e 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -167,7 +167,7 @@ u8 h8_build_id_and_function_spec_version(char *buf, u8 buf_len) return i; } -static void h8_smbios_strings(device_t dev, struct smbios_type11 *t) +static void h8_smbios_strings(struct device * dev, struct smbios_type11 *t) { char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; @@ -180,7 +180,7 @@ struct device_operations h8_dev_ops = { .get_smbios_strings = h8_smbios_strings }; -static void h8_enable(device_t dev) +static void h8_enable(struct device * dev) { struct ec_lenovo_h8_config *conf = dev->chip_info; u8 val, tmp; diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index cb0e27b..3ca2606 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -102,7 +102,7 @@ void pmh7_register_write(int reg, int val) #ifndef __PRE_RAM__ #ifndef __SMM__ -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index f0a2308..900b13a 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -141,7 +141,7 @@ static void ene_kb3940q_log_events(void) #endif } -static void ene_kb3940q_init(device_t dev) +static void ene_kb3940q_init(struct device * dev) { if (!dev->enabled) return; @@ -153,13 +153,13 @@ static void ene_kb3940q_init(device_t dev) } -static void ene_kb3940q_read_resources(device_t dev) +static void ene_kb3940q_read_resources(struct device * dev) { /* This function avoids an error on serial console. */ } -static void ene_kb3940q_enable_resources(device_t dev) +static void ene_kb3940q_enable_resources(struct device * dev) { /* This function avoids an error on serial console. */ } @@ -174,7 +174,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index b9cb68f..f6c95bc 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -156,7 +156,7 @@ void ec_it8518_enable_wake_events(void) } #ifndef __SMM__ -static void it8518_init(device_t dev) +static void it8518_init(struct device * dev) { if (!dev->enabled) return; @@ -166,13 +166,13 @@ static void it8518_init(device_t dev) } -static void it8518_read_resources(device_t dev) +static void it8518_read_resources(struct device * dev) { /* This function avoids an error on serial console. */ } -static void it8518_enable_resources(device_t dev) +static void it8518_enable_resources(struct device * dev) { /* This function avoids an error on serial console. */ } @@ -187,7 +187,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; -static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index 4d3b30a..1ad52bb 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -121,7 +121,7 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg) } #if !defined(__PRE_RAM__) && !defined(__SMM__) -static void mec1308_enable(device_t dev) +static void mec1308_enable(struct device * dev) { struct ec_smsc_mec1308_config *conf = dev->chip_info;

1 0

Patch set updated for coreboot: b82d83d mainboard: Don't hide pointer behind typedef
by Edward O'Callaghan 25 Oct '14

25 Oct '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7139 -gerrit commit b82d83d74e41a12ce09ab658c9813328136d6c10 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 21 09:54:41 2014 +1100 mainboard: Don't hide pointer behind typedef Change-Id: I4a0e4e1598e16e13b43401c7e834b292121b63ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advansus/a785e-i/mainboard.c | 2 +- src/mainboard/amd/bimini_fam10/mainboard.c | 4 ++-- src/mainboard/amd/dbm690t/mainboard.c | 4 ++-- src/mainboard/amd/dbm690t/mptable.c | 2 +- src/mainboard/amd/dinar/mainboard.c | 2 +- src/mainboard/amd/dinar/mptable.c | 2 +- src/mainboard/amd/inagua/mainboard.c | 2 +- src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/mahogany/mainboard.c | 8 ++++---- src/mainboard/amd/mahogany/mptable.c | 2 +- src/mainboard/amd/mahogany_fam10/mainboard.c | 8 ++++---- src/mainboard/amd/mahogany_fam10/mptable.c | 2 +- src/mainboard/amd/olivehill/mainboard.c | 2 +- src/mainboard/amd/olivehill/mptable.c | 2 +- src/mainboard/amd/olivehillplus/mainboard.c | 2 +- src/mainboard/amd/olivehillplus/mptable.c | 2 +- src/mainboard/amd/parmer/mainboard.c | 2 +- src/mainboard/amd/parmer/mptable.c | 2 +- src/mainboard/amd/persimmon/mainboard.c | 2 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/amd/pistachio/mainboard.c | 4 ++-- src/mainboard/amd/pistachio/mptable.c | 2 +- src/mainboard/amd/rumba/mainboard.c | 2 +- src/mainboard/amd/serengeti_cheetah/mainboard.c | 2 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 4 ++-- src/mainboard/amd/serengeti_cheetah_fam10/mptable.c | 4 ++-- src/mainboard/amd/south_station/mainboard.c | 2 +- src/mainboard/amd/south_station/mptable.c | 2 +- src/mainboard/amd/thatcher/mainboard.c | 2 +- src/mainboard/amd/thatcher/mptable.c | 2 +- src/mainboard/amd/tilapia_fam10/mainboard.c | 14 +++++++------- src/mainboard/amd/tilapia_fam10/mptable.c | 2 +- src/mainboard/amd/torpedo/mainboard.c | 2 +- src/mainboard/amd/torpedo/mptable.c | 2 +- src/mainboard/amd/union_station/mainboard.c | 2 +- src/mainboard/amd/union_station/mptable.c | 2 +- src/mainboard/apple/macbook21/mainboard.c | 4 ++-- src/mainboard/arima/hdama/mptable.c | 10 +++++----- src/mainboard/asrock/939a785gmh/mainboard.c | 4 ++-- src/mainboard/asrock/939a785gmh/mptable.c | 2 +- src/mainboard/asrock/e350m1/mainboard.c | 2 +- src/mainboard/asrock/e350m1/mptable.c | 2 +- src/mainboard/asrock/imb-a180/mainboard.c | 2 +- src/mainboard/asrock/imb-a180/mptable.c | 2 +- src/mainboard/asus/a8n_e/mptable.c | 2 +- src/mainboard/asus/dsbf/mainboard.c | 2 +- src/mainboard/asus/f2a85-m/mainboard.c | 2 +- src/mainboard/asus/f2a85-m/mptable.c | 2 +- src/mainboard/asus/k8v-x/mainboard.c | 2 +- src/mainboard/asus/m2n-e/mainboard.c | 2 +- src/mainboard/asus/m2n-e/mptable.c | 2 +- src/mainboard/asus/m2v/mainboard.c | 2 +- src/mainboard/asus/m4a78-em/mainboard.c | 8 ++++---- src/mainboard/asus/m4a78-em/mptable.c | 2 +- src/mainboard/asus/m4a785-m/mainboard.c | 10 +++++----- src/mainboard/asus/m4a785-m/mptable.c | 2 +- src/mainboard/asus/m5a88-v/mainboard.c | 2 +- src/mainboard/avalue/eax-785e/mainboard.c | 2 +- src/mainboard/bachmann/ot200/mainboard.c | 2 +- src/mainboard/broadcom/blast/mptable.c | 4 ++-- src/mainboard/dmp/vortex86ex/mainboard.c | 2 +- src/mainboard/emulation/qemu-armv7/mainboard.c | 2 +- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/emulation/qemu-q35/mainboard.c | 2 +- src/mainboard/getac/p470/mainboard.c | 6 +++--- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 2 +- src/mainboard/gigabyte/m57sli/mainboard.c | 2 +- src/mainboard/gigabyte/m57sli/mptable.c | 2 +- src/mainboard/gigabyte/ma785gm/mainboard.c | 8 ++++---- src/mainboard/gigabyte/ma785gm/mptable.c | 2 +- src/mainboard/gigabyte/ma785gmt/mainboard.c | 12 ++++++------ src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +- src/mainboard/gigabyte/ma78gm/mainboard.c | 6 +++--- src/mainboard/gigabyte/ma78gm/mptable.c | 2 +- src/mainboard/gizmosphere/gizmo/mainboard.c | 4 ++-- src/mainboard/gizmosphere/gizmo/mptable.c | 2 +- src/mainboard/google/bolt/mainboard.c | 6 +++--- src/mainboard/google/butterfly/mainboard.c | 6 +++--- src/mainboard/google/daisy/mainboard.c | 4 ++-- src/mainboard/google/falco/mainboard.c | 6 +++--- src/mainboard/google/link/mainboard.c | 6 +++--- src/mainboard/google/nyan/mainboard.c | 4 ++-- src/mainboard/google/nyan_big/mainboard.c | 4 ++-- src/mainboard/google/panther/mainboard.c | 4 ++-- src/mainboard/google/parrot/mainboard.c | 6 +++--- src/mainboard/google/peach_pit/mainboard.c | 4 ++-- src/mainboard/google/peppy/mainboard.c | 6 +++--- src/mainboard/google/rambi/mainboard.c | 6 +++--- src/mainboard/google/samus/mainboard.c | 6 +++--- src/mainboard/google/slippy/mainboard.c | 6 +++--- src/mainboard/google/storm/mainboard.c | 4 ++-- src/mainboard/google/stout/mainboard.c | 4 ++-- src/mainboard/hp/dl145_g1/mptable.c | 2 +- src/mainboard/hp/dl145_g3/mptable.c | 8 ++++---- src/mainboard/hp/dl165_g6_fam10/mptable.c | 8 ++++---- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 2 +- src/mainboard/ibase/mb899/mainboard.c | 2 +- src/mainboard/ibm/e325/mptable.c | 4 ++-- src/mainboard/ibm/e326/mptable.c | 4 ++-- src/mainboard/iei/kino-780am2-fam10/mainboard.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +- src/mainboard/intel/baskingridge/mainboard.c | 2 +- src/mainboard/intel/bayleybay_fsp/mainboard.c | 2 +- src/mainboard/intel/cougar_canyon2/mainboard.c | 2 +- src/mainboard/intel/eagleheights/mptable.c | 2 +- src/mainboard/intel/emeraldlake2/mainboard.c | 2 +- src/mainboard/intel/jarrell/mptable.c | 4 ++-- src/mainboard/intel/minnowmax/mainboard.c | 2 +- src/mainboard/intel/mohonpeak/mainboard.c | 2 +- src/mainboard/intel/truxton/mptable.c | 2 +- src/mainboard/intel/wtm2/mainboard.c | 2 +- src/mainboard/intel/xe7501devkit/mptable.c | 2 +- src/mainboard/iwave/iWRainbowG6/mainboard.c | 2 +- src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +- src/mainboard/iwill/dk8_htx/mainboard.c | 2 +- src/mainboard/iwill/dk8_htx/mptable.c | 4 ++-- src/mainboard/iwill/dk8s2/mptable.c | 4 ++-- src/mainboard/iwill/dk8x/mptable.c | 4 ++-- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 2 +- src/mainboard/jetway/pa78vm5/mainboard.c | 8 ++++---- src/mainboard/jetway/pa78vm5/mptable.c | 2 +- src/mainboard/kontron/986lcd-m/mainboard.c | 2 +- src/mainboard/kontron/kt690/mainboard.c | 4 ++-- src/mainboard/kontron/kt690/mptable.c | 2 +- src/mainboard/kontron/ktqm77/mainboard.c | 6 +++--- src/mainboard/lenovo/t520/mainboard.c | 4 ++-- src/mainboard/lenovo/t530/mainboard.c | 4 ++-- src/mainboard/lenovo/t60/mainboard.c | 7 ++++--- src/mainboard/lenovo/x200/mainboard.c | 4 ++-- src/mainboard/lenovo/x201/mainboard.c | 6 +++--- src/mainboard/lenovo/x220/mainboard.c | 4 ++-- src/mainboard/lenovo/x230/mainboard.c | 4 ++-- src/mainboard/lenovo/x60/mainboard.c | 8 +++++--- src/mainboard/lippert/frontrunner-af/mainboard.c | 2 +- src/mainboard/lippert/frontrunner-af/mptable.c | 2 +- src/mainboard/lippert/toucan-af/mainboard.c | 2 +- src/mainboard/lippert/toucan-af/mptable.c | 2 +- src/mainboard/msi/ms7135/mptable.c | 2 +- src/mainboard/msi/ms7260/mainboard.c | 2 +- src/mainboard/msi/ms7260/mptable.c | 2 +- src/mainboard/msi/ms9185/mptable.c | 4 ++-- src/mainboard/msi/ms9282/mainboard.c | 2 +- src/mainboard/msi/ms9282/mptable.c | 2 +- src/mainboard/msi/ms9652_fam10/mainboard.c | 2 +- src/mainboard/msi/ms9652_fam10/mptable.c | 2 +- src/mainboard/newisys/khepri/mptable.c | 4 ++-- src/mainboard/nvidia/l1_2pvv/mainboard.c | 2 +- src/mainboard/nvidia/l1_2pvv/mptable.c | 8 ++++---- src/mainboard/packardbell/ms2290/mainboard.c | 2 +- src/mainboard/rca/rm4100/mainboard.c | 4 ++-- src/mainboard/roda/rk886ex/mainboard.c | 4 ++-- src/mainboard/roda/rk9/mainboard.c | 2 +- src/mainboard/samsung/lumpy/mainboard.c | 8 +++----- src/mainboard/samsung/stumpy/mainboard.c | 2 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 21 +++++++++++---------- src/mainboard/siemens/sitemp_g1p1/mptable.c | 2 +- src/mainboard/sunw/ultra40/mptable.c | 2 +- src/mainboard/supermicro/h8dme/mptable.c | 2 +- src/mainboard/supermicro/h8dmr/mptable.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qgi/mainboard.c | 2 +- src/mainboard/supermicro/h8qgi/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8scm/mainboard.c | 2 +- src/mainboard/supermicro/h8scm/mptable.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 6 +++--- src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +- src/mainboard/supermicro/x6dai_g/mptable.c | 2 +- src/mainboard/supermicro/x6dhe_g/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhe_g2/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig2/mptable.c | 4 ++-- src/mainboard/supermicro/x7db8/mainboard.c | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 4 ++-- src/mainboard/technexion/tim5690/mptable.c | 2 +- src/mainboard/technexion/tim8690/mainboard.c | 6 +++--- src/mainboard/technexion/tim8690/mptable.c | 2 +- src/mainboard/thomson/ip1000/mainboard.c | 4 ++-- src/mainboard/tyan/s2735/mptable.c | 2 +- src/mainboard/tyan/s2850/mptable.c | 4 ++-- src/mainboard/tyan/s2875/mptable.c | 4 ++-- src/mainboard/tyan/s2880/mptable.c | 6 +++--- src/mainboard/tyan/s2881/mptable.c | 2 +- src/mainboard/tyan/s2882/mptable.c | 6 +++--- src/mainboard/tyan/s2885/mptable.c | 2 +- src/mainboard/tyan/s2891/mainboard.c | 2 +- src/mainboard/tyan/s2891/mptable.c | 2 +- src/mainboard/tyan/s2892/mainboard.c | 2 +- src/mainboard/tyan/s2892/mptable.c | 2 +- src/mainboard/tyan/s2895/mainboard.c | 2 +- src/mainboard/tyan/s2895/mptable.c | 2 +- src/mainboard/tyan/s2912/mptable.c | 2 +- src/mainboard/tyan/s2912_fam10/mptable.c | 2 +- src/mainboard/tyan/s4880/mptable.c | 6 +++--- src/mainboard/tyan/s4882/mptable.c | 6 +++--- src/mainboard/tyan/s8226/mainboard.c | 2 +- src/mainboard/tyan/s8226/mptable.c | 2 +- src/mainboard/via/epia-m850/mainboard.c | 2 +- src/mainboard/winent/mb6047/mainboard.c | 2 +- src/mainboard/winent/mb6047/mptable.c | 2 +- 202 files changed, 342 insertions(+), 340 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 9b6450d..686e968 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in A785E-I board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 32c8862..cd4f50e 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -100,7 +100,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -123,7 +123,7 @@ static void get_ide_dma66(void) * enable the dedicated function in bimini board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index 43a8d91..b92426c 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -119,7 +119,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -180,7 +180,7 @@ static void set_thermal_config(void) * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 09d137a..c154fe4 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 00f1a84..83171a0 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -68,7 +68,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in dinar board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); } diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 4e481f5..e796ffe 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sb700; u32 apicid_rd890; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index dc23007..0c57350 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -74,7 +74,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 7686bd2..65f67cc 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 0e542ff..e851e8f 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -37,7 +37,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -50,7 +50,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -97,7 +97,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index bd31846..bebf041 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 7d4514a..8f90235 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -37,7 +37,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -50,7 +50,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -98,7 +98,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index ac40c84..961a111 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index db4a3ff..d209582 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -182,7 +182,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index 6073fd4..1e58d88 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 73660e4..0ca9217 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 2ba714a..4b192c2 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in parmer board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 05da01a..7999dd8 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 58ac983..34918a8 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -151,7 +151,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 1227d89..1ae44c4 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 75f92bd..db2cbcf 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -76,7 +76,7 @@ static void set_thermal_config(void) u8 byte, byte2; u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* set adt7475 */ ADT7475_write_byte(0x40, 0x04); @@ -250,7 +250,7 @@ static void set_thermal_config(void) * enable the dedicated function in pistachio board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index 09d137a..c154fe4 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c index 5725c78..2f6af29 100644 --- a/src/mainboard/amd/rumba/mainboard.c +++ b/src/mainboard/amd/rumba/mainboard.c @@ -7,7 +7,7 @@ static void init(struct device *dev) { - device_t nic = NULL; + struct device * nic = NULL; unsigned bus = 0; unsigned devfn = PCI_DEVFN(0xd, 0); int nicirq = 1; diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.c b/src/mainboard/amd/serengeti_cheetah/mainboard.c index b9c88f6..26f61f8 100644 --- a/src/mainboard/amd/serengeti_cheetah/mainboard.c +++ b/src/mainboard/amd/serengeti_cheetah/mainboard.c @@ -5,7 +5,7 @@ #include <arch/acpigen.h> #include "mainboard.h" -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 866875d..341b367 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -114,7 +114,7 @@ static void *smp_write_config_table(void *v) for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 5335cb8..3b4731b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -134,7 +134,7 @@ static void *smp_write_config_table(void *v) if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; int jj; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 43d6a78..1be0c0a 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -77,7 +77,7 @@ static void southstation_led_init(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); southstation_led_init(); diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index c2ec4a2..0446e6c 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index 834117e..e7b7ecf 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in thatcher board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { msr_t msr; diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 8ddd1b6..e34b899 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 48e4c17..efea2fa 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -102,7 +102,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -127,7 +127,7 @@ static void get_ide_dma66(void) u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -157,7 +157,7 @@ static void set_gpio40_gfx(void) { u8 byte; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -212,7 +212,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -273,7 +273,7 @@ static void set_thermal_config(void) * enable the dedicated function in tilapia board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ b/src/mainboard/amd/tilapia_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 9b52b89..f5f9c94 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -52,7 +52,7 @@ void set_pcie_dereset(void) /************************************************* * enable the dedicated function in torpedo board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); } diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 477d97a..53038dd 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -186,7 +186,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 8816e8d..ca2e887 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index c2ec4a2..0446e6c 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 99527c1..c9858d8 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -41,12 +41,12 @@ int get_cst_entries(acpi_cstate_t **entries) return 0; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; } diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 6ee2704..c1a6cef 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -13,7 +13,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -48,7 +48,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) static unsigned max_apicid(void) { unsigned max; - device_t dev; + struct device * dev; max = 0; for(dev = all_devices; dev; dev = dev->next) { if (dev->path.type != DEVICE_PATH_APIC) @@ -84,7 +84,7 @@ static void *smp_write_config_table(void *v) apicid_8131_1 = apicid_base + 1; apicid_8131_2 = apicid_base + 2; { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1)); @@ -206,7 +206,7 @@ static void *smp_write_config_table(void *v) static void reboot_if_hotswap(void) { /* Hack patch work around for hot swap enable 33mhz problem */ - device_t dev; + struct device * dev; uint32_t data; unsigned long htic; int reset; diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 58ad8b2..a8d2913 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -67,7 +67,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -95,7 +95,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c index 790d1da..0d174bc 100644 --- a/src/mainboard/asrock/939a785gmh/mptable.c +++ b/src/mainboard/asrock/939a785gmh/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index a98a179..1f554f2 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 14fa316..23b5261 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index ac40c84..961a111 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index d9ca7b7..38db63a 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -183,7 +183,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c index a954d92..b6e1059 100644 --- a/src/mainboard/asus/a8n_e/mptable.c +++ b/src/mainboard/asus/a8n_e/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/asus/dsbf/mainboard.c b/src/mainboard/asus/dsbf/mainboard.c index 1d666c9..cf0c044 100644 --- a/src/mainboard/asus/dsbf/mainboard.c +++ b/src/mainboard/asus/dsbf/mainboard.c @@ -27,7 +27,7 @@ #include <device/pci_ops.h> #include <arch/io.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 191eea8..ff4eb20 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in thatcher board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { msr_t msr; diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index cc81819..e5d7603 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -149,7 +149,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index cd45213..2898b51 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -27,7 +27,7 @@ u32 vt8237_ide_80pin_detect(struct device *dev) { - device_t lpc_dev; + struct device * lpc_dev; u16 acpi_io_base; u32 gpio_in; u32 res; diff --git a/src/mainboard/asus/m2n-e/mainboard.c b/src/mainboard/asus/m2n-e/mainboard.c index 2c18100..7bf4639 100644 --- a/src/mainboard/asus/m2n-e/mainboard.c +++ b/src/mainboard/asus/m2n-e/mainboard.c @@ -21,7 +21,7 @@ #include <device/device.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c index 333ec49..69a5260 100644 --- a/src/mainboard/asus/m2n-e/mptable.c +++ b/src/mainboard/asus/m2n-e/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) struct mp_config_table *mc; unsigned int sbdn; int i, j, bus_isa; - device_t dev; + struct device * dev; struct resource *res; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c index 21adac0..cbacc88 100644 --- a/src/mainboard/asus/m2v/mainboard.c +++ b/src/mainboard/asus/m2v/mainboard.c @@ -26,7 +26,7 @@ u32 vt8237_ide_80pin_detect(struct device *dev) { - device_t lpc_dev; + struct device * lpc_dev; u16 acpi_io_base; u32 gpio_in; u32 res; diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index 1a2e9fc..b32ca0c 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -36,7 +36,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -61,7 +61,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -91,7 +91,7 @@ void set_pcie_reset() u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -118,7 +118,7 @@ u8 is_dev3_present(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ b/src/mainboard/asus/m4a78-em/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index b1154ab..edaecab 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -100,7 +100,7 @@ void set_pcie_reset() u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -129,7 +129,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -190,7 +190,7 @@ static void set_thermal_config(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ b/src/mainboard/asus/m4a785-m/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 8ee338e..1da327b 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in M5A88-V board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 6ce3469..6ee5923 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in EAX-785E board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c index d4b0b2d..ea13cef 100644 --- a/src/mainboard/bachmann/ot200/mainboard.c +++ b/src/mainboard/bachmann/ot200/mainboard.c @@ -46,7 +46,7 @@ static void init(struct device *dev) u32 chksum = 0; char block[20]; msr_t reset; - device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52); + struct device * eeprom_dev = dev_find_slot_on_smbus(1, 0x52); if (eeprom_dev == 0) { printk(BIOS_WARNING, "eeprom not found\n"); diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index d7ae6b7..9d415d2 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index 2761035..381658a 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -25,7 +25,7 @@ #include <device/pci_def.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index 83a55e3..815f50e 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -16,7 +16,7 @@ #include <console/console.h> #include <device/device.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Enable qemu/armv7 device...\n"); } diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index a8a61c4..6d1f2b0 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -30,7 +30,7 @@ static const unsigned char qemu_i440fx_irqs[] = { 11, 10, 10, 11, }; -static void qemu_nb_init(device_t dev) +static void qemu_nb_init(struct device * dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index e991b53..622ea54 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -33,7 +33,7 @@ static const unsigned char qemu_q35_irqs[] = { 10, 10, 11, 11, }; -static void qemu_nb_init(device_t dev) +static void qemu_nb_init(struct device * dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 2b33ff0..1dc881a 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -62,7 +62,7 @@ static void pcie_limit_power(void) // machine. It should set the slot numbers and enable power // limitation for the PCIe slots. - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(28,0)); if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0); @@ -79,14 +79,14 @@ static void pcie_limit_power(void) } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { ec_enable(); } // mainboard_enable is executed as first thing after // enumerate_buses(). Is there no mainboard_init()? -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index 0af6cf0..9e8c7bf 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c index 291d4f7..a668696 100644 --- a/src/mainboard/gigabyte/m57sli/mainboard.c +++ b/src/mainboard/gigabyte/m57sli/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 1536823..43459bc 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index cd06069..9fe9c7f 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -35,7 +35,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -60,7 +60,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -98,7 +98,7 @@ static void set_gpio40_gfx(void) u8 byte; // u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -134,7 +134,7 @@ static void set_gpio40_gfx(void) * enable the dedicated function in ma785gm board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma785gm/mptable.c +++ b/src/mainboard/gigabyte/ma785gm/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 89b50bb..f591ebb 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -98,7 +98,7 @@ void set_pcie_reset() int is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -128,7 +128,7 @@ static void set_gpio40_gfx(void) u8 byte; // u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -183,7 +183,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -244,7 +244,7 @@ static void set_thermal_config(void) * enable the dedicated function in ma785gmt board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ b/src/mainboard/gigabyte/ma785gmt/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 49df0c2..2fd5c52 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -38,7 +38,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -51,7 +51,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -71,7 +71,7 @@ u8 is_dev3_present(void) * enable the dedicated function in board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ b/src/mainboard/gigabyte/ma78gm/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index a9afdfb..ad8fa58 100755 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -55,7 +55,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -78,7 +78,7 @@ static void mainboard_enable(device_t dev) void mainboard_final( void *chip_info ); void mainboard_final( void *chip_info ) { - device_t ahci_dev; + struct device * ahci_dev; u32 ABAR; u8 *memptr; diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index b98598a..8301bd5 100755 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/google/bolt/mainboard.c b/src/mainboard/google/bolt/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/bolt/mainboard.c +++ b/src/mainboard/google/bolt/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 655fc2f..c4006c6 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -194,7 +194,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { u32 search_address = 0x0; size_t search_length = -1; @@ -258,7 +258,7 @@ static void mainboard_init(device_t dev) } } -static int butterfly_onboard_smbios_data(device_t dev, int *handle, +static int butterfly_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -278,7 +278,7 @@ static int butterfly_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 0adadb6..fc9a08c 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -258,7 +258,7 @@ static void gpio_init(void) } /* this happens after cpu_init where exynos resources are set */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { int dp_tries; struct s5p_dp_device dp_device = { @@ -322,7 +322,7 @@ static void mainboard_init(device_t dev) // gpio_info(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; diff --git a/src/mainboard/google/falco/mainboard.c b/src/mainboard/google/falco/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/falco/mainboard.c +++ b/src/mainboard/google/falco/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index ed40f8f..d1a3856 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -149,7 +149,7 @@ static int int15_handler(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ link_ec_init(); @@ -166,7 +166,7 @@ static void mainboard_init(device_t dev) } } -static int link_onboard_smbios_data(device_t dev, int *handle, +static int link_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -204,7 +204,7 @@ static int link_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 6fa8a95..d7df116 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -232,7 +232,7 @@ static void setup_ec_spi(void) spi->rx_frame_header_enable = 1; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { set_clock_sources(); @@ -284,7 +284,7 @@ static void mainboard_init(device_t dev) setup_ec_spi(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 4a05991..908d610 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -232,7 +232,7 @@ static void setup_ec_spi(void) spi->rx_frame_header_enable = 1; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { set_clock_sources(); @@ -281,7 +281,7 @@ static void mainboard_init(device_t dev) setup_ec_spi(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c index 5058eca..a1bd459 100644 --- a/src/mainboard/google/panther/mainboard.c +++ b/src/mainboard/google/panther/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { lan_init(); } @@ -52,7 +52,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 547680e..207bcfd 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -48,13 +48,13 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ parrot_ec_init(); } -static int parrot_onboard_smbios_data(device_t dev, int *handle, +static int parrot_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -85,7 +85,7 @@ static int parrot_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 1fb441d..53db9fa 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -405,7 +405,7 @@ static void sdmmc_vdd(void) } /* this happens after cpu_init where exynos resources are set */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* we'll stick with the crummy u-boot struct for now.*/ /* doing this as an auto since the struct has to be writeable */ @@ -462,7 +462,7 @@ static void mainboard_init(device_t dev) setup_usb(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/peppy/mainboard.c +++ b/src/mainboard/google/peppy/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 19579fb..54b347a 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -127,12 +127,12 @@ static int int15_handler(void) } #endif -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -161,7 +161,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c index 7977ce3..de7f434 100644 --- a/src/mainboard/google/samus/mainboard.c +++ b/src/mainboard/google/samus/mainboard.c @@ -42,12 +42,12 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -112,7 +112,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 0b0182f..4792ea9 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -20,11 +20,11 @@ #include <device/device.h> #include <boot/coreboot_tables.h> -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 9bcbfe4..58d89b8 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -48,7 +48,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { struct device *ethernet_dev = NULL; @@ -70,7 +70,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index b9af38b..7e81143 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); if (dev) { diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 6c71bad..6b3032b 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; int i; struct resource *res; for(i=0; i<3; i++) { @@ -90,7 +90,7 @@ static void *smp_write_config_table(void *v) outb(0x0e, 0x4d1); { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) // hide XIOAPIC PCI configuration space { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { uint32_t dword; @@ -151,7 +151,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 86f2cc6..175cfe5 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; int i; struct resource *res; for(i=0; i<3; i++) { @@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v) outb(0x0e, 0x4d1); { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; @@ -103,7 +103,7 @@ static void *smp_write_config_table(void *v) // hide XIOAPIC PCI configuration space { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { uint32_t dword; @@ -130,7 +130,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index f858455..3384a9f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -41,7 +41,7 @@ static void pavilion_cold_boot_init(void) pavilion_m6_1035dx_ec_init(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index f47b9d9..d12e759 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -144,7 +144,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index a2a10a1..ba6a09e 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -31,7 +31,7 @@ // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c index 6eb6390..50f8031 100644 --- a/src/mainboard/ibm/e325/mptable.c +++ b/src/mainboard/ibm/e325/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) /* Legacy IOAPIC #2 */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131-1 apic #3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c index f271166..d85e609 100644 --- a/src/mainboard/ibm/e326/mptable.c +++ b/src/mainboard/ibm/e326/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) /* Legacy IOAPIC #2 */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131-1 apic #3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index 43ff9c1..9d67e2b 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -53,7 +53,7 @@ u8 is_dev3_present(void) * enable the dedicated function in kino board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index a6839fc..be142aa 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index feae6ef..d32ca91 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -38,7 +38,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/cougar_canyon2/mainboard.c b/src/mainboard/intel/cougar_canyon2/mainboard.c index 0ea03d3..f0062d5 100644 --- a/src/mainboard/intel/cougar_canyon2/mainboard.c +++ b/src/mainboard/intel/cougar_canyon2/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c index 809feec..78dfb62 100644 --- a/src/mainboard/intel/eagleheights/mptable.c +++ b/src/mainboard/intel/eagleheights/mptable.c @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b; int bus_isa, i; uint32_t pin, route; - device_t dev; + struct device * dev; struct resource *res; unsigned long rcba; diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 347ce8a..1f92309 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c index 21664ce..6dcf7d7 100644 --- a/src/mainboard/intel/jarrell/mptable.c +++ b/src/mainboard/intel/jarrell/mptable.c @@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c index 3da1e23..ce9872a 100644 --- a/src/mainboard/intel/minnowmax/mainboard.c +++ b/src/mainboard/intel/minnowmax/mainboard.c @@ -25,7 +25,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/mohonpeak/mainboard.c b/src/mainboard/intel/mohonpeak/mainboard.c index 7559fc2..387931d 100644 --- a/src/mainboard/intel/mohonpeak/mainboard.c +++ b/src/mainboard/intel/mohonpeak/mainboard.c @@ -24,7 +24,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c index 9ad6ea6..2c7eb92 100644 --- a/src/mainboard/intel/truxton/mptable.c +++ b/src/mainboard/intel/truxton/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) u8 bus_pea0 = 0; u8 bus_pea1 = 0; u8 bus_aioc; - device_t dev; + struct device * dev; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index a6839fc..be142aa 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c index cc7eda5..65e4bcc 100644 --- a/src/mainboard/intel/xe7501devkit/mptable.c +++ b/src/mainboard/intel/xe7501devkit/mptable.c @@ -19,7 +19,7 @@ static int bus_isa; static void xe7501devkit_register_ioapics(struct mp_config_table *mc) { - device_t dev; + struct device * dev; struct resource *res; // TODO: Gack. This is REALLY ugly. diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c index dfc6636..457c88f 100644 --- a/src/mainboard/iwave/iWRainbowG6/mainboard.c +++ b/src/mainboard/iwave/iWRainbowG6/mainboard.c @@ -22,7 +22,7 @@ #include <console/console.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c index 87de022..da83738 100644 --- a/src/mainboard/iwave/iWRainbowG6/mptable.c +++ b/src/mainboard/iwave/iWRainbowG6/mptable.c @@ -36,7 +36,7 @@ void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { diff --git a/src/mainboard/iwill/dk8_htx/mainboard.c b/src/mainboard/iwill/dk8_htx/mainboard.c index 0202b50..909e5a9 100644 --- a/src/mainboard/iwill/dk8_htx/mainboard.c +++ b/src/mainboard/iwill/dk8_htx/mainboard.c @@ -7,7 +7,7 @@ #include <cpu/amd/amdk8_sysconf.h> #include "mainboard.h" -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index ff6e582..416cd17 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -126,7 +126,7 @@ static void *smp_write_config_table(void *v) for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c index c7bb33d..622b412 100644 --- a/src/mainboard/iwill/dk8s2/mptable.c +++ b/src/mainboard/iwill/dk8s2/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c index c7bb33d..622b412 100644 --- a/src/mainboard/iwill/dk8x/mptable.c +++ b/src/mainboard/iwill/dk8x/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d67e072..92c8d70 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -153,7 +153,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 4390605..2c9606a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -116,7 +116,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index 373ebb5..6da52fc 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -39,7 +39,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -52,7 +52,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -72,7 +72,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -100,7 +100,7 @@ u8 is_dev3_present(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c index 7cabdf1..0c7130b 100644 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ b/src/mainboard/jetway/pa78vm5/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index afca796..0ae64b5 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -164,7 +164,7 @@ static void hwm_setup(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index 717c399..a88a2c8 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -119,7 +119,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -180,7 +180,7 @@ static void set_thermal_config(void) * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/kontron/kt690/mptable.c +++ b/src/mainboard/kontron/kt690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 715ec56..6f6c2d8 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -172,7 +172,7 @@ static int int15_handler(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ @@ -181,7 +181,7 @@ static void mainboard_enable(device_t dev) unsigned disable = 0; if ((get_option(&disable, "ethernet1") == CB_SUCCESS) && disable) { - device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); + struct device * nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); if (nic) { printk(BIOS_DEBUG, "DISABLE FIRST NIC!\n"); nic->enabled = 0; @@ -189,7 +189,7 @@ static void mainboard_enable(device_t dev) } disable = 0; if ((get_option(&disable, "ethernet2") == CB_SUCCESS) && disable) { - device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); + struct device * nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); if (nic) { printk(BIOS_DEBUG, "DISABLE SECOND NIC!\n"); nic->enabled = 0; diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index 387bbe0..ddd6d22 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -65,7 +65,7 @@ static void mainboard_init(device_t dev) /* mainboard_enable is executed as first thing after enumerate_buses(). */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index f8c9dae..922b424 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -69,7 +69,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 79b3da8..d960b11 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -61,10 +61,11 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { struct southbridge_intel_i82801gx_config *config; - device_t dev0, idedev; + struct device * dev0; + struct device * idedev; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); @@ -95,7 +96,7 @@ static void mainboard_init(device_t dev) ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 0054064..c79b552 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -45,7 +45,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* This sneaked in here, because X200 SuperIO chip isn't really connected to anything and hence we don't init it. @@ -53,7 +53,7 @@ static void mainboard_init(device_t dev) pc_keyboard_init(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 5b76be2..f61bb9a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -71,7 +71,7 @@ const char *smbios_mainboard_bios_version(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { printk(BIOS_SPEW, "starting SPI configuration\n"); @@ -117,9 +117,9 @@ static void fill_ssdt(void) drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { - device_t dev0; + struct device * dev0; u16 pmbase; dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 00e7991..c86825e 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -49,7 +49,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -72,7 +72,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index a060015..28d7344 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -50,7 +50,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -73,7 +73,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 1d29c71..9f0cda4 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -56,9 +56,11 @@ int get_cst_entries(acpi_cstate_t **entries) return ARRAY_SIZE(cst_entries); } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { - device_t dev0, idedev, sdhci_dev; + struct device * dev0; + struct device * idedev; + struct device * sdhci_dev; ec_clr_bit(0x03, 2); @@ -115,7 +117,7 @@ static void fill_ssdt(void) drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index ee538c3..983df2c 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -163,7 +163,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 078601e..6d91730 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 9e44a21..28ac9ba 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -130,7 +130,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 078601e..6d91730 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c index b43a516..0c7032f 100644 --- a/src/mainboard/msi/ms7135/mptable.c +++ b/src/mainboard/msi/ms7135/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; u32 dword; diff --git a/src/mainboard/msi/ms7260/mainboard.c b/src/mainboard/msi/ms7260/mainboard.c index 492693a..d4e111f 100644 --- a/src/mainboard/msi/ms7260/mainboard.c +++ b/src/mainboard/msi/ms7260/mainboard.c @@ -23,7 +23,7 @@ #if 0 -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } #endif diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c index ea003a8..a200b70 100644 --- a/src/mainboard/msi/ms7260/mptable.c +++ b/src/mainboard/msi/ms7260/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index b30ab73..fc00858 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); @@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c index c7e459a..54cdc3b 100644 --- a/src/mainboard/msi/ms9282/mainboard.c +++ b/src/mainboard/msi/ms9282/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index 1764cf3..432e702 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c index 96760d6..7fc97f0 100644 --- a/src/mainboard/msi/ms9652_fam10/mainboard.c +++ b/src/mainboard/msi/ms9652_fam10/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index 09a25f2..1b9b349 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c index 1d7c79e..ede913f 100644 --- a/src/mainboard/newisys/khepri/mptable.c +++ b/src/mainboard/newisys/khepri/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c index 291d4f7..a668696 100644 --- a/src/mainboard/nvidia/l1_2pvv/mainboard.c +++ b/src/mainboard/nvidia/l1_2pvv/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c index e991efd..5cdad5b 100644 --- a/src/mainboard/nvidia/l1_2pvv/mptable.c +++ b/src/mainboard/nvidia/l1_2pvv/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; @@ -117,7 +117,7 @@ static void *smp_write_config_table(void *v) //Slot PCIE for (j = 2; j < 8; j++) { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0)); if (!dev || !dev->enabled) continue; @@ -128,7 +128,7 @@ static void *smp_write_config_table(void *v) //Slot PCI 32 { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0)); if (dev && dev->enabled) { for (i = 0; i < 4; i++) @@ -148,7 +148,7 @@ static void *smp_write_config_table(void *v) //Slot PCIE for (j = 2; j < 8; j++) { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0)); if (!dev || !dev->enabled) continue; diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index c14e9b7..c5b51e0 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -58,7 +58,7 @@ int get_cst_entries(acpi_cstate_t ** entries) -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { u16 pmbase; diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c index 2e3191b..421c916 100644 --- a/src/mainboard/rca/rm4100/mainboard.c +++ b/src/mainboard/rca/rm4100/mainboard.c @@ -20,12 +20,12 @@ #include <device/device.h> -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { // TODO Switch parport LEDs again } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { // TODO Switch parport LEDs dev->ops->init = mainboard_init; diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 4c7fffa..5421d13 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -63,14 +63,14 @@ static void dump_runtime_registers(void) } #endif -static void mainboard_final(device_t dev) +static void mainboard_final(struct device * dev) { /* Enable Dummy DCC ON# for DVI */ printk(BIOS_DEBUG, "Laptop handling...\n"); outb(inb(0x60f) & ~(1 << 5), 0x60f); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { /* Configure the MultiKey controller */ // m3885_configure_multikey(); diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index acf8023..39ade3f 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -44,7 +44,7 @@ static void ec_setup(void) send_ec_command(0xad); /* Set_Thml_Value */ } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { ec_setup(); /* LCD panel type is SIO GPIO40-43. diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 3bdd4d9..d53bf9e 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -46,9 +46,7 @@ void mainboard_suspend_resume(void) send_ec_command(EC_ACPI_ENABLE); } - - -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ lumpy_ec_init(); @@ -80,7 +78,7 @@ static int lumpy_smbios_type41_irq(int *handle, unsigned long *current, } -static int lumpy_onboard_smbios_data(device_t dev, int *handle, +static int lumpy_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -101,7 +99,7 @@ static int lumpy_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 347ce8a..1f92309 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 77be0af..219527a 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -389,7 +389,7 @@ static void pm_init( void ) { u16 word; u8 byte; - device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + struct device * sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); /* set SB600 GPIO 64 to GPIO with pull-up */ byte = pm2_ioread(0x42); @@ -432,7 +432,7 @@ static void set_thermal_config(void) { u8 byte, byte2; u8 cpu_pwm_conf, case_pwm_conf; - device_t sm_dev; + struct device * sm_dev; struct fan_control cpu_fan_control, case_fan_control; const char *name = NULL; @@ -614,8 +614,8 @@ static void patch_mmio_nonposted( void ) resource_t rbase, rend; u32 base, limit; struct resource *resource; - device_t dev; - device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1)); + struct device * dev; + struct device * k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1)); printk(BIOS_DEBUG,"%s ...\n", __func__); @@ -668,7 +668,7 @@ struct { unsigned int plx_present = 0; -static void update_subsystemid( device_t dev ) +static void update_subsystemid(struct device * dev) { int i; @@ -680,7 +680,7 @@ static void update_subsystemid( device_t dev ) } printk(BIOS_INFO, "%s [%x/%x]\n", dev_name(dev), dev->subsystem_vendor, dev->subsystem_device ); for( i=0; slot[i].bus < 255; i++) { - device_t d; + struct device * d; d = dev_find_slot(slot[i].bus,slot[i].devfn); if( d ) { printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device); @@ -695,10 +695,11 @@ static void update_subsystemid( device_t dev ) * @param */ -static void detect_hw_variant( device_t dev ) +static void detect_hw_variant(struct device * dev) { - device_t nb_dev =0, dev2 = 0; + struct device * nb_dev = NULL; + struct device * dev2 = NULL; struct southbridge_amd_rs690_config *cfg; u32 lc_state, id = 0; @@ -807,7 +808,7 @@ static void smm_lock( void ) * @param the root device */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE INT15_function_extensions int15_func; @@ -833,7 +834,7 @@ static void mainboard_init(device_t dev) * enable the dedicated function in sina board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "%s %s[%x/%x] %s\n", diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index de5151d..194b5ba 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0)); if (dev) { diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index 1ba1dcf..6259278 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index 17067ed..d53b498 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index 11db23f..5a24259 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index 4e2d48c..5c88156 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index 8f12e22..cdce2f9 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -65,7 +65,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in h8qgi board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 4fbb4c8..79f8a5e 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8scm/mainboard.c b/src/mainboard/supermicro/h8scm/mainboard.c index 23b1d72..de1dead 100644 --- a/src/mainboard/supermicro/h8scm/mainboard.c +++ b/src/mainboard/supermicro/h8scm/mainboard.c @@ -67,7 +67,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in h8scm board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index 18e1e8c..4908dcb 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -49,7 +49,7 @@ u8 is_dev3_present(void) ***/ void set_pcie_reset(void) { - device_t pcie_core_dev; + struct device * pcie_core_dev; pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); @@ -58,7 +58,7 @@ void set_pcie_reset(void) void set_pcie_dereset(void) { - device_t pcie_core_dev; + struct device * pcie_core_dev; pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); @@ -69,7 +69,7 @@ void set_pcie_dereset(void) * enable the dedicated function in h8scm board. * This function called early than sr5650_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 84593fc..864cdd1 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c index 0efae77..4185a54 100644 --- a/src/mainboard/supermicro/x6dai_g/mptable.c +++ b/src/mainboard/supermicro/x6dai_g/mptable.c @@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* southbridge */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index ab73fc7..18fe954 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -21,7 +21,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* esb6300_2 */ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; - device_t dev; + struct device * dev; /* PXHd apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index a2b8c8d..c4d690e 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -21,7 +21,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* esb6300_2 */ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; - device_t dev; + struct device * dev; /* PXHd apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c index f9165d6..935ae8c 100644 --- a/src/mainboard/supermicro/x6dhr_ig/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(2, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c index b5ba6b1..56aec2e 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c index 1d666c9..cf0c044 100644 --- a/src/mainboard/supermicro/x7db8/mainboard.c +++ b/src/mainboard/supermicro/x7db8/mainboard.c @@ -27,7 +27,7 @@ #include <device/pci_ops.h> #include <arch/io.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 3423e51..da4ed9a 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -117,7 +117,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -222,7 +222,7 @@ static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) * enable the dedicated function in tim5690 board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { u16 gpio_base = IT8712F_SIMPLE_IO_BASE; #if CONFIG_VGA_ROM_RUN diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/technexion/tim5690/mptable.c +++ b/src/mainboard/technexion/tim5690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 6010eb1..14811bb 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -53,7 +53,7 @@ static void enable_onboard_nic(void) { u8 byte; - device_t sm_dev; + struct device * sm_dev; printk(BIOS_INFO, "enable_onboard_nic.\n"); @@ -79,7 +79,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -140,7 +140,7 @@ static void set_thermal_config(void) * enable the dedicated function in tim8690 board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index 7267696..9bd4f53 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -84,13 +84,13 @@ static void flash_gpios(void) } } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { parport_gpios(); flash_gpios(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c index 9073728..9f65205 100644 --- a/src/mainboard/tyan/s2735/mptable.c +++ b/src/mainboard/tyan/s2735/mptable.c @@ -19,7 +19,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 371d9a3..3145e32 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 90299a7..798ea64 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index 32fc639..cbefcdb 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -120,7 +120,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index 7df5e87..d28a104 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index 6c07965..b06b49c 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -11,7 +11,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -118,7 +118,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index 26081c7..6413230 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/tyan/s2891/mainboard.c +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index cb49434..f52a07b 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/tyan/s2892/mainboard.c +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index 882ac69..d3dc505 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c index 604df51..85f5556 100644 --- a/src/mainboard/tyan/s2895/mainboard.c +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -12,7 +12,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index 20fa92c..3c4242f 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c index 133ce43..8620cd4 100644 --- a/src/mainboard/tyan/s2912/mptable.c +++ b/src/mainboard/tyan/s2912/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index e15387d..0b7ce31 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index dcc0fd8..3ec04bb 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 2); @@ -120,7 +120,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index 350b55c..3d22fd9 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 1); @@ -119,7 +119,7 @@ static void *smp_write_config_table(void *v) apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s8226/mainboard.c b/src/mainboard/tyan/s8226/mainboard.c index 9e8160a..6f094cb 100644 --- a/src/mainboard/tyan/s8226/mainboard.c +++ b/src/mainboard/tyan/s8226/mainboard.c @@ -67,7 +67,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in s8226 board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index dbe682c..146c21b 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -95,7 +95,7 @@ static int vx900_int15_handler(void) } #endif -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { (void)dev; diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/winent/mb6047/mainboard.c +++ b/src/mainboard/winent/mb6047/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c index 26e79ca..afbb8b9 100644 --- a/src/mainboard/winent/mb6047/mptable.c +++ b/src/mainboard/winent/mb6047/mptable.c @@ -33,7 +33,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword;

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Patch set updated for coreboot: a55626c util/inteltool: add ibex peak default gpio registers
by Alexander Couzens 25 Oct '14

25 Oct '14

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7030 -gerrit commit a55626c7247d5f3220d126642abd256edc7f46ad Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Oct 8 03:53:53 2014 +0200 util/inteltool: add ibex peak default gpio registers Default gpio registers taken from Intel documentation 5 Series Chipset Change-Id: I41688e29fcd6e53c863ba908b2b5b27287fb1dc0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/inteltool/gpio.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index dfb0819..7454fb2 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -258,6 +258,44 @@ static const io_register_t pch_gpio_registers[] = { { 0x78, 4, "RESERVED" }, { 0x7c, 4, "RESERVED" }, }; +/* Default values for Ibex Peak mobile chipsets */ +static const gpio_default_t ib_pch_mobile_defaults[] = { + { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */ + { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */ + { 0x0c, 0x02fe0100 }, /* GP_LVL */ + { 0x18, 0x00040000 }, /* GPO_BLINK */ + { 0x1c, 0x00000000 }, /* GP_SER_BLINK */ + { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */ + { 0x2c, 0x00000000 }, /* GP_INV */ + { 0x30, 0x020300fe }, /* GPIO_USE_SEL2 */ + { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */ + { 0x38, 0xa4aa0003 }, /* GP_LVL2 */ + { 0x40, 0x00000000 }, /* GPIO_USE_SEL3 */ + { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */ + { 0x48, 0x00000000 }, /* GP_LVL3 */ + { 0x60, 0x01000000 }, /* GP_RST_SEL1 */ + { 0x64, 0x00000000 }, /* GP_RST_SEL2 */ + { 0x68, 0x00000000 }, /* GP_RST_SEL3 */ +}; +/* Default values for Ibex Peak desktop chipsets */ +static const gpio_default_t ib_pch_desktop_defaults[] = { + { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */ + { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */ + { 0x0c, 0x02fe0100 }, /* GP_LVL */ + { 0x18, 0x00040000 }, /* GPO_BLINK */ + { 0x1c, 0x00000000 }, /* GP_SER_BLINK */ + { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */ + { 0x2c, 0x00000000 }, /* GP_INV */ + { 0x30, 0x020300ff }, /* GPIO_USE_SEL2 */ + { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */ + { 0x38, 0xa4aa0003 }, /* GP_LVL2 */ + { 0x40, 0x00000100 }, /* GPIO_USE_SEL3 */ + { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */ + { 0x48, 0x00000000 }, /* GP_LVL3 */ + { 0x60, 0x01000000 }, /* GP_RST_SEL1 */ + { 0x64, 0x00000000 }, /* GP_RST_SEL2 */ + { 0x68, 0x00000000 }, /* GP_RST_SEL3 */ +}; /* Default values for Cougar Point desktop chipsets */ static const gpio_default_t cp_pch_desktop_defaults[] = { { 0x00, 0xb96ba1ff }, @@ -417,6 +455,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = pch_gpio_registers; size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = ib_pch_desktop_defaults; + defaults_size = ARRAY_SIZE(ib_pch_desktop_defaults); break; case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: case PCI_DEVICE_ID_INTEL_3400_MOBILE: @@ -428,6 +468,8 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = pch_gpio_registers; size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = ib_pch_mobile_defaults; + defaults_size = ARRAY_SIZE(ib_pch_mobile_defaults); break; case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67:

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coreboot-gerrit October 2014